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| author | Wade Fife <wade.fife@ettus.com> | 2020-02-21 16:45:34 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-03-09 13:43:05 -0500 |
| commit | aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6 (patch) | |
| tree | 47da005fc4da215f05513b4655cfbfff3e0d777e /fpga/usrp3/lib | |
| parent | fc895feacb8dde3b02c9a4eccb4b4f4a654f2881 (diff) | |
| download | uhd-aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6.tar.gz uhd-aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6.tar.bz2 uhd-aebcaea5eb4e28c5c2a1c78b5e8dd42e5d1247b6.zip | |
sim: Add item support to RFNoC simulation
This adds variants of the send and recv methods in RfnocBlockCtrlBfm
and ChdrIfaceBfm that input/output items instead of CHDR words.
Diffstat (limited to 'fpga/usrp3/lib')
6 files changed, 6 insertions, 6 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv index e4753e92f..5fc9e71fb 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/rfnoc_block_axi_ram_fifo_tb.sv @@ -92,7 +92,7 @@ module rfnoc_block_axi_ram_fifo_tb #( AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0); // Bus functional model for a software block controller - RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = + RfnocBlockCtrlBfm #(CHDR_W) blk_ctrl = new(backend, m_ctrl, s_ctrl); // Connect block controller to BFMs diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv index e6f2c4d6b..fbb017fb5 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/rfnoc_block_ddc_tb.sv @@ -70,7 +70,7 @@ module rfnoc_block_ddc_tb(); AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0); // Bus functional model for a software block controller - RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = + RfnocBlockCtrlBfm #(CHDR_W, SAMP_W) blk_ctrl = new(backend, m_ctrl, s_ctrl); // Connect block controller to BFMs diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv index 8151ed761..7af3bc9b4 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/rfnoc_block_duc_tb.sv @@ -70,7 +70,7 @@ module rfnoc_block_duc_tb(); AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0); // Bus functional model for a software block controller - RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = + RfnocBlockCtrlBfm #(CHDR_W, SAMP_W) blk_ctrl = new(backend, m_ctrl, s_ctrl); // Connect block controller to BFMs diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv index 412963dc7..0f442ddd4 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/rfnoc_block_fft_tb.sv @@ -70,7 +70,7 @@ module rfnoc_block_fft_tb(); AxiStreamIf #(CHDR_W) s_chdr (rfnoc_chdr_clk, 1'b0); // Bus functional model for a software block controller - RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = + RfnocBlockCtrlBfm #(CHDR_W, SAMP_W) blk_ctrl = new(backend, m_ctrl, s_ctrl); // Connect block controller to BFMs diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv index fedb4f46b..88995e01c 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/rfnoc_block_fir_filter_tb.sv @@ -96,7 +96,7 @@ module rfnoc_block_fir_filter_tb #( AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS] (rfnoc_chdr_clk, 1'b0); // Bus functional model for a software block controller - RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = new(backend, m_ctrl, s_ctrl); + RfnocBlockCtrlBfm #(CHDR_W, SAMP_W) blk_ctrl = new(backend, m_ctrl, s_ctrl); // Connect block controller to BFMs for (genvar i = 0; i < NUM_PORTS; i++) begin : gen_bfm_connections diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv index 553b0e33e..7dfa00fe5 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/rfnoc_block_radio_tb.sv @@ -90,7 +90,7 @@ module rfnoc_block_radio_tb #( typedef ChdrData #(CHDR_W, ITEM_W)::item_t sample_t; // Bus functional model for a software block controller - RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = new(backend, m_ctrl, s_ctrl); + RfnocBlockCtrlBfm #(CHDR_W, ITEM_W) blk_ctrl = new(backend, m_ctrl, s_ctrl); // Connect block controller to BFMs for (genvar i = 0; i < NUM_PORTS; i++) begin : gen_bfm_connections |