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| author | Wade Fife <wade.fife@ettus.com> | 2021-09-01 15:27:45 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2021-09-08 08:36:05 -0500 |
| commit | 66267f515802ff3f965fd44e1f0d3097ada7484f (patch) | |
| tree | 909154ba1870a25d17dbe08323863b41613240bf /fpga/usrp3/lib | |
| parent | e3072176b0990aa17a62768d2d1cb62141898308 (diff) | |
| download | uhd-66267f515802ff3f965fd44e1f0d3097ada7484f.tar.gz uhd-66267f515802ff3f965fd44e1f0d3097ada7484f.tar.bz2 uhd-66267f515802ff3f965fd44e1f0d3097ada7484f.zip | |
fpga: tools: Add UHD_FPGA_DIR definition to synthesis
This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to
the location of the UHD "fpga" directory. This allows you to include
files in your out-of-tree modules relative to the FPGA directory. For
example, you could include the library header file rfnoc_chdr_utils.vh
using the following:
`include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
Some simulators may not support `" outside of the context of a `define,
in which case you can do the following:
`define RFNOC_CHDR_UTILS_PATH \
`"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`"
`include `RFNOC_CHDR_UTILS_PATH
Diffstat (limited to 'fpga/usrp3/lib')
0 files changed, 0 insertions, 0 deletions