rfnoc: Fix noc_shell direction comments

Some comments describing data flow direction were wrong. This commit
updates the Mako files and updates the noc_shell modules with newly
generated versions.

18 files changed, 86 insertions, 81 deletions

diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/noc_shell_addsub.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/noc_shell_addsub.v
index 333f6cbfb..ae21cb308 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/noc_shell_addsub.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/noc_shell_addsub.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -25,7 +25,6 @@ module noc_shell_addsub #(
   parameter       CHDR_W          = 64,
   parameter [5:0] MTU             = 10,
   parameter       USE_IMPL        = "Verilog"
-
 ) (
   //---------------------
   // Framework Interface
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v
index 29d8dfdab..539622831 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/noc_shell_axi_ram_fifo.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_axi_ram_fifo
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the axi_ram_fifo block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -212,7 +212,7 @@ module noc_shell_axi_ram_fifo #(
 
   assign axis_chdr_clk = rfnoc_chdr_clk;
   assign axis_chdr_rst = rfnoc_chdr_rst;
-  
+
   //---------------------
   // Input Data Paths
   //---------------------
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v
index c4b362cd6..a4874114f 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/noc_shell_ddc.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_ddc
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the ddc block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -99,7 +99,7 @@ module noc_shell_ddc #(
   output wire [NUM_PORTS*16-1:0]     m_in_axis_tlength,
   output wire [NUM_PORTS-1:0]        m_in_axis_teov,
   output wire [NUM_PORTS-1:0]        m_in_axis_teob,
-  // Data Stream to User Logic: out
+  // Data Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_axis_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_axis_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_axis_tlast,
@@ -222,7 +222,7 @@ module noc_shell_ddc #(
 
   assign axis_data_clk = ce_clk;
   assign axis_data_rst = ce_rst;
-  
+
   //---------------------
   // Input Data Paths
   //---------------------
@@ -251,7 +251,7 @@ module noc_shell_ddc #(
       .m_axis_tready      (m_in_axis_tready[i]),
       .m_axis_ttimestamp  (m_in_axis_ttimestamp[64*i+:64]),
       .m_axis_thas_time   (m_in_axis_thas_time[i]),
-      .m_axis_tlength     (m_in_axis_tlength[i*16+:16]),
+      .m_axis_tlength     (m_in_axis_tlength[16*i+:16]),
       .m_axis_teov        (m_in_axis_teov[i]),
       .m_axis_teob        (m_in_axis_teob[i]),
       .flush_en           (data_i_flush_en),
@@ -267,13 +267,14 @@ module noc_shell_ddc #(
 
   for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
     axis_data_to_chdr #(
-      .CHDR_W         (CHDR_W),
-      .ITEM_W         (32),
-      .NIPC           (1),
-      .SYNC_CLKS      (0),
-      .INFO_FIFO_SIZE ($clog2(32)),
-      .PYLD_FIFO_SIZE ($clog2(MTU)),
-      .MTU            (MTU)
+      .CHDR_W          (CHDR_W),
+      .ITEM_W          (32),
+      .NIPC            (1),
+      .SYNC_CLKS       (0),
+      .INFO_FIFO_SIZE  ($clog2(32)),
+      .PYLD_FIFO_SIZE  ($clog2(MTU)),
+      .MTU             (MTU),
+      .SIDEBAND_AT_END (1)
     ) axis_data_to_chdr_out_out (
       .axis_chdr_clk      (rfnoc_chdr_clk),
       .axis_chdr_rst      (rfnoc_chdr_rst),
@@ -290,6 +291,7 @@ module noc_shell_ddc #(
       .s_axis_tready      (s_out_axis_tready[i]),
       .s_axis_ttimestamp  (s_out_axis_ttimestamp[64*i+:64]),
       .s_axis_thas_time   (s_out_axis_thas_time[i]),
+      .s_axis_tlength     (16'd0),
       .s_axis_teov        (s_out_axis_teov[i]),
       .s_axis_teob        (s_out_axis_teob[i]),
       .flush_en           (data_o_flush_en),
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/noc_shell_duc.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/noc_shell_duc.v
index a7416e510..5645a2442 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/noc_shell_duc.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/noc_shell_duc.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_duc
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the duc block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -99,7 +99,7 @@ module noc_shell_duc #(
   output wire [NUM_PORTS*16-1:0]     m_in_axis_tlength,
   output wire [NUM_PORTS-1:0]        m_in_axis_teov,
   output wire [NUM_PORTS-1:0]        m_in_axis_teob,
-  // Data Stream to User Logic: out
+  // Data Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_axis_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_axis_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_axis_tlast,
@@ -222,7 +222,7 @@ module noc_shell_duc #(
 
   assign axis_data_clk = ce_clk;
   assign axis_data_rst = ce_rst;
-  
+
   //---------------------
   // Input Data Paths
   //---------------------
@@ -251,7 +251,7 @@ module noc_shell_duc #(
       .m_axis_tready      (m_in_axis_tready[i]),
       .m_axis_ttimestamp  (m_in_axis_ttimestamp[64*i+:64]),
       .m_axis_thas_time   (m_in_axis_thas_time[i]),
-      .m_axis_tlength     (m_in_axis_tlength[i*16+:16]),
+      .m_axis_tlength     (m_in_axis_tlength[16*i+:16]),
       .m_axis_teov        (m_in_axis_teov[i]),
       .m_axis_teob        (m_in_axis_teob[i]),
       .flush_en           (data_i_flush_en),
@@ -267,13 +267,14 @@ module noc_shell_duc #(
 
   for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
     axis_data_to_chdr #(
-      .CHDR_W         (CHDR_W),
-      .ITEM_W         (32),
-      .NIPC           (1),
-      .SYNC_CLKS      (0),
-      .INFO_FIFO_SIZE ($clog2(32)),
-      .PYLD_FIFO_SIZE ($clog2(MTU)),
-      .MTU            (MTU)
+      .CHDR_W          (CHDR_W),
+      .ITEM_W          (32),
+      .NIPC            (1),
+      .SYNC_CLKS       (0),
+      .INFO_FIFO_SIZE  ($clog2(32)),
+      .PYLD_FIFO_SIZE  ($clog2(MTU)),
+      .MTU             (MTU),
+      .SIDEBAND_AT_END (1)
     ) axis_data_to_chdr_out_out (
       .axis_chdr_clk      (rfnoc_chdr_clk),
       .axis_chdr_rst      (rfnoc_chdr_rst),
@@ -290,6 +291,7 @@ module noc_shell_duc #(
       .s_axis_tready      (s_out_axis_tready[i]),
       .s_axis_ttimestamp  (s_out_axis_ttimestamp[64*i+:64]),
       .s_axis_thas_time   (s_out_axis_thas_time[i]),
+      .s_axis_tlength     (16'd0),
       .s_axis_teov        (s_out_axis_teov[i]),
       .s_axis_teob        (s_out_axis_teob[i]),
       .flush_en           (data_o_flush_en),
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/noc_shell_fft.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/noc_shell_fft.v
index 3841130c9..31c2f320a 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/noc_shell_fft.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/noc_shell_fft.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_fft
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the fft block.
 //   See the RFNoC specification for more information about NoC shells.
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/noc_shell_fir_filter.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/noc_shell_fir_filter.v
index 6bb4f57be..8614f0f29 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/noc_shell_fir_filter.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/noc_shell_fir_filter.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_fir_filter
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the fir_filter block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -103,13 +103,13 @@ module noc_shell_fir_filter #(
   output wire [NUM_PORTS-1:0]        m_in_context_tlast,
   output wire [NUM_PORTS-1:0]        m_in_context_tvalid,
   input  wire [NUM_PORTS-1:0]        m_in_context_tready,
-  // Payload Stream to User Logic: out
+  // Payload Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_payload_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_payload_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tlast,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tvalid,
   output wire [NUM_PORTS-1:0]        s_out_payload_tready,
-  // Context Stream to User Logic: out
+  // Context Stream from User Logic: out
   input  wire [NUM_PORTS*CHDR_W-1:0] s_out_context_tdata,
   input  wire [NUM_PORTS*4-1:0]      s_out_context_tuser,
   input  wire [NUM_PORTS-1:0]        s_out_context_tlast,
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/noc_shell_fosphor.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/noc_shell_fosphor.v
index dd1845b40..1eecf3a0a 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/noc_shell_fosphor.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/noc_shell_fosphor.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2020 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_fosphor
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the fosphor block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -229,7 +229,7 @@ module noc_shell_fosphor #(
 
   assign axis_data_clk = ce_clk;
   assign axis_data_rst = ce_rst;
-  
+
   //---------------------
   // Input Data Paths
   //---------------------
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/noc_shell_keep_one_in_n.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/noc_shell_keep_one_in_n.v
index 78572597e..c3fd16bc7 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/noc_shell_keep_one_in_n.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/noc_shell_keep_one_in_n.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -23,8 +23,8 @@
 module noc_shell_keep_one_in_n #(
   parameter [9:0] THIS_PORTID     = 10'd0,
   parameter       CHDR_W          = 64,
-  parameter       NUM_PORTS       = 1,
-  parameter [5:0] MTU             = 10
+  parameter [5:0] MTU             = 10,
+  parameter       NUM_PORTS       = 1
 ) (
   //---------------------
   // Framework Interface
@@ -95,7 +95,7 @@ module noc_shell_keep_one_in_n #(
   output wire [NUM_PORTS*16-1:0]     m_in_axis_tlength,
   output wire [NUM_PORTS-1:0]        m_in_axis_teov,
   output wire [NUM_PORTS-1:0]        m_in_axis_teob,
-  // Data Stream to User Logic: out
+  // Data Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_axis_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_axis_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_axis_tlast,
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_logpwr/noc_shell_logpwr.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_logpwr/noc_shell_logpwr.v
index e68f4e680..434793ffd 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_logpwr/noc_shell_logpwr.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_logpwr/noc_shell_logpwr.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -85,13 +85,13 @@ module noc_shell_logpwr #(
   output wire [NUM_PORTS-1:0]        m_in_context_tlast,
   output wire [NUM_PORTS-1:0]        m_in_context_tvalid,
   input  wire [NUM_PORTS-1:0]        m_in_context_tready,
-  // Payload Stream to User Logic: out
+  // Payload Stream from User Logic: out
   input  wire [NUM_PORTS*16*1-1:0]   s_out_payload_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_payload_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tlast,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tvalid,
   output wire [NUM_PORTS-1:0]        s_out_payload_tready,
-  // Context Stream to User Logic: out
+  // Context Stream from User Logic: out
   input  wire [NUM_PORTS*CHDR_W-1:0] s_out_context_tdata,
   input  wire [NUM_PORTS*4-1:0]      s_out_context_tuser,
   input  wire [NUM_PORTS-1:0]        s_out_context_tlast,
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/noc_shell_moving_avg.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/noc_shell_moving_avg.v
index 8bd699c58..c44d28eea 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/noc_shell_moving_avg.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/noc_shell_moving_avg.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -96,13 +96,13 @@ module noc_shell_moving_avg #(
   output wire [NUM_PORTS-1:0]        m_in_context_tlast,
   output wire [NUM_PORTS-1:0]        m_in_context_tvalid,
   input  wire [NUM_PORTS-1:0]        m_in_context_tready,
-  // Payload Stream to User Logic: out
+  // Payload Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_payload_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_payload_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tlast,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tvalid,
   output wire [NUM_PORTS-1:0]        s_out_payload_tready,
-  // Context Stream to User Logic: out
+  // Context Stream from User Logic: out
   input  wire [NUM_PORTS*CHDR_W-1:0] s_out_context_tdata,
   input  wire [NUM_PORTS*4-1:0]      s_out_context_tuser,
   input  wire [NUM_PORTS-1:0]        s_out_context_tlast,
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/noc_shell_null_src_sink.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/noc_shell_null_src_sink.v
index 3676ffbd3..177b58af2 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/noc_shell_null_src_sink.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/noc_shell_null_src_sink.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_null_src_sink
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the null_src_sink block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -23,9 +23,9 @@
 module noc_shell_null_src_sink #(
   parameter [9:0] THIS_PORTID     = 10'd0,
   parameter       CHDR_W          = 64,
-  parameter       ITEM_W          = 32,
-  parameter       NIPC            = 2,
-  parameter [5:0] MTU             = 10
+  parameter [5:0] MTU             = 10,
+  parameter       NIPC            = CHDR_W/32,
+  parameter       ITEM_W          = 32
 ) (
   //---------------------
   // Framework Interface
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/noc_shell_radio.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/noc_shell_radio.v
index faf58840f..5909e0e39 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/noc_shell_radio.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_radio/noc_shell_radio.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2019 Ettus Research, A National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_radio
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the radio block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -115,7 +115,7 @@ module noc_shell_radio #(
   output wire [NUM_PORTS*16-1:0]     m_in_axis_tlength,
   output wire [NUM_PORTS-1:0]        m_in_axis_teov,
   output wire [NUM_PORTS-1:0]        m_in_axis_teob,
-  // Data Stream to User Logic: out
+  // Data Stream from User Logic: out
   input  wire [NUM_PORTS*ITEM_W*NIPC-1:0]   s_out_axis_tdata,
   input  wire [NUM_PORTS*NIPC-1:0]      s_out_axis_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_axis_tlast,
@@ -238,7 +238,7 @@ module noc_shell_radio #(
 
   assign axis_data_clk = radio_clk;
   assign axis_data_rst = radio_rst;
-  
+
   //---------------------
   // Input Data Paths
   //---------------------
@@ -267,7 +267,7 @@ module noc_shell_radio #(
       .m_axis_tready      (m_in_axis_tready[i]),
       .m_axis_ttimestamp  (m_in_axis_ttimestamp[64*i+:64]),
       .m_axis_thas_time   (m_in_axis_thas_time[i]),
-      .m_axis_tlength     (m_in_axis_tlength[i*16+:16]),
+      .m_axis_tlength     (m_in_axis_tlength[16*i+:16]),
       .m_axis_teov        (m_in_axis_teov[i]),
       .m_axis_teob        (m_in_axis_teob[i]),
       .flush_en           (data_i_flush_en),
@@ -283,13 +283,14 @@ module noc_shell_radio #(
 
   for (i = 0; i < NUM_PORTS; i = i + 1) begin: gen_output_out
     axis_data_to_chdr #(
-      .CHDR_W         (CHDR_W),
-      .ITEM_W         (ITEM_W),
-      .NIPC           (NIPC),
-      .SYNC_CLKS      (0),
-      .INFO_FIFO_SIZE ($clog2(32)),
-      .PYLD_FIFO_SIZE ($clog2(MTU)),
-      .MTU            (MTU)
+      .CHDR_W          (CHDR_W),
+      .ITEM_W          (ITEM_W),
+      .NIPC            (NIPC),
+      .SYNC_CLKS       (0),
+      .INFO_FIFO_SIZE  ($clog2(32)),
+      .PYLD_FIFO_SIZE  ($clog2(MTU)),
+      .MTU             (MTU),
+      .SIDEBAND_AT_END (1)
     ) axis_data_to_chdr_out_out (
       .axis_chdr_clk      (rfnoc_chdr_clk),
       .axis_chdr_rst      (rfnoc_chdr_rst),
@@ -306,6 +307,7 @@ module noc_shell_radio #(
       .s_axis_tready      (s_out_axis_tready[i]),
       .s_axis_ttimestamp  (s_out_axis_ttimestamp[64*i+:64]),
       .s_axis_thas_time   (s_out_axis_thas_time[i]),
+      .s_axis_tlength     (16'd0),
       .s_axis_teov        (s_out_axis_teov[i]),
       .s_axis_teob        (s_out_axis_teob[i]),
       .flush_en           (data_o_flush_en),
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/noc_shell_replay.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/noc_shell_replay.v
index 55ab08b51..51f018b99 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/noc_shell_replay.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/noc_shell_replay.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_replay
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the replay block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -97,7 +97,7 @@ module noc_shell_replay #(
   output wire [NUM_PORTS*16-1:0]     m_in_axis_tlength,
   output wire [NUM_PORTS-1:0]        m_in_axis_teov,
   output wire [NUM_PORTS-1:0]        m_in_axis_teob,
-  // Data Stream to User Logic: out
+  // Data Stream from User Logic: out
   input  wire [NUM_PORTS*32*MEM_DATA_W/32-1:0]   s_out_axis_tdata,
   input  wire [NUM_PORTS*MEM_DATA_W/32-1:0]      s_out_axis_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_axis_tlast,
@@ -221,7 +221,7 @@ module noc_shell_replay #(
 
   assign axis_data_clk = mem_clk;
   assign axis_data_rst = mem_rst;
-  
+
   //---------------------
   // Input Data Paths
   //---------------------
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/noc_shell_siggen.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/noc_shell_siggen.v
index 6f14430b7..4e8b99e98 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/noc_shell_siggen.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/noc_shell_siggen.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -84,7 +84,7 @@ module noc_shell_siggen #(
   // AXI-Stream Data Clock and Reset
   output wire               axis_data_clk,
   output wire               axis_data_rst,
-  // Data Stream to User Logic: out
+  // Data Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_axis_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_axis_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_axis_tlast,
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_split_stream/noc_shell_split_stream.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_split_stream/noc_shell_split_stream.v
index e7a865e4e..8d6c1ebff 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_split_stream/noc_shell_split_stream.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_split_stream/noc_shell_split_stream.v
@@ -1,11 +1,11 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_split_stream
 //
-// Description: 
+// Description:
 //
 //   This is a tool-generated NoC-shell for the split_stream block.
 //   See the RFNoC specification for more information about NoC shells.
@@ -138,7 +138,7 @@ module noc_shell_split_stream #(
 
   assign axis_chdr_clk = rfnoc_chdr_clk;
   assign axis_chdr_rst = rfnoc_chdr_rst;
-  
+
   //---------------------
   // Input Data Paths
   //---------------------
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/noc_shell_switchboard.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/noc_shell_switchboard.v
index 9d66ad908..2beb37ef3 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/noc_shell_switchboard.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/noc_shell_switchboard.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/noc_shell_vector_iir.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/noc_shell_vector_iir.v
index 959ec4124..fd80ac71d 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/noc_shell_vector_iir.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/noc_shell_vector_iir.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -96,13 +96,13 @@ module noc_shell_vector_iir #(
   output wire [NUM_PORTS-1:0]        m_in_context_tlast,
   output wire [NUM_PORTS-1:0]        m_in_context_tvalid,
   input  wire [NUM_PORTS-1:0]        m_in_context_tready,
-  // Payload Stream to User Logic: out
+  // Payload Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_payload_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_payload_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tlast,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tvalid,
   output wire [NUM_PORTS-1:0]        s_out_payload_tready,
-  // Context Stream to User Logic: out
+  // Context Stream from User Logic: out
   input  wire [NUM_PORTS*CHDR_W-1:0] s_out_context_tdata,
   input  wire [NUM_PORTS*4-1:0]      s_out_context_tuser,
   input  wire [NUM_PORTS-1:0]        s_out_context_tlast,
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/noc_shell_window.v b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/noc_shell_window.v
index 24d37020d..7855d1ee8 100644
--- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/noc_shell_window.v
+++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/noc_shell_window.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2020 Ettus Research, a National Instruments Brand
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
@@ -97,13 +97,13 @@ module noc_shell_window #(
   output wire [NUM_PORTS-1:0]        m_in_context_tlast,
   output wire [NUM_PORTS-1:0]        m_in_context_tvalid,
   input  wire [NUM_PORTS-1:0]        m_in_context_tready,
-  // Payload Stream to User Logic: out
+  // Payload Stream from User Logic: out
   input  wire [NUM_PORTS*32*1-1:0]   s_out_payload_tdata,
   input  wire [NUM_PORTS*1-1:0]      s_out_payload_tkeep,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tlast,
   input  wire [NUM_PORTS-1:0]        s_out_payload_tvalid,
   output wire [NUM_PORTS-1:0]        s_out_payload_tready,
-  // Context Stream to User Logic: out
+  // Context Stream from User Logic: out
   input  wire [NUM_PORTS*CHDR_W-1:0] s_out_context_tdata,
   input  wire [NUM_PORTS*4-1:0]      s_out_context_tuser,
   input  wire [NUM_PORTS-1:0]        s_out_context_tlast,