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authorWade Fife <wade.fife@ettus.com>2021-04-05 16:02:45 -0500
committerWade Fife <wade.fife@ettus.com>2021-04-09 17:26:59 -0500
commit0b965d579e2df962b91dac141eef6668f932e992 (patch)
tree75b7baffd8364cacbf17b77c4ce3defd2c795fbc /fpga/usrp3/lib
parentc3508cbf4ea3965e7b7acebfba176ca058545b77 (diff)
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fpga: lib: Fix simulation of axi_fir_filter
The always(*) block was never executing in some simulators because there were no signals on the right-hand side in the block. Changing it to an initial block ensures it always runs.
Diffstat (limited to 'fpga/usrp3/lib')
-rw-r--r--fpga/usrp3/lib/rfnoc/axi_fir_filter.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp3/lib/rfnoc/axi_fir_filter.v b/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
index 4fffab8af..7efa60a97 100644
--- a/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
+++ b/fpga/usrp3/lib/rfnoc/axi_fir_filter.v
@@ -116,7 +116,7 @@ module axi_fir_filter #(
end
// Coefficients are static
end else begin
- always @(*) begin
+ initial begin
for (k = 0; k < NUM_SLICES; k = k + 1) begin
coeffs[k] <= COEFFS_VEC[COEFF_WIDTH*k +: COEFF_WIDTH];
coeff_load_stb <= 1'b1;