diff options
| author | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-03-25 15:59:03 -0700 |
| commit | 04292f9b109479b639add31f83fd240a6387f488 (patch) | |
| tree | 4b8723a4ae63626029704f901ee0083bb23bc1e9 /fpga/usrp3/lib/xge/Makefile.srcs | |
| parent | 09915aa57bc88099cbcbbe925946ae65bc0ad8f0 (diff) | |
| parent | ff8a1252f3a51369abe0a165d963b781089ec66c (diff) | |
| download | uhd-04292f9b109479b639add31f83fd240a6387f488.tar.gz uhd-04292f9b109479b639add31f83fd240a6387f488.tar.bz2 uhd-04292f9b109479b639add31f83fd240a6387f488.zip | |
Merge branch 'master' into mwest/b200_docs
Diffstat (limited to 'fpga/usrp3/lib/xge/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/lib/xge/Makefile.srcs | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/xge/Makefile.srcs b/fpga/usrp3/lib/xge/Makefile.srcs new file mode 100644 index 000000000..5af520788 --- /dev/null +++ b/fpga/usrp3/lib/xge/Makefile.srcs @@ -0,0 +1,29 @@ +################################################## +# OpenCore XGE MAC Sources +################################################## +XGE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/xge/, \ +rtl/verilog/fault_sm.v \ +rtl/verilog/generic_fifo.v \ +rtl/verilog/generic_fifo_ctrl.v \ +rtl/verilog/generic_mem_xilinx_block.v \ +rtl/verilog/generic_mem_medium.v \ +rtl/verilog/generic_mem_small.v \ +rtl/verilog/meta_sync.v \ +rtl/verilog/meta_sync_single.v \ +rtl/verilog/rx_checker.v \ +rtl/verilog/rx_data_fifo.v \ +rtl/verilog/rx_dequeue.v \ +rtl/verilog/rx_enqueue.v \ +rtl/verilog/rx_hold_fifo.v \ +rtl/verilog/sync_clk_core.v \ +rtl/verilog/sync_clk_wb.v \ +rtl/verilog/sync_clk_xgmii_tx.v \ +rtl/verilog/tx_checker.v \ +rtl/verilog/tx_data_fifo.v \ +rtl/verilog/tx_dequeue.v \ +rtl/verilog/tx_enqueue.v \ +rtl/verilog/tx_hold_fifo.v \ +rtl/verilog/wishbone_if.v \ +rtl/verilog/xge_mac.v \ +)) + |