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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/wishbone/Makefile.srcs | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/wishbone/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/lib/wishbone/Makefile.srcs | 19 |
1 files changed, 0 insertions, 19 deletions
diff --git a/fpga/usrp3/lib/wishbone/Makefile.srcs b/fpga/usrp3/lib/wishbone/Makefile.srcs deleted file mode 100644 index 6459de834..000000000 --- a/fpga/usrp3/lib/wishbone/Makefile.srcs +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright 2010-2012 Ettus Research LLC -# - -################################################## -# Wishbone Perifs -################################################## -WISHBONE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/wishbone/, \ -simple_uart_rx.v \ -simple_uart_tx.v \ -simple_uart.v \ -wb_1master.v \ -settings_bus.v \ -settings_readback.v \ -i2c_master_top.v \ -i2c_master_bit_ctrl.v \ -i2c_master_byte_ctrl.v \ -axi_stream_to_wb.v \ -)) |