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| author | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
|---|---|---|
| committer | Ben Hilburn <ben.hilburn@ettus.com> | 2013-10-10 10:17:27 -0700 |
| commit | 0df4b801a34697f2058b4a7b95e08d2a0576c9db (patch) | |
| tree | be10e78d1a97c037a9e7492360a178d1873b9c09 /fpga/usrp3/lib/wishbone/Makefile.srcs | |
| parent | 6e7bc850b66e8188718248b76b729c7cf9c89700 (diff) | |
| download | uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.gz uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.tar.bz2 uhd-0df4b801a34697f2058b4a7b95e08d2a0576c9db.zip | |
Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus.
Diffstat (limited to 'fpga/usrp3/lib/wishbone/Makefile.srcs')
| -rw-r--r-- | fpga/usrp3/lib/wishbone/Makefile.srcs | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/wishbone/Makefile.srcs b/fpga/usrp3/lib/wishbone/Makefile.srcs new file mode 100644 index 000000000..6459de834 --- /dev/null +++ b/fpga/usrp3/lib/wishbone/Makefile.srcs @@ -0,0 +1,19 @@ +# +# Copyright 2010-2012 Ettus Research LLC +# + +################################################## +# Wishbone Perifs +################################################## +WISHBONE_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/wishbone/, \ +simple_uart_rx.v \ +simple_uart_tx.v \ +simple_uart.v \ +wb_1master.v \ +settings_bus.v \ +settings_readback.v \ +i2c_master_top.v \ +i2c_master_bit_ctrl.v \ +i2c_master_byte_ctrl.v \ +axi_stream_to_wb.v \ +)) |