Pushing the bulk of UHD-3.7.0 code.

9 files changed, 110 insertions, 165 deletions

diff --git a/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v
index 6a415dae5..2ae61a32d 100644
--- a/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v
+++ b/fpga/usrp3/lib/vita/chdr_12sc_to_16sc.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v
index 39ee2ccc9..c0c853fb9 100644
--- a/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_12sc.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 module chdr_16sc_to_12sc
   #(parameter BASE=0)
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v b/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v
index 8754d9702..74aff2f08 100644
--- a/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_32f.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 
diff --git a/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v b/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v
index 57aa666b8..506f7b49f 100644
--- a/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v
+++ b/fpga/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //selectable conversion chain
 
diff --git a/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v b/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v
index 9cff1427e..681379b1a 100644
--- a/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v
+++ b/fpga/usrp3/lib/vita/chdr_32f_to_16sc.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 
 module chdr_32f_to_16sc
diff --git a/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v b/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v
index 3ede9f578..dad252d95 100644
--- a/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v
+++ b/fpga/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v
@@ -2,19 +2,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 //selectable conversion chain
 
diff --git a/fpga/usrp3/lib/vita/new_rx_control.v b/fpga/usrp3/lib/vita/new_rx_control.v
index bf058c817..a0deca241 100644
--- a/fpga/usrp3/lib/vita/new_rx_control.v
+++ b/fpga/usrp3/lib/vita/new_rx_control.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2013 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+
 
 // HALT brings RX to an idle state as quickly as possible if RX is running
 // without running the risk of leaving a packet fragment in downstream FIFO's.
@@ -128,57 +116,68 @@ module new_rx_control
 	  clear_halt <= 1'b0;
        end
      else
-       case(ibs_state)
+       case (ibs_state)
 	 IBS_IDLE : begin
 	   clear_halt <= 1'b0; // Incase we got here through a HALT.
-	   if(command_valid)
-	     if(stop)
-	       ibs_state <= IBS_IDLE;//IBS_ZEROLEN;
-	     else if(late & ~send_imm)
-	       ibs_state <= IBS_LATECMD;
-	     else if(now | send_imm)
-	       begin
-		  ibs_state <= IBS_RUNNING;
-		  lines_left <= numlines;
-		  repeat_lines <= numlines;
-		  chain_sav <= chain;
-		  reload_sav <= reload;
-	       end
+	   if (command_valid)
+	     // There is a valid command to pop from FIFO.
+	     if (stop) begin
+		// Stop bit set in this command, go idle.
+		ibs_state <= IBS_IDLE;//IBS_ZEROLEN;
+	     end else if (late & ~send_imm) begin
+		// Got this command later than its execution time.
+		ibs_state <= IBS_LATECMD;
+	     end else if (now | send_imm) begin
+		// Either its time to run this command or it should run immediately without a time.
+		ibs_state <= IBS_RUNNING;
+		lines_left <= numlines;
+		repeat_lines <= numlines;
+		chain_sav <= chain;
+		reload_sav <= reload;
+	     end
 	 end // case: IBS_IDLE
 	 
-	 IBS_RUNNING : // need to check for full
-	   if(strobe)
-	     if(full)
-	       ibs_state <= IBS_OVERRUN;
-	     else
-	       if(lines_left == 1)
-		 // Provide Halt mechanism used to bring RX into known IDLE state
-		 // at re-initialization.
-		 if (halt)
-		   begin
-		      ibs_state <= IBS_IDLE;
-		      clear_halt <= 1'b1;
-		   end
-		 else if(chain_sav)
-		    if(command_valid)
-		     begin
+	 IBS_RUNNING : begin 
+	    if (strobe) begin 
+	       if (full) begin
+		  // Framing FIFO is full and we have just overrun.
+		  ibs_state <= IBS_OVERRUN;
+	       end else if (lines_left == 1) begin
+		  // Provide Halt mechanism used to bring RX into known IDLE state
+		  // at re-initialization.
+		  if (halt) begin
+		     ibs_state <= IBS_IDLE;
+		     clear_halt <= 1'b1;
+		  end else if (chain_sav) begin
+		     // If chain_sav is true then execute the next command now this one finished.
+		     if (command_valid) begin
 			lines_left <= numlines;
 			repeat_lines <= numlines;
 			chain_sav <= chain;
 			reload_sav <= reload;
-			if(stop)
-			  ibs_state <= IBS_IDLE;
+			// If the new command includes stop then go idle.
+			if (stop) begin
+			   ibs_state <= IBS_IDLE;
+			end
+		     end else if (reload_sav) begin
+			// There is no new command to pop from FIFO so re-run previous command.
+			lines_left <= repeat_lines;
+		     end else begin
+			// Chain has been broken, no commands left in FIFO and reload not set.
+			ibs_state <= IBS_BROKENCHAIN;
 		     end
-		   else if(reload_sav)
-		     lines_left <= repeat_lines;
-		   else
-		     ibs_state <= IBS_BROKENCHAIN;
-		 else
-		   ibs_state <= IBS_IDLE;
-	       else
-		 lines_left <= lines_left - 28'd1;
-
-
+		  end else begin // if (chain_sav)
+		     // Chain is not true, so don't look for new command, instead go idle.
+		     ibs_state <= IBS_IDLE;
+		  end
+	       end else begin // if (lines_left == 1)
+		  // Still counting down lines in current command.
+		  lines_left <= lines_left - 28'd1;
+	       end
+	    end // if (strobe)
+	 end // case: IBS_RUNNING
+	 
+	 
 	IBS_OVERRUN: if(err_tready_int) ibs_state <= IBS_OVR_TIME;
 	IBS_OVR_TIME: if(err_tready_int) ibs_state <= IBS_OVR_DATA;
 	IBS_OVR_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
@@ -207,7 +206,7 @@ module new_rx_control
      endcase // case (ibs_state)
 
    assign run = (ibs_state == IBS_RUNNING);
-   assign eob = strobe & (lines_left == 1) & ( ~chain_sav | (command_valid & stop) | (~command_valid & ~reload_sav) | halt);
+   assign eob = strobe && (lines_left == 1) && ( !chain_sav || (command_valid && stop) || (!command_valid && !reload_sav) || halt);
 
    always @*
      case (ibs_state)
@@ -239,7 +238,7 @@ module new_rx_control
 
 
    assign debug[3:0] =  ibs_state;
-   assign debug[7:4] =  {2'b0, command_valid, command_ready};
+   assign debug[9:4] =  {send_imm,chain,reload,stop, command_valid, command_ready};
    
    axi_fifo_short #(.WIDTH(65)) output_fifo
      (
diff --git a/fpga/usrp3/lib/vita/new_rx_framer.v b/fpga/usrp3/lib/vita/new_rx_framer.v
index 6594baa83..ab67ced0a 100644
--- a/fpga/usrp3/lib/vita/new_rx_framer.v
+++ b/fpga/usrp3/lib/vita/new_rx_framer.v
@@ -39,7 +39,8 @@ module new_rx_framer
 
    wire [15:0] 	  maxlen;
    reg [31:0] 	  holding;
-
+    
+	
    // FIXME need to handle case where hdr fifo is full (i.e. too many tiny packets)
    assign full = (sample_space == 16'd0) | (sample_space == 16'd1) | ~hdr_tready;
    
@@ -52,6 +53,10 @@ module new_rx_framer
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(sid),.changed(sid_changed));
 
+   localparam START = 0;
+   localparam SECOND = 1;
+   localparam FIRST = 2;
+   
    reg [1:0] 	  instate;
    reg [15:0] 	  numsamps;
    reg 		  nearly_eop;
@@ -60,52 +65,61 @@ module new_rx_framer
    always @(posedge clk)
      if(reset | clear)
        begin
-	  instate <= 0;
+	  instate <= START;
 	  numsamps <= 0;
 	  nearly_eop <= 0;
 	  
        end
      else if (run)
        case(instate)
-	 0 :
+	 //
+	 // Start a new packet in this state
+	 //
+	 START :
 	   if(strobe)
 	     if(eop)
 	       begin
-		  instate <= 0;
+		  instate <= START;
 		  numsamps <= 0;
 		  nearly_eop <= 0;
 	       end
 	     else
 	       begin
-		  instate <= 1;
+		  instate <= SECOND;
 		  numsamps <= numsamps + 1;
 		  nearly_eop <= (numsamps >= (maxlen-2));
-	       end
-	 1 :
+	       end // else: !if(eop)
+	 //
+	 // Second 32 bit sample in a 64bit word
+	 //
+	 SECOND :
 	   if(strobe)
 	     if(eop)
 	       begin
-		  instate <= 0;
+		  instate <= START;
 		  numsamps <= 0;
 		  nearly_eop <= 0;
 	       end
 	     else
 	       begin
-		  instate <= 2;
+		  instate <= FIRST;
 		  numsamps <= numsamps + 1;
 		  nearly_eop <= (numsamps >= (maxlen-2));
-	       end
-	 2 :
+	       end // else: !if(eop)
+	 //
+	 // First 32bit sample in a 64bit word.
+	 //
+	 FIRST :
 	   if(strobe)
 	     if(eop)
 	       begin
-		  instate <= 0;
+		  instate <= START;
 		  numsamps <= 0;
 		  nearly_eop <= 0;
 	       end
 	     else
 	       begin
-		  instate <= 1;
+		  instate <= SECOND;
 		  numsamps <= numsamps + 1;
 		  nearly_eop <= (numsamps >= (maxlen-2));
 	       end
@@ -115,7 +129,7 @@ module new_rx_framer
      if(strobe && run)
        begin
 	  holding <= sample;
-	  if(instate == 0)
+	  if(instate == START)
 	    hold_time <= vita_time;
        end
 
@@ -140,12 +154,12 @@ module new_rx_framer
  
    wire 	  eop = eob | nearly_eop | full;
    
-   wire [63:0] 	  sample_tdata = instate == 1 ? {holding, sample} : {sample, 32'h0};
+   wire [63:0] 	  sample_tdata = (instate == SECOND) ? {holding, sample} : {sample, 32'h0};
    wire 	  sample_tlast = eop;
-   wire 	  sample_tvalid = run & strobe & ( (instate == 1) | eop );
+   wire 	  sample_tvalid = run & strobe & ( (instate == SECOND) | eop );
    wire 	  sample_tready;
    
-   wire [80:0] 	  hdr_tdata = {eob,len[13:0],2'b0,(instate == 0) ? vita_time : hold_time};
+   wire [80:0] 	  hdr_tdata = {eob,len[13:0],2'b0,(instate == START) ? vita_time : hold_time};
    wire 	  hdr_tvalid = sample_tlast && sample_tvalid && sample_tready;
    wire 	  hdr_tready;
 
@@ -222,6 +236,22 @@ module new_rx_framer
     assign debug[19:16] =  {1'b0, o_tlast_int, o_tvalid_int, o_tready_int};
  -----/\----- EXCLUDED -----/\----- */
   
+   assign debug = {
+		   sample_tlast, //15
+		   sample_tvalid,//14
+		   sample_tready,//13
+		   dfifo_tvalid, //12
+		   dfifo_tready, //11
+		   hdr_tvalid,   //10
+		   hdr_tready,   //9
+		   hfifo_tvalid, //8
+		   hfifo_tready, //7
+		   eob,           //6
+		   nearly_eop,    //5
+		   full,          //4
+		   outstate[1:0], //3:2
+		   instate[1:0]   //1:0
+		   };
    
 
 endmodule // new_rx_framer
diff --git a/fpga/usrp3/lib/vita/trigger_context_pkt.v b/fpga/usrp3/lib/vita/trigger_context_pkt.v
index 7ce553f19..b67fa4313 100644
--- a/fpga/usrp3/lib/vita/trigger_context_pkt.v
+++ b/fpga/usrp3/lib/vita/trigger_context_pkt.v
@@ -1,19 +1,7 @@
 //
 // Copyright 2011 Ettus Research LLC
 //
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
+