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authorBen Hilburn <ben.hilburn@ettus.com>2014-07-22 15:52:30 -0700
committerBen Hilburn <ben.hilburn@ettus.com>2014-07-22 15:52:30 -0700
commit5a5c5b59608403eb7cd6a72ab7814a368f6c360b (patch)
tree864b24d0874fc4eb144bd8015c29eb4520b4b554 /fpga/usrp3/lib/timing/pps.v
parentfe9db33c9833e485c31b48ad8808ad4419c5138f (diff)
parentb63507efb3cf1a8fa20794c452d57028e18da182 (diff)
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Merge branch 'maint'
Diffstat (limited to 'fpga/usrp3/lib/timing/pps.v')
-rw-r--r--fpga/usrp3/lib/timing/pps.v22
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diff --git a/fpga/usrp3/lib/timing/pps.v b/fpga/usrp3/lib/timing/pps.v
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+//
+// Copyright 2014 Ettus Research LLC
+//
+
+module pps_generator
+ #(parameter CLK_FREQ=0, DUTY=25)
+ (input clk, input reset, output pps);
+
+ reg[31:0] count;
+
+ always @(posedge clk) begin
+ if (reset) begin
+ count <= 32'b1;
+ end else if (count >= CLK_FREQ) begin
+ count <= 32'b1;
+ end else begin
+ count <= count + 1'b1;
+ end
+ end
+
+ assign pps = (count < CLK_FREQ * DUTY / 100);
+endmodule //pps_generator