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authorAndrew Moch <Andrew.Moch@ni.com>2020-03-19 19:55:53 +0100
committerWade Fife <wade.fife@ettus.com>2020-03-23 08:23:51 -0500
commit5c7237fb407cfccaee205980d97e40ce10768c2a (patch)
treedbdba3dcefff2d3cdeab27fa371c203b3398aa81 /fpga/usrp3/lib/sim
parentb721621237c0cd4150e9310cf443d4fb3a735388 (diff)
downloaduhd-5c7237fb407cfccaee205980d97e40ce10768c2a.tar.gz
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fpga: Fix errors found by linting with vsim
Diffstat (limited to 'fpga/usrp3/lib/sim')
-rw-r--r--fpga/usrp3/lib/sim/arm_deframer/Makefile1
-rw-r--r--fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv4
-rw-r--r--fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv6
-rw-r--r--fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv21
4 files changed, 16 insertions, 16 deletions
diff --git a/fpga/usrp3/lib/sim/arm_deframer/Makefile b/fpga/usrp3/lib/sim/arm_deframer/Makefile
index eb7231d5e..3075cf3cc 100644
--- a/fpga/usrp3/lib/sim/arm_deframer/Makefile
+++ b/fpga/usrp3/lib/sim/arm_deframer/Makefile
@@ -33,6 +33,7 @@ SIM_TOP = arm_deframer_tb
SIM_SRCS = $(abspath \
$(SIM_PROTORFNOC_SRCS) \
+$(RFNOC_SRCS) \
arm_deframer_tb.sv \
)
diff --git a/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv b/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv
index 0b1f4414c..7b1310e9c 100644
--- a/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv
+++ b/fpga/usrp3/lib/sim/axi/axis_width_conv/axis_width_conv_tb.sv
@@ -172,7 +172,7 @@ module axis_width_conv_tb();
// - words: The size of the packet in words
// - inst: The instance number of the module to send to
// - gaps: If 1 then insert bubble cycles randomly in the stream
- task push_test_pkt(input integer words, input integer inst, input logic gaps);
+ task automatic push_test_pkt(input integer words, input integer inst, input logic gaps);
begin
logic [(MAX_IN_WORDS*WORD_W)-1:0] data = 0;
logic [MAX_IN_WORDS-1:0] keep = 0;
@@ -217,7 +217,7 @@ module axis_width_conv_tb();
// - inst: The instance number of the module to send to
// - gaps: If 1 then insert bubble cycles randomly in the stream
// - ok: If 1 then all sanity checks have passed
- task pull_test_pkt(input integer words, input integer inst, input logic gaps, output logic ok);
+ task automatic pull_test_pkt(input integer words, input integer inst, input logic gaps, output logic ok);
begin
logic [(MAX_OUT_WORDS*WORD_W)-1:0] pull_data = 0;
logic [MAX_OUT_WORDS-1:0] pull_keep = 0;
diff --git a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
index 53aae3719..e47145088 100644
--- a/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
+++ b/fpga/usrp3/lib/sim/io_cap_gen/cap_pattern_verifier/cap_pattern_verifier_tb.sv
@@ -36,8 +36,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0000),
.RAMP_STOP(14'h3FFF),
- .RAMP_INCR(14'h0001),
- .NTH_CYCLE(1)
+ .RAMP_INCR(14'h0001)
) dut0 (
.clk(clk),
.rst(rst),
@@ -54,8 +53,7 @@ module cap_pattern_verifier_tb();
.PATTERN("RAMP"),
.RAMP_START(14'h0100),
.RAMP_STOP(14'h0FFF),
- .RAMP_INCR(14'h0001),
- .NTH_CYCLE(1)
+ .RAMP_INCR(14'h0001)
) dut1 (
.clk(clk),
.rst(rst),
diff --git a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
index 38664c20f..f209820df 100644
--- a/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
+++ b/fpga/usrp3/lib/sim/packet_proc/chdr_dechunker/chdr_dechunker_tb.sv
@@ -29,7 +29,17 @@ module chdr_dechunker_tb();
reg [31:0] o_xfer_count = 0, i_xfer_count = 0;
reg [63:0] o_last_tdata = 0;
-
+ reg [63:0] i_tdata;
+ reg i_tlast;
+ reg i_tvalid;
+ wire i_tready;
+
+ wire [63:0] o_tdata;
+ wire o_tlast, o_tvalid, o_tready;
+
+ reg result;
+
+
always #10 clk = ~clk;
initial $dumpfile("chdr_dechunker_tb.vcd");
@@ -106,15 +116,6 @@ module chdr_dechunker_tb();
#100 reset = 0;
end
- reg [63:0] i_tdata;
- reg i_tlast;
- reg i_tvalid;
- wire i_tready;
-
- wire [63:0] o_tdata;
- wire o_tlast, o_tvalid, o_tready;
-
- reg result;
initial begin
quantum <= 8;
i_tvalid <= 0;