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| author | Jesse Zhang <65556515+jessezhang-ni@users.noreply.github.com> | 2020-07-24 00:08:18 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-07-30 12:50:30 -0500 |
| commit | 8db024d43bbb7cd05f5b18dd3d7cec09cac6ec4b (patch) | |
| tree | eddf1deb08c700e58996b6ea84fd77948caf0d8c /fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/Makefile | |
| parent | 25a0e462ddc8ca737415dbae4feb90787e6a35b2 (diff) | |
| download | uhd-8db024d43bbb7cd05f5b18dd3d7cec09cac6ec4b.tar.gz uhd-8db024d43bbb7cd05f5b18dd3d7cec09cac6ec4b.tar.bz2 uhd-8db024d43bbb7cd05f5b18dd3d7cec09cac6ec4b.zip | |
fpga: Add Switchboard RFNoC block
Diffstat (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/Makefile')
| -rw-r--r-- | fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/Makefile | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/Makefile b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/Makefile new file mode 100644 index 000000000..7615450b6 --- /dev/null +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_switchboard/Makefile @@ -0,0 +1,44 @@ +# +# Copyright 2020 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +#------------------------------------------------- +# Top-of-Makefile +#------------------------------------------------- +# Define BASE_DIR to point to the "top" dir. +BASE_DIR = $(abspath ../../../../top) +# Include viv_sim_preample after defining BASE_DIR +include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak + +#------------------------------------------------- +# Design Specific +#------------------------------------------------- +# Include makefiles and sources for the DUT and its +# dependencies. +include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs +include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs +include Makefile.srcs + +DESIGN_SRCS += $(abspath \ +$(RFNOC_CORE_SRCS) \ +$(RFNOC_UTIL_SRCS) \ +$(RFNOC_OOT_SRCS) \ +) + +#------------------------------------------------- +# Testbench Specific +#------------------------------------------------- +SIM_TOP = rfnoc_block_switchboard_all_tb +SIM_SRCS = \ +$(abspath rfnoc_block_switchboard_tb.sv) \ +$(abspath rfnoc_block_switchboard_all_tb.sv) \ + +#------------------------------------------------- +# Bottom-of-Makefile +#------------------------------------------------- +# Include all simulator specific makefiles here +# Each should define a unique target to simulate +# e.g. xsim, vsim, etc and a common "clean" target +include $(BASE_DIR)/../tools/make/viv_simulator.mak |