fpga: lib: Update round_sd to eliminate X from simulation

The asynchronous feedback loop on the err signal causes X to get stuck
on the sum signal when simulating. This change adds a check for
simulation only to force X to 0 so that unknown inputs get resolved
once the inputs are known.

Also added default values to the ports out and strobe_out, since having
them uninitialized and without reset was causing simulation issues in
other modules. The FPGA will initialize them to 0, so this change makes
the code equivalent to real hardware behavior.

1 files changed, 45 insertions, 14 deletions

diff --git a/fpga/usrp3/lib/dsp/round_sd.v b/fpga/usrp3/lib/dsp/round_sd.v
index 37aef53f0..a265141e6 100644
--- a/fpga/usrp3/lib/dsp/round_sd.v
+++ b/fpga/usrp3/lib/dsp/round_sd.v
@@ -1,33 +1,64 @@
 //
-// Copyright 2016 Ettus Research
-// Copyright 2018 Ettus Research, a National Instruments Company
+// Copyright 2021 Ettus Research, a National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 
 module round_sd #(
-  parameter WIDTH_IN=18,
-  parameter WIDTH_OUT=16,
-  parameter DISABLE_SD=0
-)(
-  input clk, input reset,
-  input [WIDTH_IN-1:0] in, input strobe_in,
-  output reg [WIDTH_OUT-1:0] out, output reg strobe_out
+  parameter WIDTH_IN   = 18,
+  parameter WIDTH_OUT  = 16,
+  parameter DISABLE_SD = 0
+) (
+  input                      clk,
+  input                      reset,
+  input      [ WIDTH_IN-1:0] in,
+  input                      strobe_in,
+  output reg [WIDTH_OUT-1:0] out         = 0,
+  output reg                 strobe_out  = 0
 );
 
   localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
 
   wire [ERR_WIDTH-1:0] err;
-  wire [WIDTH_IN-1:0]  err_ext, sum;
+  wire [WIDTH_IN-1:0]  err_ext, err_ext_01, sum;
   wire [WIDTH_OUT-1:0] out_pre;
   wire                 strobe_pre;
 
-  sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
+  sign_extend #(
+    .bits_in  (ERR_WIDTH),
+    .bits_out (WIDTH_IN)
+  ) ext_err (
+    .in  (err),
+    .out (err_ext)
+  );
 
-  add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg (
-    .clk(clk), .rst(reset), .in1(in), .in2((DISABLE_SD == 0) ? err_ext : {WIDTH_IN{1'b0}}), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_pre));
+  assign err_ext_01 =
+    //synthesis translate_off
+    // Disallow X from getting stuck on the err_ext feedback path in simulation
+    (^err_ext === 1'bX) ? 0 :
+    //synthesis translate_on
+    err_ext;
 
-  round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out_pre), .err(err));
+  add2_and_clip_reg #(
+    .WIDTH (WIDTH_IN)
+  ) add2_and_clip_reg (
+    .clk        (clk),
+    .rst        (reset),
+    .in1        (in),
+    .in2        ((DISABLE_SD == 0) ? err_ext_01 : {WIDTH_IN{1'b0}}),
+    .strobe_in  (strobe_in),
+    .sum        (sum),
+    .strobe_out (strobe_pre)
+  );
+
+  round #(
+    .bits_in  (WIDTH_IN),
+    .bits_out (WIDTH_OUT)
+  ) round_sum (
+    .in  (sum),
+    .out (out_pre),
+    .err (err)
+  );
 
   always @(posedge clk) begin
     if (reset) begin