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| author | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-10-07 11:25:20 +0200 |
| commit | fd3e84941de463fa1a7ebab0a69515b4bf2614cd (patch) | |
| tree | 3fa721a13d41d2c0451d663a59a220a38fd5e614 /fpga/usrp3/lib/dsp/srl.v | |
| parent | 3b66804e41891e358c790b453a7a59ec7462dba4 (diff) | |
| download | uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.gz uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.tar.bz2 uhd-fd3e84941de463fa1a7ebab0a69515b4bf2614cd.zip | |
Removed copy of FPGA source files.
Diffstat (limited to 'fpga/usrp3/lib/dsp/srl.v')
| -rw-r--r-- | fpga/usrp3/lib/dsp/srl.v | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/fpga/usrp3/lib/dsp/srl.v b/fpga/usrp3/lib/dsp/srl.v deleted file mode 100644 index bbd8ac1c9..000000000 --- a/fpga/usrp3/lib/dsp/srl.v +++ /dev/null @@ -1,27 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// - - - -module srl - #(parameter WIDTH=18) - (input clk, - input rst, - input write, - input [WIDTH-1:0] in, - input [3:0] addr, - output [WIDTH-1:0] out); - - genvar i; - generate - for (i=0;i<WIDTH;i=i+1) - begin : gen_srl - SRL16E - srl16e(.Q(out[i]), - .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]), - .CE(write|rst),.CLK(clk),.D(in[i])); - end - endgenerate - -endmodule // srl |