Pushing the bulk of UHD-3.7.0 code.

1 files changed, 18 insertions, 22 deletions

diff --git a/fpga/usrp3/lib/dsp/rx_frontend.v b/fpga/usrp3/lib/dsp/rx_frontend.v
index ebe19240c..e34a2954b 100644
--- a/fpga/usrp3/lib/dsp/rx_frontend.v
+++ b/fpga/usrp3/lib/dsp/rx_frontend.v
@@ -14,8 +14,9 @@ module rx_frontend
     );
    
    reg [15:0] 	  adc_i, adc_q;
-   wire [17:0] 	  adc_i_ofs, adc_q_ofs;
-   wire [35:0] 	  corr_i, corr_q; wire [17:0] 	  mag_corr,phase_corr;
+   wire [23:0] 	  adc_i_ofs, adc_q_ofs;
+   wire [35:0] 	  corr_i, corr_q; 
+   wire [17:0] 	  mag_corr,phase_corr;
    wire 	  swap_iq;
    
    setting_reg #(.my_addr(BASE), .width(1)) sr_8
@@ -36,43 +37,38 @@ module rx_frontend
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_corr),.changed());
 
+   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_i,8'b00}),.out(adc_i_ofs));
+   
+   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .in({adc_q,8'b00}),.out(adc_q_ofs));
+   
    generate
       if(IQCOMP_EN == 1)
 	begin
-	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_i,2'b00}),.out(adc_i_ofs));
-	   
-	   rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_q,2'b00}),.out(adc_q_ofs));
-	   
 	   MULT18X18S mult_mag_corr
-	     (.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
+	     (.P(corr_i), .A(adc_i_ofs[23:6]), .B(mag_corr), .C(clk), .CE(1), .R(rst) ); 
 	   
 	   MULT18X18S mult_phase_corr
-	     (.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
+	     (.P(corr_q), .A(adc_i_ofs[23:6]), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
 	   
 	   add2_and_clip_reg #(.WIDTH(24)) add_clip_i
 	     (.clk(clk), .rst(rst), 
-	      .in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1),
+	      .in1(adc_i_ofs), .in2(corr_i[35:12]), .strobe_in(1'b1),
 	      .sum(i_out), .strobe_out());
 	   
 	   add2_and_clip_reg #(.WIDTH(24)) add_clip_q
 	     (.clk(clk), .rst(rst), 
-	      .in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1),
+	      .in1(adc_q_ofs), .in2(corr_q[35:12]), .strobe_in(1'b1),
 	      .sum(q_out), .strobe_out());
 	end // if (IQCOMP_EN == 1)
       else
 	begin
-	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_i,8'b00}),.out(i_out));
-	   
-	   rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
-	     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	      .in({adc_q,8'b00}),.out(q_out));
+	   assign i_out = adc_i_ofs;
+	   assign q_out = adc_q_ofs;
 	end // else: !if(IQCOMP_EN == 1)
-      endgenerate
+   endgenerate
    
 endmodule // rx_frontend