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| author | Max Köhler <max.koehler@ni.com> | 2020-06-15 13:14:02 +0200 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-06-15 13:54:35 -0500 |
| commit | f17a5113e228ac1bc5312193eb8f687e127184a3 (patch) | |
| tree | b0e223a7bd8e9b5a207b060aeaf60c9e74390997 /fpga/usrp3/lib/control/Makefile.srcs | |
| parent | 06452806dcbb9721078e5951ffba13e5cb71ec86 (diff) | |
| download | uhd-f17a5113e228ac1bc5312193eb8f687e127184a3.tar.gz uhd-f17a5113e228ac1bc5312193eb8f687e127184a3.tar.bz2 uhd-f17a5113e228ac1bc5312193eb8f687e127184a3.zip | |
fpga: tools: remove temporary Xilinx directories for BD recreation
During recreation of block diagrams any RTL modules will be kept in
hidden directories within the build directory. Updates of the RTL
sources might not be taken into account. Solution is to remove Xilinx's
hidden project directories before calling vivado.
Diffstat (limited to 'fpga/usrp3/lib/control/Makefile.srcs')
0 files changed, 0 insertions, 0 deletions