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| author | Wade Fife <wade.fife@ettus.com> | 2021-04-16 15:02:24 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-06-03 11:26:54 -0500 |
| commit | da46dddbebab2ddb1f25f2f200431c2299b395f4 (patch) | |
| tree | 9144092aa8dc2474926a8900e32d18f5eb61a6d4 /fpga/usrp3/lib/axi4s_sv | |
| parent | f9c97371048bfc69182187e6d8904a01efbe6d79 (diff) | |
| download | uhd-da46dddbebab2ddb1f25f2f200431c2299b395f4.tar.gz uhd-da46dddbebab2ddb1f25f2f200431c2299b395f4.tar.bz2 uhd-da46dddbebab2ddb1f25f2f200431c2299b395f4.zip | |
fpga: lib: Add modports to SV AXI-Stream blocks
Diffstat (limited to 'fpga/usrp3/lib/axi4s_sv')
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv | 4 | ||||
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv | 4 | ||||
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv | 4 | ||||
| -rw-r--r-- | fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv index 398942210..57124a0b5 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_add_bytes.sv @@ -29,8 +29,8 @@ module axi4s_add_bytes #( int ADD_BYTES = 6, bit SYNC = 1 ) ( - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o // AxiStreamIf or AxiStreamPacketIf ); localparam BYTES_PER_WORD = i.DATA_WIDTH/8; diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv index 647e1dc1c..c3c71999d 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_fifo.sv @@ -16,8 +16,8 @@ module axi4s_fifo #( ) ( // Clock domain: i.clk (o.clk is unused) input logic clear=1'b0, - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o, // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o, // AxiStreamIf or AxiStreamPacketIf output logic [15:0] space, output logic [15:0] occupied ); diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv index 4321d87d4..382cdb13b 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv @@ -35,8 +35,8 @@ module axi4s_remove_bytes #( REM_START=0, REM_END=8 )( - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o // AxiStreamIf or AxiStreamPacketIf ); localparam BYTES_PER_WORD = i.DATA_WIDTH/8; diff --git a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv index f05f70438..0660ee961 100644 --- a/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv +++ b/fpga/usrp3/lib/axi4s_sv/axi4s_width_conv.sv @@ -25,8 +25,8 @@ module axi4s_width_conv #( bit O_USER_TRAILING_BYTES = 0, bit SYNC_CLKS = 1 ) ( - interface i, // AxiStreamIf or AxiStreamPacketIf - interface o // AxiStreamIf or AxiStreamPacketIf + interface.slave i, // AxiStreamIf or AxiStreamPacketIf + interface.master o // AxiStreamIf or AxiStreamPacketIf ); localparam IWIDTH =i.DATA_WIDTH; |