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| author | Wade Fife <wade.fife@ettus.com> | 2020-07-02 13:50:23 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-07-20 15:33:22 -0500 |
| commit | e962cc4a5e51e2326eb656ee2a779ea26774687b (patch) | |
| tree | 48a02d613160a7d3a84d6dea351ae1c4be7d5c4a /fpga/usrp3/lib/axi4lite_sv | |
| parent | dc32aa5cd4fb174ee3c616f854f499a53137aa75 (diff) | |
| download | uhd-e962cc4a5e51e2326eb656ee2a779ea26774687b.tar.gz uhd-e962cc4a5e51e2326eb656ee2a779ea26774687b.tar.bz2 uhd-e962cc4a5e51e2326eb656ee2a779ea26774687b.zip | |
fpga: rfnoc: Fix testbenches to run under ModelSim
This updates the makefiles for the testbenches so they can be run using
"make modelsim" without any additional hacks. The "xsim" and "vsim"
simulation targets also still work.
Diffstat (limited to 'fpga/usrp3/lib/axi4lite_sv')
0 files changed, 0 insertions, 0 deletions