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| author | Wade Fife <wade.fife@ettus.com> | 2022-02-07 14:18:06 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2022-02-10 19:46:39 -0700 |
| commit | 6936a9ac664cbc312fd17a5ebab9b40069615f7a (patch) | |
| tree | c1375221ca842698627a93056bb038f00b0f14a6 /fpga/usrp3/build.py | |
| parent | 4ea32ae32de0cc3e5b04b5203806bc6604f3d493 (diff) | |
| download | uhd-6936a9ac664cbc312fd17a5ebab9b40069615f7a.tar.gz uhd-6936a9ac664cbc312fd17a5ebab9b40069615f7a.tar.bz2 uhd-6936a9ac664cbc312fd17a5ebab9b40069615f7a.zip | |
fpga: rfnoc: Change AWIDTH default for axi_ram_fifo
Change AWIDTH to be the same as MEM_ADDR_W by default. Current USRPs
assume the AXI address width is the same as MEM_ADDR_W.
Diffstat (limited to 'fpga/usrp3/build.py')
0 files changed, 0 insertions, 0 deletions