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authorJosh Blum <josh@joshknows.com>2012-04-02 18:36:11 -0700
committerJosh Blum <josh@joshknows.com>2012-04-02 18:36:11 -0700
commit5918cec1b9d394f0a63dfe04b2c82df97333f1d1 (patch)
tree83be0bf1e788890e1995ae4d6c326819a295f7e9 /fpga/usrp2
parent2cd44069945ff14f59a5b48439d46dac0dfb4035 (diff)
parent4c111800a139a544f9280e1a7b114c027c55a89e (diff)
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Merge branch 'fpga_maint' into maint
Diffstat (limited to 'fpga/usrp2')
-rw-r--r--fpga/usrp2/gpif/slave_fifo.v8
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v2
2 files changed, 5 insertions, 5 deletions
diff --git a/fpga/usrp2/gpif/slave_fifo.v b/fpga/usrp2/gpif/slave_fifo.v
index b1d642fca..e75f28913 100644
--- a/fpga/usrp2/gpif/slave_fifo.v
+++ b/fpga/usrp2/gpif/slave_fifo.v
@@ -150,7 +150,7 @@ module slave_fifo
STATE_DATA_RX:
begin
- if(data_rx_src_rdy && data_rx_dst_rdy && (transfer_count != data_transfer_size))
+ if(data_rx_src_rdy && data_rx_dst_rdy)
transfer_count <= transfer_count + 1;
else
state <= STATE_IDLE;
@@ -170,7 +170,7 @@ module slave_fifo
STATE_DATA_TX:
begin
- if(data_tx_dst_rdy && data_tx_src_rdy && (transfer_count != data_transfer_size))
+ if(data_tx_dst_rdy && data_tx_src_rdy)
transfer_count <= transfer_count + 1;
else
state <= STATE_IDLE;
@@ -197,8 +197,8 @@ module slave_fifo
// fifo signal assignments and enables
//enable fifos
- assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF;
- assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE;
+ assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF && (transfer_count != data_transfer_size);
+ assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE && (transfer_count != data_transfer_size);
assign ctrl_rx_dst_rdy = (state == STATE_CTRL_RX) && ~FX2_CF;
assign ctrl_tx_src_rdy = (state == STATE_CTRL_TX) && ~FX2_CE;
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 26714b669..09b7e11f1 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -413,7 +413,7 @@ module u1plus_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd9, 16'd1}; //major, minor
+ localparam compat_num = {16'd9, 16'd2}; //major, minor
wire [31:0] reg_test32;