moved usrp1 and usrp2 fpga dirs into fpga subdirectory

653 files changed, 1558782 insertions, 0 deletions

diff --git a/fpga/usrp2/boot_cpld/.gitignore b/fpga/usrp2/boot_cpld/.gitignore
new file mode 100644
index 000000000..45cf9a86b
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/.gitignore
@@ -0,0 +1,38 @@
+/*_xdb
+/*.restore
+/*.xrpt
+/*.zip
+/xst
+/_ngo
+/_xmsgs
+/*.log
+/*.stx
+/*.tspec
+/*.xml
+/*.gyd
+/*.ngr
+/*.tim
+/*.err
+/*.lso
+/*.bld
+/*.cmd_log
+/*.ise_ISE_Backup
+/*.ipf_ISE_Backup
+/*.mfd
+/*.vm6
+/*.syr
+/*.xst
+/*.csv
+/*.html
+/*.jed
+/*.pad
+/*.ng*
+/*.pnx
+/*.rpt
+/*.prj
+/*_html
+/*.cel
+/_pace.ucf
+/*.lock
+/*.tfi
+/templates
diff --git a/fpga/usrp2/boot_cpld/_impact.cmd b/fpga/usrp2/boot_cpld/_impact.cmd
new file mode 100755
index 000000000..4af86cb02
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/_impact.cmd
@@ -0,0 +1,34 @@
+loadProjectFile -file "C:\cygwin\home\matt\usrp2\fpga\boot_cpld/boot_cpld.ipf"

+setMode -ss

+setMode -sm

+setMode -hw140

+setMode -spi

+setMode -acecf

+setMode -acempm

+setMode -pff

+setMode -bs

+setMode -bs

+setMode -bs

+setMode -bs

+setCable -port auto

+Identify 

+identifyMPM 

+assignFile -p 1 -file "C:/cygwin/home/matt/usrp2/fpga/boot_cpld/boot_cpld.jed"

+Program -p 1 -e -v -defaultVersion 0 

+Program -p 1 -e -v -defaultVersion 0 

+Program -p 1 -e -v -defaultVersion 0 

+Program -p 1 -e -v -defaultVersion 0 

+Program -p 1 -e -v -defaultVersion 0 

+Program -p 1 -e -v -defaultVersion 0 

+Identify 

+identifyMPM 

+Identify 

+identifyMPM 

+Identify 

+identifyMPM 

+Identify 

+identifyMPM 

+Identify 

+identifyMPM 

+setMode -bs

+deleteDevice -position 1

diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ipf b/fpga/usrp2/boot_cpld/boot_cpld.ipf
new file mode 100755
index 000000000..8acb6821e
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.ipf
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ise b/fpga/usrp2/boot_cpld/boot_cpld.ise
new file mode 100755
index 000000000..7252d3768
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.ise
diff --git a/fpga/usrp2/boot_cpld/boot_cpld.lfp b/fpga/usrp2/boot_cpld/boot_cpld.lfp
new file mode 100755
index 000000000..0f0c8f2e2
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.lfp
@@ -0,0 +1,5 @@
+# begin LFP file C:\cygwin\home\matt\u2f\boot_cpld\boot_cpld.lfp

+designfile boot_cpld.v

+parttype xc9572xl-vq44-10

+bus_delimiter 0;

+set_busdelim_onsave 1;

diff --git a/fpga/usrp2/boot_cpld/boot_cpld.ucf b/fpga/usrp2/boot_cpld/boot_cpld.ucf
new file mode 100755
index 000000000..789bb1d96
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.ucf
@@ -0,0 +1,34 @@
+NET "CLK_25MHZ"  LOC = "P5"  ; 

+NET "CLK_25MHZ_EN"  LOC = "P6"  ; 

+NET "LED<0>"  LOC = "P12"  ; 

+NET "LED<1>"  LOC = "P8"  ; 

+NET "LED<2>"  LOC = "P7"  ; 

+NET "DEBUG<0>"  LOC = "P1"  ; 

+NET "DEBUG<1>"  LOC = "P2"  ; 

+NET "DEBUG<2>"  LOC = "P3"  ; 

+NET "DEBUG<3>"  LOC = "P29"  ; 

+NET "DEBUG<4>"  LOC = "P30"  ; 

+NET "DEBUG<5>"  LOC = "P31"  ; 

+NET "DEBUG<6>"  LOC = "P32"  ; 

+NET "DEBUG<7>"  LOC = "P33"  ; 

+NET "DEBUG<8>"  LOC = "P34"  ; 

+NET "POR"  LOC = "P42"  ; 

+NET "SD_nCS"  LOC = "P20"  ; 

+NET "SD_Din"  LOC = "P21"  ; 

+NET "SD_CLK"  LOC = "P22"  ; 

+NET "SD_Dout"  LOC = "P23"  ; 

+NET "SD_DAT1"  LOC = "P27"  ; 

+NET "SD_DAT2"  LOC = "P28"  ; 

+NET "SD_prot"  LOC = "P19"  ;

+NET "SD_det"  LOC = "P36"  ;

+NET "CFG_INIT_B"  LOC = "P38"  ; 

+NET "CFG_Din"  LOC = "P37"  ; 

+NET "CFG_CCLK"  LOC = "P41"  ; 

+NET "CFG_DONE"  LOC = "P40"  ; 

+NET "CFG_PROG_B"  LOC = "P39"  ; 

+NET "CPLD_CLK"  LOC = "P13"  ; 

+NET "START"  LOC = "P14"  ;

+NET "MODE"  LOC = "P18"  ;

+NET "DONE"  LOC = "P16"  ;

+NET "detached"  LOC = "P43"  ;

+NET "CPLD_misc"  LOC = "P44"  ;

diff --git a/fpga/usrp2/boot_cpld/boot_cpld.v b/fpga/usrp2/boot_cpld/boot_cpld.v
new file mode 100755
index 000000000..2ffc6daed
--- /dev/null
+++ b/fpga/usrp2/boot_cpld/boot_cpld.v
@@ -0,0 +1,95 @@
+`timescale 1ns / 1ps
+// ////////////////////////////////////////////////////////////////////////////////
+// Boot CPLD design, only for u2_rev2
+// ////////////////////////////////////////////////////////////////////////////////
+
+module boot_cpld
+  (input CLK_25MHZ,
+   output CLK_25MHZ_EN,
+   output [2:0] LED,
+   output [8:0] DEBUG,
+   input 	 POR,
+   
+   // To SD Card
+   output 	 SD_nCS,
+   output 	 SD_Din,
+   output 	 SD_CLK,
+   input 	 SD_Dout,
+   input 	 SD_DAT1,  // Unused
+   input 	 SD_DAT2,  // Unused
+   input         SD_prot,  // Write Protect
+   input         SD_det,   // Card Detect
+   
+   // To FPGA Config Interface
+   input 	 CFG_INIT_B,
+   output 	 CFG_Din,     // Also used in Data interface
+   output 	 CFG_CCLK,
+   input 	 CFG_DONE,
+   output 	 CFG_PROG_B,
+   
+   // To FPGA data interface
+   output 	 CPLD_CLK,
+   input 	 START,
+   input 	 MODE,
+   input 	 DONE,
+   output 	 detached,
+   input         CPLD_misc   // Unused for now
+   );
+   
+   assign 	 CLK_25MHZ_EN = 1'b1;
+   
+   assign 	 LED[0] = ~CFG_DONE;
+   assign 	 LED[1] = CFG_INIT_B;
+   assign 	 LED[2] = ~CFG_PROG_B;
+   			
+   wire 	 en_outs;
+   wire [3:0] 	 set_sel = 4'd0;
+   
+   assign 	 CPLD_CLK = CFG_CCLK;
+   assign 	 DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout, 
+				START, MODE, DONE, CPLD_misc};
+
+   // Handle cutover to FPGA control of SD
+   wire 	 fpga_takeover = ~CPLD_misc;
+   wire 	 SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int;
+
+   assign 	 SD_CLK = fpga_takeover ? START : SD_CLK_int;
+   assign 	 SD_nCS = fpga_takeover ? MODE : SD_nCS_int;
+   assign 	 SD_Din = fpga_takeover ? DONE : SD_Din_int;
+   assign 	 CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int;
+
+   spi_boot #(.width_set_sel_g(4),  // How many sets (16)
+	      .width_bit_cnt_g(6),  // Block length (12 is faster, 6 is minimum)
+	      .width_img_cnt_g(2),  // How many images per set
+	      .num_bits_per_img_g(20), // Image size, 20 = 1MB
+	      .sd_init_g(1),           // SD-specific initialization
+	      .mmc_compat_clk_div_g(0),// No MMC support
+	      .width_mmc_clk_div_g(0), // No MMC support
+	      .reset_level_g(0))       // Active low reset
+     
+     spi_boot(.clk_i(CLK_25MHZ), 
+	      .reset_i(POR),
+	      
+	      // To SD Card
+	      .spi_clk_o(SD_CLK_int), 
+	      .spi_cs_n_o(SD_nCS_int),
+	      .spi_data_in_i(SD_Dout), 
+	      .spi_data_out_o(SD_Din_int), 
+	      .spi_en_outs_o(en_outs), 
+	      
+	      // Data Port
+	      .start_i(START),
+	      .mode_i(MODE), // 0->conf mode, 1->data mode  
+	      .detached_o(detached), 
+	      .dat_done_i(DONE), 
+	      .set_sel_i(set_sel),
+	      
+	      // To FPGA
+	      .config_n_o(CFG_PROG_B), 
+	      .cfg_init_n_i(CFG_INIT_B), 
+	      .cfg_done_i(CFG_DONE), 
+	      .cfg_clk_o(CFG_CCLK), 
+	      .cfg_dat_o(CFG_Din_int)
+	      );
+   
+endmodule // boot_cpld
diff --git a/fpga/usrp2/control_lib/.gitignore b/fpga/usrp2/control_lib/.gitignore
new file mode 100644
index 000000000..025385cff
--- /dev/null
+++ b/fpga/usrp2/control_lib/.gitignore
@@ -0,0 +1,5 @@
+/a.out
+/*.vcd
+/*.lxt
+/*.sav
+/*.log
diff --git a/fpga/usrp2/control_lib/CRC16_D16.v b/fpga/usrp2/control_lib/CRC16_D16.v
new file mode 100644
index 000000000..7e2816af1
--- /dev/null
+++ b/fpga/usrp2/control_lib/CRC16_D16.v
@@ -0,0 +1,89 @@
+///////////////////////////////////////////////////////////////////////
+// File:  CRC16_D16.v                             
+// Date:  Sun Jun 17 06:42:55 2007                                                      
+//                                                                     
+// Copyright (C) 1999-2003 Easics NV.                 
+// This source file may be used and distributed without restriction    
+// provided that this copyright statement is not removed from the file 
+// and that any derivative work contains the original copyright notice
+// and the associated disclaimer.
+//
+// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
+// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+//
+// Purpose: Verilog module containing a synthesizable CRC function
+//   * polynomial: (0 5 12 16)
+//   * data width: 16
+//                                                                     
+// Info: tools@easics.be
+//       http://www.easics.com                                  
+///////////////////////////////////////////////////////////////////////
+
+
+module CRC16_D16
+  (input [15:0] Data,
+   input [15:0] CRC,
+   output [15:0] NewCRC);
+
+   assign 	 NewCRC = nextCRC16_D16(Data,CRC);
+   
+  // polynomial: (0 5 12 16)
+  // data width: 16
+  // convention: the first serial data bit is D[15]
+  function [15:0] nextCRC16_D16;
+
+    input [15:0] Data;
+    input [15:0] CRC;
+
+    reg [15:0] D;
+    reg [15:0] C;
+    reg [15:0] NewCRC;
+
+  begin
+
+    D = Data;
+    C = CRC;
+
+    NewCRC[0] = D[12] ^ D[11] ^ D[8] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ 
+                C[8] ^ C[11] ^ C[12];
+    NewCRC[1] = D[13] ^ D[12] ^ D[9] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ 
+                C[9] ^ C[12] ^ C[13];
+    NewCRC[2] = D[14] ^ D[13] ^ D[10] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ 
+                C[10] ^ C[13] ^ C[14];
+    NewCRC[3] = D[15] ^ D[14] ^ D[11] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ 
+                C[11] ^ C[14] ^ C[15];
+    NewCRC[4] = D[15] ^ D[12] ^ D[8] ^ D[4] ^ C[4] ^ C[8] ^ C[12] ^ 
+                C[15];
+    NewCRC[5] = D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[8] ^ D[5] ^ D[4] ^ 
+                D[0] ^ C[0] ^ C[4] ^ C[5] ^ C[8] ^ C[9] ^ C[11] ^ C[12] ^ 
+                C[13];
+    NewCRC[6] = D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[9] ^ D[6] ^ D[5] ^ 
+                D[1] ^ C[1] ^ C[5] ^ C[6] ^ C[9] ^ C[10] ^ C[12] ^ 
+                C[13] ^ C[14];
+    NewCRC[7] = D[15] ^ D[14] ^ D[13] ^ D[11] ^ D[10] ^ D[7] ^ D[6] ^ 
+                D[2] ^ C[2] ^ C[6] ^ C[7] ^ C[10] ^ C[11] ^ C[13] ^ 
+                C[14] ^ C[15];
+    NewCRC[8] = D[15] ^ D[14] ^ D[12] ^ D[11] ^ D[8] ^ D[7] ^ D[3] ^ 
+                C[3] ^ C[7] ^ C[8] ^ C[11] ^ C[12] ^ C[14] ^ C[15];
+    NewCRC[9] = D[15] ^ D[13] ^ D[12] ^ D[9] ^ D[8] ^ D[4] ^ C[4] ^ 
+                C[8] ^ C[9] ^ C[12] ^ C[13] ^ C[15];
+    NewCRC[10] = D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[5] ^ C[5] ^ C[9] ^ 
+                 C[10] ^ C[13] ^ C[14];
+    NewCRC[11] = D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[6] ^ C[6] ^ C[10] ^ 
+                 C[11] ^ C[14] ^ C[15];
+    NewCRC[12] = D[15] ^ D[8] ^ D[7] ^ D[4] ^ D[0] ^ C[0] ^ C[4] ^ C[7] ^ 
+                 C[8] ^ C[15];
+    NewCRC[13] = D[9] ^ D[8] ^ D[5] ^ D[1] ^ C[1] ^ C[5] ^ C[8] ^ C[9];
+    NewCRC[14] = D[10] ^ D[9] ^ D[6] ^ D[2] ^ C[2] ^ C[6] ^ C[9] ^ C[10];
+    NewCRC[15] = D[11] ^ D[10] ^ D[7] ^ D[3] ^ C[3] ^ C[7] ^ C[10] ^ 
+                 C[11];
+
+    nextCRC16_D16 = NewCRC;
+
+  end
+
+  endfunction
+
+endmodule
+
diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v
new file mode 100644
index 000000000..fed2791f9
--- /dev/null
+++ b/fpga/usrp2/control_lib/atr_controller.v
@@ -0,0 +1,57 @@
+
+// Automatic transmit/receive switching of control pins to daughterboards
+// Store everything in registers for now, but could use a RAM for more
+// complex state machines in the future
+
+module atr_controller
+  (input clk_i, input rst_i,
+   input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
+   input we_i, input stb_i, input cyc_i, output reg ack_o,
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
+   
+   reg [3:0] state;
+   reg [31:0] atr_ram [0:15];  // DP distributed RAM
+
+   // WB Interface
+   always @(posedge clk_i)
+     if(we_i & stb_i & cyc_i)
+       begin
+	  if(sel_i[3])
+	    atr_ram[adr_i[5:2]][31:24] <= dat_i[31:24];
+	  if(sel_i[2])
+	    atr_ram[adr_i[5:2]][23:16] <= dat_i[23:16];
+	  if(sel_i[1])
+	    atr_ram[adr_i[5:2]][15:8] <= dat_i[15:8];
+	  if(sel_i[0])
+	    atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
+       end // if (we_i & stb_i & cyc_i)
+
+   always @(posedge clk_i)
+     dat_o <= atr_ram[adr_i[5:2]];
+   
+   always @(posedge clk_i)
+     ack_o <= stb_i & cyc_i & ~ack_o;
+
+   // Control side of DP RAM
+   assign     ctrl_lines = atr_ram[state];
+
+   // Put a more complex state machine with time delays and multiple states here
+   //  if daughterboard requires more complex sequencing
+   localparam ATR_IDLE = 4'd0;
+   localparam ATR_TX = 4'd1;
+   localparam ATR_RX = 4'd2;
+   localparam ATR_FULL_DUPLEX = 4'd3;
+   
+   always @(posedge clk_i)
+     if(rst_i)
+       state <= ATR_IDLE;
+     else
+       case ({run_rx,run_tx})
+	 2'b00 : state <= ATR_IDLE;
+	 2'b01 : state <= ATR_TX;
+	 2'b10 : state <= ATR_RX;
+	 2'b11 : state <= ATR_FULL_DUPLEX;
+       endcase // case({run_rx,run_tx})
+   
+endmodule // atr_controller
diff --git a/fpga/usrp2/control_lib/bin2gray.v b/fpga/usrp2/control_lib/bin2gray.v
new file mode 100644
index 000000000..513402163
--- /dev/null
+++ b/fpga/usrp2/control_lib/bin2gray.v
@@ -0,0 +1,10 @@
+
+
+module bin2gray
+  #(parameter WIDTH=8)
+    (input [WIDTH-1:0] bin,
+     output [WIDTH-1:0] gray);
+
+   assign 		gray = (bin >> 1) ^ bin;
+   
+endmodule // bin2gray
diff --git a/fpga/usrp2/control_lib/bootrom.mem b/fpga/usrp2/control_lib/bootrom.mem
new file mode 100644
index 000000000..d688b4342
--- /dev/null
+++ b/fpga/usrp2/control_lib/bootrom.mem
@@ -0,0 +1,26 @@
+00000C000F03
+101400000000
+    //  SPI: Set Divider to div by 2
+//  Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds
+1018_0000_0001    //  SPI: Choose AD9510
+1010_0000_3418    //  SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word
+1000_0000_0010    //  SPI: AD9510 A:0 D:10  Set up AD9510 SPI
+1010_0000_3518    //  SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word
+ffff_ffff_ffff  // terminate
+#//  First 16 bits are address, last 32 are data
+#//  First 4 bits of address select which slave
+//		 6'd01 : addr_data = {13'h45,8'h00};   // CLK2 drives distribution, everything on
+//		 6'd02 : addr_data = {13'h3D,8'h80};   // Turn on output 1, normal levels
+//		 6'd03 : addr_data = {13'h4B,8'h80};   // Bypass divider 1 (div by 1)
+//		 6'd04 : addr_data = {13'h08,8'h47};   // POS PFD, Dig LK Det, Charge Pump normal	
+//		 6'd05 : addr_data = {13'h09,8'h70};   // Max Charge Pump current
+//		 6'd06 : addr_data = {13'h0A,8'h04};   // Normal operation, Prescalar Div by 2, PLL On
+//		 6'd07 : addr_data = {13'h0B,8'h00};   // RDIV MSB (6 bits)
+//		 6'd08 : addr_data = {13'h0C,8'h01};   // RDIV LSB (8 bits), Div by 1
+//		 6'd09 : addr_data = {13'h0D,8'h00};   // Everything normal, Dig Lock Det
+//		 6'd10 : addr_data = {13'h07,8'h00};	// Disable LOR detect - LOR causes failure...
+//		 6'd11 : addr_data = {13'h04,8'h00};	// A Counter = Don't Care
+//		 6'd12 : addr_data = {13'h05,8'h00};	// B Counter MSB = 0
+//		 6'd13 : addr_data = {13'h06,8'h05};   // B Counter LSB = 5
+ //      default : addr_data = {13'h5A,8'h01}; // Register Update
+// @ 55        // Jump to new address 8'h55
diff --git a/fpga/usrp2/control_lib/clock_bootstrap_rom.v b/fpga/usrp2/control_lib/clock_bootstrap_rom.v
new file mode 100644
index 000000000..46563db65
--- /dev/null
+++ b/fpga/usrp2/control_lib/clock_bootstrap_rom.v
@@ -0,0 +1,34 @@
+
+
+module clock_bootstrap_rom(input [15:0] addr, output [47:0] data);
+
+   reg [47:0] rom [0:15];
+   
+   //initial
+   //  $readmemh("bootrom.mem", rom);
+
+   assign     data = rom[addr];
+
+   initial 
+     begin
+	//  First 16 bits are address, last 32 are data
+	//  First 4 bits of address select which slave
+	rom[0] = 48'h0000_0C00_0F03;  //  Both clk sel choose ext ref (0), both are enabled (1), turn off SERDES, ADCs, turn on leds
+	rom[1] = 48'h1014_0000_0000;  //  SPI: Set Divider to div by 2
+	rom[2] = 48'h1018_0000_0001;  //  SPI: Choose AD9510
+	rom[3] = 48'h1010_0000_3418;  //  SPI: Auto-slave select, interrupt when done, TX_NEG, 24-bit word
+	rom[4] = 48'h1000_0000_0010;  //  SPI: AD9510 A:0 D:10  Set up AD9510 SPI
+	rom[5] = 48'h1010_0000_3518;  //  SPI: SEND IT Auto-slave select, interrupt when done, TX_NEG, 24-bit word
+	rom[6] = 48'hffff_ffff_ffff;  // terminate
+	rom[7] = 48'hffff_ffff_ffff;  // terminate
+	rom[8] = 48'hffff_ffff_ffff;  // terminate
+	rom[9] = 48'hffff_ffff_ffff;  // terminate
+	rom[10] = 48'hffff_ffff_ffff;  // terminate
+	rom[11] = 48'hffff_ffff_ffff;  // terminate
+	rom[12] = 48'hffff_ffff_ffff;  // terminate
+	rom[13] = 48'hffff_ffff_ffff;  // terminate
+	rom[14] = 48'hffff_ffff_ffff;  // terminate
+	rom[15] = 48'hffff_ffff_ffff;  // terminate
+     end // initial begin
+   
+endmodule // clock_bootstrap_rom
diff --git a/fpga/usrp2/control_lib/clock_control.v b/fpga/usrp2/control_lib/clock_control.v
new file mode 100644
index 000000000..1bbe6bd75
--- /dev/null
+++ b/fpga/usrp2/control_lib/clock_control.v
@@ -0,0 +1,115 @@
+
+
+// AD9510 Register Map (from datasheet Rev. A)
+
+/* INSTRUCTION word format (16 bits)
+ * 15       Read = 1, Write = 0
+ * 14:13    W1/W0,  Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream
+ * 12:0     Address
+ */
+
+/* ADDR     Contents             Value (hex)
+ * 00       Serial Config Port   10 (def) -- MSB first, SDI/SDO separate
+ * 04       A Counter
+ * 05-06    B Counter
+ * 07-0A    PLL Control
+ * 0B-0C    R Divider
+ * 0D       PLL Control
+ * 34-3A    Fine Delay
+ * 3C-3F    LVPECL Outs
+ * 40-43    LVDS/CMOS Outs
+ * 45       Clock select, power down
+ * 48-57    Dividers
+ * 58       Func and Sync
+ * 5A       Update regs
+ */
+
+
+module clock_control
+  (input reset,
+   input aux_clk,            // 25MHz, for before fpga clock is active
+   input clk_fpga,           // real 100 MHz FPGA clock
+   output [1:0] clk_en,      // controls source of reference clock
+   output [1:0] clk_sel,     // controls source of reference clock
+   input clk_func,          // FIXME needs to be some kind of out SYNC or reset to 9510
+   input clk_status,         // Monitor PLL or SYNC status
+   
+   output sen,        // Enable for the AD9510
+   output sclk,       // FIXME these need to be shared
+   input sdi,
+   output sdo
+   );
+   
+   wire   read = 1'b0;    // Always write for now
+   wire [1:0] w = 2'b00;  // Always send 1 byte at a time
+   
+   assign     clk_sel = 2'b00;  // Both outputs from External Ref (SMA)
+   assign     clk_en = 2'b11;   // Both outputs enabled
+   
+   reg [20:0] addr_data;
+
+   reg [5:0]  entry;
+   reg 	      start;
+   reg [7:0]  counter;
+   reg [23:0] command;
+   
+   always @*
+     case(entry)
+       6'd00 : addr_data = {13'h00,8'h10};   // Serial setup
+       6'd01 : addr_data = {13'h45,8'h00};   // CLK2 drives distribution, everything on
+       6'd02 : addr_data = {13'h3D,8'h80};   // Turn on output 1, normal levels
+       6'd03 : addr_data = {13'h4B,8'h80};   // Bypass divider 1 (div by 1)
+       6'd04 : addr_data = {13'h08,8'h47};   // POS PFD, Dig LK Det, Charge Pump normal	
+       6'd05 : addr_data = {13'h09,8'h70};   // Max Charge Pump current
+       6'd06 : addr_data = {13'h0A,8'h04};   // Normal operation, Prescalar Div by 2, PLL On
+       6'd07 : addr_data = {13'h0B,8'h00};   // RDIV MSB (6 bits)
+       6'd08 : addr_data = {13'h0C,8'h01};   // RDIV LSB (8 bits), Div by 1
+       6'd09 : addr_data = {13'h0D,8'h00};   // Everything normal, Dig Lock Det
+       6'd10 : addr_data = {13'h07,8'h00};	// Disable LOR detect - LOR causes failure...
+       6'd11 : addr_data = {13'h04,8'h00};	// A Counter = Don't Care
+       6'd12 : addr_data = {13'h05,8'h00};	// B Counter MSB = 0
+       6'd13 : addr_data = {13'h06,8'h05};   // B Counter LSB = 5
+       default : addr_data = {13'h5A,8'h01}; // Register Update
+     endcase // case(entry)
+
+   wire [5:0]  lastentry = 6'd15;
+   wire        done = (counter == 8'd49);
+   
+   always @(posedge aux_clk)
+     if(reset)
+       begin
+	  entry <= #1 6'd0;
+	  start <= #1 1'b1;
+       end
+     else if(start)
+       start <= #1 1'b0;
+     else if(done && (entry<lastentry))
+       begin
+	  entry <= #1 entry + 6'd1;
+	  start <= #1 1'b1;
+       end
+   
+   always @(posedge aux_clk)
+     if(reset)
+       begin
+	  counter <= #1 7'd0;
+	  command <= #1 20'd0;
+       end
+     else if(start)
+       begin
+	  counter <= #1 7'd1;
+	  command <= #1 {read,w,addr_data};
+       end
+     else if( |counter && ~done )
+       begin
+	  counter <= #1 counter + 7'd1;
+	  if(~counter[0])
+	    command <= {command[22:0],1'b0};
+       end
+   
+   
+   assign sen = (done | counter == 8'd0);  // CSB is high when we're not doing anything
+   assign sclk = ~counter[0];
+   assign sdo = command[23];
+   
+endmodule // clock_control
diff --git a/fpga/usrp2/control_lib/clock_control_tb.v b/fpga/usrp2/control_lib/clock_control_tb.v
new file mode 100644
index 000000000..4e705cf23
--- /dev/null
+++ b/fpga/usrp2/control_lib/clock_control_tb.v
@@ -0,0 +1,35 @@
+
+
+module clock_control_tb();
+   
+  clock_control clock_control
+    (.reset(reset),
+     .aux_clk(aux_clk),  
+     .clk_fpga(clk_fpga),
+     .clk_en(clk_en),    
+     .clk_sel(clk_sel),  
+     .clk_func(clk_func), 
+     .clk_status(clk_status),
+     
+     .sen(sen),   
+     .sclk(sclk), 
+     .sdi(sdi),
+     .sdo(sdo)
+     );
+
+   reg reset, aux_clk;
+   
+   wire [1:0] clk_sel, clk_en;
+   
+   initial reset = 1'b1;
+   initial #1000 reset = 1'b0;
+   
+   initial aux_clk = 1'b0;
+   always #10 aux_clk = ~aux_clk;
+   
+   initial $dumpfile("clock_control_tb.vcd");
+   initial $dumpvars(0,clock_control_tb);
+   
+   initial #10000 $finish;
+   
+endmodule // clock_control_tb
diff --git a/fpga/usrp2/control_lib/cmdfile b/fpga/usrp2/control_lib/cmdfile
new file mode 100644
index 000000000..cb3756cfc
--- /dev/null
+++ b/fpga/usrp2/control_lib/cmdfile
@@ -0,0 +1,18 @@
+# My stuff
+-y .
+-y ../u2_basic
+-y ../control_lib
+-y ../sdr_lib
+
+# Models
+-y ../models
+
+# Open Cores
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/wb_conbus/rtl/verilog
++incdir+../opencores/wb_conbus/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+-y ../opencores/aemb/rtl/verilog
+-y ../opencores/simple_gpio/rtl
diff --git a/fpga/usrp2/control_lib/dcache.v b/fpga/usrp2/control_lib/dcache.v
new file mode 100644
index 000000000..9063bf02a
--- /dev/null
+++ b/fpga/usrp2/control_lib/dcache.v
@@ -0,0 +1,165 @@
+
+module dcache
+  #(parameter AWIDTH=14,
+    parameter CWIDTH=6)
+    (input wb_clk_i,
+     input wb_rst_i,
+     
+     input [AWIDTH-1:0] dwb_adr_i,
+     input dwb_stb_i,
+     input dwb_we_i,
+     input [3:0] dwb_sel_i,
+     input [31:0] dwb_dat_i,
+     output [31:0] dwb_dat_o,
+     output dwb_ack_o,
+     
+     input [31:0] dram_dat_i,
+     output [31:0] dram_dat_o,
+     output [AWIDTH-1:0] dram_adr_o,
+     output dram_we_o,
+     output dram_en_o,
+     output [3:0] dram_sel_o );
+
+   localparam TAGWIDTH = AWIDTH-CWIDTH-2;
+   reg 	      stb_d1, ack_d1, miss_d1;
+   reg [AWIDTH-1:0] held_addr;
+   reg [31:0] 	    ddata [0:(1<<CWIDTH)-1];
+   reg [TAGWIDTH-1:0] dtags [0:(1<<CWIDTH)-1];
+   reg 		      dvalid [0:(1<<CWIDTH)-1];
+   
+   wire [CWIDTH-1:0]  rd_line, wr_line;
+   wire [TAGWIDTH-1:0] wr_tags;
+   wire 	       cache_write, invalidate;
+   wire [31:0] 	       wr_data;
+   
+   // /////////////////////////////////////
+   // Write into cache
+   integer 	      i;
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       for(i=0;i<(1<<CWIDTH);i=i+1)
+	 dvalid[i] <= 0;
+     else
+       if(invalidate)
+	 dvalid[wr_line] <= 1'b0;
+       else if(cache_write)
+	 dvalid[wr_line] <= 1'b1;
+   
+   always @(posedge wb_clk_i)
+     if(cache_write)
+       begin
+	  ddata[wr_line] <= wr_data;
+	  dtags[wr_line] <= wr_tags;
+       end
+   
+   // //////////////////////////////////////
+   // Read from Cache
+   wire [TAGWIDTH-1:0] tag_out = dtags[rd_line];
+   wire 	       valid_out = dvalid[rd_line];
+   wire [31:0] 	       data_out	= ddata[rd_line];
+   wire 	       cache_hit = valid_out & (tag_out == dwb_adr_i[AWIDTH-1:CWIDTH+2]);
+   wire 	       cache_miss = ~cache_hit;
+
+   // //////////////////////////////////////
+   // Handle 1-cycle delay of Block-RAM
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       stb_d1 <= 0;
+     else
+       stb_d1 <= dwb_stb_i;
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       held_addr <= 0;
+     else
+       held_addr <= dwb_adr_i;
+   
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       ack_d1 <= 1'b0;
+     else 
+       ack_d1 <= dwb_ack_o;
+
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       miss_d1 <= 0;
+     else 
+       miss_d1 <= cache_miss;
+
+`define DC_NOCACHE
+//`define DC_BASIC
+//`define DC_FORWARDING_DP
+//`define DC_FORWARDING_SP
+//`define DC_PREFETCH
+
+`ifdef DC_NOCACHE
+   assign 	       dwb_dat_o = dram_dat_i;
+   assign 	       dwb_ack_o = dwb_stb_i & (dwb_we_i | (stb_d1 & ~ack_d1));
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = dwb_stb_i;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = 0;
+   assign 	       wr_line = 0;
+   assign 	       wr_tags = 0;
+   assign 	       wr_data = 0;
+   assign 	       cache_write = 0;
+   assign 	       invalidate = 0; 	       
+`endif
+   
+`ifdef DC_BASIC    // Very basic, no forwarding, 2 wait states on miss
+   assign 	       dwb_dat_o = data_out;
+   assign 	       dwb_ack_o = dwb_stb_i & cache_hit;
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = dwb_stb_i;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = dwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = rd_line;
+   assign 	       wr_tags = dwb_adr_i[AWIDTH-1:CWIDTH+2];
+   assign 	       wr_data = dwb_we_i ? dwb_dat_i : dram_dat_i;
+   assign 	       cache_write = dwb_stb_i & (dwb_we_i | (stb_d1 & miss_d1));
+   assign 	       invalidate = dwb_we_i & ~(&dwb_sel_i);
+`endif
+   
+`ifdef DC_FORWARDING_DP   // Simple forwarding, 1 wait state on miss, dual-port ram
+   assign 	       dwb_dat_o = cache_hit ? data_out : dram_dat_i;
+   assign 	       dwb_ack_o = dwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = 1'b1;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = dwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = held_addr[CWIDTH+1:2];
+   assign 	       wr_tags = held_addr[AWIDTH-1:CWIDTH+2];	       
+   assign 	       wr_data = dram_dat_i;
+   assign 	       cache_write = dwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
+   assign 	       invalidate = 0; 	       
+`endif
+
+`ifdef DC_FORWARDING_SP   // Simple forwarding, 1 wait state on miss, single-port ram
+   assign 	       dwb_dat_o = cache_hit ? data_out : dram_dat_i;
+   assign 	       dwb_ack_o = dwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
+   assign 	       dram_adr_o = dwb_adr_i;
+   assign 	       dram_en_o = 1'b1;
+   assign 	       dram_dat_o = dwb_dat_i;
+   assign 	       dram_we_o = dwb_we_i;
+   assign 	       dram_sel_o = dwb_sel_i;	       
+   assign 	       rd_line = dwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = rd_line;
+   assign 	       wr_tags = dwb_adr_i[AWIDTH-1:CWIDTH+2];
+   assign 	       wr_data = dram_dat_i;
+   assign 	       cache_write = dwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
+   assign 	       invalidate = 0; 	       
+`endif
+
+`ifdef DC_PREFETCH   // Forwarding plus prefetch
+
+`endif
+   
+   
+endmodule // dcache
+
diff --git a/fpga/usrp2/control_lib/decoder_3_8.v b/fpga/usrp2/control_lib/decoder_3_8.v
new file mode 100644
index 000000000..729b45d18
--- /dev/null
+++ b/fpga/usrp2/control_lib/decoder_3_8.v
@@ -0,0 +1,21 @@
+
+module decoder_3_8 
+  (input [2:0] sel, 
+   output reg [7:0] res);
+
+   always @(sel or res)
+     begin
+        case (sel)
+          3'b000 : res = 8'b00000001;
+          3'b001 : res = 8'b00000010;
+          3'b010 : res = 8'b00000100;
+          3'b011 : res = 8'b00001000;
+          3'b100 : res = 8'b00010000;
+          3'b101 : res = 8'b00100000;
+          3'b110 : res = 8'b01000000;
+          default : res = 8'b10000000;
+        endcase // case(sel)
+     end // always @ (sel or res)
+
+endmodule // decoder_3_8
+
diff --git a/fpga/usrp2/control_lib/dpram32.v b/fpga/usrp2/control_lib/dpram32.v
new file mode 100644
index 000000000..4da621823
--- /dev/null
+++ b/fpga/usrp2/control_lib/dpram32.v
@@ -0,0 +1,82 @@
+
+// Dual ported RAM
+//    Addresses are byte-oriented, so botton 2 address bits are ignored.
+//    AWIDTH of 13 allows you to address 8K bytes.  
+//    For Spartan 3, if the total RAM size is not a multiple of 8K then BRAM space is wasted
+// RAM_SIZE parameter allows odd-sized RAMs, like 24K
+
+module dpram32 #(parameter AWIDTH=15, 
+		 parameter RAM_SIZE=16384)
+  (input clk,
+   
+   input [AWIDTH-1:0] adr1_i,
+   input [31:0] dat1_i,
+   output reg [31:0] dat1_o,
+   input we1_i,
+   input en1_i,
+   input [3:0] sel1_i,
+
+   input [AWIDTH-1:0] adr2_i,
+   input [31:0] dat2_i,
+   output reg [31:0] dat2_o,
+   input we2_i,
+   input en2_i,
+   input [3:0] sel2_i );
+   
+   reg [7:0]   ram0 [0:(RAM_SIZE/4)-1];
+   reg [7:0]   ram1 [0:(RAM_SIZE/4)-1];
+   reg [7:0]   ram2 [0:(RAM_SIZE/4)-1];
+   reg [7:0]   ram3 [0:(RAM_SIZE/4)-1];
+
+   //  This is how we used to size the RAM -->  
+   //      reg [7:0]   ram3 [0:(1<<(AWIDTH-2))-1];
+   
+   // Port 1
+   always @(posedge clk)
+     if(en1_i) dat1_o[31:24] <= ram3[adr1_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en1_i) dat1_o[23:16] <= ram2[adr1_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en1_i) dat1_o[15:8] <= ram1[adr1_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en1_i) dat1_o[7:0] <= ram0[adr1_i[AWIDTH-1:2]];
+   
+   always @(posedge clk)
+     if(we1_i & en1_i & sel1_i[3])
+       ram3[adr1_i[AWIDTH-1:2]] <= dat1_i[31:24];
+   always @(posedge clk)
+     if(we1_i & en1_i & sel1_i[2])
+       ram2[adr1_i[AWIDTH-1:2]] <= dat1_i[23:16];
+   always @(posedge clk)
+     if(we1_i & en1_i & sel1_i[1])
+       ram1[adr1_i[AWIDTH-1:2]] <= dat1_i[15:8];
+   always @(posedge clk)
+     if(we1_i & en1_i & sel1_i[0])
+       ram0[adr1_i[AWIDTH-1:2]] <= dat1_i[7:0];
+   
+   // Port 2
+   always @(posedge clk)
+     if(en2_i) dat2_o[31:24] <= ram3[adr2_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en2_i) dat2_o[23:16] <= ram2[adr2_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en2_i) dat2_o[15:8] <= ram1[adr2_i[AWIDTH-1:2]];
+   always @(posedge clk)
+     if(en2_i) dat2_o[7:0] <= ram0[adr2_i[AWIDTH-1:2]];
+   
+   always @(posedge clk)
+     if(we2_i & en2_i & sel2_i[3])
+       ram3[adr2_i[AWIDTH-1:2]] <= dat2_i[31:24];
+   always @(posedge clk)
+     if(we2_i & en2_i & sel2_i[2])
+       ram2[adr2_i[AWIDTH-1:2]] <= dat2_i[23:16];
+   always @(posedge clk)
+     if(we2_i & en2_i & sel2_i[1])
+       ram1[adr2_i[AWIDTH-1:2]] <= dat2_i[15:8];
+   always @(posedge clk)
+     if(we2_i & en2_i & sel2_i[0])
+       ram0[adr2_i[AWIDTH-1:2]] <= dat2_i[7:0];
+   
+endmodule // dpram32
+
+
diff --git a/fpga/usrp2/control_lib/fifo_tb.v b/fpga/usrp2/control_lib/fifo_tb.v
new file mode 100644
index 000000000..616fe4ee7
--- /dev/null
+++ b/fpga/usrp2/control_lib/fifo_tb.v
@@ -0,0 +1,151 @@
+module fifo_tb();
+   
+   reg clk, rst;
+   wire short_full, short_empty, long_full, long_empty;
+   wire casc2_full, casc2_empty;
+   reg 	read, write;
+   
+   wire [7:0] short_do, long_do;
+   wire [7:0] casc2_do;
+   reg [7:0]  di;
+
+   reg 	      clear = 0;
+   
+   shortfifo #(.WIDTH(8)) shortfifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
+      .read(read),.write(write),.full(short_full),.empty(short_empty));
+   
+   longfifo #(.WIDTH(8), .SIZE(4)) longfifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
+      .read(read),.write(write),.full(long_full),.empty(long_empty));
+   
+   cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
+     (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
+      .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
+   
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #50 clk = ~clk;
+   
+   initial di = 8'hAE;
+   initial read = 0;
+   initial write = 0;
+
+   always @(posedge clk)
+     if(write)
+       di <= di + 1;
+   
+   always @(posedge clk)
+     begin
+	if(short_full != long_full)
+	  $display("Error: FULL mismatch");
+	if(short_empty != long_empty)
+	  $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
+	if(read & (short_do != long_do))
+	  $display("Error: DATA mismatch");
+     end
+   
+   initial $dumpfile("fifo_tb.vcd");
+   initial $dumpvars(0,fifo_tb);
+
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	repeat (10)
+	  @(posedge clk);
+	write <= 1;
+	@(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	read <= 1;
+	@(posedge clk);
+	read <= 0;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+
+	repeat(10)
+	  begin
+	     write <= 1;
+	     @(posedge clk);
+	     write <= 0;
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	     read <= 1;
+	     @(posedge clk);
+	     read <= 0;
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	  end // repeat (10)
+	
+	write <= 1;
+	repeat (4)
+	  @(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	read <= 1;
+	repeat (4)
+	  @(posedge clk);
+	read <= 0;
+	@(posedge clk);
+
+
+	write <= 1;
+	repeat (4)
+	  @(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	repeat (4)
+	  begin
+	     read <= 1;
+	     @(posedge clk);
+	     read <= 0;
+	     @(posedge clk);
+	  end
+
+	write <= 1;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	read <= 1;
+	repeat (5)
+	  @(posedge clk);
+	write <= 0;
+	  @(posedge clk);
+	  @(posedge clk);
+	read <= 0;
+	@(posedge clk);
+
+	write <= 1;
+	repeat (16)
+	  @(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	
+	read <= 1;
+	repeat (16)
+	  @(posedge clk);
+	read <= 0;
+	@(posedge clk);
+		 
+	repeat (10)
+	  @(posedge clk);
+	$finish;
+     end
+endmodule // longfifo_tb
diff --git a/fpga/usrp2/control_lib/gray2bin.v b/fpga/usrp2/control_lib/gray2bin.v
new file mode 100644
index 000000000..5df40bd52
--- /dev/null
+++ b/fpga/usrp2/control_lib/gray2bin.v
@@ -0,0 +1,13 @@
+
+
+module gray2bin
+  #(parameter WIDTH=8)
+    (input [WIDTH-1:0] gray,
+     output reg [WIDTH-1:0] bin);
+
+   integer 		i;
+   always @(gray)
+     for(i = 0;i<WIDTH;i=i+1)
+	  bin[i] = ^(gray>>i);
+   
+endmodule // gray2bin
diff --git a/fpga/usrp2/control_lib/gray_send.v b/fpga/usrp2/control_lib/gray_send.v
new file mode 100644
index 000000000..7fc07d40c
--- /dev/null
+++ b/fpga/usrp2/control_lib/gray_send.v
@@ -0,0 +1,29 @@
+
+
+
+module gray_send
+  #(parameter WIDTH = 8)
+    (input clk_in, input [WIDTH-1:0] addr_in,
+     input clk_out, output reg [WIDTH-1:0] addr_out);
+
+   reg [WIDTH-1:0] gray_clkin, gray_clkout, gray_clkout_d1;
+   wire [WIDTH-1:0] gray, bin;
+
+   bin2gray #(.WIDTH(WIDTH)) b2g (.bin(addr_in), .gray(gray) );
+
+   always @(posedge clk_in)
+     gray_clkin <= gray;
+
+   always @(posedge clk_out)
+     gray_clkout <= gray_clkin;
+
+   always @(posedge clk_out)
+     gray_clkout_d1 <= gray_clkout;
+   
+   gray2bin #(.WIDTH(WIDTH)) g2b (.gray(gray_clkout_d1), .bin(bin) );
+
+   // FIXME we may not need the next register, but it may help timing
+   always @(posedge clk_out)
+     addr_out <= bin;
+   
+endmodule // gray_send
diff --git a/fpga/usrp2/control_lib/icache.v b/fpga/usrp2/control_lib/icache.v
new file mode 100644
index 000000000..bd21f47cc
--- /dev/null
+++ b/fpga/usrp2/control_lib/icache.v
@@ -0,0 +1,135 @@
+
+module icache
+  #(parameter AWIDTH=14,
+    parameter CWIDTH=6)
+
+    (input wb_clk_i,
+     input wb_rst_i,
+     input [AWIDTH-1:0] iwb_adr_i,
+     input iwb_stb_i,
+     output [31:0] iwb_dat_o,
+     output iwb_ack_o,
+     input [31:0] iram_dat_i,
+     output [AWIDTH-1:0] iram_adr_o,
+     output iram_en_o,
+     input flush);
+
+   localparam TAGWIDTH = AWIDTH-CWIDTH-2;
+   reg 	      stb_d1, ack_d1, miss_d1;
+   reg [AWIDTH-1:0] held_addr;
+   reg [31:0] 	    idata [0:(1<<CWIDTH)-1];
+   reg [TAGWIDTH-1:0] itags [0:(1<<CWIDTH)-1];
+   reg 		      ivalid [0:(1<<CWIDTH)-1];
+   
+   wire [CWIDTH-1:0]  rd_line, wr_line;
+   wire [TAGWIDTH-1:0] wr_tags;
+   wire 	       store_in_cache;
+
+   // /////////////////////////////////////
+   // Write into cache
+   integer 	      i;
+   always @(posedge wb_clk_i)
+     if(wb_rst_i | flush)
+       for(i=0;i<(1<<CWIDTH);i=i+1)
+	 ivalid[i] <= 0;
+     else
+       if(store_in_cache)
+	 ivalid[wr_line] <= 1'b1;
+   
+   always @(posedge wb_clk_i)
+     if(store_in_cache)
+       begin
+	  idata[wr_line] <= iram_dat_i;
+	  itags[wr_line] <= wr_tags;
+       end
+   
+   // //////////////////////////////////////
+   // Read from Cache
+   wire [TAGWIDTH-1:0] tag_out = itags[rd_line];
+   wire 	       valid_out = ivalid[rd_line];
+   wire [31:0] 	       data_out	= idata[rd_line];
+   wire 	       cache_hit = valid_out & (tag_out == iwb_adr_i[AWIDTH-1:CWIDTH+2]);
+   wire 	       cache_miss = ~cache_hit;
+
+   // //////////////////////////////////////
+   // Handle 1-cycle delay of Block-RAM
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       stb_d1 <= 0;
+     else
+       stb_d1 <= iwb_stb_i;
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       held_addr <= 0;
+     else
+       held_addr <= iwb_adr_i;
+   
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       ack_d1 <= 1'b0;
+     else 
+       ack_d1 <= iwb_ack_o;
+
+   always @(posedge wb_clk_i) 
+     if(wb_rst_i)
+       miss_d1 <= 0;
+     else 
+       miss_d1 <= cache_miss;
+
+//`define IC_NOCACHE
+//`define IC_BASIC
+//`define IC_FORWARDING_DP
+`define IC_FORWARDING_SP
+//`define IC_PREFETCH
+
+`ifdef IC_NOCACHE
+   assign 	       iwb_dat_o = iram_dat_i;
+   assign 	       iwb_ack_o = iwb_stb_i & (stb_d1 & ~ack_d1);
+   assign 	       iram_adr_o = iwb_adr_i;
+   assign 	       iram_en_o = 1'b1;
+   assign 	       rd_line = 0;
+   assign 	       wr_line = 0;
+   assign 	       wr_tags = 0;
+   assign 	       store_in_cache = 0;
+`endif
+   
+`ifdef IC_BASIC    // Very basic, no forwarding, 2 wait states on miss
+   assign 	       iwb_dat_o = data_out;
+   assign 	       iwb_ack_o = iwb_stb_i & cache_hit;
+   assign 	       iram_adr_o = iwb_adr_i;
+   assign 	       iram_en_o = 1'b1;
+   assign 	       rd_line = iwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = rd_line;
+   assign 	       wr_tags = iwb_adr_i[AWIDTH-1:CWIDTH+2];
+   assign 	       store_in_cache = stb_d1 & miss_d1;
+`endif
+   
+`ifdef IC_FORWARDING_DP   // Simple forwarding, 1 wait state on miss, dual-port ram
+   assign 	       iwb_dat_o = cache_hit ? data_out : iram_dat_i;
+   assign 	       iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
+   assign 	       iram_adr_o = iwb_adr_i;
+   assign 	       iram_en_o = 1'b1;
+   assign 	       rd_line = iwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = held_addr[CWIDTH+1:2];
+   assign 	       wr_tags = held_addr[AWIDTH-1:CWIDTH+2];	       
+   assign 	       store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
+`endif
+
+`ifdef IC_FORWARDING_SP   // Simple forwarding, 1 wait state on miss, single-port ram
+   assign 	       iwb_dat_o = cache_hit ? data_out : iram_dat_i;
+   assign 	       iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
+   assign 	       iram_adr_o = iwb_adr_i;
+   assign 	       iram_en_o = 1'b1;
+   assign 	       rd_line = iwb_adr_i[CWIDTH+1:2];
+   assign 	       wr_line = rd_line;
+   assign 	       wr_tags = iwb_adr_i[AWIDTH-1:CWIDTH+2];
+   assign 	       store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
+`endif
+
+`ifdef IC_PREFETCH   // Forwarding plus prefetch
+
+`endif
+   
+   
+endmodule // icache
diff --git a/fpga/usrp2/control_lib/longfifo.v b/fpga/usrp2/control_lib/longfifo.v
new file mode 100644
index 000000000..bf3338e0b
--- /dev/null
+++ b/fpga/usrp2/control_lib/longfifo.v
@@ -0,0 +1,150 @@
+
+// FIFO intended to be interchangeable with shortfifo, but
+//  based on block ram instead of SRL16's
+//  only one clock domain
+
+// Port A is write port, Port B is read port
+
+module longfifo
+  #(parameter WIDTH=32, SIZE=9)
+    (input clk, input rst,
+     input [WIDTH-1:0] datain,
+     output [WIDTH-1:0] dataout,
+     input read,
+     input write,
+     input clear,
+     output full,
+     output empty,
+     output reg [15:0] space,
+     output reg [15:0] occupied);
+
+   // Read side states
+   localparam 	  EMPTY = 0;
+   localparam 	  PRE_READ = 1;
+   localparam 	  READING = 2;
+
+   reg [SIZE-1:0] wr_addr, rd_addr;
+   reg [1:0] 	  read_state;
+
+   reg 	  empty_reg, full_reg;
+   always @(posedge clk)
+     if(rst)
+       wr_addr <= 0;
+     else if(clear)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= wr_addr + 1;
+
+   ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+     ram (.clka(clk),
+	  .ena(1'b1),
+	  .wea(write),
+	  .addra(wr_addr),
+	  .dia(datain),
+	  .doa(),
+
+	  .clkb(clk),
+	  .enb((read_state==PRE_READ)|read),
+	  .web(0),
+	  .addrb(rd_addr),
+	  .dib(0),
+	  .dob(dataout));
+
+   always @(posedge clk)
+     if(rst)
+       begin
+	  read_state <= EMPTY;
+	  rd_addr <= 0;
+	  empty_reg <= 1;
+       end
+     else
+       if(clear)
+	 begin
+	    read_state <= EMPTY;
+	    rd_addr <= 0;
+	    empty_reg <= 1;
+	 end
+       else 
+	 case(read_state)
+	   EMPTY :
+	     if(write)
+	       begin
+		  //rd_addr <= wr_addr;
+		  read_state <= PRE_READ;
+	       end
+	   PRE_READ :
+	     begin
+		read_state <= READING;
+		empty_reg <= 0;
+		rd_addr <= rd_addr + 1;
+	     end
+	   
+	   READING :
+	     if(read)
+	       if(rd_addr == wr_addr)
+		 begin
+		    empty_reg <= 1;
+		    if(write)
+		      read_state <= PRE_READ;
+		    else
+		      read_state <= EMPTY;
+		 end
+	       else
+		 rd_addr <= rd_addr + 1;
+	 endcase // case(read_state)
+
+   wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
+   wire 	   becoming_full = wr_addr == dont_write_past_me;
+     
+   always @(posedge clk)
+     if(rst)
+       full_reg <= 0;
+     else if(clear)
+       full_reg <= 0;
+     else if(read & ~write)
+       full_reg <= 0;
+     //else if(write & ~read & (wr_addr == (rd_addr-3)))
+     else if(write & ~read & becoming_full)
+       full_reg <= 1;
+
+   //assign empty = (read_state != READING);
+   assign empty = empty_reg;
+
+   // assign full = ((rd_addr - 1) == wr_addr);
+   assign full = full_reg;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE)-2;
+   always @(posedge clk)
+     if(rst)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+   
+   /*
+   wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // Approximate, for simulation only
+   assign occupied = {{16-SIZE{1'b0}},fullness};
+
+   wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2;  // Approximate, for SERDES flow control
+   assign space = {{16-SIZE{1'b0}},free_space};
+    */  
+
+   
+endmodule // longfifo
diff --git a/fpga/usrp2/control_lib/medfifo.v b/fpga/usrp2/control_lib/medfifo.v
new file mode 100644
index 000000000..5a77e8c16
--- /dev/null
+++ b/fpga/usrp2/control_lib/medfifo.v
@@ -0,0 +1,49 @@
+
+module medfifo
+  #(parameter WIDTH=32,
+    parameter DEPTH=1)
+    (input clk, input rst,
+     input [WIDTH-1:0] datain,
+     output [WIDTH-1:0] dataout,
+     input read,
+     input write,
+     input clear,
+     output full,
+     output empty,
+     output [7:0] space,
+     output [7:0] occupied);
+
+   localparam 		NUM_FIFOS = (1<<DEPTH);
+   
+   wire [WIDTH-1:0] 	dout [0:NUM_FIFOS-1];
+   wire [0:NUM_FIFOS-1] full_x;
+   wire [0:NUM_FIFOS-1] empty_x;
+
+   shortfifo #(.WIDTH(WIDTH))
+     head (.clk(clk),.rst(rst),
+	   .datain(datain),.write(write),.full(full),
+	   .dataout(dout[0]),.read(~empty_x[0] & ~full_x[1]),.empty(empty_x[0]),
+	   .clear(clear),.space(space[4:0]),.occupied() );
+   
+   shortfifo #(.WIDTH(WIDTH))
+     tail (.clk(clk),.rst(rst),
+	   .datain(dout[NUM_FIFOS-2]),.write(~empty_x[NUM_FIFOS-2] & ~full_x[NUM_FIFOS-1]),.full(full_x[NUM_FIFOS-1]),
+	   .dataout(dataout),.read(read),.empty(empty),
+	   .clear(clear),.space(),.occupied(occupied[4:0]) );
+
+   genvar 		i;
+   generate
+      for(i = 1; i < NUM_FIFOS-1 ; i = i + 1)
+	begin : gen_depth
+	   shortfifo #(.WIDTH(WIDTH))
+	     shortfifo (.clk(clk),.rst(rst),
+			.datain(dout[i-1]),.write(~full_x[i] & ~empty_x[i-1]),.full(full_x[i]),
+			.dataout(dout[i]),.read(~full_x[i+1] & ~empty_x[i]),.empty(empty_x[i]),
+			.clear(clear),.space(),.occupied() );
+	end
+   endgenerate
+
+   assign space[7:5] = 0;
+   assign occupied[7:5] = 0;
+   
+endmodule // medfifo
diff --git a/fpga/usrp2/control_lib/mux4.v b/fpga/usrp2/control_lib/mux4.v
new file mode 100644
index 000000000..31c85c832
--- /dev/null
+++ b/fpga/usrp2/control_lib/mux4.v
@@ -0,0 +1,16 @@
+
+
+module mux4
+  #(parameter WIDTH=32, parameter DISABLED=0)
+    (input en,
+     input [1:0] sel,
+     input [WIDTH-1:0] i0,
+     input [WIDTH-1:0] i1,
+     input [WIDTH-1:0] i2,
+     input [WIDTH-1:0] i3,
+     output [WIDTH-1:0] o);
+
+   assign 		o = en ? (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0)) :
+			DISABLED;
+   
+endmodule // mux4
diff --git a/fpga/usrp2/control_lib/mux8.v b/fpga/usrp2/control_lib/mux8.v
new file mode 100644
index 000000000..9db96a60f
--- /dev/null
+++ b/fpga/usrp2/control_lib/mux8.v
@@ -0,0 +1,21 @@
+
+
+module mux8
+  #(parameter WIDTH=32, parameter DISABLED=0)
+    (input en,
+     input [2:0] sel,
+     input [WIDTH-1:0] i0,
+     input [WIDTH-1:0] i1,
+     input [WIDTH-1:0] i2,
+     input [WIDTH-1:0] i3,
+     input [WIDTH-1:0] i4,
+     input [WIDTH-1:0] i5,
+     input [WIDTH-1:0] i6,
+     input [WIDTH-1:0] i7,
+     output [WIDTH-1:0] o);
+
+   assign 		o = en ? (sel[2] ? (sel[1] ? (sel[0] ? i7 : i6) : (sel[0] ? i5 : i4)) :
+				  (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0))) :
+			DISABLED;
+   
+endmodule // mux8
diff --git a/fpga/usrp2/control_lib/mux_32_4.v b/fpga/usrp2/control_lib/mux_32_4.v
new file mode 100644
index 000000000..fef5812e9
--- /dev/null
+++ b/fpga/usrp2/control_lib/mux_32_4.v
@@ -0,0 +1,13 @@
+
+
+module mux_32_4
+  (input [1:0] sel,
+   input [31:0] in0,
+   input [31:0] in1,
+   input [31:0] in2,
+   input [31:0] in3,
+   output [31:0] out);
+
+   assign 	 out = sel[1] ? (sel[0] ? in3 : in2) : (sel[0] ? in1 : in0);
+
+endmodule // mux_32_4
diff --git a/fpga/usrp2/control_lib/newfifo/.gitignore b/fpga/usrp2/control_lib/newfifo/.gitignore
new file mode 100644
index 000000000..cba7efc8e
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/.gitignore
@@ -0,0 +1 @@
+a.out
diff --git a/fpga/usrp2/control_lib/newfifo/buffer_int.v b/fpga/usrp2/control_lib/newfifo/buffer_int.v
new file mode 100644
index 000000000..b45ed3532
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/buffer_int.v
@@ -0,0 +1,168 @@
+
+// FIFO Interface to the 2K buffer RAMs
+// Read port is read-acknowledge
+// FIXME do we want to be able to interleave reads and writes?
+
+module buffer_int
+  #(parameter BUF_NUM = 0,
+    parameter BUF_SIZE = 9)
+    (// Control Interface
+     input clk,
+     input rst,
+     input [31:0] ctrl_word,
+     input go,
+     output done,
+     output error,
+     output idle,
+     output [1:0] flag,
+     
+     // Buffer Interface
+     output en_o,
+     output we_o,
+     output reg [BUF_SIZE-1:0] addr_o,
+     output [31:0] dat_to_buf,
+     input [31:0] dat_from_buf,
+     
+     // Write FIFO Interface
+     input [31:0] wr_data_i,
+     input [3:0] wr_flags_i,
+     input wr_ready_i,
+     output wr_ready_o,
+     
+     // Read FIFO Interface
+     output [31:0] rd_data_o,
+     output [3:0] rd_flags_o,
+     output rd_ready_o,
+     input rd_ready_i
+     );
+   
+   reg [31:0] ctrl_reg;
+   reg 	      go_reg;
+   
+   always @(posedge clk)
+     go_reg <= go;
+   
+   always @(posedge clk)
+     if(rst)
+       ctrl_reg <= 0;
+     else
+       if(go & (ctrl_word[31:28] == BUF_NUM))
+	 ctrl_reg <= ctrl_word;
+   
+   wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0];
+   wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE];
+
+   wire       read = ctrl_reg[22];
+   wire       write = ctrl_reg[23];
+   wire       clear = ctrl_reg[24];
+   //wire [2:0] port = ctrl_reg[27:25];  // Ignored in this block
+   //wire [3:0] buff_num = ctrl_reg[31:28];  // Ignored here ?
+   
+   localparam IDLE = 3'd0;
+   localparam PRE_READ = 3'd1;
+   localparam READING = 3'd2;
+   localparam WRITING = 3'd3;
+   localparam ERROR = 3'd4;
+   localparam DONE = 3'd5;
+   
+   reg [2:0]  state;
+   reg 	      rd_sop, rd_eop;
+   wire       wr_sop, wr_eop, wr_error;
+   reg [1:0]  rd_occ;
+   wire [1:0] wr_occ;
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  state <= IDLE;
+	  rd_sop <= 0;
+	  rd_eop <= 0;
+	  rd_occ <= 0;
+       end
+     else
+       if(clear)
+	 begin
+	    state <= IDLE;
+	    rd_sop <= 0;
+	    rd_eop <= 0;
+	    rd_occ <= 0;
+	 end
+       else 
+	 case(state)
+	   IDLE :
+	     if(go_reg & read)
+	       begin
+		  addr_o <= firstline;
+		  state <= PRE_READ;
+	       end
+	     else if(go_reg & write)
+	       begin
+		  addr_o <= firstline;
+		  state <= WRITING;
+	       end
+	   
+	   PRE_READ :
+	     begin
+		state <= READING;
+		addr_o <= addr_o + 1;
+		rd_occ <= 2'b00;
+		rd_sop <= 1;
+		rd_eop <= 0;
+	     end
+	   
+	   READING :
+	     if(rd_ready_i)
+	       begin
+		  rd_sop <= 0;
+		  addr_o <= addr_o + 1;
+		  if(addr_o == lastline)
+		    begin
+		       rd_eop <= 1;
+		       // FIXME assign occ here
+		       rd_occ <= 0;
+		    end
+		  else
+		    rd_eop <= 0;
+		  if(rd_eop)
+		    state <= DONE;
+	       end
+	   
+	   WRITING :
+	     begin
+		if(wr_ready_i)
+		  begin
+		     addr_o <= addr_o + 1;
+		     if(wr_error)
+		       begin
+			  state <= ERROR;
+			  // Save OCC flags here
+		       end
+		     else if((addr_o == lastline)||wr_eop)
+		       state <= DONE;
+		  end // if (wr_ready_i)
+	     end // case: WRITING
+	   
+	 endcase // case(state)
+   
+   assign     dat_to_buf = wr_data_i;
+   assign     rd_data_o = dat_from_buf;
+
+   assign     rd_flags_o = { rd_occ[1:0], rd_eop, rd_sop };
+   assign     rd_ready_o = (state == READING);
+   
+   assign     wr_sop = wr_flags_i[0];
+   assign     wr_eop = wr_flags_i[1];
+   assign     wr_occ = wr_flags_i[3:2];
+   assign     wr_error = wr_sop & wr_eop;
+   assign     wr_ready_o = (state == WRITING);
+
+   assign     we_o = (state == WRITING);
+   //assign     we_o = (state == WRITING) && wr_ready_i;  // always write to avoid timing issue
+
+   assign     en_o = ~((state==READING)& ~rd_ready_i);   // FIXME potential critical path
+   
+   assign     done = (state == DONE);
+   assign     error = (state == ERROR);
+   assign     idle = (state == IDLE);
+
+endmodule // buffer_int
diff --git a/fpga/usrp2/control_lib/newfifo/buffer_int_tb.v b/fpga/usrp2/control_lib/newfifo/buffer_int_tb.v
new file mode 100644
index 000000000..df54dcc0b
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/buffer_int_tb.v
@@ -0,0 +1,418 @@
+
+module buffer_int_tb ();
+
+   reg clk = 0;
+   reg rst = 1;
+
+   initial #100 rst = 0;
+   always #5 clk = ~clk;
+
+   wire en, we;
+   wire [8:0] addr;
+   wire [31:0] fifo2buf, buf2fifo;
+   
+   wire [31:0] rd_data_o;
+   wire [3:0]  rd_flags_o;
+   wire        rd_sop_o, rd_eop_o;
+   reg 	       rd_error_i = 0, rd_read_i = 0;
+   
+   reg [31:0]  wr_data_i = 0;
+   wire [3:0]  wr_flags_i;
+   reg 	       wr_eop_i = 0, wr_sop_i = 0;
+   reg 	       wr_write_i = 0;
+   wire        wr_ready_o, wr_full_o;
+   
+   reg 	       clear = 0, write = 0, read = 0;
+   reg [8:0]   firstline = 0, lastline = 0;
+   wire [3:0]  step = 1;
+   wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline};
+   reg 	       go = 0;
+   wire        done, error;
+
+   assign      wr_flags_i = {2'b00, wr_eop_i, wr_sop_i};
+   assign      rd_sop_o = rd_flags_o[0];
+   assign      rd_eop_o = rd_flags_o[1];
+   
+   buffer_int buffer_int
+     (.clk(clk),.rst(rst),
+      .ctrl_word(ctrl_word),.go(go),
+      .done(done),.error(error),
+      
+      // Buffer Interface
+      .en_o(en),.we_o(we),.addr_o(addr),
+      .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo),
+
+      // Write FIFO Interface
+      .wr_data_i(wr_data_i), .wr_flags_i(wr_flags_i), .wr_write_i(wr_write_i), .wr_ready_o(wr_ready_o),
+
+      // Read FIFO Interface
+      .rd_data_o(rd_data_o), .rd_flags_o(rd_flags_o), .rd_ready_o(rd_ready_o), .rd_read_i(rd_read_i)
+      );
+   
+   reg 	       ram_en = 0, ram_we = 0;
+   reg [8:0]   ram_addr = 0;
+   reg [31:0]  ram_data = 0;
+   
+   ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port
+     (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(),
+      .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) );
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	FillRAM;
+
+	ResetBuffer;
+	SetBufferRead(5,10);
+	$display("Testing full read, no wait states.");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(6,0);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferRead(5,10);
+	$display("Testing full read, 2 wait states.");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(6,2);
+	repeat (10)
+	  @(posedge clk);
+
+	ResetBuffer;
+	SetBufferRead(5,10);
+	$display("Testing partial read, 0 wait states, then nothing after last.");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(3,0);
+	repeat (10)
+	  @(posedge clk);
+
+	ResetBuffer;
+	SetBufferRead(5,10);
+	$display("Testing partial read, 0 wait states, then done at same time as last.");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(2,0);
+	ReadALine;
+	repeat (10)
+	  @(posedge clk);
+
+	ResetBuffer;
+	SetBufferRead(5,10);
+	$display("Testing partial read, 3 wait states, then error at same time as last.");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(2,3);
+	rd_error_i <= 1;
+	ReadALine;
+	rd_error_i <= 0;
+	repeat (10)
+	  @(posedge clk);
+
+	ResetBuffer;
+	SetBufferRead(500,511);
+	$display("Testing full read, to the end of the buffer.");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(12,0);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferRead(0,511);
+	$display("Testing full read, start to end of the buffer.");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(512,0);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferRead(505,3);
+	$display("Testing full read, wraparound");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(11,0);
+	repeat (10)
+	  @(posedge clk);
+
+	ResetBuffer;
+	SetBufferWrite(10,15);
+	$display("Testing Full Write, no wait states");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	WriteLines(6,0,72);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferWrite(18,23);
+	$display("Testing Full Write, 1 wait states");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	WriteLines(6,1,101);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferWrite(27,40);
+	$display("Testing Partial Write, 0 wait states");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	WriteLines(6,0,201);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferWrite(45,200);
+	$display("Testing Partial Write, 0 wait states, then done and write simultaneously");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	wr_sop_i <= 1; wr_eop_i <= 0;
+	WriteLines(6,0,301);
+	wr_sop_i <= 0; wr_eop_i <= 1;
+	WriteALine(400);
+	wr_sop_i <= 0; wr_eop_i <= 0;
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferWrite(55,200);
+	$display("Testing Partial Write, 0 wait states, then error");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	WriteLines(6,0,501);
+	wr_sop_i <= 1; wr_eop_i <= 1;
+	WriteALine(400);
+	@(posedge clk);
+	repeat (10)
+	  @(posedge clk);
+	wr_sop_i <= 0; wr_eop_i <= 0;
+	
+	ResetBuffer;
+	SetBufferRead(0,82);
+	$display("Testing read after all the writes");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(83,0);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferWrite(508,4);
+	$display("Testing wraparound write");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	WriteLines(9,0,601);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferRead(506,10);
+	$display("Reading wraparound write");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(17,0);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferWrite(0,511);
+	$display("Testing Whole Buffer write");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	WriteLines(512,0,1000);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferRead(0,511);
+	$display("Reading Whole Buffer write");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(512,0);
+	repeat (10)
+	  @(posedge clk);
+
+	/*
+	ResetBuffer;
+	SetBufferWrite(5,10);
+	$display("Testing Write Too Many");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	WriteLines(12,0,2000);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferRead(0,15);
+	$display("Reading back Write Too Many");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(16,0);
+	repeat (10)
+	  @(posedge clk);
+	*/
+	ResetBuffer;
+	SetBufferWrite(15,20);
+	$display("Testing Write One Less Than Full");
+	while(!wr_ready_o)
+	  @(posedge clk);
+	wr_sop_i <= 1; wr_eop_i <= 0;
+	WriteALine(400);
+	wr_sop_i <= 0; wr_eop_i <= 0;
+	WriteLines(3,0,2000);
+	wr_sop_i <= 0; wr_eop_i <= 1;
+	WriteALine(400);
+	wr_sop_i <= 0; wr_eop_i <= 0;
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	SetBufferRead(13,22);
+	$display("Reading back Write One Less Than Full");
+	while(!rd_sop_o)
+	  @(posedge clk);
+	ReadLines(10,0);
+	repeat (10)
+	  @(posedge clk);
+	
+	ResetBuffer;
+	repeat(100)
+	  @(posedge clk);
+	$finish;
+     end
+   
+   always @(posedge clk)
+     if(rd_read_i == 1'd1)
+       $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_data_o, rd_sop_o, rd_eop_o);
+
+   always @(posedge clk)
+     if(wr_write_i == 1'd1)
+       $display("WRITE Buffer %d,  wr_ready_o %d, wr_full_o %d", wr_data_i, wr_ready_o, wr_full_o);
+	   
+   initial begin
+      $dumpfile("buffer_int_tb.lxt");
+      $dumpvars(0,buffer_int_tb);
+   end
+
+   task FillRAM;
+      begin
+	 ram_addr <= 0;
+	 ram_data <= 0;
+	 @(posedge clk);
+	 ram_en <= 1;
+	 ram_we <= 1;
+	 @(posedge clk);
+	 repeat (511)
+	   begin
+	      ram_addr <= ram_addr + 1;
+	      ram_data <= ram_data + 1;
+	      ram_en <= 1;
+	      ram_we <= 1;
+	      @(posedge clk);
+	   end
+	 ram_en <= 0;
+	 ram_we <= 0;
+	 @(posedge clk);
+	 $display("Filled the RAM");
+      end
+   endtask // FillRAM
+
+   task ResetBuffer;
+      begin
+	 clear <= 1; read <= 0; write <= 0;
+	 go <= 1;
+	 @(posedge clk);
+	 go <= 0;
+	 @(posedge clk);
+	 $display("Buffer Reset");
+      end
+   endtask // ClearBuffer
+   
+   task SetBufferWrite;
+      input [8:0] start;
+      input [8:0] stop;
+      begin
+	 clear <= 0; read <= 0; write <= 1;
+	 firstline <= start;
+	 lastline <= stop;
+	 go <= 1;
+	 @(posedge clk);
+	 go <= 0;
+	 @(posedge clk);
+	 $display("Buffer Set for Write");
+      end
+   endtask // SetBufferWrite
+   
+   task SetBufferRead;
+      input [8:0] start;
+      input [8:0] stop;
+      begin
+	 clear <= 0; read <= 1; write <= 0;
+	 firstline <= start;
+	 lastline <= stop;
+	 go <= 1;
+	 @(posedge clk);
+	 go <= 0;
+	 @(posedge clk);
+	 $display("Buffer Set for Read");
+      end
+   endtask // SetBufferRead
+
+   task ReadALine;
+      begin
+	 while(~rd_ready_o)
+	   @(posedge clk);
+	 #1 rd_read_i <= 1;
+	 @(posedge clk);
+	 rd_read_i <= 0;
+      end
+   endtask // ReadALine
+
+   task ReadLines;
+      input [9:0] lines;
+      input [7:0] wait_states;
+      begin
+	 $display("Read Lines: Number %d, Wait States %d",lines,wait_states);
+	 repeat (lines)
+	   begin
+	      ReadALine;
+	      repeat (wait_states)
+		@(posedge clk);
+	   end
+      end
+   endtask // ReadLines
+   
+   task WriteALine;
+      input [31:0] value;
+      begin
+	 while(~wr_ready_o)
+	   @(posedge clk);
+	 #1 wr_write_i <= 1;
+	 wr_data_i <= value;
+	 @(posedge clk);
+	 wr_write_i <= 0;
+      end
+   endtask // WriteALine
+   
+   task WriteLines;
+      input [9:0] lines;
+      input [7:0] wait_states;
+      input [31:0] value;
+      begin
+	 $display("Write Lines: Number %d, Wait States %d",lines,wait_states);
+	 repeat(lines)
+	   begin
+	      value <= value + 1;
+	      WriteALine(value);
+	      repeat(wait_states)
+		@(posedge clk);
+	   end
+      end
+   endtask // WriteLines
+   
+endmodule // buffer_int_tb
diff --git a/fpga/usrp2/control_lib/newfifo/buffer_pool.v b/fpga/usrp2/control_lib/newfifo/buffer_pool.v
new file mode 100644
index 000000000..41ac1deb3
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/buffer_pool.v
@@ -0,0 +1,283 @@
+
+// Buffer pool.  Contains 8 buffers, each 2K (512 by 32).  Each buffer
+// is a dual-ported RAM.  Port A on each of them is indirectly connected 
+// to the wishbone bus by a bridge.  Port B may be connected any one of the
+// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected.  The wishbone bus
+// provides access to all 8 buffers, and also controls the connections
+// between the ports and the buffers, allocating them as needed.
+
+// wb_adr is 16 bits -- 
+//  bits 13:11 select which buffer
+//  bits 10:2 select line in buffer
+//  bits 1:0 are unused (32-bit access only)
+
+// BUF_SIZE is in address lines (i.e. log2 of number of lines).  
+// For S3 it should be 9 (512 words, 2KB)
+// For V5 it should be at least 10 (1024 words, 4KB) or 11 (2048 words, 8KB)
+
+module buffer_pool
+  #(parameter BUF_SIZE = 9,
+    parameter SET_ADDR = 64)
+    (input wb_clk_i,
+     input wb_rst_i,
+     input wb_we_i,
+     input wb_stb_i,
+     input [15:0] wb_adr_i,
+     input [31:0] wb_dat_i,   
+     output [31:0] wb_dat_o,
+     output reg wb_ack_o,
+     output wb_err_o,
+     output wb_rty_o,
+   
+     input stream_clk,
+     input stream_rst,
+     
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     output [31:0] status,
+     output sys_int_o,
+     
+     output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3,
+     output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7,
+     
+     // Write Interfaces
+     input [31:0] wr0_data_i, input [3:0] wr0_flags_i, input wr0_ready_i, output wr0_ready_o,
+     input [31:0] wr1_data_i, input [3:0] wr1_flags_i, input wr1_ready_i, output wr1_ready_o,
+     input [31:0] wr2_data_i, input [3:0] wr2_flags_i, input wr2_ready_i, output wr2_ready_o,
+     input [31:0] wr3_data_i, input [3:0] wr3_flags_i, input wr3_ready_i, output wr3_ready_o,
+     
+     // Read Interfaces
+     output [31:0] rd0_data_o, output [3:0] rd0_flags_o, output rd0_ready_o, input rd0_ready_i, 
+     output [31:0] rd1_data_o, output [3:0] rd1_flags_o, output rd1_ready_o, input rd1_ready_i, 
+     output [31:0] rd2_data_o, output [3:0] rd2_flags_o, output rd2_ready_o, input rd2_ready_i, 
+     output [31:0] rd3_data_o, output [3:0] rd3_flags_o, output rd3_ready_o, input rd3_ready_i
+     );
+   
+   wire [7:0] 	   sel_a;
+   
+   wire [BUF_SIZE-1:0] 	   buf_addra = wb_adr_i[BUF_SIZE+1:2];     // ignore address 1:0, 32-bit access only
+   wire [2:0] 		   which_buf = wb_adr_i[BUF_SIZE+4:BUF_SIZE+2];   // address 15:14 selects the buffer pool
+   
+   decoder_3_8 dec(.sel(which_buf),.res(sel_a));
+   
+   genvar 	 i;
+   
+   wire 	 go;
+
+   reg [2:0] 	 port[0:7];	 
+   reg [3:0] 	 read_src[0:3];
+   reg [3:0] 	 write_src[0:3];
+   
+   wire [7:0] 	 done;
+   wire [7:0] 	 error;
+   wire [7:0] 	 idle;
+   
+   wire [31:0] 	 buf_doa[0:7];
+   
+   wire [7:0] 	 buf_enb;
+   wire [7:0] 	 buf_web;
+   wire [BUF_SIZE-1:0] 	 buf_addrb[0:7];
+   wire [31:0] 	 buf_dib[0:7];
+   wire [31:0] 	 buf_dob[0:7];
+   
+   wire [31:0] 	 wr_data_i[0:7];
+   wire [3:0] 	 wr_flags_i[0:7];
+   wire [7:0] 	 wr_ready_i;
+   wire [7:0] 	 wr_ready_o;
+   
+   wire [31:0] 	 rd_data_o[0:7];
+   wire [3:0] 	 rd_flags_o[0:7];
+   wire [7:0] 	 rd_ready_o;
+   wire [7:0] 	 rd_ready_i;
+   
+   assign 	 status = {8'd0,idle[7:0],error[7:0],done[7:0]};
+
+   assign 	 s0 = buf_addrb[0];
+   assign 	 s1 = buf_addrb[1];
+   assign 	 s2 = buf_addrb[2];
+   assign 	 s3 = buf_addrb[3];
+   assign 	 s4 = buf_addrb[4];
+   assign 	 s5 = buf_addrb[5];
+   assign 	 s6 = buf_addrb[6];
+   assign 	 s7 = buf_addrb[7];
+   
+   wire [31:0] 	 fifo_ctrl;
+   setting_reg #(.my_addr(SET_ADDR)) 
+     sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
+	  .out(fifo_ctrl),.changed(go));
+
+   integer 	 k;
+   always @(posedge stream_clk)
+     if(stream_rst)
+       for(k=0;k<8;k=k+1)
+	 port[k] <= 4;   // disabled
+     else
+       for(k=0;k<8;k=k+1)
+	 if(go & (fifo_ctrl[31:28]==k))
+	   port[k] <= fifo_ctrl[27:25];
+
+   always @(posedge stream_clk)
+     if(stream_rst)
+       for(k=0;k<4;k=k+1)
+	 read_src[k] <= 8;  // disabled
+     else
+       for(k=0;k<4;k=k+1)
+	 if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k))
+	   read_src[k] <= fifo_ctrl[31:28];
+   
+   always @(posedge stream_clk)
+     if(stream_rst)
+       for(k=0;k<4;k=k+1)
+	 write_src[k] <= 8;  // disabled
+     else
+       for(k=0;k<4;k=k+1)
+	 if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k))
+	   write_src[k] <= fifo_ctrl[31:28];
+   
+   generate
+      for(i=0;i<8;i=i+1)
+	begin : gen_buffer
+	   RAMB16_S36_S36 dpram
+	     (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0),
+	      .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i),
+	      .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0),
+	      .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) );
+	   
+/*	   
+	   ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer
+	     (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i),
+	      .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]),
+	      .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
+	      .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i]));
+ 
+ */
+	   
+	   buffer_int #(.BUF_NUM(i),.BUF_SIZE(BUF_SIZE)) buffer_int
+	     (.clk(stream_clk),.rst(stream_rst),
+	      .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
+	      .done(done[i]),.error(error[i]),.idle(idle[i]),
+	      .en_o(buf_enb[i]),
+	      .we_o(buf_web[i]),
+	      .addr_o(buf_addrb[i]),
+	      .dat_to_buf(buf_dib[i]),
+	      .dat_from_buf(buf_dob[i]),
+	      .wr_data_i(wr_data_i[i]),
+	      .wr_flags_i(wr_flags_i[i]),
+	      .wr_ready_i(wr_ready_i[i]),
+	      .wr_ready_o(wr_ready_o[i]),
+	      .rd_data_o(rd_data_o[i]),
+	      .rd_flags_o(rd_flags_o[i]),
+	      .rd_ready_o(rd_ready_o[i]),
+	      .rd_ready_i(rd_ready_i[i]) );
+	   mux4 #(.WIDTH(37))
+	     mux4_wr (.en(~port[i][2]),.sel(port[i][1:0]),
+		      .i0({wr0_data_i,wr0_flags_i,wr0_ready_i}),
+		      .i1({wr1_data_i,wr1_flags_i,wr1_ready_i}),
+		      .i2({wr2_data_i,wr2_flags_i,wr2_ready_i}),
+		      .i3({wr3_data_i,wr3_flags_i,wr3_ready_i}),
+		      .o({wr_data_i[i],wr_flags_i[i],wr_ready_i[i]}) );
+	   mux4 #(.WIDTH(1))
+	     mux4_rd (.en(~port[i][2]),.sel(port[i][1:0]),
+		      .i0(rd0_ready_i),.i1(rd1_ready_i),.i2(rd2_ready_i),.i3(rd3_ready_i),
+		      .o(rd_ready_i[i]));
+	end // block: gen_buffer
+   endgenerate
+
+   //----------------------------------------------------------------------
+   // Wishbone Outputs
+
+   // Use the following lines if ram output and mux can be made fast enough
+
+   assign wb_err_o = 1'b0;  // Unused for now
+   assign wb_rty_o = 1'b0;  // Unused for now
+   
+   always @(posedge wb_clk_i)
+     wb_ack_o <= wb_stb_i & ~wb_ack_o;
+   assign wb_dat_o = buf_doa[which_buf];
+
+   // Use this if we can't make the RAM+MUX fast enough
+   // reg [31:0] wb_dat_o_reg;
+   // reg 	      stb_d1;
+
+   // always @(posedge wb_clk_i)
+   //  begin
+   //   wb_dat_o_reg <= buf_doa[which_buf];
+   //   stb_d1 <= wb_stb_i;
+   //   wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
+   //  end
+   //assign     wb_dat_o = wb_dat_o_reg;
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_wr0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), 
+	      .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+	      .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+	      .o(wr0_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_wr1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), 
+	      .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+	      .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+	      .o(wr1_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_wr2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), 
+	      .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+	      .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+	      .o(wr2_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_wr3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), 
+	      .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), .i2(wr_ready_o[2]), .i3(wr_ready_o[3]),
+	      .i4(wr_ready_o[4]), .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),
+	      .o(wr3_ready_o));
+
+   mux8 #(.WIDTH(37)) 
+     mux8_rd0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), 
+	      .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+	      .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+	      .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+	      .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+	      .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+	      .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+	      .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+	      .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+	      .o({rd0_data_o,rd0_flags_o,rd0_ready_o}));
+   
+   mux8 #(.WIDTH(37)) 
+     mux8_rd1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), 
+	      .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+	      .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+	      .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+	      .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+	      .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+	      .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+	      .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+	      .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+	      .o({rd1_data_o,rd1_flags_o,rd1_ready_o}));
+   
+   mux8 #(.WIDTH(37)) 
+     mux8_rd2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), 
+	      .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+	      .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+	      .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+	      .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+	      .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+	      .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+	      .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+	      .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+	      .o({rd2_data_o,rd2_flags_o,rd2_ready_o}));
+   
+   mux8 #(.WIDTH(37)) 
+     mux8_rd3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), 
+	      .i0({rd_data_o[0],rd_flags_o[0],rd_ready_o[0]}),
+	      .i1({rd_data_o[1],rd_flags_o[1],rd_ready_o[1]}),
+	      .i2({rd_data_o[2],rd_flags_o[2],rd_ready_o[2]}),
+	      .i3({rd_data_o[3],rd_flags_o[3],rd_ready_o[3]}),
+	      .i4({rd_data_o[4],rd_flags_o[4],rd_ready_o[4]}),
+	      .i5({rd_data_o[5],rd_flags_o[5],rd_ready_o[5]}),
+	      .i6({rd_data_o[6],rd_flags_o[6],rd_ready_o[6]}),
+	      .i7({rd_data_o[7],rd_flags_o[7],rd_ready_o[7]}),
+	      .o({rd3_data_o,rd3_flags_o,rd3_ready_o}));
+   
+   assign sys_int_o = (|error) | (|done);
+   
+endmodule // buffer_pool
diff --git a/fpga/usrp2/control_lib/newfifo/buffer_pool_tb.v b/fpga/usrp2/control_lib/newfifo/buffer_pool_tb.v
new file mode 100644
index 000000000..91a01d268
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/buffer_pool_tb.v
@@ -0,0 +1,58 @@
+
+module buffer_pool_tb();
+   
+   wire wb_clk_i;
+   wire wb_rst_i;
+   wire wb_we_i;
+   wire wb_stb_i;
+   wire [15:0] wb_adr_i;
+   wire [31:0] wb_dat_i;   
+   wire [31:0] wb_dat_o;
+   wire wb_ack_o;
+   wire wb_err_o;
+   wire wb_rty_o;
+
+   wire stream_clk, stream_rst;
+
+   wire set_stb;
+   wire [7:0] set_addr;
+   wire [31:0] set_data;
+
+   wire [31:0] wr0_data, wr1_data, wr2_data, wr3_data;
+   wire [31:0] rd0_data, rd1_data, rd2_data, rd3_data;
+   wire [3:0]  wr0_flags, wr1_flags, wr2_flags, wr3_flags;
+   wire [3:0]  rd0_flags, rd1_flags, rd2_flags, rd3_flags;
+   wire        wr0_ready, wr1_ready, wr2_ready, wr3_ready;
+   wire        rd0_ready, rd1_ready, rd2_ready, rd3_ready;
+   wire        wr0_write, wr1_write, wr2_write, wr3_write;
+   wire        rd0_read, rd1_read, rd2_read, rd3_read;
+
+   buffer_pool dut
+     (.wb_clk_i(wb_clk_i),
+      .wb_rst_i(wb_rst_i),
+      .wb_we_i(wb_we_i),
+      .wb_stb_i(wb_stb_i),
+      .wb_adr_i(wb_adr_i),
+      .wb_dat_i(wb_dat_i),   
+      .wb_dat_o(wb_dat_o),
+      .wb_ack_o(wb_ack_o),
+      .wb_err_o(wb_err_o),
+      .wb_rty_o(wb_rty_o),
+      
+      .stream_clk(stream_clk),
+      .stream_rst(stream_rst),
+      
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      
+      .wr0_data_i(wr0_data), .wr0_write_i(wr0_write), .wr0_flags_i(wr0_flags), .wr0_ready_o(wr0_ready),
+      .wr1_data_i(wr1_data), .wr1_write_i(wr1_write), .wr1_flags_i(wr1_flags), .wr1_ready_o(wr1_ready),
+      .wr2_data_i(wr2_data), .wr2_write_i(wr2_write), .wr2_flags_i(wr2_flags), .wr2_ready_o(wr2_ready),
+      .wr3_data_i(wr3_data), .wr3_write_i(wr3_write), .wr3_flags_i(wr3_flags), .wr3_ready_o(wr3_ready),
+      
+      .rd0_data_o(rd0_data), .rd0_read_i(rd0_read), .rd0_flags_o(rd0_flags), .rd0_ready_o(rd0_ready),
+      .rd1_data_o(rd1_data), .rd1_read_i(rd1_read), .rd1_flags_o(rd1_flags), .rd1_ready_o(rd1_ready),
+      .rd2_data_o(rd2_data), .rd2_read_i(rd2_read), .rd2_flags_o(rd2_flags), .rd2_ready_o(rd2_ready),
+      .rd3_data_o(rd3_data), .rd3_read_i(rd3_read), .rd3_flags_o(rd3_flags), .rd3_ready_o(rd3_ready)
+      );
+   
+endmodule // buffer_pool_tb
diff --git a/fpga/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/fpga/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
new file mode 100644
index 000000000..5f9aeff9b
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
@@ -0,0 +1,76 @@
+
+module fifo19_to_fifo36
+  (input clk, input reset, input clear,
+   input [18:0] f19_datain,
+   input f19_src_rdy_i,
+   output f19_dst_rdy_o,
+
+   output [35:0] f36_dataout,
+   output f36_src_rdy_o,
+   input f36_dst_rdy_i,
+   output [31:0] debug
+   );
+
+   reg 	 f36_sof, f36_eof, f36_occ;
+   
+   reg [1:0] state;
+   reg [15:0] dat0, dat1;
+
+   wire f19_sof  = f19_datain[16];
+   wire f19_eof  = f19_datain[17];
+   wire f19_occ  = f19_datain[18];
+
+   wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & ((state==0)|xfer_out))
+       f36_sof 	<= f19_sof;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & ((state != 2)|xfer_out))
+       f36_eof 	<= f19_eof;
+
+   always @(posedge clk)    // FIXME check this
+     if(f19_eof)
+       f36_occ 	<= {state[0],f19_occ};
+     else
+       f36_occ 	<= 0;
+   
+   always @(posedge clk)
+     if(reset)
+       state 	<= 0;
+     else
+       if(f19_src_rdy_i)
+	 case(state)
+	   0 : 
+	     if(f19_eof)
+	       state <= 2;
+	     else
+	       state <= 1;
+	   1 : 
+	     state <= 2;
+	   2 : 
+	     if(xfer_out)
+	       if(~f19_eof)
+		 state 	   <= 1;
+	   // remain in state 2 if we are at eof
+	 endcase // case(state)
+       else
+	 if(xfer_out)
+	   state 	   <= 0;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & (state==1))
+       dat1 		   <= f19_datain;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & ((state==0) | xfer_out))
+       dat0 		   <= f19_datain;
+   
+   assign    f19_dst_rdy_o  = xfer_out | (state != 2);
+   assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+   assign    f36_src_rdy_o  = (state == 2);
+
+   assign    debug = state;
+   
+endmodule // fifo19_to_fifo36
diff --git a/fpga/usrp2/control_lib/newfifo/fifo19_to_ll8.v b/fpga/usrp2/control_lib/newfifo/fifo19_to_ll8.v
new file mode 100644
index 000000000..4707f7523
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo19_to_ll8.v
@@ -0,0 +1,53 @@
+
+module fifo19_to_ll8
+  (input clk, input reset, input clear,
+   input [18:0] f19_data,
+   input f19_src_rdy_i,
+   output f19_dst_rdy_o,
+
+   output reg [7:0] ll_data,
+   output ll_sof_n,
+   output ll_eof_n,
+   output ll_src_rdy_n,
+   input ll_dst_rdy_n);
+
+   wire  ll_sof, ll_eof, ll_src_rdy;
+   assign ll_sof_n 	= ~ll_sof;
+   assign ll_eof_n 	= ~ll_eof;
+   assign ll_src_rdy_n 	= ~ll_src_rdy;
+   wire ll_dst_rdy 	= ~ll_dst_rdy_n;
+
+   wire   f19_sof 	= f19_data[16];
+   wire   f19_eof 	= f19_data[17];
+   wire   f19_occ 	= f19_data[18];
+   
+   wire advance, end_early;
+   reg state;
+
+   always @(posedge clk)
+     if(reset)
+       state 	  <= 0;
+     else
+       if(advance)
+	 if(ll_eof)
+	   state  <= 0;
+	 else
+	   state  <= state + 1;
+
+   always @*
+     case(state)
+       0 : ll_data = f19_data[15:8];
+       1 : ll_data = f19_data[7:0];
+       default : ll_data = f19_data[15:8];
+       endcase // case (state)
+   
+   assign ll_sof 	 = (state==0) & f19_sof;
+   assign ll_eof 	 = f19_eof & ((f19_occ==1)|(state==1));
+   
+   assign ll_src_rdy 	 = f19_src_rdy_i;
+
+   assign advance 	 = ll_src_rdy & ll_dst_rdy;
+   assign f19_dst_rdy_o  = advance & ((state==1)|ll_eof);
+   
+endmodule // fifo19_to_ll8
+
diff --git a/fpga/usrp2/control_lib/newfifo/fifo36_to_fifo18.v b/fpga/usrp2/control_lib/newfifo/fifo36_to_fifo18.v
new file mode 100644
index 000000000..b636ab9ca
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo36_to_fifo18.v
@@ -0,0 +1,40 @@
+
+module fifo36_to_fifo18
+  (input clk, input reset, input clear,
+   input [35:0] f36_datain,
+   input f36_src_rdy_i,
+   output f36_dst_rdy_o,
+   
+   output [17:0] f18_dataout,
+   output f18_src_rdy_o,
+   input f18_dst_rdy_i );
+
+   wire   f36_sof  = f36_datain[32];
+   wire   f36_eof  = f36_datain[33];
+   wire   f36_occ  = f36_datain[35:34];
+
+   reg phase;
+
+   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
+   
+   assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+   assign f18_dataout[16]  = phase ? 0 : f36_sof;
+   assign f18_dataout[17]  = phase ? f36_eof : half_line;
+   
+   assign f18_src_rdy_o    = f36_src_rdy_i;
+   assign f36_dst_rdy_o    = (phase | half_line) & f18_dst_rdy_i;
+	
+   wire f18_xfer 	   = f18_src_rdy_o & f18_dst_rdy_i;
+   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+
+   always @(posedge clk)
+     if(reset)
+       phase 		  <= 0;
+     else if(f36_xfer)
+       phase 		  <= 0;
+     else if(f18_xfer)
+       phase 		  <= 1;
+   
+       
+endmodule // fifo36_to_fifo18
+
diff --git a/fpga/usrp2/control_lib/newfifo/fifo36_to_fifo19.v b/fpga/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
new file mode 100644
index 000000000..de249aaeb
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
@@ -0,0 +1,41 @@
+
+module fifo36_to_fifo19
+  (input clk, input reset, input clear,
+   input [35:0] f36_datain,
+   input f36_src_rdy_i,
+   output f36_dst_rdy_o,
+   
+   output [18:0] f19_dataout,
+   output f19_src_rdy_o,
+   input f19_dst_rdy_i );
+
+   wire   f36_sof  = f36_datain[32];
+   wire   f36_eof  = f36_datain[33];
+   wire   f36_occ  = f36_datain[35:34];
+
+   reg phase;
+
+   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
+   
+   assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+   assign f19_dataout[16]  = phase ? 0 : f36_sof;
+   assign f19_dataout[17]  = phase ? f36_eof : half_line;
+   assign f19_dataout[18]  = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
+   
+   assign f19_src_rdy_o    = f36_src_rdy_i;
+   assign f36_dst_rdy_o    = (phase | half_line) & f19_dst_rdy_i;
+	
+   wire f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+
+   always @(posedge clk)
+     if(reset)
+       phase 		  <= 0;
+     else if(f36_xfer)
+       phase 		  <= 0;
+     else if(f19_xfer)
+       phase 		  <= 1;
+   
+       
+endmodule // fifo36_to_fifo19
+
diff --git a/fpga/usrp2/control_lib/newfifo/fifo36_to_ll8.v b/fpga/usrp2/control_lib/newfifo/fifo36_to_ll8.v
new file mode 100644
index 000000000..0dee1dfc6
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo36_to_ll8.v
@@ -0,0 +1,60 @@
+
+module fifo36_to_ll8
+  (input clk, input reset, input clear,
+   input [35:0] f36_data,
+   input f36_src_rdy_i,
+   output f36_dst_rdy_o,
+
+   output reg [7:0] ll_data,
+   output ll_sof_n,
+   output ll_eof_n,
+   output ll_src_rdy_n,
+   input ll_dst_rdy_n,
+
+   output [31:0] debug);
+
+   wire  ll_sof, ll_eof, ll_src_rdy;
+   assign ll_sof_n = ~ll_sof;
+   assign ll_eof_n = ~ll_eof;
+   assign ll_src_rdy_n = ~ll_src_rdy;
+   wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+   wire   f36_sof = f36_data[32];
+   wire   f36_eof = f36_data[33];
+   wire   f36_occ = f36_data[35:34];
+   wire advance, end_early;
+   reg [1:0] state;
+   assign debug    = {29'b0,state};
+
+   always @(posedge clk)
+     if(reset)
+       state 	  <= 0;
+     else
+       if(advance)
+	 if(ll_eof)
+	   state  <= 0;
+	 else
+	   state  <= state + 1;
+
+   always @*
+     case(state)
+       0 : ll_data = f36_data[31:24];
+       1 : ll_data = f36_data[23:16];
+       2 : ll_data = f36_data[15:8];
+       3 : ll_data = f36_data[7:0];
+       default : ll_data = f36_data[31:24];
+       endcase // case (state)
+   
+   assign ll_sof 	 = (state==0) & f36_sof;
+   assign ll_eof 	 = f36_eof & (((state==0)&(f36_occ==1)) |
+			       ((state==1)&(f36_occ==2)) |
+			       ((state==2)&(f36_occ==3)) |
+			       (state==3));
+   
+   assign ll_src_rdy 	 = f36_src_rdy_i;
+
+   assign advance 	 = ll_src_rdy & ll_dst_rdy;
+   assign f36_dst_rdy_o  = advance & ((state==3)|ll_eof);
+   assign debug 	 = state;
+   
+endmodule // ll8_to_fifo36
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_2clock.v b/fpga/usrp2/control_lib/newfifo/fifo_2clock.v
new file mode 100644
index 000000000..34c85ccb4
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_2clock.v
@@ -0,0 +1,117 @@
+
+// FIXME ignores the AWIDTH (fifo size) parameter
+
+module fifo_2clock
+  #(parameter WIDTH=36, SIZE=6)
+   (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+    input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+    input arst);
+   
+   wire [SIZE:0] level_rclk, level_wclk; // xilinx adds an extra bit if you ask for accurate levels
+   wire 	 full, empty, write, read;
+
+   assign dst_rdy_o  = ~full;
+   assign src_rdy_o  = ~empty;
+   assign write      = src_rdy_i & dst_rdy_o;
+   assign read 	     = src_rdy_o & dst_rdy_i;
+
+   generate
+      if(WIDTH==36)
+	if(SIZE==9)
+	  fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+	       (.rst(arst),
+		.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else if(SIZE==11)
+	  fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk 
+		     (.rst(arst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else if(SIZE==6)
+	  fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk 
+		     (.rst(arst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else
+	  fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+	       (.rst(arst),
+		.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      else if((WIDTH==19)|(WIDTH==18))
+	if(SIZE==4)
+	  fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
+		     (.rst(arst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+   endgenerate
+   
+   assign occupied  = {{(16-SIZE-1){1'b0}},level_rclk};
+   assign space     = ((1<<SIZE)+1)-level_wclk;
+   
+endmodule // fifo_2clock
+
+/*
+`else
+   // ISE sucks, so the following doesn't work properly
+
+   reg [AWIDTH-1:0] wr_addr, rd_addr;
+   wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
+   wire [AWIDTH-1:0] next_rd_addr;
+   wire 	    enb_read;
+   
+   // Write side management
+   wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
+   always @(posedge wclk or posedge arst)
+     if(arst)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= next_wr_addr;
+   assign 	    full = (next_wr_addr == rd_addr_wclk);
+
+   //  RAM for data storage.  Data out is registered, complicating the
+   //     read side logic
+   ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
+     (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
+      .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
+
+   // Read side management
+   reg 		    data_valid;
+   assign 	    empty = ~data_valid;
+   assign 	    next_rd_addr = rd_addr + data_valid;
+   assign 	    enb_read = read | ~data_valid;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       rd_addr <= 0;
+     else if(read)
+       rd_addr <= rd_addr + 1;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       data_valid <= 0;
+     else
+       if(read & (next_rd_addr == wr_addr_rclk))
+	 data_valid <= 0;
+       else if(next_rd_addr != wr_addr_rclk)
+	 data_valid <= 1;
+	 
+   // Send pointers across clock domains via gray code
+   gray_send #(.WIDTH(AWIDTH)) send_wr_addr
+     (.clk_in(wclk),.addr_in(wr_addr),
+      .clk_out(rclk),.addr_out(wr_addr_rclk) );
+   
+   gray_send #(.WIDTH(AWIDTH)) send_rd_addr
+     (.clk_in(rclk),.addr_in(rd_addr),
+      .clk_out(wclk),.addr_out(rd_addr_wclk) );
+
+   // Generate fullness info, these are approximate and may be delayed 
+   // and are only for higher-level flow control.  
+   // Only full and empty are guaranteed exact.
+   always @(posedge wclk) 
+     level_wclk <= wr_addr - rd_addr_wclk;
+   always @(posedge rclk) 
+     level_rclk <= wr_addr_rclk - rd_addr;
+`endif
+endmodule // fifo_2clock
+
+*/
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_2clock_cascade.v b/fpga/usrp2/control_lib/newfifo/fifo_2clock_cascade.v
new file mode 100644
index 000000000..5ce726977
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_2clock_cascade.v
@@ -0,0 +1,35 @@
+
+module fifo_2clock_cascade
+  #(parameter WIDTH=32, SIZE=9)
+   (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
+    input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
+    input arst);
+   
+   wire [WIDTH-1:0] data_int1, data_int2;
+   wire 	    src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2;
+   wire [SIZE-1:0]  level_wclk, level_rclk;
+   wire [4:0] 	    s1_space, s1_occupied, s2_space, s2_occupied;
+   wire [15:0] 	    l_space, l_occupied;
+   
+   fifo_short #(.WIDTH(WIDTH)) shortfifo
+     (.clk(wclk), .reset(arst), .clear(0),
+      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1),
+      .space(s1_space), .occupied(s1_occupied) );
+   
+   fifo_2clock #(.WIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock
+     (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space),
+      .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied),
+      .arst(arst) );
+   
+   fifo_short #(.WIDTH(WIDTH)) shortfifo2
+     (.clk(rclk), .reset(arst), .clear(0),
+      .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2),
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+      .space(s2_space), .occupied(s2_occupied));
+
+   // Be conservative -- Only advertise space from input side of fifo, occupied from output side
+   assign 	    space = {11'b0,s1_space} + l_space;
+   assign 	    occupied = {11'b0,s2_occupied} + l_occupied;
+   
+endmodule // fifo_2clock_cascade
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_cascade.v b/fpga/usrp2/control_lib/newfifo/fifo_cascade.v
new file mode 100644
index 000000000..fdd8449bc
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_cascade.v
@@ -0,0 +1,52 @@
+
+
+// This FIFO exists to provide an intermediate point for the data on its
+// long trek from one RAM (in the buffer pool) to another (in the longfifo)
+// The shortfifo is more flexible in its placement since it is based on
+// distributed RAM
+
+// This one has the shortfifo on both the in and out sides.
+module fifo_cascade
+  #(parameter WIDTH=32, SIZE=9)
+    (input clk, input reset, input clear,
+     input [WIDTH-1:0] datain,
+     input src_rdy_i,
+     output dst_rdy_o,
+     output [WIDTH-1:0] dataout,
+     output src_rdy_o,
+     input dst_rdy_i,
+     output [15:0] space,
+     output [15:0] occupied);
+
+   wire [WIDTH-1:0] data_int, data_int2;
+   wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2;
+   
+   wire [4:0] 	    s1_space, s1_occupied, s2_space, s2_occupied;
+   wire [15:0] 	    l_space, l_occupied;
+   
+   fifo_short #(.WIDTH(WIDTH)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1),
+      .space(s1_space),.occupied(s1_occupied) );
+      
+   fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1),
+      .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2),
+      .space(l_space),.occupied(l_occupied) );
+   
+   fifo_short #(.WIDTH(WIDTH)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2),
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+      .space(s2_space),.occupied(s2_occupied) );
+   
+   assign 	    space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
+   assign 	    occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied;
+      
+endmodule // cascadefifo2
+
+
+
+
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_long.v b/fpga/usrp2/control_lib/newfifo/fifo_long.v
new file mode 100644
index 000000000..0426779f6
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_long.v
@@ -0,0 +1,148 @@
+
+// FIFO intended to be interchangeable with shortfifo, but
+//  based on block ram instead of SRL16's
+//  only one clock domain
+
+// Port A is write port, Port B is read port
+
+module fifo_long
+  #(parameter WIDTH=32, SIZE=9)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] datain,
+    input src_rdy_i,
+    output dst_rdy_o,
+    output [WIDTH-1:0] dataout,
+    output src_rdy_o,
+    input dst_rdy_i,
+    
+    output reg [15:0] space,
+    output reg [15:0] occupied);
+   
+   wire write 	     = src_rdy_i & dst_rdy_o;
+   wire read 	     = dst_rdy_i & src_rdy_o;
+   wire full, empty;
+   
+   assign dst_rdy_o  = ~full;
+   assign src_rdy_o  = ~empty;
+   
+   // Read side states
+   localparam 	  EMPTY = 0;
+   localparam 	  PRE_READ = 1;
+   localparam 	  READING = 2;
+
+   reg [SIZE-1:0] wr_addr, rd_addr;
+   reg [1:0] 	  read_state;
+
+   reg 	  empty_reg, full_reg;
+   always @(posedge clk)
+     if(reset)
+       wr_addr <= 0;
+     else if(clear)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= wr_addr + 1;
+
+   ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+     ram (.clka(clk),
+	  .ena(1'b1),
+	  .wea(write),
+	  .addra(wr_addr),
+	  .dia(datain),
+	  .doa(),
+
+	  .clkb(clk),
+	  .enb((read_state==PRE_READ)|read),
+	  .web(0),
+	  .addrb(rd_addr),
+	  .dib(0),
+	  .dob(dataout));
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  read_state <= EMPTY;
+	  rd_addr <= 0;
+	  empty_reg <= 1;
+       end
+     else
+       if(clear)
+	 begin
+	    read_state <= EMPTY;
+	    rd_addr <= 0;
+	    empty_reg <= 1;
+	 end
+       else 
+	 case(read_state)
+	   EMPTY :
+	     if(write)
+	       begin
+		  //rd_addr <= wr_addr;
+		  read_state <= PRE_READ;
+	       end
+	   PRE_READ :
+	     begin
+		read_state <= READING;
+		empty_reg <= 0;
+		rd_addr <= rd_addr + 1;
+	     end
+	   
+	   READING :
+	     if(read)
+	       if(rd_addr == wr_addr)
+		 begin
+		    empty_reg <= 1;
+		    if(write)
+		      read_state <= PRE_READ;
+		    else
+		      read_state <= EMPTY;
+		 end
+	       else
+		 rd_addr <= rd_addr + 1;
+	 endcase // case(read_state)
+
+   wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
+   wire 	   becoming_full = wr_addr == dont_write_past_me;
+     
+   always @(posedge clk)
+     if(reset)
+       full_reg <= 0;
+     else if(clear)
+       full_reg <= 0;
+     else if(read & ~write)
+       full_reg <= 0;
+     //else if(write & ~read & (wr_addr == (rd_addr-3)))
+     else if(write & ~read & becoming_full)
+       full_reg <= 1;
+
+   //assign empty = (read_state != READING);
+   assign empty = empty_reg;
+
+   // assign full = ((rd_addr - 1) == wr_addr);
+   assign full = full_reg;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE)-2;
+   always @(posedge clk)
+     if(reset)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+   
+endmodule // fifo_long
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_new_tb.vcd b/fpga/usrp2/control_lib/newfifo/fifo_new_tb.vcd
new file mode 100644
index 000000000..796889e7d
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_new_tb.vcd
@@ -0,0 +1,5506 @@
+$date
+	Thu Mar 19 17:21:11 2009
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module fifo_new_tb $end
+$var wire 1 ! dst_rdy_f36i $end
+$var wire 36 " f36_in [35:0] $end
+$var wire 36 # i1 [35:0] $end
+$var wire 1 $ i1_dr $end
+$var wire 1 % i1_sr $end
+$var wire 19 & i2 [18:0] $end
+$var wire 1 ' i2_dr $end
+$var wire 1 ( i2_sr $end
+$var wire 19 ) i3 [18:0] $end
+$var wire 1 * i3_dr $end
+$var wire 1 + i3_sr $end
+$var wire 36 , i4 [35:0] $end
+$var wire 1 - i4_sr $end
+$var wire 8 . ll_data [7:0] $end
+$var wire 1 / ll_dst_rdy_n $end
+$var wire 1 0 ll_eof_n $end
+$var wire 1 1 ll_sof_n $end
+$var wire 1 2 ll_src_rdy_n $end
+$var reg 1 3 clear $end
+$var reg 1 4 clk $end
+$var reg 16 5 count [15:0] $end
+$var reg 1 6 dst_rdy_f36o $end
+$var reg 32 7 f36_data [31:0] $end
+$var reg 1 8 f36_eof $end
+$var reg 2 9 f36_occ [1:0] $end
+$var reg 1 : f36_sof $end
+$var reg 1 ; i4_dr $end
+$var reg 1 < rst $end
+$var reg 1 = src_rdy_f36i $end
+$scope module fifo_short1 $end
+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 36 @ datain [35:0] $end
+$var wire 36 A dataout [35:0] $end
+$var wire 1 $ dst_rdy_i $end
+$var wire 1 ! dst_rdy_o $end
+$var wire 1 B read $end
+$var wire 1 C reset $end
+$var wire 1 D src_rdy_i $end
+$var wire 1 % src_rdy_o $end
+$var wire 1 E write $end
+$var reg 4 F a [3:0] $end
+$var reg 1 G empty $end
+$var reg 1 H full $end
+$var reg 5 I occupied [4:0] $end
+$var reg 5 J space [4:0] $end
+$scope begin gen_srl16[0] $end
+$scope module srl16e $end
+$var wire 1 K A0 $end
+$var wire 1 L A1 $end
+$var wire 1 M A2 $end
+$var wire 1 N A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 O D $end
+$var wire 1 P Q $end
+$var reg 16 Q data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[1] $end
+$scope module srl16e $end
+$var wire 1 R A0 $end
+$var wire 1 S A1 $end
+$var wire 1 T A2 $end
+$var wire 1 U A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 V D $end
+$var wire 1 W Q $end
+$var reg 16 X data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[2] $end
+$scope module srl16e $end
+$var wire 1 Y A0 $end
+$var wire 1 Z A1 $end
+$var wire 1 [ A2 $end
+$var wire 1 \ A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 ] D $end
+$var wire 1 ^ Q $end
+$var reg 16 _ data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[3] $end
+$scope module srl16e $end
+$var wire 1 ` A0 $end
+$var wire 1 a A1 $end
+$var wire 1 b A2 $end
+$var wire 1 c A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 d D $end
+$var wire 1 e Q $end
+$var reg 16 f data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[4] $end
+$scope module srl16e $end
+$var wire 1 g A0 $end
+$var wire 1 h A1 $end
+$var wire 1 i A2 $end
+$var wire 1 j A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 k D $end
+$var wire 1 l Q $end
+$var reg 16 m data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[5] $end
+$scope module srl16e $end
+$var wire 1 n A0 $end
+$var wire 1 o A1 $end
+$var wire 1 p A2 $end
+$var wire 1 q A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 r D $end
+$var wire 1 s Q $end
+$var reg 16 t data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[6] $end
+$scope module srl16e $end
+$var wire 1 u A0 $end
+$var wire 1 v A1 $end
+$var wire 1 w A2 $end
+$var wire 1 x A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 y D $end
+$var wire 1 z Q $end
+$var reg 16 { data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[7] $end
+$scope module srl16e $end
+$var wire 1 | A0 $end
+$var wire 1 } A1 $end
+$var wire 1 ~ A2 $end
+$var wire 1 !" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 "" D $end
+$var wire 1 #" Q $end
+$var reg 16 $" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[8] $end
+$scope module srl16e $end
+$var wire 1 %" A0 $end
+$var wire 1 &" A1 $end
+$var wire 1 '" A2 $end
+$var wire 1 (" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 )" D $end
+$var wire 1 *" Q $end
+$var reg 16 +" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[9] $end
+$scope module srl16e $end
+$var wire 1 ," A0 $end
+$var wire 1 -" A1 $end
+$var wire 1 ." A2 $end
+$var wire 1 /" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 0" D $end
+$var wire 1 1" Q $end
+$var reg 16 2" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[10] $end
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diff --git a/fpga/usrp2/control_lib/newfifo/fifo_short.v b/fpga/usrp2/control_lib/newfifo/fifo_short.v
new file mode 100644
index 000000000..53a7603c7
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_short.v
@@ -0,0 +1,95 @@
+
+module fifo_short
+  #(parameter WIDTH=32)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] datain,
+    input src_rdy_i,
+    output dst_rdy_o,
+    output [WIDTH-1:0] dataout,
+    output src_rdy_o,
+    input dst_rdy_i,
+    
+    output reg [4:0] space,
+    output reg [4:0] occupied);
+
+   reg full, empty;
+   wire write 	     = src_rdy_i & dst_rdy_o;
+   wire read 	     = dst_rdy_i & src_rdy_o;
+
+   assign dst_rdy_o  = ~full;
+   assign src_rdy_o  = ~empty;
+   
+   reg [3:0] 	  a;
+   genvar 	  i;
+   
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl16
+	   SRL16E
+	     srl16e(.Q(dataout[i]),
+		    .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+		    .CE(write),.CLK(clk),.D(datain[i]));
+	end
+   endgenerate
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full <= 0;
+       end
+     else if(clear)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full<= 0;
+       end
+     else if(read & ~write)
+       begin
+	  full <= 0;
+	  if(a==0)
+	    empty <= 1;
+	  else
+	    a <= a - 1;
+       end
+     else if(write & ~read)
+       begin
+	  empty <= 0;
+	  if(~empty)
+	    a <= a + 1;
+	  if(a == 14)
+	    full <= 1;
+       end
+
+   // NOTE will fail if you write into a full fifo or read from an empty one
+
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
+   
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(reset)
+       space <= 16;
+     else if(clear)
+       space <= 16;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+      
+endmodule // fifo_short
+
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_spec.txt b/fpga/usrp2/control_lib/newfifo/fifo_spec.txt
new file mode 100644
index 000000000..133b9fa8e
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_spec.txt
@@ -0,0 +1,36 @@
+
+
+FIFO and Buffer Interface Spec
+
+Buffer Interface Data Wires -- matches fifo36
+     DATA[31:0]
+     FLAGS[3:0]
+     Bit 0	SOP
+     Bit 1	EOP
+	If SOP=1 && EOP=1, OCC contains error flags
+     Bits 3:2	OCC[1:0] --> 00 = all 4 bytes
+		     01 = 1 byte
+		     10 = 2 bytes
+		     11 = 3 bytes
+
+fifo36 -->  {OCC[1:0],EOP,SOP,DATA[31:0]}
+       OCC same as buffer interface
+
+fifo19 -->  {OCC,EOP,SOP,DATA[15:0]}    
+       Doesn't fit well into BRAM, dist RAM ok
+       OCC = 1 means last word is half full
+	   = 0 means last word is full
+
+fifo18 -->  {EOP,SOP,DATA[15:0]}
+       No half-word capability?  Should we drop sop instead?
+
+Control Wires - Data into FIFO
+	SRC_RDY_i    Upstream has data for me
+	DST_RDY_o    I have space
+		     Transfer occurs if SRC_RDI_i && DST_RDY_o
+	
+Control Wires - Data out of FIFO
+	SRC_RDY_o    I have data for downstream
+	DST_RDY_i    Downstream has space
+		     Transfer occurs if SRC_RDI_o && DST_RDY_i
+	
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_tb.v b/fpga/usrp2/control_lib/newfifo/fifo_tb.v
new file mode 100644
index 000000000..f561df7fa
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/fifo_tb.v
@@ -0,0 +1,158 @@
+module fifo_new_tb();
+   
+   reg clk = 0;
+   reg rst = 1;
+   reg clear = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data = 0;
+   reg [1:0] f36_occ = 0;
+   reg f36_sof = 0, f36_eof = 0;
+   
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg src_rdy_f36i  = 0;
+   wire dst_rdy_f36i;
+
+   wire [35:0] f36_out, f36_out2;
+   wire src_rdy_f36o;
+   reg dst_rdy_f36o  = 0;
+   
+   //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+   //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+   wire i1_sr, i1_dr;
+   wire i2_sr, i2_dr;
+   wire i3_sr, i3_dr;
+   reg i4_dr = 0;
+   wire i4_sr;
+      
+   wire [35:0] i1, i4;
+   wire [18:0] i2, i3;
+   
+   wire [7:0] ll_data;
+   wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+   
+   fifo_short #(.WIDTH(36)) fifo_short1
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+      .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+   fifo19_to_ll8 fifo19_to_ll8
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+   ll8_to_fifo19 ll8_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+      .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+      .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+     
+   task ReadFromFIFO36;
+      begin
+	 $display("Read from FIFO36");
+	 #1 i4_dr <= 1;
+	 while(1)
+	   begin
+	      while(~i4_sr)
+		@(posedge clk);
+	      $display("Read: %h",i4);
+	      @(posedge clk);
+	   end
+      end
+   endtask // ReadFromFIFO36
+
+   reg [15:0] count;
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+	 count 	      <= 4;
+	 src_rdy_f36i <= 1;
+	 f36_data     <= data_start;
+	 f36_sof      <= 1;
+	 f36_eof      <= 0;
+	 f36_occ      <= 0;
+	
+	 $display("Put Packet in FIFO36");
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 $display("PPI_FIFO36: Entered First Line");
+	 f36_sof <= 0;
+	 while(count+4 < data_len)
+	   begin
+	      f36_data <= f36_data + 32'h01010101;
+	      count    <= count + 4;
+	      while(~dst_rdy_f36i)
+		@(posedge clk);
+	      @(posedge clk);
+	      $display("PPI_FIFO36: Entered New Line");
+	   end
+	 f36_data  <= f36_data + 32'h01010101;
+	 f36_eof   <= 1;
+	 if(count + 4 == data_len)
+	   f36_occ <= 0;
+	 else if(count + 3 == data_len)
+	   f36_occ <= 3;
+	 else if(count + 2 == data_len)
+	   f36_occ <= 2;
+	 else
+	   f36_occ <= 1;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 f36_occ      <= 0;
+	 f36_eof      <= 0;
+	 f36_data     <= 0;
+	 src_rdy_f36i <= 0;
+	 $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("fifo_new_tb.vcd");
+   initial $dumpvars(0,fifo_new_tb);
+
+   initial
+     begin
+	@(negedge rst);
+	//#10000;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	@(posedge clk);
+	PutPacketInFIFO36(32'hA0B0C0D0,12);
+	@(posedge clk);
+	@(posedge clk);
+	#10000;
+	@(posedge clk);
+	PutPacketInFIFO36(32'hE0F0A0B0,36);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // longfifo_tb
diff --git a/fpga/usrp2/control_lib/newfifo/ll8_shortfifo.v b/fpga/usrp2/control_lib/newfifo/ll8_shortfifo.v
new file mode 100644
index 000000000..39ada9a4f
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/ll8_shortfifo.v
@@ -0,0 +1,13 @@
+
+
+module ll8_shortfifo
+  (input clk, input reset, input clear,
+   input [7:0] datain, input sof_i, input eof_i, input error_i, input src_rdy_i, output dst_rdy_o,
+   output [7:0] dataout, output sof_o, output eof_o, output error_o, output src_rdy_o, input dst_rdy_i);
+
+   fifo_short #(.WIDTH(11)) fifo_short
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain({error_i,eof_i,sof_i,datain}), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout({error_o,eof_o,sof_o,dataout}), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
+
+endmodule // ll8_shortfifo
diff --git a/fpga/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/fpga/usrp2/control_lib/newfifo/ll8_to_fifo19.v
new file mode 100644
index 000000000..af3b91afb
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/ll8_to_fifo19.v
@@ -0,0 +1,73 @@
+
+module ll8_to_fifo19
+  (input clk, input reset, input clear,
+   input [7:0] ll_data,
+   input ll_sof_n,
+   input ll_eof_n,
+   input ll_src_rdy_n,
+   output ll_dst_rdy_n,
+
+   output [18:0] f19_data,
+   output f19_src_rdy_o,
+   input f19_dst_rdy_i );
+   
+   localparam XFER_EMPTY       = 0;
+   localparam XFER_HALF        = 1;
+   localparam XFER_HALF_WRITE  = 3;
+   
+   // Why anybody would use active low in an FPGA is beyond me...
+   wire  ll_sof      = ~ll_sof_n;
+   wire  ll_eof      = ~ll_eof_n;
+   wire  ll_src_rdy  = ~ll_src_rdy_n;
+   wire  ll_dst_rdy;
+   assign    ll_dst_rdy_n  = ~ll_dst_rdy;
+   
+   wire  xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire  xfer_in 	   = ll_src_rdy & ll_dst_rdy; 
+   
+   reg 	 hold_sof;
+   wire  f19_sof, f19_eof, f19_occ;
+   
+   reg [1:0] state;
+   reg [7:0] hold_reg;
+   
+   always @(posedge clk)
+     if(ll_src_rdy & (state==XFER_EMPTY))
+       hold_reg 	      <= ll_data;
+   
+   always @(posedge clk)
+     if(ll_sof & (state==XFER_EMPTY))
+       hold_sof 	      <= 1;
+     else if(xfer_out)
+       hold_sof 	      <= 0;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state 		      <= XFER_EMPTY;
+     else
+       case(state)
+	 XFER_EMPTY :
+	   if(ll_src_rdy)
+	     if(ll_eof)
+	       state 	      <= XFER_HALF_WRITE;
+	     else
+	       state 	      <= XFER_HALF;
+	 XFER_HALF :
+	   if(ll_src_rdy & f19_dst_rdy_i)
+	       state 	      <= XFER_EMPTY;
+         XFER_HALF_WRITE :
+	   if(f19_dst_rdy_i)
+	     state 	<= XFER_EMPTY;
+       endcase // case (state)
+      
+   assign ll_dst_rdy 	 = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
+   assign f19_src_rdy_o  = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+   
+   assign f19_sof 	 = hold_sof | (ll_sof & (state==XFER_HALF));
+   assign f19_eof 	 = (state == XFER_HALF_WRITE) | ll_eof;
+   assign f19_occ 	 = (state == XFER_HALF_WRITE);
+   
+   assign f19_data 	 = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
+      
+endmodule // ll8_to_fifo19
+
diff --git a/fpga/usrp2/control_lib/newfifo/ll8_to_fifo36.v b/fpga/usrp2/control_lib/newfifo/ll8_to_fifo36.v
new file mode 100644
index 000000000..108daa903
--- /dev/null
+++ b/fpga/usrp2/control_lib/newfifo/ll8_to_fifo36.v
@@ -0,0 +1,97 @@
+
+module ll8_to_fifo36
+  (input clk, input reset, input clear,
+   input [7:0] ll_data,
+   input ll_sof_n,
+   input ll_eof_n,
+   input ll_src_rdy_n,
+   output ll_dst_rdy_n,
+
+   output [35:0] f36_data,
+   output f36_src_rdy_o,
+   input f36_dst_rdy_i );
+
+   wire f36_write    = f36_src_rdy_o & f36_dst_rdy_i;
+      
+   // Why anybody would use active low in an FPGA is beyond me...
+   wire  ll_sof      = ~ll_sof_n;
+   wire  ll_eof      = ~ll_eof_n;
+   wire  ll_src_rdy  = ~ll_src_rdy_n;
+   wire  ll_dst_rdy;
+   assign    ll_dst_rdy_n = ~ll_dst_rdy;
+
+   reg 	 f36_sof, f36_eof;
+   reg [1:0] f36_occ;
+   
+   
+   reg [2:0] state;
+   reg [7:0] dat0, dat1, dat2, dat3;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state==0)|f36_write))
+       f36_sof <= ll_sof;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state !=4)|f36_write))
+       f36_eof <= ll_eof;
+
+   always @(posedge clk)
+     if(ll_eof)
+       f36_occ <= state[1:0] + 1;
+     else
+       f36_occ <= 0;
+   
+   always @(posedge clk)
+     if(reset)
+       state   <= 0;
+     else
+       if(ll_src_rdy)
+	 case(state)
+	   0 : 
+	     if(ll_eof)
+	       state <= 4;
+	     else
+	       state <= 1;
+	   1 : 
+	     if(ll_eof)
+	       state <= 4;
+	     else
+	       state <= 2;
+	   2 : 
+	     if(ll_eof)
+	       state <= 4;
+	     else 
+	       state <= 3;
+	   3 : state <= 4;
+	   4 : 
+	     if(f36_dst_rdy_i)
+	       if(ll_eof)
+		 state 	   <= 4;
+	       else
+		 state 	   <= 1;
+	 endcase // case(state)
+       else
+	 if(f36_write)
+	   state 	   <= 0;
+
+   always @(posedge clk)
+     if(ll_src_rdy & (state==3))
+       dat3 		   <= ll_data;
+
+   always @(posedge clk)
+     if(ll_src_rdy & (state==2))
+       dat2 		   <= ll_data;
+
+   always @(posedge clk)
+     if(ll_src_rdy & (state==1))
+       dat1 		   <= ll_data;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state==0) | f36_write))
+       dat0 		   <= ll_data;
+   
+   assign    ll_dst_rdy     = f36_dst_rdy_i | (state != 4);
+   assign    f36_data 	    = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3};  // FIXME endianess
+   assign    f36_src_rdy_o  = (state == 4);
+      
+endmodule // ll8_to_fifo36
diff --git a/fpga/usrp2/control_lib/nsgpio.v b/fpga/usrp2/control_lib/nsgpio.v
new file mode 100644
index 000000000..937ea7020
--- /dev/null
+++ b/fpga/usrp2/control_lib/nsgpio.v
@@ -0,0 +1,107 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores Simple General Purpose IO core                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+
+module nsgpio
+  (input clk_i, input rst_i, 
+   input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] dat_i, 
+   output reg [31:0] dat_o, output reg ack_o,
+   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
+   inout [31:0] gpio
+   );
+
+   reg [63:0] 	ctrl;
+   reg [31:0] 	line;
+   reg [31:0] 	lgpio;               // LatchedGPIO pins
+   reg [31:0] 	ddr;
+   
+   wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       begin
+          ctrl <= 64'h0;
+          line <= 0;
+       end
+     else if (wb_wr)
+       case( adr_i[3:2] )
+	 2'b00 : 
+           line <= dat_i;
+	 2'b01 :
+	   ddr[31:0] <= dat_i;
+	 2'b10 :
+	   ctrl[63:32] <= dat_i;
+	 2'b11 :
+	   ctrl[31:0] <= dat_i;
+       endcase // case( adr_i[3:2] )
+   
+   always @(posedge clk_i)
+     case (adr_i[3:2])
+       2'b00 :
+	 dat_o <= lgpio;
+       2'b01 :
+	 dat_o <= ddr;
+       2'b10 :
+	 dat_o <= ctrl[63:32];
+       2'b11 :
+	 dat_o <= ctrl[31:0];
+     endcase // case(adr_i[3:2])
+   
+   always @(posedge clk_i or posedge rst_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & !ack_o;
+   
+   // latch GPIO input pins
+   always @(posedge clk_i)
+     lgpio <= gpio;
+   
+   // assign GPIO outputs
+   integer   n;
+   reg [31:0] igpio; // temporary internal signal
+   
+   always @(ctrl or line or debug_1 or debug_0 or atr)
+     for(n=0;n<32;n=n+1)
+       igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : 
+			     (ctrl[2*n] ?  atr[n] : line[n]) )
+	 : 1'bz;
+   
+   assign     gpio = igpio;
+   
+endmodule
+
diff --git a/fpga/usrp2/control_lib/oneshot_2clk.v b/fpga/usrp2/control_lib/oneshot_2clk.v
new file mode 100644
index 000000000..72f16a4b3
--- /dev/null
+++ b/fpga/usrp2/control_lib/oneshot_2clk.v
@@ -0,0 +1,35 @@
+
+// Retime a single bit from one clock domain to another
+// Guarantees that no matter what the relative clock rates, if the in signal is high for at least
+//   one clock cycle in the clk_in domain, then the out signal will be high for at least one
+//   clock cycle in the clk_out domain.  If the in signal goes high again before the process is done
+//   the behavior is undefined.  No other guarantees.  Designed for passing reset into a new
+//   clock domain.
+
+module oneshot_2clk
+  (input clk_in,
+   input in,
+   input clk_out,
+   output reg out);
+
+   reg 	  del_in = 0;
+   reg 	  sendit = 0, gotit = 0;
+   reg 	  sendit_d = 0, gotit_d = 0;
+   
+   always @(posedge clk_in) del_in <= in;
+
+   always @(posedge clk_in)
+     if(in & ~del_in)  // we have a positive edge
+       sendit <= 1;
+     else if(gotit)
+       sendit <= 0;
+
+   always @(posedge clk_out) sendit_d <= sendit;
+   always @(posedge clk_out) out <= sendit_d;
+
+   always @(posedge clk_in) gotit_d <= out;
+   always @(posedge clk_in) gotit <= gotit_d;
+
+endmodule // oneshot_2clk
+
+  
diff --git a/fpga/usrp2/control_lib/pic.v b/fpga/usrp2/control_lib/pic.v
new file mode 100644
index 000000000..9b9944d4a
--- /dev/null
+++ b/fpga/usrp2/control_lib/pic.v
@@ -0,0 +1,183 @@
+
+// Heavily modified by M. Ettus, 2009, little original code remains
+// Modified by M. Ettus, 2008 for 32 bit width
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores         Simple Programmable Interrupt Controller ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+//
+// This is a simple Programmable Interrupt Controller.
+// The number of interrupts is depending on the databus size.
+// There's one interrupt input per databit (i.e. 16 interrupts for a 16
+// bit databus).
+// All attached devices share the same CPU priority level.
+//
+//
+//
+// Registers:
+//
+// 0x00: EdgeEnable Register
+//       bits 7:0 R/W  Edge Enable '1' = edge triggered interrupt source
+//                                 '0' = level triggered interrupt source
+// 0x01: PolarityRegister
+//       bits 7:0 R/W Polarity     '1' = high level / rising edge
+//                                 '0' = low level / falling edge
+// 0x02: MaskRegister
+//       bits 7:0 R/W Mask         '1' = interrupt masked (disabled)
+//                                 '0' = interrupt not masked (enabled)
+// 0x03: PendingRegister
+//       bits 7:0 R/W Pending      '1' = interrupt pending
+//                                 '0' = no interrupt pending
+//
+// A CPU interrupt is generated when an interrupt is pending and its
+// MASK bit is cleared.
+//
+//
+//
+// HOWTO:
+//
+// Clearing pending interrupts:
+// Writing a '1' to a bit in the interrupt pending register clears the
+// interrupt. Make sure to clear the interrupt at the source before
+// writing to the interrupt pending register. Otherwise the interrupt
+// will be set again.
+//
+// Priority based interrupts:
+// Upon reception of an interrupt, check the interrupt register and
+// determine the highest priority interrupt. Mask all interrupts from the
+// current level to the lowest level. This negates the interrupt line, and
+// makes sure only interrupts with a higher level are triggered. After
+// completion of the interrupt service routine, clear the interrupt source,
+// the interrupt bit in the pending register, and restore the MASK register
+// to it's previous state.
+//
+// Addapt the core for fewer interrupt sources:
+// If less than 8 interrupt sources are required, than the 'is' parameter
+// can be set to the amount of required interrupts. Interrupts are mapped
+// starting at the LSBs. So only the 'is' LSBs per register are valid. All
+// other bits (i.e. the 8-'is' MSBs) are set to zero '0'.
+// Codesize is approximately linear to the amount of interrupts. I.e. using
+// 4 instead of 8 interrupt sources reduces the size by approx. half.
+//
+
+
+module pic
+  (input clk_i, input rst_i, input cyc_i, input stb_i,
+   input [2:0] adr_i, 
+   input we_i, 
+   input [31:0] dat_i, 
+   output reg [31:0] dat_o, 
+   output reg ack_o, 
+   output reg int_o,
+   input [31:0] irq
+   );
+
+   reg [31:0] 	pol, edgen, pending, mask;   // register bank
+   reg [31:0] 	lirq, dirq;                  // latched irqs, delayed latched irqs
+   
+   // latch interrupt inputs
+   always @(posedge clk_i)
+     lirq <=  irq;
+   
+   // generate delayed latched irqs
+   always @(posedge clk_i)
+     dirq <=  lirq;
+
+   // generate actual triggers
+   function trigger;
+      input 	edgen, pol, lirq, dirq;
+      reg 	edge_irq, level_irq;
+      begin
+	 edge_irq  = pol ? (lirq & ~dirq) : (dirq & ~lirq);
+	 level_irq = pol ? lirq : ~lirq;
+	 trigger = edgen ? edge_irq : level_irq;
+      end
+   endfunction
+   
+   reg  [31:0] irq_event;
+   integer     n;
+   always @(posedge clk_i)
+     for(n = 0; n < 32; n = n+1)
+       irq_event[n] <=  trigger(edgen[n], pol[n], lirq[n], dirq[n]);
+
+   // generate wishbone register bank writes
+   wire        wb_acc = cyc_i & stb_i;                   // WISHBONE access
+   wire        wb_wr  = wb_acc & we_i;                   // WISHBONE write access
+
+   always @(posedge clk_i)
+     if (rst_i)
+       begin
+          pol   <=  0;              // clear polarity register
+          edgen <=  0;              // clear edge enable register
+          mask  <=  0;              // mask all interrupts
+       end
+     else if(wb_wr)                               // wishbone write cycle??
+       case (adr_i) // synopsys full_case parallel_case
+         3'd0 : edgen <=  dat_i;        // EDGE-ENABLE register
+         3'd1 : pol   <=  dat_i;        // POLARITY register
+         3'd2 : mask  <=  dat_i;        // MASK register
+         3'd3 : ;                       // PENDING register is a special case (see below)
+	 3'd4 : ;                       // Priority encoded live (pending & ~mask)
+       endcase
+
+   // pending register is a special case
+   always @(posedge clk_i)
+     if (rst_i)
+       pending <=  0;            // clear all pending interrupts
+     else if ( wb_wr & (adr_i == 3'd3) )
+       pending <=  (pending & ~dat_i) | irq_event;
+     else
+       pending <=  pending | irq_event;
+
+   wire [31:0] live_enc;
+   priority_enc priority_enc ( .in(pending & ~mask), .out(live_enc) );
+   
+   always @(posedge clk_i)
+      case (adr_i) // synopsys full_case parallel_case
+        3'd0 : dat_o <= edgen;
+        3'd1 : dat_o <= pol;
+        3'd2 : dat_o <= mask;
+        3'd3 : dat_o <= pending;
+	3'd4 : dat_o <= live_enc;
+      endcase
+
+   always @(posedge clk_i)
+     ack_o <=  wb_acc & !ack_o;
+
+   always @(posedge clk_i)
+     if(rst_i)
+       int_o <=  0;
+     else
+       int_o <=  |(pending & ~mask);
+   
+endmodule
diff --git a/fpga/usrp2/control_lib/priority_enc.v b/fpga/usrp2/control_lib/priority_enc.v
new file mode 100644
index 000000000..916192445
--- /dev/null
+++ b/fpga/usrp2/control_lib/priority_enc.v
@@ -0,0 +1,44 @@
+
+module priority_enc
+  (input [31:0] in,
+   output reg [31:0] out);
+
+   always @*
+     casex(in)
+       32'b1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 31;
+       32'b01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 30;
+       32'b001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 29;
+       32'b0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 28;
+       32'b0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 27;
+       32'b0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 26;
+       32'b0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 25;
+       32'b0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 24;
+       32'b0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 23;
+       32'b0000_0000_01xx_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 22;
+       32'b0000_0000_001x_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 21;
+       32'b0000_0000_0001_xxxx_xxxx_xxxx_xxxx_xxxx : out <= 20;
+       32'b0000_0000_0000_1xxx_xxxx_xxxx_xxxx_xxxx : out <= 19;
+       32'b0000_0000_0000_01xx_xxxx_xxxx_xxxx_xxxx : out <= 18;
+       32'b0000_0000_0000_001x_xxxx_xxxx_xxxx_xxxx : out <= 17;
+       32'b0000_0000_0000_0001_xxxx_xxxx_xxxx_xxxx : out <= 16;
+       32'b0000_0000_0000_0000_1xxx_xxxx_xxxx_xxxx : out <= 15;
+       32'b0000_0000_0000_0000_01xx_xxxx_xxxx_xxxx : out <= 14;
+       32'b0000_0000_0000_0000_001x_xxxx_xxxx_xxxx : out <= 13;
+       32'b0000_0000_0000_0000_0001_xxxx_xxxx_xxxx : out <= 12;
+       32'b0000_0000_0000_0000_0000_1xxx_xxxx_xxxx : out <= 11;
+       32'b0000_0000_0000_0000_0000_01xx_xxxx_xxxx : out <= 10;
+       32'b0000_0000_0000_0000_0000_001x_xxxx_xxxx : out <=  9;
+       32'b0000_0000_0000_0000_0000_0001_xxxx_xxxx : out <=  8;
+       32'b0000_0000_0000_0000_0000_0000_1xxx_xxxx : out <=  7;
+       32'b0000_0000_0000_0000_0000_0000_01xx_xxxx : out <=  6;
+       32'b0000_0000_0000_0000_0000_0000_001x_xxxx : out <=  5;
+       32'b0000_0000_0000_0000_0000_0000_0001_xxxx : out <=  4;
+       32'b0000_0000_0000_0000_0000_0000_0000_1xxx : out <=  3;
+       32'b0000_0000_0000_0000_0000_0000_0000_01xx : out <=  2;
+       32'b0000_0000_0000_0000_0000_0000_0000_001x : out <=  1;
+       32'b0000_0000_0000_0000_0000_0000_0000_0001 : out <=  0;
+       32'b0000_0000_0000_0000_0000_0000_0000_0000 : out <= 32'hFFFF_FFFF;
+       default : out <= 32'hFFFF_FFFF;
+     endcase // casex (in)
+   
+endmodule // priority_enc
diff --git a/fpga/usrp2/control_lib/ram_2port.v b/fpga/usrp2/control_lib/ram_2port.v
new file mode 100644
index 000000000..3716a7c8a
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_2port.v
@@ -0,0 +1,42 @@
+
+
+module ram_2port
+  #(parameter DWIDTH=32,
+    parameter AWIDTH=9)
+    (input clka,
+     input ena,
+     input wea,
+     input [AWIDTH-1:0] addra,
+     input [DWIDTH-1:0] dia,
+     output reg [DWIDTH-1:0] doa,
+     
+     input clkb,
+     input enb,
+     input web,
+     input [AWIDTH-1:0] addrb,
+     input [DWIDTH-1:0] dib,
+     output reg [DWIDTH-1:0] dob);
+   
+   reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+   integer 	    i;
+   initial
+     for(i=0;i<(1<<AWIDTH);i=i+1)
+       ram[i] <= {DWIDTH{1'b0}};
+   
+   always @(posedge clka) begin
+      if (ena)
+        begin
+           if (wea)
+             ram[addra] <= dia;
+           doa <= ram[addra];
+        end
+   end
+   always @(posedge clkb) begin
+      if (enb)
+        begin
+           if (web)
+             ram[addrb] <= dib;
+           dob <= ram[addrb];
+        end
+   end
+endmodule // ram_2port
diff --git a/fpga/usrp2/control_lib/ram_harv_cache.v b/fpga/usrp2/control_lib/ram_harv_cache.v
new file mode 100644
index 000000000..29fdebf7a
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_harv_cache.v
@@ -0,0 +1,75 @@
+
+
+// Dual ported, Harvard architecture, cached ram
+
+module ram_harv_cache
+  #(parameter AWIDTH=15,parameter RAM_SIZE=16384,parameter ICWIDTH=6,parameter DCWIDTH=6)
+    (input wb_clk_i, input wb_rst_i,
+     
+     input [AWIDTH-1:0] ram_loader_adr_i,
+     input [31:0] ram_loader_dat_i,
+     input ram_loader_stb_i,
+     input [3:0] ram_loader_sel_i,
+     input ram_loader_we_i,
+     output ram_loader_ack_o,
+     input ram_loader_done_i,
+     
+     input [AWIDTH-1:0] iwb_adr_i,
+     input iwb_stb_i,
+     output [31:0] iwb_dat_o,
+     output iwb_ack_o,
+     
+     input [AWIDTH-1:0] dwb_adr_i,
+     input [31:0] dwb_dat_i, 
+     output [31:0] dwb_dat_o,
+     input dwb_we_i,
+     output dwb_ack_o,
+     input dwb_stb_i,
+     input [3:0] dwb_sel_i,
+
+     input flush_icache );
+
+   wire [31:0] 	 iram_dat, dram_dat_i, dram_dat_o;
+   wire [AWIDTH-1:0] iram_adr, dram_adr;
+   wire 	     iram_en, dram_en, dram_we;
+   wire [3:0] 	     dram_sel;
+   
+   dpram32 #(.AWIDTH(AWIDTH),.RAM_SIZE(RAM_SIZE)) sys_ram
+     (.clk(wb_clk_i),
+
+      .adr1_i(ram_loader_done_i ? iram_adr : ram_loader_adr_i),
+      .dat1_i(ram_loader_dat_i),
+      .dat1_o(iram_dat),
+      .we1_i(ram_loader_done_i ? 1'b0 : ram_loader_we_i),
+      .en1_i(ram_loader_done_i ? iram_en : ram_loader_stb_i),
+      .sel1_i(ram_loader_done_i ? 4'hF : ram_loader_sel_i),
+
+      .adr2_i(dram_adr),.dat2_i(dram_dat_i),.dat2_o(dram_dat_o),
+      .we2_i(dram_we),.en2_i(dram_en),.sel2_i(dram_sel) );
+
+   // Data bus side
+   dcache #(.AWIDTH(AWIDTH),.CWIDTH(DCWIDTH))
+     dcache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
+	    .dwb_adr_i(dwb_adr_i),.dwb_stb_i(dwb_stb_i),
+	    .dwb_we_i(dwb_we_i),.dwb_sel_i(dwb_sel_i),
+	    .dwb_dat_i(dwb_dat_i),.dwb_dat_o(dwb_dat_o),
+	    .dwb_ack_o(dwb_ack_o),
+	    .dram_dat_i(dram_dat_o),.dram_dat_o(dram_dat_i),.dram_adr_o(dram_adr),
+	    .dram_we_o(dram_we),.dram_en_o(dram_en), .dram_sel_o(dram_sel) );
+	    
+   // Instruction bus side
+   icache #(.AWIDTH(AWIDTH),.CWIDTH(ICWIDTH))
+     icache(.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
+	    .iwb_adr_i(iwb_adr_i),.iwb_stb_i(iwb_stb_i),
+	    .iwb_dat_o(iwb_dat_o),.iwb_ack_o(iwb_ack_o),
+	    .iram_dat_i(iram_dat),.iram_adr_o(iram_adr),.iram_en_o(iram_en),
+	    .flush(flush_icache));
+
+   // RAM loader
+   assign 	 ram_loader_ack_o = ram_loader_stb_i;
+
+   // Performance Monitoring
+   wire 	 i_wait = iwb_stb_i & ~iwb_ack_o;
+   wire 	 d_wait = dwb_stb_i & ~dwb_ack_o;
+   
+endmodule // ram_harv_cache
diff --git a/fpga/usrp2/control_lib/ram_loader.v b/fpga/usrp2/control_lib/ram_loader.v
new file mode 100644
index 000000000..cb67de739
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_loader.v
@@ -0,0 +1,225 @@
+
+// Adapted from VHDL code in spi_boot by Arnim Legauer
+//  Added a full wishbone master interface (32-bit)
+
+module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384)
+  (input clk_i, input rst_i,
+   // CPLD Interface
+   input cfg_clk_i, input cfg_data_i,
+   output start_o, output mode_o, output done_o,
+   input detached_i,
+   // Wishbone interface
+   output wire [31:0] wb_dat_o,
+   output reg [AWIDTH-1:0] wb_adr_o,
+   output wb_stb_o,
+   output wb_cyc_o,
+   output reg [3:0] wb_sel_o,
+   output reg wb_we_o,
+   input wb_ack_i,
+   output ram_loader_done_o);
+   
+   //  FSM to control start signal, clocked on main clock
+   localparam FSM1_WAIT_DETACH = 2'b00;
+   localparam FSM1_CHECK_NO_DONE = 2'b01;
+   localparam FSM1_WAIT_DONE = 2'b10;
+   
+   reg [1:0]  start_fsm_q, start_fsm_s;
+   reg 	      start_q, enable_q, start_s, enable_s;
+   reg 	      done_q, done_s;
+   
+   always @(posedge clk_i or posedge rst_i)
+     if(rst_i)
+       begin
+	  start_fsm_q <= FSM1_WAIT_DETACH;
+	  start_q <= 1'b0;
+	  enable_q <= 1'b0;
+       end
+     else
+       begin
+	  start_fsm_q <= start_fsm_s;
+	  enable_q <= enable_s;
+	  start_q <= start_s;
+       end // else: !if(rst_i)
+   
+   always @*
+     case(start_fsm_q)
+       FSM1_WAIT_DETACH:
+	 if(detached_i == 1'b1)
+	   begin
+	      start_fsm_s <= FSM1_CHECK_NO_DONE;
+	      enable_s <= 1'b1;
+	      start_s <= 1'b1;
+	   end
+	 else
+	   begin
+	      start_fsm_s <= FSM1_WAIT_DETACH;
+	      enable_s <= enable_q;
+	      start_s <= start_q;
+	   end // else: !if(detached_i == 1'b1)
+       FSM1_CHECK_NO_DONE:
+	 if(~done_q)
+	   begin
+	      start_fsm_s  <= FSM1_WAIT_DONE;
+	      enable_s <= enable_q;
+	      start_s <= start_q;
+	   end
+	 else
+	   begin
+	      start_fsm_s  <= FSM1_CHECK_NO_DONE;
+	      enable_s <= enable_q;
+	      start_s <= start_q;
+	   end // else: !if(~done_q)
+       FSM1_WAIT_DONE:
+	 if(done_q)
+	   begin
+	      start_fsm_s  <= FSM1_WAIT_DETACH;
+	      enable_s <= 1'b0;
+	      start_s <= 1'b0;
+	   end
+	 else
+	   begin
+	      start_fsm_s  <= FSM1_WAIT_DONE;
+	      enable_s <= enable_q;
+	      start_s <= start_q;
+	   end // else: !if(done_q)
+       default:
+	 begin
+	    start_fsm_s  <= FSM1_WAIT_DETACH;
+	    enable_s <= enable_q;
+	    start_s <= start_q;
+	 end // else: !if(done_q)
+     endcase // case(start_fsm_q)
+   
+   //  FSM running on data clock
+
+   localparam FSM2_IDLE = 3'b000;
+   localparam FSM2_WE_ON = 3'b001;
+   localparam FSM2_WE_OFF = 3'b010;
+   localparam FSM2_INC_ADDR1 = 3'b011;
+   localparam FSM2_INC_ADDR2 = 3'b100;
+   localparam FSM2_FINISHED = 3'b101;
+   
+   reg [AWIDTH-1:0] addr_q;
+   reg [7:0] 	    shift_dat_q, ser_dat_q;
+   reg [2:0] 	    bit_q, fsm_q, fsm_s;
+   reg 		    bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, inc_addr_s;
+   
+   always @(posedge cfg_clk_i or posedge rst_i)
+     if(rst_i)
+       begin
+	  addr_q <= 0;
+	  shift_dat_q <= 8'd0;
+	  ser_dat_q <= 8'd0;
+	  bit_q <= 3'd0;
+	  bit_ovfl_q <= 1'b0;
+	  fsm_q <= FSM2_IDLE;
+	  ram_we_q <= 1'b0;
+	  done_q <= 1'b0;
+	  mode_q <= 1'b0;
+       end
+     else
+       begin
+	  if(inc_addr_s)
+	    addr_q <= addr_q + 1;
+	  if(enable_q)
+	    begin
+	       bit_q <= bit_q + 1;
+	       bit_ovfl_q <= (bit_q == 3'd7);
+	       shift_dat_q[0] <= cfg_data_i;
+	       shift_dat_q[7:1] <= shift_dat_q[6:0];
+	    end
+	  if(bit_ovfl_q)
+	    ser_dat_q <= shift_dat_q;
+
+	  fsm_q <= fsm_s;
+
+	  ram_we_q <= ram_we_s;
+
+	  if(done_s)
+	    done_q <= 1'b1;
+	  mode_q <= mode_s;
+       end // else: !if(rst_i)
+
+   always @*
+     begin
+	inc_addr_s <= 1'b0;
+	ram_we_s <= 1'b0;
+	done_s <= 1'b0;
+	fsm_s <= FSM2_IDLE;
+	mode_s <= 1'b0;
+
+	case(fsm_q)
+	  FSM2_IDLE :
+	    if(start_q)
+	      if(bit_ovfl_q)
+		fsm_s <= FSM2_WE_ON;
+	  FSM2_WE_ON:
+	    begin
+	       ram_we_s <= 1'b1;
+	       fsm_s <= FSM2_WE_OFF;
+	    end
+	  FSM2_WE_OFF:
+	    begin
+	       ram_we_s <= 1'b1;
+	       fsm_s <= FSM2_INC_ADDR1;
+	    end
+	  FSM2_INC_ADDR1:
+	    fsm_s <= FSM2_INC_ADDR2;
+	  FSM2_INC_ADDR2:
+	    if(addr_q == (RAM_SIZE-1))
+	    //if(&addr_q)
+	      begin
+		 fsm_s <= FSM2_FINISHED;
+		 done_s <= 1'b1;
+		 mode_s <= 1'b1;
+	      end
+	    else
+	      begin
+		 inc_addr_s <= 1'b1;
+		 fsm_s <= FSM2_IDLE;
+	      end // else: !if(&addr_q)
+	  FSM2_FINISHED:
+	    begin
+	       fsm_s <= FSM2_FINISHED;
+	       mode_s <= 1'b1;
+	    end
+	endcase // case(fsm_q)
+     end // always @ *
+   
+   assign start_o = start_q;
+   assign mode_o = mode_q;
+   assign done_o = start_q ? done_q : 1'b1;
+   wire [AWIDTH-1:0] ram_addr = addr_q;
+   wire [7:0] ram_data = ser_dat_q;
+   assign ram_loader_done_o = (fsm_q == FSM2_FINISHED);
+   
+   // wishbone master, only writes
+   reg [7:0] dat_holder;
+   assign    wb_dat_o = {4{dat_holder}};
+   assign    wb_stb_o = wb_we_o;
+   assign    wb_cyc_o = wb_we_o;
+   
+   always @(posedge clk_i or posedge rst_i)
+     if(rst_i)
+       begin
+	  dat_holder <= 8'd0;
+	  wb_adr_o <= 0;
+	  wb_sel_o <= 4'b0000;
+	  wb_we_o <= 1'b0;
+       end
+     else if(ram_we_q)
+       begin
+	  dat_holder <= ram_data;
+	  wb_adr_o <= ram_addr;
+	  wb_we_o <= 1'b1;
+	  case(ram_addr[1:0])   // Big Endian
+	    2'b00 : wb_sel_o <= 4'b1000;
+	    2'b01 : wb_sel_o <= 4'b0100;
+	    2'b10 : wb_sel_o <= 4'b0010;
+	    2'b11 : wb_sel_o <= 4'b0001;
+	  endcase // case(ram_addr[1:0])
+       end // if (ram_we_q)
+     else if(wb_ack_i)
+       wb_we_o <= 1'b0;
+      
+endmodule // ram_loader
diff --git a/fpga/usrp2/control_lib/ram_wb_harvard.v b/fpga/usrp2/control_lib/ram_wb_harvard.v
new file mode 100644
index 000000000..c3efc12e0
--- /dev/null
+++ b/fpga/usrp2/control_lib/ram_wb_harvard.v
@@ -0,0 +1,86 @@
+
+// Dual ported RAM for Harvard architecture processors
+//    Does no forwarding
+//    Addresses are byte-oriented, so botton 2 address bits are ignored.  FIXME
+//    AWIDTH of 13 gives 8K bytes.  For Spartan 3, if the total RAM size is not a
+//    multiple of 8K then BRAM space is wasted
+
+module ram_wb_harvard #(parameter AWIDTH=13)
+  (input wb_clk_i,
+   input wb_rst_i,
+   
+   input [AWIDTH-1:0] iwb_adr_i,
+   input [31:0] iwb_dat_i,
+   output reg [31:0] iwb_dat_o,
+   input iwb_we_i,
+   output reg iwb_ack_o,
+   input iwb_stb_i,
+   input [3:0] iwb_sel_i,
+   
+   input [AWIDTH-1:0] dwb_adr_i,
+   input [31:0] dwb_dat_i,
+   output reg [31:0] dwb_dat_o,
+   input dwb_we_i,
+   output reg dwb_ack_o,
+   input dwb_stb_i,
+   input [3:0] dwb_sel_i);
+   
+   reg [7:0] 	 ram0 [0:(1<<(AWIDTH-2))-1];
+   reg [7:0] 	 ram1 [0:(1<<(AWIDTH-2))-1];
+   reg [7:0] 	 ram2 [0:(1<<(AWIDTH-2))-1];
+   reg [7:0] 	 ram3 [0:(1<<(AWIDTH-2))-1];
+   
+   // Instruction Read Port
+   always @(posedge wb_clk_i)
+     iwb_ack_o <= iwb_stb_i & ~iwb_ack_o;
+   
+   always @(posedge wb_clk_i)
+     iwb_dat_o[31:24] <= ram3[iwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     iwb_dat_o[23:16] <= ram2[iwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     iwb_dat_o[15:8] <= ram1[iwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     iwb_dat_o[7:0] <= ram0[iwb_adr_i[AWIDTH-1:2]];
+   
+   always @(posedge wb_clk_i)
+     if(iwb_we_i & iwb_stb_i & iwb_sel_i[3])
+       ram3[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[31:24];
+   always @(posedge wb_clk_i)
+     if(iwb_we_i & iwb_stb_i & iwb_sel_i[2])
+       ram2[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[23:16];
+   always @(posedge wb_clk_i)
+     if(iwb_we_i & iwb_stb_i & iwb_sel_i[1])
+       ram1[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[15:8];
+   always @(posedge wb_clk_i)
+     if(iwb_we_i & iwb_stb_i & iwb_sel_i[0])
+       ram0[iwb_adr_i[AWIDTH-1:2]] <= iwb_dat_i[7:0];
+   
+   // Data Port
+   always @(posedge wb_clk_i)
+     dwb_ack_o <= dwb_stb_i & ~dwb_ack_o;
+   
+   always @(posedge wb_clk_i)
+     dwb_dat_o[31:24] <= ram3[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     dwb_dat_o[23:16] <= ram2[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     dwb_dat_o[15:8] <= ram1[dwb_adr_i[AWIDTH-1:2]];
+   always @(posedge wb_clk_i)
+     dwb_dat_o[7:0]  <= ram0[dwb_adr_i[AWIDTH-1:2]];
+   
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[3])
+       ram3[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[31:24];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[2])
+       ram2[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[23:16];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[1])
+       ram1[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[15:8];
+   always @(posedge wb_clk_i)
+     if(dwb_we_i & dwb_stb_i & dwb_sel_i[0])
+       ram0[dwb_adr_i[AWIDTH-1:2]] <= dwb_dat_i[7:0];
+   
+endmodule // ram_wb_harvard
+
diff --git a/fpga/usrp2/control_lib/reset_sync.v b/fpga/usrp2/control_lib/reset_sync.v
new file mode 100644
index 000000000..94d966840
--- /dev/null
+++ b/fpga/usrp2/control_lib/reset_sync.v
@@ -0,0 +1,16 @@
+
+
+module reset_sync
+  (input clk,
+   input reset_in,
+   output reg reset_out);
+
+   reg 	      reset_int;
+
+   always @(posedge clk or posedge reset_in)
+     if(reset_in)
+       {reset_out,reset_int} <= 2'b11;
+     else
+       {reset_out,reset_int} <= {reset_int,1'b0};
+   
+endmodule // reset_sync
diff --git a/fpga/usrp2/control_lib/sd_spi.v b/fpga/usrp2/control_lib/sd_spi.v
new file mode 100644
index 000000000..3f4d7f46a
--- /dev/null
+++ b/fpga/usrp2/control_lib/sd_spi.v
@@ -0,0 +1,70 @@
+module sd_spi
+  (input clk,
+   input rst,
+   
+   // SD Card interface
+   output reg sd_clk,
+   output sd_mosi,
+   input sd_miso,
+   
+   // Controls
+   input [7:0] clk_div,
+   input [7:0] send_dat,
+   output [7:0] rcv_dat,
+   input go,
+   output ready);
+
+   reg [7:0] clk_ctr;   
+   reg [3:0] bit_ctr;
+
+   wire      bit_ready = (clk_ctr == 8'd0);
+   wire      bit_busy = (clk_ctr != 8'd0);
+   wire      bit_done = (clk_ctr == clk_div);
+
+   wire      send_clk_hi = (clk_ctr == (clk_div>>1));
+   wire      latch_dat = (clk_ctr == (clk_div - 8'd2));     
+   wire      send_clk_lo = (clk_ctr == (clk_div - 8'd1));
+
+   wire      send_bit = (bit_ready && (bit_ctr != 0));
+   assign    ready = (bit_ctr == 0);
+   
+   always @(posedge clk)
+     if(rst)
+       clk_ctr <= 0;
+     else if(bit_done)
+       clk_ctr <= 0;
+     else if(bit_busy)
+       clk_ctr <= clk_ctr + 1;
+     else if(send_bit)
+       clk_ctr <= 1;
+
+   always @(posedge clk)
+     if(rst)
+       sd_clk <= 0;
+     else if(send_clk_hi)
+       sd_clk <= 1;
+     else if(send_clk_lo)
+       sd_clk <= 0;
+   
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else if(bit_done)
+       if(bit_ctr == 4'd8)
+	 bit_ctr <= 0;
+       else
+	 bit_ctr <= bit_ctr + 1;
+     else if(bit_ready & go)
+       bit_ctr <= 1;
+   
+   reg [7:0] shift_reg;
+   always @(posedge clk)
+     if(go)
+       shift_reg <= send_dat;
+     else if(latch_dat)
+       shift_reg <= {shift_reg[6:0],sd_miso};
+
+   assign    sd_mosi = shift_reg[7];
+   assign    rcv_dat = shift_reg;
+   
+endmodule // sd_spi
diff --git a/fpga/usrp2/control_lib/sd_spi_tb.v b/fpga/usrp2/control_lib/sd_spi_tb.v
new file mode 100644
index 000000000..e30a5bdf6
--- /dev/null
+++ b/fpga/usrp2/control_lib/sd_spi_tb.v
@@ -0,0 +1,40 @@
+
+
+module sd_spi_tb;
+
+   reg clk = 0;
+   always #5 clk = ~clk;
+   reg rst = 1;
+   initial #32 rst = 0;
+
+   wire sd_clk, sd_mosi, sd_miso;
+   wire [7:0] clk_div = 12;
+   wire [7:0] send_dat = 23;
+   wire [7:0] rcv_dat;
+
+   wire       ready;
+   reg 	      go = 0;
+   initial 
+     begin
+	repeat (100)
+	  @(posedge clk);
+	go <= 1;
+	@(posedge clk);
+	go <= 0;
+     end
+   
+   sd_spi dut(.clk(clk),.rst(rst),
+	      .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+	      .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat),
+	      .go(go),.ready(ready) );
+
+   initial    
+     begin 
+	$dumpfile("sd_spi_tb.vcd");
+	$dumpvars(0,sd_spi_tb);
+     end
+
+   initial
+     #10000 $finish();
+   
+endmodule // sd_spi_tb
diff --git a/fpga/usrp2/control_lib/sd_spi_wb.v b/fpga/usrp2/control_lib/sd_spi_wb.v
new file mode 100644
index 000000000..7a6258b56
--- /dev/null
+++ b/fpga/usrp2/control_lib/sd_spi_wb.v
@@ -0,0 +1,76 @@
+
+// Wishbone module for spi communications with an SD Card
+// The programming interface is simple -- 
+//      Write the desired clock divider to address 1 (should be 1 or higher)
+//      Status is in address 0.  A 1 indicates the last transaction is done and it is safe to
+//          send another
+//      Writing a byte to address 2 sends that byte over SPI.  When it is done, 
+//          status (addr 0) goes high again, and the received byte can be read from address 3.
+
+module sd_spi_wb
+  (input clk,
+   input rst,
+   
+   // SD Card interface
+   output sd_clk,
+   output sd_csn,
+   output sd_mosi,
+   input sd_miso,
+
+   input wb_cyc_i,
+   input wb_stb_i,
+   input wb_we_i,
+   input [1:0] wb_adr_i,
+   input [7:0] wb_dat_i,
+   output reg [7:0] wb_dat_o,
+   output reg wb_ack_o);
+
+   localparam ADDR_STATUS = 0;
+   localparam ADDR_CLKDIV = 1;
+   localparam ADDR_WRITE = 2;
+   localparam ADDR_READ = 3;
+
+   wire [7:0] status, rcv_dat;
+   reg [7:0]  clkdiv;
+   wire       ready;
+   reg 	      ack_d1;
+
+   reg 	      cs_reg;
+   assign     sd_csn = ~cs_reg;  // FIXME
+   
+   always @(posedge clk)
+     if(rst) ack_d1 <= 0;
+     else ack_d1 <= wb_ack_o;
+   
+   always @(posedge clk)
+     if(rst) wb_ack_o <= 0;
+     else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1;
+   
+   always @(posedge clk)
+     case(wb_adr_i)
+       ADDR_STATUS : wb_dat_o <= {7'd0,ready};
+       ADDR_CLKDIV : wb_dat_o <= clkdiv;
+       ADDR_READ : wb_dat_o <= rcv_dat;
+       default : wb_dat_o <= 0;
+     endcase // case(wb_adr_i)
+
+   always @(posedge clk)
+     if(rst)
+       begin
+	  clkdiv <= 200;
+	  cs_reg <= 0;
+       end
+     else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o)
+       case(wb_adr_i)
+	 ADDR_STATUS : cs_reg <= wb_dat_i;
+	 ADDR_CLKDIV : clkdiv <= wb_dat_i;
+       endcase // case(wb_adr_i)
+
+   wire       go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE);
+   
+   sd_spi sd_spi(.clk(clk),.rst(rst),
+		 .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+		 .clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat),
+		 .go(go),.ready(ready) );
+
+endmodule // sd_spi_wb
diff --git a/fpga/usrp2/control_lib/setting_reg.v b/fpga/usrp2/control_lib/setting_reg.v
new file mode 100644
index 000000000..c8aff230f
--- /dev/null
+++ b/fpga/usrp2/control_lib/setting_reg.v
@@ -0,0 +1,23 @@
+
+
+module setting_reg
+  #(parameter my_addr = 0, parameter at_reset=32'd0)
+    (input clk, input rst, input strobe, input wire [7:0] addr,
+     input wire [31:0] in, output reg [31:0] out, output reg changed);
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  out <= at_reset;
+	  changed <= 1'b0;
+       end
+     else
+       if(strobe & (my_addr==addr))
+	 begin
+	    out <= in;
+	    changed <= 1'b1;
+	 end
+       else
+	 changed <= 1'b0;
+   
+endmodule // setting_reg
diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v
new file mode 100644
index 000000000..d01a30ab4
--- /dev/null
+++ b/fpga/usrp2/control_lib/settings_bus.v
@@ -0,0 +1,49 @@
+
+// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock
+
+module settings_bus
+  #(parameter AWIDTH=16, parameter DWIDTH=32)
+    (input wb_clk, 
+     input wb_rst, 
+     input [AWIDTH-1:0] wb_adr_i,
+     input [DWIDTH-1:0] wb_dat_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output reg wb_ack_o,
+     input sys_clk,
+     output strobe,
+     output reg [7:0] addr,
+     output reg [31:0] data);
+
+   reg 	    stb_int, stb_int_d1;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  stb_int <= 1'b0;
+	  addr <= 8'd0;
+	  data <= 32'd0;
+       end
+     else if(wb_we_i & wb_stb_i)
+       begin
+	  stb_int <= 1'b1;
+	  addr <= wb_adr_i[9:2];
+	  data <= wb_dat_i;
+       end
+     else
+       stb_int <= 1'b0;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+
+   always @(posedge wb_clk)
+     stb_int_d1 <= stb_int;
+
+   //assign strobe = stb_int & ~stb_int_d1;
+   assign strobe = stb_int & wb_ack_o;
+          
+endmodule // settings_bus
+
diff --git a/fpga/usrp2/control_lib/shortfifo.v b/fpga/usrp2/control_lib/shortfifo.v
new file mode 100644
index 000000000..d8ce1428e
--- /dev/null
+++ b/fpga/usrp2/control_lib/shortfifo.v
@@ -0,0 +1,87 @@
+
+module shortfifo
+  #(parameter WIDTH=32)
+    (input clk, input rst,
+     input [WIDTH-1:0] datain,
+     output [WIDTH-1:0] dataout,
+     input read,
+     input write,
+     input clear,
+     output reg full,
+     output reg empty,
+     output reg [4:0] space,
+     output reg [4:0] occupied);
+   
+   reg [3:0] 	  a;
+   genvar 	  i;
+   
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl16
+	   SRL16E
+	     srl16e(.Q(dataout[i]),
+		    .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+		    .CE(write),.CLK(clk),.D(datain[i]));
+	end
+   endgenerate
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full <= 0;
+       end
+     else if(clear)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full<= 0;
+       end
+     else if(read & ~write)
+       begin
+	  full <= 0;
+	  if(a==0)
+	    empty <= 1;
+	  else
+	    a <= a - 1;
+       end
+     else if(write & ~read)
+       begin
+	  empty <= 0;
+	  if(~empty)
+	    a <= a + 1;
+	  if(a == 14)
+	    full <= 1;
+       end
+
+   // NOTE will fail if you write into a full fifo or read from an empty one
+
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
+   
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(rst)
+       space <= 16;
+     else if(clear)
+       space <= 16;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(rst)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+      
+endmodule // shortfifo
diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v
new file mode 100644
index 000000000..22f0e70a2
--- /dev/null
+++ b/fpga/usrp2/control_lib/simple_uart.v
@@ -0,0 +1,61 @@
+
+module simple_uart
+  #(parameter TXDEPTH = 1,
+    parameter RXDEPTH = 1)
+    (input clk_i, input rst_i,
+     input we_i, input stb_i, input cyc_i, output reg ack_o,
+     input [2:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+     output rx_int_o, output tx_int_o, output tx_o, input rx_i, output baud_o);
+   
+   // Register Map
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   wire       wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire       wb_wr  = wb_acc & we_i;            // WISHBONE write access
+   
+   reg [15:0] clkdiv;
+   wire [7:0] rx_char;
+   wire       tx_fifo_full, rx_fifo_empty;   
+   wire [7:0] tx_fifo_level, rx_fifo_level;
+   
+   always @(posedge clk_i)
+     if (rst_i)
+       ack_o <= 1'b0;
+     else
+       ack_o <= wb_acc & ~ack_o;
+   
+   always @(posedge clk_i)
+     if (rst_i)
+       clkdiv <= 0;
+     else if (wb_wr)
+       case(adr_i)
+	 SUART_CLKDIV : clkdiv <= dat_i[15:0];
+       endcase // case(adr_i)
+   
+   always @(posedge clk_i)
+     case (adr_i)
+       SUART_TXLEVEL : dat_o <= tx_fifo_level;
+       SUART_RXLEVEL : dat_o <= rx_fifo_level;
+       SUART_RXCHAR : dat_o <= rx_char;
+     endcase // case(adr_i)
+   
+   simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i == SUART_TXCHAR)),
+      .fifo_level(tx_fifo_level),.fifo_full(tx_fifo_full),
+      .clkdiv(clkdiv),.baudclk(baud_o),.tx(tx_o));
+   
+   simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
+     (.clk(clk_i),.rst(rst_i),
+      .fifo_out(rx_char),.fifo_read(ack_o && ~wb_wr && (adr_i == SUART_RXCHAR)),
+      .fifo_level(rx_fifo_level),.fifo_empty(rx_fifo_empty),
+      .clkdiv(clkdiv),.rx(rx_i));
+   
+   assign     tx_int_o = ~tx_fifo_full;
+   assign     rx_int_o = ~rx_fifo_empty;
+   
+endmodule // simple_uart
diff --git a/fpga/usrp2/control_lib/simple_uart_rx.v b/fpga/usrp2/control_lib/simple_uart_rx.v
new file mode 100644
index 000000000..debdd618b
--- /dev/null
+++ b/fpga/usrp2/control_lib/simple_uart_rx.v
@@ -0,0 +1,64 @@
+
+
+module simple_uart_rx
+  #(parameter DEPTH=0)
+    (input clk, input rst, 
+     output [7:0] fifo_out, input fifo_read, output [7:0] fifo_level, output fifo_empty, 
+     input [15:0] clkdiv, input rx);
+
+   reg 		  rx_d1, rx_d2;
+   always @(posedge clk)
+     if(rst)
+       {rx_d2,rx_d1} <= 0;
+     else
+       {rx_d2,rx_d1} <= {rx_d1,rx};
+   
+   reg [15:0] 	  baud_ctr;
+   reg [3:0] 	  bit_ctr;
+   reg [7:0] 	  sr;
+
+   wire 	  neg_trans = rx_d2 & ~rx_d1;
+   wire 	  shift_now = baud_ctr == (clkdiv>>1);
+   wire 	  stop_now = (bit_ctr == 10) && shift_now;
+   wire 	  go_now = (bit_ctr == 0) && neg_trans;
+   
+   always @(posedge clk)
+     if(rst)
+       sr <= 0;
+     else if(shift_now)
+       sr <= {rx_d2,sr[7:1]};
+   
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else
+       if(go_now)
+	 baud_ctr <= 1;
+       else if(stop_now)
+	 baud_ctr <= 0;
+       else if(baud_ctr >= clkdiv)
+	 baud_ctr <= 1;
+       else if(baud_ctr != 0)
+	 baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else 
+       if(go_now)
+	 bit_ctr <= 1;
+       else if(stop_now)
+	 bit_ctr <= 0;
+       else if(baud_ctr == clkdiv)
+	 bit_ctr <= bit_ctr + 1;
+   
+   wire 	  full;
+   wire 	  write = ~full & rx_d2 & stop_now;
+   
+   medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
+     (.clk(clk),.rst(rst),
+      .datain(sr),.write(write),.full(full),
+      .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty),
+      .clear(0),.space(),.occupied(fifo_level) );
+   
+endmodule // simple_uart_rx
diff --git a/fpga/usrp2/control_lib/simple_uart_tx.v b/fpga/usrp2/control_lib/simple_uart_tx.v
new file mode 100644
index 000000000..e11a347ed
--- /dev/null
+++ b/fpga/usrp2/control_lib/simple_uart_tx.v
@@ -0,0 +1,60 @@
+
+module simple_uart_tx
+  #(parameter DEPTH=0)
+    (input clk, input rst, 
+     input [7:0] fifo_in, input fifo_write, output [7:0] fifo_level, output fifo_full, 
+     input [15:0] clkdiv, output baudclk, output reg tx);
+   
+   reg [15:0] 	  baud_ctr;
+   reg [3:0] 	  bit_ctr;
+   
+   wire 	  read, empty;
+   wire [7:0] 	  char_to_send;
+   
+   medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
+     (.clk(clk),.rst(rst),
+      .datain(fifo_in),.write(fifo_write),.full(fifo_full),
+      .dataout(char_to_send),.read(read),.empty(empty),
+      .clear(0),.space(fifo_level),.occupied() );
+   
+   always @(posedge clk)
+     if(rst)
+       baud_ctr <= 0;
+     else if (baud_ctr >= clkdiv)
+       baud_ctr <= 0;
+     else
+       baud_ctr <= baud_ctr + 1;
+
+   always @(posedge clk)
+     if(rst)
+       bit_ctr <= 0;
+     else if(baud_ctr == clkdiv)
+       if(bit_ctr == 9)
+	 bit_ctr <= 0;
+       else if(bit_ctr != 0)
+	 bit_ctr <= bit_ctr + 1;
+       else if(~empty)
+	 bit_ctr <= 1;
+   
+   always @(posedge clk)
+     if(rst)
+       tx <= 1;
+     else
+       case(bit_ctr)
+	 0 : tx <= 1;
+	 1 : tx <= 0;
+	 2 : tx <= char_to_send[0];
+	 3 : tx <= char_to_send[1];
+	 4 : tx <= char_to_send[2];
+	 5 : tx <= char_to_send[3];
+	 6 : tx <= char_to_send[4];
+	 7 : tx <= char_to_send[5];
+	 8 : tx <= char_to_send[6];
+	 9 : tx <= char_to_send[7];
+	 default : tx <= 1;
+       endcase // case(bit_ctr)
+
+   assign 	  read = (bit_ctr == 9) && (baud_ctr == clkdiv);
+   assign 	  baudclk = (baud_ctr == 1);  // Only for debug purposes
+   
+endmodule // simple_uart_tx
diff --git a/fpga/usrp2/control_lib/spi.v b/fpga/usrp2/control_lib/spi.v
new file mode 100644
index 000000000..a80c488e9
--- /dev/null
+++ b/fpga/usrp2/control_lib/spi.v
@@ -0,0 +1,84 @@
+
+
+// AD9510 Register Map (from datasheet Rev. A)
+
+/* INSTRUCTION word format (16 bits)
+ * 15       Read = 1, Write = 0
+ * 14:13    W1/W0,  Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream
+ * 12:0     Address
+ */
+
+/* ADDR     Contents             Value (hex)
+ * 00       Serial Config Port   10 (def) -- MSB first, SDI/SDO separate
+ * 04       A Counter
+ * 05-06    B Counter
+ * 07-0A    PLL Control
+ * 0B-0C    R Divider
+ * 0D       PLL Control
+ * 34-3A    Fine Delay
+ * 3C-3F    LVPECL Outs
+ * 40-43    LVDS/CMOS Outs
+ * 45       Clock select, power down
+ * 48-57    Dividers
+ * 58       Func and Sync
+ * 5A       Update regs
+ */
+
+
+module spi
+  (input reset,
+   input clk,
+
+   // SPI signals
+   output sen, 
+   output sclk,
+   input sdi,
+   output sdo,
+
+   // Interfaces
+   input read_1,
+   input write_1,
+   input [15:0] command_1,
+   input [15:0] wdata_1,
+   output [15:0] rdata_1,
+   output reg done_1,
+   input msb_first_1,
+   input [5:0] command_width_1,
+   input [5:0] data_width_1,
+   input [7:0] clkdiv_1
+   
+   );
+
+   reg [15:0]  command, wdata, rdata;
+   reg 	       done;
+
+   always @(posedge clk)
+     if(reset)
+       done_1 <= #1 1'b0;
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  counter <= #1 7'd0;
+	  command <= #1 20'd0;
+       end
+     else if(start)
+       begin
+	  counter <= #1 7'd1;
+	  command <= #1 {read,w,addr_data};
+       end
+     else if( |counter && ~done )
+       begin
+	  counter <= #1 counter + 7'd1;
+	  if(~counter[0])
+	    command <= {command[22:0],1'b0};
+       end
+
+   wire done = (counter == 8'd49);
+   
+   assign sen = (done | counter == 8'd0);  // CSB is high when we're not doing anything
+   assign sclk = ~counter[0];
+   assign sdo = command[23];
+   
+
+endmodule // clock_control
diff --git a/fpga/usrp2/control_lib/srl.v b/fpga/usrp2/control_lib/srl.v
new file mode 100644
index 000000000..fa28c7669
--- /dev/null
+++ b/fpga/usrp2/control_lib/srl.v
@@ -0,0 +1,21 @@
+
+module srl
+  #(parameter WIDTH=18)
+    (input clk,
+     input write,
+     input [WIDTH-1:0] in,
+     input [3:0] addr,
+     output [WIDTH-1:0] out);
+   
+   genvar 		i;
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl
+	   SRL16E
+	     srl16e(.Q(out[i]),
+		    .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]),
+		    .CE(write),.CLK(clk),.D(in[i]));
+	end
+   endgenerate
+
+endmodule // srl
diff --git a/fpga/usrp2/control_lib/ss_rcvr.v b/fpga/usrp2/control_lib/ss_rcvr.v
new file mode 100644
index 000000000..8e650d21b
--- /dev/null
+++ b/fpga/usrp2/control_lib/ss_rcvr.v
@@ -0,0 +1,81 @@
+
+
+// Source-synchronous receiver
+// Assumes both clocks are at the same rate
+// Relative clock phase is
+//    unknown
+//    variable
+//    bounded
+// The output will come several cycles later than the input
+
+// This should synthesize efficiently in Xilinx distributed ram cells,
+//   which is why we use a buffer depth of 16
+
+// FIXME Async reset on rxclk side?
+
+module ss_rcvr
+  #(parameter WIDTH=16)
+    (input rxclk,
+     input sysclk,
+     input rst,
+     
+     input [WIDTH-1:0] data_in,
+     output [WIDTH-1:0] data_out,
+     output reg clock_present);
+   
+   wire [3:0] rd_addr, wr_addr;
+
+   // Distributed RAM
+   reg [WIDTH-1:0] buffer [0:15];
+   always @(posedge rxclk)
+     buffer[wr_addr] <= data_in;
+   
+   assign 	   data_out = buffer[rd_addr];
+   
+   // Write address generation
+   reg [3:0] 	   wr_counter;
+   always @(posedge rxclk or posedge rst)
+     if (rst)
+       wr_counter <= 0;
+     else
+       wr_counter <= wr_counter + 1;
+   
+   assign 	   wr_addr = {wr_counter[3], ^wr_counter[3:2], ^wr_counter[2:1], ^wr_counter[1:0]};
+   
+   // Read Address generation
+   wire [3:0] 	   wr_ctr_sys, diff, abs_diff;
+   reg [3:0] 	   wr_addr_sys_d1, wr_addr_sys_d2;
+   reg [3:0] 	   rd_counter;
+   
+   assign 	   rd_addr = {rd_counter[3], ^rd_counter[3:2], ^rd_counter[2:1], ^rd_counter[1:0]};
+   
+   always @(posedge sysclk)
+     wr_addr_sys_d1 <= wr_addr;
+   
+   always @(posedge sysclk)
+     wr_addr_sys_d2 <= wr_addr_sys_d1;
+   
+   assign 	   wr_ctr_sys = {wr_addr_sys_d2[3],^wr_addr_sys_d2[3:2],^wr_addr_sys_d2[3:1],^wr_addr_sys_d2[3:0]};
+   
+   assign 	   diff = wr_ctr_sys - rd_counter;
+   assign 	   abs_diff = diff[3] ? (~diff+1) : diff;
+   
+   always @(posedge sysclk)
+     if(rst)
+       begin
+	  clock_present <= 0;
+	  rd_counter <= 0;
+       end
+     else 
+       if(~clock_present)
+	 if(abs_diff > 5)
+	   clock_present <= 1;
+	 else
+	   ;
+       else
+	 if(abs_diff<3)
+	   clock_present <= 0;
+	 else
+	   rd_counter <= rd_counter + 1;
+
+endmodule // ss_rcvr
diff --git a/fpga/usrp2/control_lib/system_control.v b/fpga/usrp2/control_lib/system_control.v
new file mode 100644
index 000000000..5d89f13db
--- /dev/null
+++ b/fpga/usrp2/control_lib/system_control.v
@@ -0,0 +1,47 @@
+// System bootup order:
+//    0 - Internal POR to reset this block.  Maybe control it from CPLD in the future?
+//    1 - Everything in reset
+//    2 - Take RAM Loader out of reset
+//    3 - When RAM Loader done, take processor and wishbone out of reset
+
+module system_control 
+  (input wb_clk_i,
+   output reg ram_loader_rst_o,
+   output reg wb_rst_o,
+   input ram_loader_done_i
+   );
+
+   reg 		POR = 1'b1;
+   reg [3:0] 	POR_ctr;
+
+   initial POR_ctr = 4'd0;
+   always @(posedge wb_clk_i)
+     if(POR_ctr == 4'd15)
+       POR <= 1'b0;
+     else
+       POR_ctr <= POR_ctr + 4'd1;
+   
+   always @(posedge POR or posedge wb_clk_i)
+     if(POR)
+       ram_loader_rst_o <= 1'b1;
+     else
+       ram_loader_rst_o <= #1 1'b0;
+
+   // Main system reset
+   reg 		delayed_rst;
+   
+   always @(posedge POR or posedge wb_clk_i)
+     if(POR)
+       begin
+	  wb_rst_o <= 1'b1;
+	  delayed_rst <= 1'b1;
+       end
+     else if(ram_loader_done_i)
+       begin
+	  delayed_rst <= 1'b0;
+	  wb_rst_o <= delayed_rst;
+       end
+
+endmodule // system_control
+
+
diff --git a/fpga/usrp2/control_lib/system_control_tb.v b/fpga/usrp2/control_lib/system_control_tb.v
new file mode 100644
index 000000000..a8eff4811
--- /dev/null
+++ b/fpga/usrp2/control_lib/system_control_tb.v
@@ -0,0 +1,57 @@
+
+
+module system_control_tb();
+   
+   reg 	aux_clk, clk_fpga;
+   wire wb_clk, dsp_clk;
+   wire wb_rst, dsp_rst, rl_rst, proc_rst;
+
+   reg 	rl_done, clock_ready;
+   
+   initial aux_clk = 1'b0;
+   always #25 aux_clk = ~aux_clk;
+
+   initial clk_fpga = 1'b0;
+
+   initial clock_ready = 1'b0;
+   initial
+     begin
+	@(negedge proc_rst);
+	#1003 clock_ready <= 1'b1;
+     end
+
+   always #7 clk_fpga = ~clk_fpga;
+      
+   initial begin
+      $dumpfile("system_control_tb.vcd");
+      $dumpvars(0,system_control_tb);
+   end
+
+   initial #10000 $finish;
+
+   initial
+     begin
+	@(negedge rl_rst);
+	rl_done <= 1'b0;
+	#1325 rl_done <= 1'b1;
+     end
+
+   initial
+     begin
+	@(negedge proc_rst);
+	clock_ready <= 1'b0;
+	#327 clock_ready <= 1'b1;
+     end
+     
+   system_control 
+     system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
+		    .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
+		    .ram_loader_rst_o(rl_rst),
+		    .processor_rst_o(proc_rst),
+		    .wb_rst_o(wb_rst),
+		    .dsp_rst_o(dsp_rst),
+		    .ram_loader_done_i(rl_done),
+		    .clock_ready_i(clock_ready),
+		    .debug_o());
+   
+endmodule // system_control_tb
diff --git a/fpga/usrp2/control_lib/traffic_cop.v b/fpga/usrp2/control_lib/traffic_cop.v
new file mode 100644
index 000000000..e7579656a
--- /dev/null
+++ b/fpga/usrp2/control_lib/traffic_cop.v
@@ -0,0 +1,25 @@
+
+module traffic_cop();
+
+
+endmodule // traffic_cop
+
+
+
+/*
+ 
+ Traffic Cop to control buffer pool
+ 
+ Inputs
+ 
+ Commands
+ 
+ Basic Operations
+ 
+ Outputs
+ 
+ 
+ 
+ 
+ 
+ */
diff --git a/fpga/usrp2/control_lib/wb_1master.v b/fpga/usrp2/control_lib/wb_1master.v
new file mode 100644
index 000000000..fb313efae
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_1master.v
@@ -0,0 +1,464 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE Connection Bus Top Level		                 ////
+////                                                             ////
+////                                                             ////
+////  Original Author: Johny Chi		                 ////
+////                   chisuhua@yahoo.com.cn                     ////
+////  Modified By Matt Ettus, matt@ettus.com                     ////
+////                                                             ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2000, 2007 Authors and OPENCORES.ORG           ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+//
+//   Up to 8 slaves share a Wishbone Bus connection to 1 master
+
+  module wb_1master
+    #(parameter	decode_w = 8,			// address decode width
+      parameter	s0_addr = 8'h0,			// slave 0 address
+      parameter	s0_mask = 8'h0,			// slave 0 don't cares
+      parameter	s1_addr = 8'h0,			// slave 1 address
+      parameter	s1_mask = 8'h0,			// slave 1 don't cares
+      parameter	s2_addr = 8'h0,			// slave 2 address
+      parameter	s2_mask = 8'h0,			// slave 2 don't cares
+      parameter	s3_addr = 8'h0,			// slave 3 address
+      parameter	s3_mask = 8'h0,			// slave 3 don't cares
+      parameter	s4_addr = 8'h0,			// slave 4 address
+      parameter	s4_mask = 8'h0,			// slave 4 don't cares
+      parameter	s5_addr = 8'h0,			// slave 5 address
+      parameter	s5_mask = 8'h0,			// slave 5 don't cares
+      parameter	s6_addr = 8'h0,			// slave 6 address
+      parameter	s6_mask = 8'h0,			// slave 6 don't cares
+      parameter	s7_addr = 8'h0,			// slave 7 address
+      parameter	s7_mask = 8'h0,			// slave 7 don't cares
+      parameter	s8_addr = 8'h0,			// slave 8 address
+      parameter	s8_mask = 8'h0,			// slave 8 don't cares
+      parameter	s9_addr = 8'h0,			// slave 9 address
+      parameter	s9_mask = 8'h0,			// slave 9 don't cares
+      parameter	sa_addr = 8'h0,			// slave a address
+      parameter	sa_mask = 8'h0,			// slave a don't cares
+      parameter	sb_addr = 8'h0,			// slave b address
+      parameter	sb_mask = 8'h0,			// slave b don't cares
+      parameter	sc_addr = 8'h0,			// slave c address
+      parameter	sc_mask = 8'h0,			// slave c don't cares
+      parameter	sd_addr = 8'h0,			// slave d address
+      parameter	sd_mask = 8'h0,			// slave d don't cares
+      parameter	se_addr = 8'h0,			// slave e address
+      parameter	se_mask = 8'h0,			// slave e don't cares
+      parameter	sf_addr = 8'h0,			// slave f address
+      parameter	sf_mask = 8'h0,			// slave f don't cares
+            
+      parameter	dw = 32,		// Data bus Width
+      parameter	aw = 32,		// Address bus Width
+      parameter	sw = 4)                 // Number of Select Lines
+      
+      (input clk_i, 
+       input rst_i,
+       
+       // Master  Interface
+       input [dw-1:0]   m0_dat_i,
+       output [dw-1:0] 	m0_dat_o,
+       input [aw-1:0] 	m0_adr_i,
+       input [sw-1:0] 	m0_sel_i,
+       input 		m0_we_i,
+       input 		m0_cyc_i,
+       input 		m0_stb_i,
+       output 		m0_ack_o,
+       output 		m0_err_o,
+       output 		m0_rty_o,
+       
+       // Slave Interfaces
+       input [dw-1:0] 	s0_dat_i,
+       output [dw-1:0] 	s0_dat_o,
+       output [aw-1:0] 	s0_adr_o,
+       output [sw-1:0] 	s0_sel_o,
+       output 		s0_we_o,
+       output 		s0_cyc_o,
+       output 		s0_stb_o,
+       input 		s0_ack_i,
+       input 		s0_err_i,
+       input 		s0_rty_i,
+       
+       input [dw-1:0] 	s1_dat_i,
+       output [dw-1:0] 	s1_dat_o,
+       output [aw-1:0] 	s1_adr_o,
+       output [sw-1:0] 	s1_sel_o,
+       output 		s1_we_o,
+       output 		s1_cyc_o,
+       output 		s1_stb_o,
+       input 		s1_ack_i,
+       input 		s1_err_i,
+       input 		s1_rty_i,
+       
+       input [dw-1:0] 	s2_dat_i,
+       output [dw-1:0] 	s2_dat_o,
+       output [aw-1:0] 	s2_adr_o,
+       output [sw-1:0] 	s2_sel_o,
+       output 		s2_we_o,
+       output 		s2_cyc_o,
+       output 		s2_stb_o,
+       input 		s2_ack_i,
+       input 		s2_err_i,
+       input 		s2_rty_i,
+       
+       input [dw-1:0] 	s3_dat_i,
+       output [dw-1:0] 	s3_dat_o,
+       output [aw-1:0] 	s3_adr_o,
+       output [sw-1:0] 	s3_sel_o,
+       output 		s3_we_o,
+       output 		s3_cyc_o,
+       output 		s3_stb_o,
+       input 		s3_ack_i,
+       input 		s3_err_i,
+       input 		s3_rty_i,
+       
+       input [dw-1:0] 	s4_dat_i,
+       output [dw-1:0] 	s4_dat_o,
+       output [aw-1:0] 	s4_adr_o,
+       output [sw-1:0] 	s4_sel_o,
+       output 		s4_we_o,
+       output 		s4_cyc_o,
+       output 		s4_stb_o,
+       input 		s4_ack_i,
+       input 		s4_err_i,
+       input 		s4_rty_i,
+       
+       input [dw-1:0] 	s5_dat_i,
+       output [dw-1:0] 	s5_dat_o,
+       output [aw-1:0] 	s5_adr_o,
+       output [sw-1:0] 	s5_sel_o,
+       output 		s5_we_o,
+       output 		s5_cyc_o,
+       output 		s5_stb_o,
+       input 		s5_ack_i,
+       input 		s5_err_i,
+       input 		s5_rty_i,
+       
+       input [dw-1:0] 	s6_dat_i,
+       output [dw-1:0] 	s6_dat_o,
+       output [aw-1:0] 	s6_adr_o,
+       output [sw-1:0] 	s6_sel_o,
+       output 		s6_we_o,
+       output 		s6_cyc_o,
+       output 		s6_stb_o,
+       input 		s6_ack_i,
+       input 		s6_err_i,
+       input 		s6_rty_i,
+       
+       input [dw-1:0] 	s7_dat_i,
+       output [dw-1:0] 	s7_dat_o,
+       output [aw-1:0] 	s7_adr_o,
+       output [sw-1:0] 	s7_sel_o,
+       output 		s7_we_o,
+       output 		s7_cyc_o,
+       output 		s7_stb_o,
+       input 		s7_ack_i,
+       input 		s7_err_i,
+       input 		s7_rty_i,
+
+       input [dw-1:0] 	s8_dat_i,
+       output [dw-1:0] 	s8_dat_o,
+       output [aw-1:0] 	s8_adr_o,
+       output [sw-1:0] 	s8_sel_o,
+       output 		s8_we_o,
+       output 		s8_cyc_o,
+       output 		s8_stb_o,
+       input 		s8_ack_i,
+       input 		s8_err_i,
+       input 		s8_rty_i,
+       
+       input [dw-1:0] 	s9_dat_i,
+       output [dw-1:0] 	s9_dat_o,
+       output [aw-1:0] 	s9_adr_o,
+       output [sw-1:0] 	s9_sel_o,
+       output 		s9_we_o,
+       output 		s9_cyc_o,
+       output 		s9_stb_o,
+       input 		s9_ack_i,
+       input 		s9_err_i,
+       input 		s9_rty_i,
+       
+       input [dw-1:0] 	sa_dat_i,
+       output [dw-1:0] 	sa_dat_o,
+       output [aw-1:0] 	sa_adr_o,
+       output [sw-1:0] 	sa_sel_o,
+       output 		sa_we_o,
+       output 		sa_cyc_o,
+       output 		sa_stb_o,
+       input 		sa_ack_i,
+       input 		sa_err_i,
+       input 		sa_rty_i,
+       
+       input [dw-1:0] 	sb_dat_i,
+       output [dw-1:0] 	sb_dat_o,
+       output [aw-1:0] 	sb_adr_o,
+       output [sw-1:0] 	sb_sel_o,
+       output 		sb_we_o,
+       output 		sb_cyc_o,
+       output 		sb_stb_o,
+       input 		sb_ack_i,
+       input 		sb_err_i,
+       input 		sb_rty_i,
+       
+       input [dw-1:0] 	sc_dat_i,
+       output [dw-1:0] 	sc_dat_o,
+       output [aw-1:0] 	sc_adr_o,
+       output [sw-1:0] 	sc_sel_o,
+       output 		sc_we_o,
+       output 		sc_cyc_o,
+       output 		sc_stb_o,
+       input 		sc_ack_i,
+       input 		sc_err_i,
+       input 		sc_rty_i,
+       
+       input [dw-1:0] 	sd_dat_i,
+       output [dw-1:0] 	sd_dat_o,
+       output [aw-1:0] 	sd_adr_o,
+       output [sw-1:0] 	sd_sel_o,
+       output 		sd_we_o,
+       output 		sd_cyc_o,
+       output 		sd_stb_o,
+       input 		sd_ack_i,
+       input 		sd_err_i,
+       input 		sd_rty_i,
+       
+       input [dw-1:0] 	se_dat_i,
+       output [dw-1:0] 	se_dat_o,
+       output [aw-1:0] 	se_adr_o,
+       output [sw-1:0] 	se_sel_o,
+       output 		se_we_o,
+       output 		se_cyc_o,
+       output 		se_stb_o,
+       input 		se_ack_i,
+       input 		se_err_i,
+       input 		se_rty_i,
+       
+       input [dw-1:0] 	sf_dat_i,
+       output [dw-1:0] 	sf_dat_o,
+       output [aw-1:0] 	sf_adr_o,
+       output [sw-1:0] 	sf_sel_o,
+       output 		sf_we_o,
+       output 		sf_cyc_o,
+       output 		sf_stb_o,
+       input 		sf_ack_i,
+       input 		sf_err_i,
+       input 		sf_rty_i
+       );
+   
+   // ////////////////////////////////////////////////////////////////
+   //
+   // Local wires
+   //
+   
+   wire [15:0] 		ssel_dec;
+   reg [dw-1:0] 	i_dat_s;	// internal share bus , slave data to master
+   
+   // Master output Interface
+   assign 		m0_dat_o = i_dat_s;
+   
+   always @*
+     case(ssel_dec)
+       1   : i_dat_s <= s0_dat_i;
+       2   : i_dat_s <= s1_dat_i;
+       4   : i_dat_s <= s2_dat_i;
+       8   : i_dat_s <= s3_dat_i;
+       16  : i_dat_s <= s4_dat_i;
+       32  : i_dat_s <= s5_dat_i;
+       64  : i_dat_s <= s6_dat_i;
+       128 : i_dat_s <= s7_dat_i;
+       256 : i_dat_s <= s8_dat_i;
+       512 : i_dat_s <= s9_dat_i;
+       1024 : i_dat_s <= sa_dat_i;
+       2048 : i_dat_s <= sb_dat_i;
+       4096 : i_dat_s <= sc_dat_i;
+       8192 : i_dat_s <= sd_dat_i;
+       16384 : i_dat_s <= se_dat_i;
+       32768 : i_dat_s <= sf_dat_i;
+       default : i_dat_s <= s0_dat_i;
+     endcase // case(ssel_dec)
+   
+   assign 		{m0_ack_o, m0_err_o, m0_rty_o} 
+     =  {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i |
+	 s8_ack_i | s9_ack_i | sa_ack_i | sb_ack_i | sc_ack_i | sd_ack_i | se_ack_i | sf_ack_i ,
+	 s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i |
+	 s8_err_i | s9_err_i | sa_err_i | sb_err_i | sc_err_i | sd_err_i | se_err_i | sf_err_i ,
+	 s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i |
+	 s8_rty_i | s9_rty_i | sa_rty_i | sb_rty_i | sc_rty_i | sd_rty_i | se_rty_i | sf_rty_i };
+
+   // Slave output interfaces
+   assign 		s0_adr_o = m0_adr_i;
+   assign 		s0_sel_o = m0_sel_i;
+   assign 		s0_dat_o = m0_dat_i;
+   assign 		s0_we_o = m0_we_i;
+   assign 		s0_cyc_o = m0_cyc_i;
+   assign 		s0_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[0];   
+   
+   assign 		s1_adr_o = m0_adr_i;
+   assign 		s1_sel_o = m0_sel_i;
+   assign 		s1_dat_o = m0_dat_i;
+   assign 		s1_we_o = m0_we_i;
+   assign 		s1_cyc_o = m0_cyc_i;
+   assign 		s1_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[1];   
+   
+   assign 		s2_adr_o = m0_adr_i;
+   assign 		s2_sel_o = m0_sel_i;
+   assign 		s2_dat_o = m0_dat_i;
+   assign 		s2_we_o = m0_we_i;
+   assign 		s2_cyc_o = m0_cyc_i;
+   assign 		s2_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[2];   
+   
+   assign 		s3_adr_o = m0_adr_i;
+   assign 		s3_sel_o = m0_sel_i;
+   assign 		s3_dat_o = m0_dat_i;
+   assign 		s3_we_o = m0_we_i;
+   assign 		s3_cyc_o = m0_cyc_i;
+   assign 		s3_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[3];   
+   
+   assign 		s4_adr_o = m0_adr_i;
+   assign 		s4_sel_o = m0_sel_i;
+   assign 		s4_dat_o = m0_dat_i;
+   assign 		s4_we_o = m0_we_i;
+   assign 		s4_cyc_o = m0_cyc_i;
+   assign 		s4_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[4];   
+   
+   assign 		s5_adr_o = m0_adr_i;
+   assign 		s5_sel_o = m0_sel_i;
+   assign 		s5_dat_o = m0_dat_i;
+   assign 		s5_we_o = m0_we_i;
+   assign 		s5_cyc_o = m0_cyc_i;
+   assign 		s5_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[5];   
+   
+   assign 		s6_adr_o = m0_adr_i;
+   assign 		s6_sel_o = m0_sel_i;
+   assign 		s6_dat_o = m0_dat_i;
+   assign 		s6_we_o = m0_we_i;
+   assign 		s6_cyc_o = m0_cyc_i;
+   assign 		s6_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[6];   
+   
+   assign 		s7_adr_o = m0_adr_i;
+   assign 		s7_sel_o = m0_sel_i;
+   assign 		s7_dat_o = m0_dat_i;
+   assign 		s7_we_o = m0_we_i;
+   assign 		s7_cyc_o = m0_cyc_i;
+   assign 		s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7];   
+   
+   assign 		s8_adr_o = m0_adr_i;
+   assign 		s8_sel_o = m0_sel_i;
+   assign 		s8_dat_o = m0_dat_i;
+   assign 		s8_we_o = m0_we_i;
+   assign 		s8_cyc_o = m0_cyc_i;
+   assign 		s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8];   
+   
+   assign 		s9_adr_o = m0_adr_i;
+   assign 		s9_sel_o = m0_sel_i;
+   assign 		s9_dat_o = m0_dat_i;
+   assign 		s9_we_o = m0_we_i;
+   assign 		s9_cyc_o = m0_cyc_i;
+   assign 		s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];   
+   
+   assign 		sa_adr_o = m0_adr_i;
+   assign 		sa_sel_o = m0_sel_i;
+   assign 		sa_dat_o = m0_dat_i;
+   assign 		sa_we_o = m0_we_i;
+   assign 		sa_cyc_o = m0_cyc_i;
+   assign 		sa_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];   
+   
+   assign 		sb_adr_o = m0_adr_i;
+   assign 		sb_sel_o = m0_sel_i;
+   assign 		sb_dat_o = m0_dat_i;
+   assign 		sb_we_o = m0_we_i;
+   assign 		sb_cyc_o = m0_cyc_i;
+   assign 		sb_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];   
+   
+   assign 		sc_adr_o = m0_adr_i;
+   assign 		sc_sel_o = m0_sel_i;
+   assign 		sc_dat_o = m0_dat_i;
+   assign 		sc_we_o = m0_we_i;
+   assign 		sc_cyc_o = m0_cyc_i;
+   assign 		sc_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];   
+   
+   assign 		sd_adr_o = m0_adr_i;
+   assign 		sd_sel_o = m0_sel_i;
+   assign 		sd_dat_o = m0_dat_i;
+   assign 		sd_we_o = m0_we_i;
+   assign 		sd_cyc_o = m0_cyc_i;
+   assign 		sd_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];   
+   
+   assign 		se_adr_o = m0_adr_i;
+   assign 		se_sel_o = m0_sel_i;
+   assign 		se_dat_o = m0_dat_i;
+   assign 		se_we_o = m0_we_i;
+   assign 		se_cyc_o = m0_cyc_i;
+   assign 		se_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];   
+   
+   assign 		sf_adr_o = m0_adr_i;
+   assign 		sf_sel_o = m0_sel_i;
+   assign 		sf_dat_o = m0_dat_i;
+   assign 		sf_we_o = m0_we_i;
+   assign 		sf_cyc_o = m0_cyc_i;
+   assign 		sf_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];   
+   
+   // Address decode logic
+   // WARNING -- must make sure these are mutually exclusive!
+
+
+   assign 		ssel_dec[0] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s0_addr) & s0_mask);
+   assign 		ssel_dec[1] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s1_addr) & s1_mask);
+   assign 		ssel_dec[2] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s2_addr) & s2_mask);
+   assign 		ssel_dec[3] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s3_addr) & s3_mask);
+   assign 		ssel_dec[4] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s4_addr) & s4_mask);
+   assign 		ssel_dec[5] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s5_addr) & s5_mask);
+   assign 		ssel_dec[6] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s6_addr) & s6_mask);
+   assign 		ssel_dec[7] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s7_addr) & s7_mask);
+   assign 		ssel_dec[8] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s8_addr) & s8_mask);
+   assign 		ssel_dec[9] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ s9_addr) & s9_mask);
+   assign 		ssel_dec[10] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sa_addr) & sa_mask);
+   assign 		ssel_dec[11] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sb_addr) & sb_mask);
+   assign 		ssel_dec[12] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sc_addr) & sc_mask);
+   assign 		ssel_dec[13] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sd_addr) & sd_mask);
+   assign 		ssel_dec[14] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ se_addr) & se_mask);
+   assign 		ssel_dec[15] = ~|((m0_adr_i[aw-1:aw-decode_w] ^ sf_addr) & sf_mask);
+
+/*
+   assign 		ssel_dec[0] = (m0_adr_i[aw -1 : aw - decode_w ] == s0_addr);
+   assign 		ssel_dec[1] = (m0_adr_i[aw -1 : aw - decode_w ] == s1_addr);
+   assign 		ssel_dec[2] = (m0_adr_i[aw -1 : aw - decode_w ] == s2_addr);
+   assign 		ssel_dec[3] = (m0_adr_i[aw -1 : aw - decode_w ] == s3_addr);
+   assign 		ssel_dec[4] = (m0_adr_i[aw -1 : aw - decode_w ] == s4_addr);
+   assign 		ssel_dec[5] = (m0_adr_i[aw -1 : aw - decode_w ] == s5_addr);
+   assign 		ssel_dec[6] = (m0_adr_i[aw -1 : aw - decode_w ] == s6_addr);
+   assign 		ssel_dec[7] = (m0_adr_i[aw -1 : aw - decode_w ] == s7_addr);
+   assign 		ssel_dec[8] = (m0_adr_i[aw -1 : aw - decode_w ] == s8_addr);
+   assign 		ssel_dec[9] = (m0_adr_i[aw -1 : aw - decode_w ] == s9_addr);
+   assign 		ssel_dec[10] = (m0_adr_i[aw -1 : aw - decode_w ] == sa_addr);
+   assign 		ssel_dec[11] = (m0_adr_i[aw -1 : aw - decode_w ] == sb_addr);
+   assign 		ssel_dec[12] = (m0_adr_i[aw -1 : aw - decode_w ] == sc_addr);
+   assign 		ssel_dec[13] = (m0_adr_i[aw -1 : aw - decode_w ] == sd_addr);
+   assign 		ssel_dec[14] = (m0_adr_i[aw -1 : aw - decode_w ] == se_addr);
+   assign 		ssel_dec[15] = (m0_adr_i[aw -1 : aw - decode_w ] == sf_addr);
+ */ 
+endmodule // wb_1master
diff --git a/fpga/usrp2/control_lib/wb_bridge_16_32.v b/fpga/usrp2/control_lib/wb_bridge_16_32.v
new file mode 100644
index 000000000..405e25c3c
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_bridge_16_32.v
@@ -0,0 +1,36 @@
+
+
+module wb_bridge_16_32
+  #(parameter AWIDTH=16)
+    (input wb_clk, input wb_rst,
+     input A_cyc_i, input A_stb_i, input A_we_i, input [3:0] A_sel_i,
+     input [AWIDTH-1:0] A_adr_i, input [31:0] A_dat_i, output [31:0] A_dat_o, output A_ack_o,
+     output B_cyc_o, output B_stb_o, output B_we_o, output [1:0] B_sel_o,
+     output [AWIDTH-1:0] B_adr_o, output [15:0] B_dat_o, input [15:0] B_dat_i, input B_ack_i
+     );
+
+   reg [15:0] 		 holding;
+   reg 			 phase;
+   
+   assign 		 B_adr_o = {A_adr_i[AWIDTH-1:2],phase,1'b0};
+   assign 		 B_cyc_o = A_cyc_i;
+   assign 		 B_stb_o = A_stb_i;
+   assign 		 B_we_o = A_we_i;
+
+   assign 		 B_dat_o = ~phase ? A_dat_i[15:0] : A_dat_i[31:16];
+   assign 		 B_sel_o = ~phase ? A_sel_i[1:0] : A_sel_i[3:2];
+
+   assign 		 A_dat_o = {B_dat_i,holding};
+   assign 		 A_ack_o = phase & B_ack_i;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       phase <= 0;
+     else if(B_ack_i)
+       phase <= ~phase;
+
+   always @(posedge wb_clk)
+     if(~phase & B_ack_i)
+       holding <= B_dat_i;
+   
+endmodule // wb_bridge_16_32
diff --git a/fpga/usrp2/control_lib/wb_bus_writer.v b/fpga/usrp2/control_lib/wb_bus_writer.v
new file mode 100644
index 000000000..fc148a0ff
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_bus_writer.v
@@ -0,0 +1,57 @@
+
+// wb_bus_writer
+//
+// WB Bus Master device to send a sequence of single-word transactions
+// based on a list in a RAM or ROM (FASM interface)
+// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]}
+// continues until it gets an all-1s entry
+
+module wb_bus_writer (input start,
+		      output done,
+		      output reg [15:0] rom_addr,
+		      input [47:0] rom_data,
+		      // WB Master Interface, don't need wb_dat_i
+		      input wb_clk_i,
+		      input wb_rst_i,
+		      output [31:0] wb_dat_o,
+		      input wb_ack_i,
+		      output [15:0] wb_adr_o,
+		      output wb_cyc_o,
+		      output [3:0] wb_sel_o,
+		      output wb_stb_o,
+		      output wb_we_o
+		      );
+
+`define IDLE 0
+`define READ 1
+   
+   reg [3:0] 		     state;
+   
+   assign 		     done = (state != `IDLE) && (&rom_data);  // Done when we see all 1s
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       begin
+	  rom_addr <= #1 0;
+	  state <= #1 0;
+       end
+     else if(start)
+       begin
+	  rom_addr <= #1 0;
+	  state <= #1 `READ;
+       end
+     else if((state == `READ) && wb_ack_i)
+       if(done)
+	 state <= #1 `IDLE;
+       else
+	 rom_addr <= #1 rom_addr + 1;
+   
+   assign wb_dat_o = rom_data[31:0];
+   assign wb_adr_o = rom_data[47:32];
+   assign wb_sel_o = 4'b1111;    // All writes are the full 32 bits
+   
+   assign wb_cyc_o = !done & (state != `IDLE);
+   assign wb_stb_o = !done & (state != `IDLE);
+   assign wb_we_o = !done & (state != `IDLE);
+   
+endmodule // wb_bus_writer
diff --git a/fpga/usrp2/control_lib/wb_output_pins32.v b/fpga/usrp2/control_lib/wb_output_pins32.v
new file mode 100644
index 000000000..1517f2066
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_output_pins32.v
@@ -0,0 +1,49 @@
+
+
+// Simple 32-bit Wishbone compatible slave output port
+// with 8-bit granularity, modeled after the one in the spec
+// Allows for readback
+// Assumes a 32-bit wishbone bus
+// Lowest order bits get sel[0]
+//
+
+module wb_output_pins32
+  (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o,
+   wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i,
+   port_output);
+
+   input wb_rst_i;
+   input wb_clk_i;
+   input wire [31:0] wb_dat_i;
+   output wire [31:0] wb_dat_o;
+   input  wb_we_i;
+   input  wire [3:0] 	 wb_sel_i;
+   input  wb_stb_i;
+   output wb_ack_o;
+   input  wb_cyc_i;
+
+   output wire [31:0] port_output;
+
+   reg [31:0] internal_reg;
+
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       internal_reg <= #1 32'b0;
+     else
+       begin
+	  if(wb_stb_i & wb_we_i & wb_sel_i[0])
+	    internal_reg[7:0] <= #1 wb_dat_i[7:0];
+	  if(wb_stb_i & wb_we_i & wb_sel_i[1])
+	    internal_reg[15:8] <= #1 wb_dat_i[15:8];
+	  if(wb_stb_i & wb_we_i & wb_sel_i[2])
+	    internal_reg[23:16] <= #1 wb_dat_i[23:16];
+	  if(wb_stb_i & wb_we_i & wb_sel_i[3])
+	    internal_reg[31:24] <= #1 wb_dat_i[31:24];
+       end // else: !if(wb_rst_i)
+
+   assign wb_dat_o = internal_reg;
+   assign port_output = internal_reg;
+   assign wb_ack_o = wb_stb_i;
+   	     
+endmodule // wb_output_pins32
+
diff --git a/fpga/usrp2/control_lib/wb_ram_block.v b/fpga/usrp2/control_lib/wb_ram_block.v
new file mode 100644
index 000000000..044d34ca4
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_ram_block.v
@@ -0,0 +1,36 @@
+
+
+// Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency
+//   These have to be a multiple of 512 lines (2K) long
+
+module wb_ram_block
+  #(parameter AWIDTH=9)
+    (input clk_i,
+     input stb_i,
+     input we_i,
+     input [AWIDTH-1:0] adr_i,
+     input [31:0] dat_i,
+     output reg [31:0] dat_o,
+     output ack_o);
+
+   reg [31:0] distram [0:1<<(AWIDTH-1)];
+
+   always @(posedge clk_i)
+     begin
+	if(stb_i & we_i)
+	  distram[adr_i] <= dat_i;
+	dat_o <= distram[adr_i];
+     end
+
+   reg stb_d1, ack_d1;
+   always @(posedge clk_i)
+     stb_d1 <= stb_i;
+   
+   always @(posedge clk_i)
+     ack_d1 <= ack_o;
+   
+   assign ack_o = stb_i & (we_i | (stb_d1 & ~ack_d1));
+endmodule // wb_ram_block
+
+
+    
diff --git a/fpga/usrp2/control_lib/wb_ram_dist.v b/fpga/usrp2/control_lib/wb_ram_dist.v
new file mode 100644
index 000000000..cffc2f423
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_ram_dist.v
@@ -0,0 +1,33 @@
+
+
+module wb_ram_dist
+  #(parameter AWIDTH=8)
+    (input clk_i,
+     input stb_i,
+     input we_i,
+     input [AWIDTH-1:0] adr_i,
+     input [31:0] dat_i,
+     input [3:0] sel_i,
+     output [31:0] dat_o,
+     output ack_o);
+
+   reg [31:0] distram [0:1<<(AWIDTH-1)];
+
+   always @(posedge clk_i)
+     begin
+	if(stb_i & we_i & sel_i[3])
+	  distram[adr_i][31:24] <= dat_i[31:24];
+	if(stb_i & we_i & sel_i[2])
+	  distram[adr_i][24:16] <= dat_i[24:16];
+	if(stb_i & we_i & sel_i[1])
+	  distram[adr_i][15:8] <= dat_i[15:8];
+	if(stb_i & we_i & sel_i[0])
+	  distram[adr_i][7:0] <= dat_i[7:0];
+     end // always @ (posedge clk_i)
+
+   assign dat_o = distram[adr_i];
+   assign ack_o = stb_i;
+
+endmodule // wb_ram_dist
+
+    
diff --git a/fpga/usrp2/control_lib/wb_readback_mux.v b/fpga/usrp2/control_lib/wb_readback_mux.v
new file mode 100644
index 000000000..3922b03e3
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_readback_mux.v
@@ -0,0 +1,60 @@
+
+
+// Note -- clocks must be synchronous (derived from the same source)
+// Assumes alt_clk is running at a multiple of wb_clk
+
+module wb_readback_mux
+  (input wb_clk_i,
+   input wb_rst_i,
+   input wb_stb_i,
+   input [15:0] wb_adr_i,
+   output reg [31:0] wb_dat_o,
+   output reg wb_ack_o,
+   
+   input [31:0] word00,
+   input [31:0] word01,
+   input [31:0] word02,
+   input [31:0] word03,
+   input [31:0] word04,
+   input [31:0] word05,
+   input [31:0] word06,
+   input [31:0] word07,
+   input [31:0] word08,
+   input [31:0] word09,
+   input [31:0] word10,
+   input [31:0] word11,
+   input [31:0] word12,
+   input [31:0] word13,
+   input [31:0] word14,
+   input [31:0] word15
+   );
+
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       wb_ack_o <= 0;
+     else
+       wb_ack_o <= wb_stb_i & ~wb_ack_o;
+   
+   always @(posedge wb_clk_i)
+     case(wb_adr_i[5:2])
+       0 : wb_dat_o <= word00;
+       1 : wb_dat_o <= word01;
+       2 : wb_dat_o <= word02;
+       3 : wb_dat_o <= word03;
+       4 : wb_dat_o <= word04;
+       5 : wb_dat_o <= word05;
+       6 : wb_dat_o <= word06;
+       7 : wb_dat_o <= word07;
+       8 : wb_dat_o <= word08;
+       9 : wb_dat_o <= word09;
+       10: wb_dat_o <= word10;
+       11: wb_dat_o <= word11;
+       12: wb_dat_o <= word12;
+       13: wb_dat_o <= word13;
+       14: wb_dat_o <= word14;
+       15: wb_dat_o <= word15;
+     endcase // case(addr_reg[3:0])
+      
+endmodule // wb_readback_mux
+
+
diff --git a/fpga/usrp2/control_lib/wb_regfile_2clock.v b/fpga/usrp2/control_lib/wb_regfile_2clock.v
new file mode 100644
index 000000000..e248e5161
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_regfile_2clock.v
@@ -0,0 +1,107 @@
+
+module wb_regfile_2clock
+  (input wb_clk_i,
+   input wb_rst_i,
+   input wb_stb_i,
+   input wb_we_i,
+   input [15:0] wb_adr_i,
+   input [3:0] wb_sel_i,
+   input [31:0] wb_dat_i,
+   output [31:0] wb_dat_o,
+   output wb_ack_o,
+   input alt_clk,
+   input alt_rst,
+   
+   output reg [31:0] reg00,
+   output reg [31:0] reg01,
+   output reg [31:0] reg02,
+   output reg [31:0] reg03,
+   output reg [31:0] reg04,
+   output reg [31:0] reg05,
+   output reg [31:0] reg06,
+   output reg [31:0] reg07
+   );
+
+   reg [15:0] 	 addr_reg;
+   reg [3:0] 	 sel_reg;
+   reg [31:0] 	 dat_reg;
+   reg 		 wr_ret1, wr_ret2, we_reg, stb_reg;
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       begin
+	  addr_reg <= 0;
+	  sel_reg <= 0;
+	  dat_reg <= 0;
+       end
+     else if(wb_stb_i & wb_we_i)
+       begin
+	  addr_reg <= wb_adr_i;
+	  sel_reg <= wb_sel_i;
+	  dat_reg <= wb_dat_i;
+       end
+   
+   always @(posedge wb_clk_i)
+     if(wb_rst_i)
+       {we_reg,stb_reg} <= 2'b0;
+     else
+       {we_reg,stb_reg} <= {wb_we_i,wb_stb_i};
+
+   assign wb_ack_o = stb_reg;
+   
+   always @(posedge alt_clk)
+     if(alt_rst)
+       {wr_ret2, wr_ret1} <= 2'b0;
+     else
+       {wr_ret2, wr_ret1} <= {wr_ret1, we_reg & stb_reg};
+   
+   always @(posedge alt_clk)
+     if(alt_rst)
+       begin
+	  reg00 <= 0;
+	  reg01 <= 0;
+	  reg02 <= 0;
+	  reg03 <= 0;
+	  reg04 <= 0;
+	  reg05 <= 0;
+	  reg06 <= 0;
+	  reg07 <= 0;
+       end // if (alt_rst)
+     else if(wr_ret2)
+       case(addr_reg[4:2])
+	 3'd0: reg00 <= { {sel_reg[3] ? dat_reg[31:24] : reg00[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg00[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg00[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg00[7:0]}};
+	 3'd1: reg01 <= { {sel_reg[3] ? dat_reg[31:24] : reg01[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg01[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg01[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg01[7:0]}};
+	 3'd2: reg02 <= { {sel_reg[3] ? dat_reg[31:24] : reg02[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg02[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg02[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg02[7:0]}};
+	 3'd3: reg03 <= { {sel_reg[3] ? dat_reg[31:24] : reg03[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg03[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg03[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg03[7:0]}};
+	 3'd4: reg04 <= { {sel_reg[3] ? dat_reg[31:24] : reg04[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg04[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg04[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg04[7:0]}};
+	 3'd5: reg05 <= { {sel_reg[3] ? dat_reg[31:24] : reg05[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg05[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg05[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg05[7:0]}};
+	 3'd6: reg06 <= { {sel_reg[3] ? dat_reg[31:24] : reg06[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg06[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg06[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg06[7:0]}};
+	 3'd7: reg07 <= { {sel_reg[3] ? dat_reg[31:24] : reg07[31:24]},
+			  {sel_reg[2] ? dat_reg[23:16] : reg07[23:16]},
+			  {sel_reg[1] ? dat_reg[15:8] : reg07[15:8]},
+			  {sel_reg[0] ? dat_reg[7:0] : reg07[7:0]}};
+       endcase // case(addr_reg[2:0])
+   
+endmodule // wb_regfile_2clock
+
diff --git a/fpga/usrp2/control_lib/wb_semaphore.v b/fpga/usrp2/control_lib/wb_semaphore.v
new file mode 100644
index 000000000..a9208e6a1
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_semaphore.v
@@ -0,0 +1,42 @@
+
+// up to 8 semaphores
+
+// After a read operation, the semaphore is always locked
+//  If it was already locked before the read (meaning someone else holds the lock)
+//    then a 1 is returned
+//  If it was not already locked (meaning the reader now holds the lock)
+//    then a 0 is returned
+
+// A write operation clears the lock
+
+module wb_semaphore 
+  #(parameter count=8, DBUS_WIDTH=32)
+    (input wb_clk_i,
+     input wb_rst_i,
+     input [DBUS_WIDTH-1:0] wb_dat_i,
+     input [2:0] wb_adr_i,
+     input wb_cyc_i,
+     input wb_stb_i,
+     input wb_we_i,
+     output wb_ack_o,
+     output [DBUS_WIDTH-1:0] wb_dat_o);
+
+   reg [count-1:0] locked;
+
+   always @(posedge clock)
+     if(wb_rst_i)
+       locked <= {count{1'b0}};
+     else if(wb_stb_i)
+       if(wb_we_i)
+	 locked[adr_i] <= 1'b0;
+       else
+	 locked[adr_i] <= 1'b1;
+
+   assign 	   wb_dat_o[DBUS_WIDTH-1:1] = {(DBUS_WIDTH-1){1'b0}};
+   assign 	   wb_dat_o[0] = locked[adr_i];
+   assign 	   wb_ack_o = wb_stb_i;
+   
+
+endmodule // wb_semaphore
+
+     
diff --git a/fpga/usrp2/control_lib/wb_sim.v b/fpga/usrp2/control_lib/wb_sim.v
new file mode 100644
index 000000000..b324e1457
--- /dev/null
+++ b/fpga/usrp2/control_lib/wb_sim.v
@@ -0,0 +1,79 @@
+
+
+module wb_sim();
+   
+   wire wb_clk, wb_rst;
+   wire start;
+
+   reg 	POR, aux_clk, clk_fpga;
+   
+   initial POR = 1'b1;
+   initial #103 POR = 1'b0;
+
+   initial aux_clk = 1'b0;
+   always #25 aux_clk = ~aux_clk;
+
+   initial clk_fpga = 1'bx;
+   initial #3007 clk_fpga = 1'b0;
+   always #7 clk_fpga = ~clk_fpga;
+      
+   initial begin
+      $dumpfile("wb_sim.vcd");
+      $dumpvars(0,wb_sim);
+   end
+
+   initial #10000 $finish;
+
+   wire [15:0] rom_addr;
+   wire [47:0] rom_data;
+   wire [31:0] wb_dat;
+   wire [15:0] wb_adr;
+   wire        wb_cyc,wb_stb,wb_we,wb_ack;
+   wire [3:0]  wb_sel;
+   
+   wire [31:0] port_output;
+
+
+   system_control system_control(.dsp_clk(dsp_clk),
+				 .reset_out(reset_out),
+				 .wb_clk_o(wb_clk),
+				 .wb_rst_o(wb_rst),
+				 .wb_rst_o_alt(wb_rst_o_alt),
+				 .start	(start),
+				 .aux_clk(aux_clk),
+				 .clk_fpga(clk_fpga),
+				 .POR	(POR),
+				 .done	(done));
+   
+   clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data));
+
+   wb_bus_writer bus_writer(.rom_addr	(rom_addr[15:0]),
+			    .wb_dat_o	(wb_dat[31:0]),
+			    .wb_adr_o	(wb_adr[15:0]),
+			    .wb_cyc_o	(wb_cyc),
+			    .wb_sel_o	(wb_sel[3:0]),
+			    .wb_stb_o	(wb_stb),
+			    .wb_we_o	(wb_we),
+			    .start	(start),
+			    .done       (done),
+			    .rom_data	(rom_data[47:0]),
+			    .wb_clk_i	(wb_clk),
+			    .wb_rst_i	(wb_rst),
+			    .wb_ack_i	(wb_ack));
+
+   wb_output_pins32 output_pins(.wb_dat_o(),
+				.wb_ack_o(wb_ack),
+				.port_output(port_output[31:0]),
+				.wb_rst_i(wb_rst),
+				.wb_clk_i(wb_clk),
+				.wb_dat_i(wb_dat[31:0]),
+				.wb_we_i(wb_we),
+				.wb_sel_i(wb_sel[3:0]),
+				.wb_stb_i(wb_stb),
+				.wb_cyc_i(wb_cyc));
+   
+   
+   
+   
+endmodule // wb_sim
+
diff --git a/fpga/usrp2/coregen/.gitignore b/fpga/usrp2/coregen/.gitignore
new file mode 100644
index 000000000..956cab52b
--- /dev/null
+++ b/fpga/usrp2/coregen/.gitignore
@@ -0,0 +1,3 @@
+/xlnx_auto*
+/*log
+/tmp
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp
new file mode 100644
index 000000000..810d64dac
--- /dev/null
+++ b/fpga/usrp2/coregen/coregen.cgp
@@ -0,0 +1,20 @@
+# Date: Thu Sep  3 17:40:48 2009
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = False
+SET workingdirectory = /home/matt/coregen/tmp
+
diff --git a/fpga/usrp2/coregen/fifo_generator_release_notes.txt b/fpga/usrp2/coregen/fifo_generator_release_notes.txt
new file mode 100644
index 000000000..554ec87f4
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_generator_release_notes.txt
@@ -0,0 +1,160 @@
+COPYRIGHT (c) 2006, 2007 XILINX, INC.
+ALL RIGHTS RESERVED
+
+Core name            : FIFO Generator 
+Version              : v4.1
+Release Date         : August 8, 2007
+File                 : fifo_generator_release_notes.txt
+
+Revision History
+Date     By            Version   Change Description
+========================================================================
+09/2006  Xilinx, Inc.  3.2       Initial creation.
+02/2007  Xilinx, Inc.  3.3       Revised for v3.3.
+02/2007  Xilinx, Inc.  3.3       Revised for v3.3 rev 1.
+08/2007  Xilinx, Inc.  3.4       Revised for v4.1.
+========================================================================
+
+INTRODUCTION
+RELEASE NOTES
+  1. General Core Design
+    1.1 Enhancements
+    1.2 Resolved Issues
+    1.3 Outstanding Issues
+  2. General Simulation
+    2.1 Enhancements
+    2.2 Resolved Issues
+    2.3 Outstanding Issues
+  3. Documentation
+    3.1 Enhancements
+    3.2 Resolved Issues
+    3.3 Outstanding Issues
+OTHER GENERAL INFORMATION
+TECHNICAL SUPPORT
+
+========================================================================
+
+INTRODUCTION
+============
+Thank you using the FIFO Generator core from Xilinx!  
+In order to obtain the latest core updates and documentation, 
+please visit the Intellectual Property page located at:
+http://www.xilinx.com/ipcenter/index.htm
+This document contains the release notes for FIFO Generator v4.1
+which includes enhancements, resolved issues and outstanding known
+issues.  For release notes and known issues for CORE Generator 9.2i IP
+Update 1 and FIFO Generator v4.1 please see Answer Record 25222.
+
+RELEASE NOTES
+=============
+This section lists any enhancements, resolved issues and outstanding
+known issues.
+
+
+1. General Core Design
+  1.1 Enhancements
+    1.1.1 Error Correction Checking (ECC) feature support for 
+          Virtex-5 block RAM FIFO configurations
+
+    1.1.2 Full range data count widths now supported for non-symmetric
+          aspect ratio configurations
+
+    1.1.3 Option to define asynchronous reset value for full condition 
+          flags (FULL, ALMOST_FULL, PROG_FULL).  Applies to block RAM, 
+          distributed RAM and shift RAM-based FIFO configurations only
+
+    1.1.4 Support added for use embedded output registers in block RAM
+          FIFO configurations (Virtex-4 and Virtex-5 only)
+
+  1.2 Resolved Issues
+    1.2.1 Coregen GUI - For built-in FIFOs,  GUI reports incorrect
+          number of built-in FIFO primitives used.
+          Change request: 4433738
+
+    1.2.2 Programmable full flag is always asserted even when FIFO is 
+          empty due to incorrect threshold setting.
+          Change request: 435835
+    
+    1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol
+          .. , these pins should be connected to the same signal" occur
+          during MAP when targeting Virtex-4 and Virtex-5.
+          Change request: 338260
+
+    1.2.4 Write Data Count and Read Data Count overestimate the number
+          of words written or read when core is configured with this 
+          combination of options: First-Word-Fall-Through(FWFT),
+          accurate data count using extra logic, non-symmetric port
+          aspect ratio.
+          Change request: 436886
+
+   1.2.5  SBITERR and DBITERR outputs are not driven in behavior
+          models.
+          Change request: 433637
+
+   1.2.6  Maximum programmable empty threshold negate value is 
+          incorrect.
+          Change request: 433921
+
+   1.2.7  Programmable full flag behavior is incorrect when the 
+          core is configured with this combination of options:
+          FWFT, non-symmetric port aspect ratio, single or 
+          multiple programmable full threshold input port.
+          Change request: 435874
+
+   1.2.8  Programmable empty flag stuck high when the core is
+          configured with this combination of options: block or
+          distributed RAM FIFO, single or multiple programmable 
+          empty threshold input port.
+          Change request: 443569
+
+  1.3 Outstanding Issues
+    1.3.1 "WARNING:Ngdbuild:452 - logical net 
+          'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during 
+          NgdBuild although programmable empty or full is not selected.          
+          Warnings can be safely ignored.
+          Change request: 431975
+
+2. General Simulation
+  2.1 Enhancements
+      None at this time.
+
+  2.2 Resolved Issues
+      None at this time.
+
+  2.3 Outstanding Issues
+    2.3.1 Ncelab warnings during Verilog structural and timing simulations 
+          in ncsim for Virtex5 Block RAM FIFOs. 
+          The simulations will be successful, but there will be warnings 
+          similar to the following in the log file: "memory index out of 
+          declared bounds" in simprims_ver_virtex5_source.v or 
+          unisims_ver_virtex5_source.v.  Cadence does not want to fix this 
+          issue. These warning messages can safely be ignored.
+          Change request: 423374, 423375
+
+3. Documentation
+  3.1 Enhancements
+    3.1.1 Added clarification on FIFO flag latency.
+  
+    3.1.1 Added clarification on actual FIFO depth.    
+
+  3.2 Resolved Issues
+      None at this time.
+      
+  3.3 Outstanding Issues
+      None at this time.
+
+
+TECHNICAL SUPPORT
+=================
+The fastest method for obtaining specific technical support for the 
+FIFO Generator core is through the http://support.xilinx.com/
+website. Questions are routed to a team of engineers with specific
+expertise in using the FIFO Generator core.  Xilinx will provide
+technical support for use of this product as described in the FIFO 
+Generator Datasheet. Xilinx cannot guarantee timing, functionality, 
+or support of this product for designs that do not follow these 
+guidelines.
+
+
+
+
diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf
new file mode 100644
index 000000000..2c3e3c200
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_generator_ug175.pdf
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc
new file mode 100644
index 000000000..b12d34d7c
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v
new file mode 100644
index 000000000..1d633384b
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.v
@@ -0,0 +1,169 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
+// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_16x19_2clk(
+	din,
+	rd_clk,
+	rd_en,
+	rst,
+	wr_clk,
+	wr_en,
+	dout,
+	empty,
+	full,
+	rd_data_count,
+	wr_data_count);
+
+
+input [18 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [18 : 0] dout;
+output empty;
+output full;
+output [4 : 0] rd_data_count;
+output [4 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_3 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(5),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(19),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(19),
+		.C_ENABLE_RLOCS(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(2),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("512x36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(15),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(14),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(5),
+		.C_RD_DEPTH(16),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(4),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(5),
+		.C_WR_DEPTH(16),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(4),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.DIN(din),
+		.RD_CLK(rd_clk),
+		.RD_EN(rd_en),
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.WR_EN(wr_en),
+		.DOUT(dout),
+		.EMPTY(empty),
+		.FULL(full),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.CLK(),
+		.INT_CLK(),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.RD_RST(),
+		.SRST(),
+		.WR_RST(),
+		.ALMOST_EMPTY(),
+		.ALMOST_FULL(),
+		.DATA_COUNT(),
+		.OVERFLOW(),
+		.PROG_EMPTY(),
+		.PROG_FULL(),
+		.VALID(),
+		.UNDERFLOW(),
+		.WR_ACK(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo
new file mode 100644
index 000000000..2e9af1efa
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_16x19_2clk YourInstanceName (
+	.din(din), // Bus [18 : 0] 
+	.rd_clk(rd_clk),
+	.rd_en(rd_en),
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.wr_en(wr_en),
+	.dout(dout), // Bus [18 : 0] 
+	.empty(empty),
+	.full(full),
+	.rd_data_count(rd_data_count), // Bus [4 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [4 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_16x19_2clk.v when simulating
+// the core, fifo_xlnx_16x19_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
new file mode 100644
index 000000000..d0f638026
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Fri Sep 11 04:33:27 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_16x19_2clk
+CSET data_count=false
+CSET data_count_width=5
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=15
+CSET full_threshold_negate_value=14
+CSET input_data_width=19
+CSET input_depth=16
+CSET output_data_width=19
+CSET output_depth=16
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=5
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=5
+# END Parameters
+GENERATE
+# CRC: 60b85dda
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
new file mode 100644
index 000000000..f1a6f7899
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.lso
@@ -0,0 +1,3 @@
+blkmemdp_v6_2
+blk_mem_gen_v2_6
+fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
new file mode 100644
index 000000000..ef33fff67
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
@@ -0,0 +1,103 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.03">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Thu Sep 10 21:33:06 2009">
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="32">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+        <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_4BIT_REGISTER" value="11"/>
+        <item dataType="int" stringID="XST_5BIT_REGISTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="28">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="1"/>
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_4BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="107">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="107"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="28">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="28"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="126">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="126"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="101"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="66">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="2"/>
+          <item dataType="int" stringID="XST_LUT2" value="18"/>
+          <item dataType="int" stringID="XST_LUT2L" value="1"/>
+          <item dataType="int" stringID="XST_LUT3" value="8"/>
+          <item dataType="int" stringID="XST_LUT4" value="30"/>
+          <item dataType="int" stringID="XST_LUT4D" value="3"/>
+          <item dataType="int" stringID="XST_LUT4L" value="3"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="126">
+          <item dataType="int" stringID="XST_FD" value="4"/>
+          <item dataType="int" stringID="XST_FDC" value="40"/>
+          <item dataType="int" stringID="XST_FDCE" value="62"/>
+          <item dataType="int" stringID="XST_FDP" value="10"/>
+          <item dataType="int" stringID="XST_FDPE" value="5"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="19">
+          <item dataType="int" stringID="XST_RAM16X1D" value="19"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+      <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="96"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="126"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="103"/>
+      <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="65"/>
+      <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="38"/>
+      <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="101"/>
+      <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="73"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
+    </section>
+  </application>
+
+</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt
new file mode 100644
index 000000000..5e1a6ed35
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_flist.txt
@@ -0,0 +1,8 @@
+# Output products list for <fifo_xlnx_16x19_2clk>
+fifo_xlnx_16x19_2clk.ngc
+fifo_xlnx_16x19_2clk.v
+fifo_xlnx_16x19_2clk.veo
+fifo_xlnx_16x19_2clk.xco
+fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_16x19_2clk_flist.txt
+fifo_xlnx_16x19_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt
new file mode 100644
index 000000000..1b5976555
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_readme.txt
@@ -0,0 +1,39 @@
+The following files were generated for 'fifo_xlnx_16x19_2clk' in directory 
+/home/matt/gnuradio.git/usrp2/fpga/coregen/:
+
+fifo_xlnx_16x19_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_16x19_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_16x19_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_16x19_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+fifo_xlnx_16x19_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+fifo_xlnx_16x19_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_16x19_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
new file mode 100644
index 000000000..8d633e9c2
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_16x19_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_16x19_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_16x19_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_16x19_2clk
+}
+# ::fifo_xlnx_16x19_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_16x19_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_16x19_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_16x19_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy
new file mode 100644
index 000000000..a87aa2f84
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.asy
@@ -0,0 +1,49 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_xlnx_2Kx36_2clk
+RECTANGLE Normal 32 32 544 672
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 144 704 144 672
+PIN 144 704 BOTTOM 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 576 208 544 208
+PIN 576 208 RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName wr_data_count[11:0]
+PINATTR Polarity OUT
+LINE Normal 576 432 544 432
+PIN 576 432 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Wide 576 592 544 592
+PIN 576 592 RIGHT 36
+PINATTR PinName rd_data_count[11:0]
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc
new file mode 100644
index 000000000..684eb74f4
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym
new file mode 100644
index 000000000..5d56b5c98
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.sym
@@ -0,0 +1,74 @@
+VERSION 5
+BEGIN SYMBOL fifo_xlnx_2Kx36_2clk
+SYMBOLTYPE BLOCK
+TIMESTAMP 2009 9 3 17 25 13
+SYMPIN 0 80 Input din[35:0]
+SYMPIN 0 144 Input wr_en
+SYMPIN 0 176 Input wr_clk
+SYMPIN 0 240 Input rd_en
+SYMPIN 0 272 Input rd_clk
+SYMPIN 144 704 Input rst
+SYMPIN 576 80 Output dout[35:0]
+SYMPIN 576 208 Output full
+SYMPIN 576 368 Output wr_data_count[11:0]
+SYMPIN 576 432 Output empty
+SYMPIN 576 592 Output rd_data_count[11:0]
+BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk
+    FONT 40 "Arial"
+END DISPLAY
+RECTANGLE N 32 32 544 672 
+BEGIN LINE W 0 80 32 80 
+END LINE
+BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 144 32 144 
+BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 176 32 176 
+BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 240 32 240 
+BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 272 32 272 
+BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 144 704 144 672 
+BEGIN DISPLAY 144 668 PIN rst ATTR PinName
+    ALIGNMENT BCENTER
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 576 80 544 80 
+END LINE
+BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 576 208 544 208 
+BEGIN DISPLAY 540 208 PIN full ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 576 368 544 368 
+END LINE
+BEGIN DISPLAY 540 368 PIN wr_data_count[11:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 576 432 544 432 
+BEGIN DISPLAY 540 432 PIN empty ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 576 592 544 592 
+END LINE
+BEGIN DISPLAY 540 592 PIN rd_data_count[11:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+END SYMBOL
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
new file mode 100644
index 000000000..0762b3ae9
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.v
@@ -0,0 +1,173 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating
+// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_2Kx36_2clk(
+	din,
+	rd_clk,
+	rd_en,
+	rst,
+	wr_clk,
+	wr_en,
+	dout,
+	empty,
+	full,
+	rd_data_count,
+	wr_data_count);
+
+
+input [35 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [35 : 0] dout;
+output empty;
+output full;
+output [11 : 0] rd_data_count;
+output [11 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_3 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(12),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("2kx18"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(2047),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(2046),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(12),
+		.C_RD_DEPTH(2048),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(11),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(12),
+		.C_WR_DEPTH(2048),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(11),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.DIN(din),
+		.RD_CLK(rd_clk),
+		.RD_EN(rd_en),
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.WR_EN(wr_en),
+		.DOUT(dout),
+		.EMPTY(empty),
+		.FULL(full),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.CLK(),
+		.INT_CLK(),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.RD_RST(),
+		.SRST(),
+		.WR_RST(),
+		.ALMOST_EMPTY(),
+		.ALMOST_FULL(),
+		.DATA_COUNT(),
+		.OVERFLOW(),
+		.PROG_EMPTY(),
+		.PROG_FULL(),
+		.VALID(),
+		.UNDERFLOW(),
+		.WR_ACK(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+// XST black box declaration
+// box_type "black_box"
+// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box"
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo
new file mode 100644
index 000000000..af9191555
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_2Kx36_2clk YourInstanceName (
+	.din(din), // Bus [35 : 0] 
+	.rd_clk(rd_clk),
+	.rd_en(rd_en),
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.wr_en(wr_en),
+	.dout(dout), // Bus [35 : 0] 
+	.empty(empty),
+	.full(full),
+	.rd_data_count(rd_data_count), // Bus [11 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [11 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating
+// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd
new file mode 100644
index 000000000..53033dc97
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd
@@ -0,0 +1,156 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating
+-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_xlnx_2Kx36_2clk IS
+	port (
+	din: IN std_logic_VECTOR(35 downto 0);
+	rd_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(35 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	rd_data_count: OUT std_logic_VECTOR(11 downto 0);
+	wr_data_count: OUT std_logic_VECTOR(11 downto 0));
+END fifo_xlnx_2Kx36_2clk;
+
+ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS
+-- synthesis translate_off
+component wrapped_fifo_xlnx_2Kx36_2clk
+	port (
+	din: IN std_logic_VECTOR(35 downto 0);
+	rd_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(35 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	rd_data_count: OUT std_logic_VECTOR(11 downto 0);
+	wr_data_count: OUT std_logic_VECTOR(11 downto 0));
+end component;
+
+-- Configuration specification 
+	for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
+		generic map(
+			c_has_int_clk => 0,
+			c_rd_freq => 1,
+			c_wr_response_latency => 1,
+			c_has_srst => 0,
+			c_has_rd_data_count => 1,
+			c_din_width => 36,
+			c_has_wr_data_count => 1,
+			c_full_flags_rst_val => 1,
+			c_implementation_type => 2,
+			c_family => "spartan3",
+			c_use_embedded_reg => 0,
+			c_has_wr_rst => 0,
+			c_wr_freq => 1,
+			c_use_dout_rst => 1,
+			c_underflow_low => 0,
+			c_has_meminit_file => 0,
+			c_has_overflow => 0,
+			c_preload_latency => 0,
+			c_dout_width => 36,
+			c_msgon_val => 1,
+			c_rd_depth => 2048,
+			c_default_value => "BlankString",
+			c_mif_file_name => "BlankString",
+			c_has_underflow => 0,
+			c_has_rd_rst => 0,
+			c_has_almost_full => 0,
+			c_has_rst => 1,
+			c_data_count_width => 12,
+			c_has_wr_ack => 0,
+			c_use_ecc => 0,
+			c_wr_ack_low => 0,
+			c_common_clock => 0,
+			c_rd_pntr_width => 11,
+			c_use_fwft_data_count => 1,
+			c_has_almost_empty => 0,
+			c_rd_data_count_width => 12,
+			c_enable_rlocs => 0,
+			c_wr_pntr_width => 11,
+			c_overflow_low => 0,
+			c_prog_empty_type => 0,
+			c_optimization_mode => 0,
+			c_wr_data_count_width => 12,
+			c_preload_regs => 1,
+			c_dout_rst_val => "0",
+			c_has_data_count => 0,
+			c_prog_full_thresh_negate_val => 2046,
+			c_wr_depth => 2048,
+			c_prog_empty_thresh_negate_val => 5,
+			c_prog_empty_thresh_assert_val => 4,
+			c_has_valid => 0,
+			c_init_wr_pntr_val => 0,
+			c_prog_full_thresh_assert_val => 2047,
+			c_use_fifo16_flags => 0,
+			c_has_backup => 0,
+			c_valid_low => 0,
+			c_prim_fifo_type => "2kx18",
+			c_count_type => 0,
+			c_prog_full_type => 0,
+			c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_xlnx_2Kx36_2clk
+		port map (
+			din => din,
+			rd_clk => rd_clk,
+			rd_en => rd_en,
+			rst => rst,
+			wr_clk => wr_clk,
+			wr_en => wr_en,
+			dout => dout,
+			empty => empty,
+			full => full,
+			rd_data_count => rd_data_count,
+			wr_data_count => wr_data_count);
+-- synthesis translate_on
+
+END fifo_xlnx_2Kx36_2clk_a;
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho
new file mode 100644
index 000000000..5165b0bc4
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vho
@@ -0,0 +1,76 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component fifo_xlnx_2Kx36_2clk
+	port (
+	din: IN std_logic_VECTOR(35 downto 0);
+	rd_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(35 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	rd_data_count: OUT std_logic_VECTOR(11 downto 0);
+	wr_data_count: OUT std_logic_VECTOR(11 downto 0));
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo_xlnx_2Kx36_2clk
+		port map (
+			din => din,
+			rd_clk => rd_clk,
+			rd_en => rd_en,
+			rst => rst,
+			wr_clk => wr_clk,
+			wr_en => wr_en,
+			dout => dout,
+			empty => empty,
+			full => full,
+			rd_data_count => rd_data_count,
+			wr_data_count => wr_data_count);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating
+-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
new file mode 100644
index 000000000..e25ad38da
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Sep  3 17:25:43 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = True
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = VHDL
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Foundation_iSE
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = True
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_2Kx36_2clk
+CSET data_count=false
+CSET data_count_width=12
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=2047
+CSET full_threshold_negate_value=2046
+CSET input_data_width=36
+CSET input_depth=2048
+CSET output_data_width=36
+CSET output_depth=2048
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=12
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=12
+# END Parameters
+GENERATE
+# CRC: 2ae9f6ef
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
new file mode 100644
index 000000000..f1a6f7899
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso
@@ -0,0 +1,3 @@
+blkmemdp_v6_2
+blk_mem_gen_v2_6
+fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
new file mode 100644
index 000000000..5108be2c5
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
@@ -0,0 +1,106 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.03">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Thu Sep  3 10:25:17 2009">
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_11BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="31">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+        <item dataType="int" stringID="XST_11BIT_REGISTER" value="11"/>
+        <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_36BIT_REGISTER" value="1"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="91">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="90"/>
+        <item dataType="int" stringID="XST_1BIT_XOR6" value="1"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="1"/>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_11BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="189">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="189"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="91">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="90"/>
+        <item dataType="int" stringID="XST_1BIT_XOR6" value="1"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="222">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="222"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="198"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="283">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="1"/>
+          <item dataType="int" stringID="XST_LUT1" value="22"/>
+          <item dataType="int" stringID="XST_LUT2" value="63"/>
+          <item dataType="int" stringID="XST_LUT3" value="19"/>
+          <item dataType="int" stringID="XST_LUT3D" value="1"/>
+          <item dataType="int" stringID="XST_LUT3L" value="3"/>
+          <item dataType="int" stringID="XST_LUT4" value="62"/>
+          <item dataType="int" stringID="XST_LUT4D" value="2"/>
+          <item dataType="int" stringID="XST_MUXCY" value="64"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XORCY" value="44"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="222">
+          <item dataType="int" stringID="XST_FD" value="4"/>
+          <item dataType="int" stringID="XST_FDC" value="103"/>
+          <item dataType="int" stringID="XST_FDCE" value="88"/>
+          <item dataType="int" stringID="XST_FDP" value="10"/>
+          <item dataType="int" stringID="XST_FDPE" value="5"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="4">
+          <item dataType="int" stringID="XST_RAMB16S9S9" value="4"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+      <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="162"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="222"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="173"/>
+      <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="198"/>
+      <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+      <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="4"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="196"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="29"/>
+    </section>
+  </application>
+
+</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
new file mode 100644
index 000000000..670d84713
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_flist.txt
@@ -0,0 +1,12 @@
+# Output products list for <fifo_xlnx_2Kx36_2clk>
+fifo_xlnx_2Kx36_2clk.asy
+fifo_xlnx_2Kx36_2clk.ngc
+fifo_xlnx_2Kx36_2clk.sym
+fifo_xlnx_2Kx36_2clk.v
+fifo_xlnx_2Kx36_2clk.veo
+fifo_xlnx_2Kx36_2clk.vhd
+fifo_xlnx_2Kx36_2clk.vho
+fifo_xlnx_2Kx36_2clk.xco
+fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_2Kx36_2clk_flist.txt
+fifo_xlnx_2Kx36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
new file mode 100644
index 000000000..1879503a9
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_readme.txt
@@ -0,0 +1,55 @@
+The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory 
+/home/matt/gnuradio.git/usrp2/fpga/coregen/:
+
+fifo_xlnx_2Kx36_2clk.asy:
+   Graphical symbol information file. Used by the ISE tools and some
+   third party tools to create a symbol representing the core.
+
+fifo_xlnx_2Kx36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_2Kx36_2clk.sym:
+   Please see the core data sheet.
+
+fifo_xlnx_2Kx36_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_2Kx36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_2Kx36_2clk.vhd:
+   VHDL wrapper file provided to support functional simulation. This
+   file contains simulation model customization data that is passed to
+   a parameterized simulation model for the core.
+
+fifo_xlnx_2Kx36_2clk.vho:
+   VHO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a VHDL design.
+
+fifo_xlnx_2Kx36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+fifo_xlnx_2Kx36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+fifo_xlnx_2Kx36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_2Kx36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
new file mode 100644
index 000000000..cac25efd2
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl
@@ -0,0 +1,84 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk
+}
+# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy
new file mode 100644
index 000000000..ecc80b648
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.asy
@@ -0,0 +1,49 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk
+RECTANGLE Normal 32 32 544 672
+LINE Wide 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName din[35:0]
+PINATTR Polarity IN
+LINE Normal 0 144 32 144
+PIN 0 144 LEFT 36
+PINATTR PinName wr_en
+PINATTR Polarity IN
+LINE Normal 0 176 32 176
+PIN 0 176 LEFT 36
+PINATTR PinName wr_clk
+PINATTR Polarity IN
+LINE Normal 0 240 32 240
+PIN 0 240 LEFT 36
+PINATTR PinName rd_en
+PINATTR Polarity IN
+LINE Normal 0 272 32 272
+PIN 0 272 LEFT 36
+PINATTR PinName rd_clk
+PINATTR Polarity IN
+LINE Normal 144 704 144 672
+PIN 144 704 BOTTOM 36
+PINATTR PinName rst
+PINATTR Polarity IN
+LINE Wide 576 80 544 80
+PIN 576 80 RIGHT 36
+PINATTR PinName dout[35:0]
+PINATTR Polarity OUT
+LINE Normal 576 208 544 208
+PIN 576 208 RIGHT 36
+PINATTR PinName full
+PINATTR Polarity OUT
+LINE Wide 576 368 544 368
+PIN 576 368 RIGHT 36
+PINATTR PinName wr_data_count[8:0]
+PINATTR Polarity OUT
+LINE Normal 576 432 544 432
+PIN 576 432 RIGHT 36
+PINATTR PinName empty
+PINATTR Polarity OUT
+LINE Wide 576 592 544 592
+PIN 576 592 RIGHT 36
+PINATTR PinName rd_data_count[8:0]
+PINATTR Polarity OUT
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc
new file mode 100644
index 000000000..55486485a
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
+$4g64g<,[o}e~g`n;"2*413&;$>"9 > %17?*nhel%fmyz cnpfc`h(|dz$Sni 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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym
new file mode 100644
index 000000000..13e8af33d
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.sym
@@ -0,0 +1,74 @@
+VERSION 5
+BEGIN SYMBOL fifo_xlnx_512x36_2clk
+SYMBOLTYPE BLOCK
+TIMESTAMP 2008 7 28 22 45 53
+SYMPIN 0 80 Input din[35:0]
+SYMPIN 0 144 Input wr_en
+SYMPIN 0 176 Input wr_clk
+SYMPIN 0 240 Input rd_en
+SYMPIN 0 272 Input rd_clk
+SYMPIN 144 704 Input rst
+SYMPIN 576 80 Output dout[35:0]
+SYMPIN 576 208 Output full
+SYMPIN 576 368 Output wr_data_count[8:0]
+SYMPIN 576 432 Output empty
+SYMPIN 576 592 Output rd_data_count[8:0]
+BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk
+    FONT 40 "Arial"
+END DISPLAY
+RECTANGLE N 32 32 544 672 
+BEGIN LINE W 0 80 32 80 
+END LINE
+BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 144 32 144 
+BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 176 32 176 
+BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 240 32 240 
+BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 0 272 32 272 
+BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 144 704 144 672 
+BEGIN DISPLAY 144 668 PIN rst ATTR PinName
+    ALIGNMENT BCENTER
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 576 80 544 80 
+END LINE
+BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 576 208 544 208 
+BEGIN DISPLAY 540 208 PIN full ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 576 368 544 368 
+END LINE
+BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+LINE N 576 432 544 432 
+BEGIN DISPLAY 540 432 PIN empty ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+BEGIN LINE W 576 592 544 592 
+END LINE
+BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName
+    ALIGNMENT RIGHT
+    FONT 24 "Arial"
+END DISPLAY
+END SYMBOL
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v
new file mode 100644
index 000000000..905069743
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.v
@@ -0,0 +1,169 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating
+// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_512x36_2clk(
+	din,
+	rd_clk,
+	rd_en,
+	rst,
+	wr_clk,
+	wr_en,
+	dout,
+	empty,
+	full,
+	rd_data_count,
+	wr_data_count);
+
+
+input [35 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [35 : 0] dout;
+output empty;
+output full;
+output [9 : 0] rd_data_count;
+output [9 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_3 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(10),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(1),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("512x36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(511),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(510),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(10),
+		.C_RD_DEPTH(512),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(9),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(10),
+		.C_WR_DEPTH(512),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(9),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.DIN(din),
+		.RD_CLK(rd_clk),
+		.RD_EN(rd_en),
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.WR_EN(wr_en),
+		.DOUT(dout),
+		.EMPTY(empty),
+		.FULL(full),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.CLK(),
+		.INT_CLK(),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.RD_RST(),
+		.SRST(),
+		.WR_RST(),
+		.ALMOST_EMPTY(),
+		.ALMOST_FULL(),
+		.DATA_COUNT(),
+		.OVERFLOW(),
+		.PROG_EMPTY(),
+		.PROG_FULL(),
+		.VALID(),
+		.UNDERFLOW(),
+		.WR_ACK(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo
new file mode 100644
index 000000000..6699ee73b
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_512x36_2clk YourInstanceName (
+	.din(din), // Bus [35 : 0] 
+	.rd_clk(rd_clk),
+	.rd_en(rd_en),
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.wr_en(wr_en),
+	.dout(dout), // Bus [35 : 0] 
+	.empty(empty),
+	.full(full),
+	.rd_data_count(rd_data_count), // Bus [9 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [9 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating
+// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd
new file mode 100644
index 000000000..d9c2dd307
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd
@@ -0,0 +1,156 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
+-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
+-- The synthesis directives "translate_off/translate_on" specified
+-- below are supported by Xilinx, Mentor Graphics and Synplicity
+-- synthesis tools. Ensure they are correct for your synthesis tool(s).
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+-- synthesis translate_off
+Library XilinxCoreLib;
+-- synthesis translate_on
+ENTITY fifo_xlnx_512x36_2clk IS
+	port (
+	din: IN std_logic_VECTOR(35 downto 0);
+	rd_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(35 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	rd_data_count: OUT std_logic_VECTOR(8 downto 0);
+	wr_data_count: OUT std_logic_VECTOR(8 downto 0));
+END fifo_xlnx_512x36_2clk;
+
+ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS
+-- synthesis translate_off
+component wrapped_fifo_xlnx_512x36_2clk
+	port (
+	din: IN std_logic_VECTOR(35 downto 0);
+	rd_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(35 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	rd_data_count: OUT std_logic_VECTOR(8 downto 0);
+	wr_data_count: OUT std_logic_VECTOR(8 downto 0));
+end component;
+
+-- Configuration specification 
+	for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
+		generic map(
+			c_has_int_clk => 0,
+			c_rd_freq => 1,
+			c_wr_response_latency => 1,
+			c_has_srst => 0,
+			c_has_rd_data_count => 1,
+			c_din_width => 36,
+			c_has_wr_data_count => 1,
+			c_full_flags_rst_val => 1,
+			c_implementation_type => 2,
+			c_family => "spartan3",
+			c_use_embedded_reg => 0,
+			c_has_wr_rst => 0,
+			c_wr_freq => 1,
+			c_use_dout_rst => 0,
+			c_underflow_low => 0,
+			c_has_meminit_file => 0,
+			c_has_overflow => 0,
+			c_preload_latency => 0,
+			c_dout_width => 36,
+			c_msgon_val => 1,
+			c_rd_depth => 512,
+			c_default_value => "BlankString",
+			c_mif_file_name => "BlankString",
+			c_has_underflow => 0,
+			c_has_rd_rst => 0,
+			c_has_almost_full => 0,
+			c_has_rst => 1,
+			c_data_count_width => 9,
+			c_has_wr_ack => 0,
+			c_use_ecc => 0,
+			c_wr_ack_low => 0,
+			c_common_clock => 0,
+			c_rd_pntr_width => 9,
+			c_use_fwft_data_count => 0,
+			c_has_almost_empty => 0,
+			c_rd_data_count_width => 9,
+			c_enable_rlocs => 0,
+			c_wr_pntr_width => 9,
+			c_overflow_low => 0,
+			c_prog_empty_type => 0,
+			c_optimization_mode => 0,
+			c_wr_data_count_width => 9,
+			c_preload_regs => 1,
+			c_dout_rst_val => "0",
+			c_has_data_count => 0,
+			c_prog_full_thresh_negate_val => 510,
+			c_wr_depth => 512,
+			c_prog_empty_thresh_negate_val => 5,
+			c_prog_empty_thresh_assert_val => 4,
+			c_has_valid => 0,
+			c_init_wr_pntr_val => 0,
+			c_prog_full_thresh_assert_val => 511,
+			c_use_fifo16_flags => 0,
+			c_has_backup => 0,
+			c_valid_low => 0,
+			c_prim_fifo_type => "512x36",
+			c_count_type => 0,
+			c_prog_full_type => 0,
+			c_memory_type => 1);
+-- synthesis translate_on
+BEGIN
+-- synthesis translate_off
+U0 : wrapped_fifo_xlnx_512x36_2clk
+		port map (
+			din => din,
+			rd_clk => rd_clk,
+			rd_en => rd_en,
+			rst => rst,
+			wr_clk => wr_clk,
+			wr_en => wr_en,
+			dout => dout,
+			empty => empty,
+			full => full,
+			rd_data_count => rd_data_count,
+			wr_data_count => wr_data_count);
+-- synthesis translate_on
+
+END fifo_xlnx_512x36_2clk_a;
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho
new file mode 100644
index 000000000..70eac27a5
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vho
@@ -0,0 +1,76 @@
+--------------------------------------------------------------------------------
+--     This file is owned and controlled by Xilinx and must be used           --
+--     solely for design, simulation, implementation and creation of          --
+--     design files limited to Xilinx devices or technologies. Use            --
+--     with non-Xilinx devices or technologies is expressly prohibited        --
+--     and immediately terminates your license.                               --
+--                                                                            --
+--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
+--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
+--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
+--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
+--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
+--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
+--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
+--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
+--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
+--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
+--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
+--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
+--     FOR A PARTICULAR PURPOSE.                                              --
+--                                                                            --
+--     Xilinx products are not intended for use in life support               --
+--     appliances, devices, or systems. Use in such applications are          --
+--     expressly prohibited.                                                  --
+--                                                                            --
+--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
+--     All rights reserved.                                                   --
+--------------------------------------------------------------------------------
+-- The following code must appear in the VHDL architecture header:
+
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component fifo_xlnx_512x36_2clk
+	port (
+	din: IN std_logic_VECTOR(35 downto 0);
+	rd_clk: IN std_logic;
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	wr_clk: IN std_logic;
+	wr_en: IN std_logic;
+	dout: OUT std_logic_VECTOR(35 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	rd_data_count: OUT std_logic_VECTOR(8 downto 0);
+	wr_data_count: OUT std_logic_VECTOR(8 downto 0));
+end component;
+
+-- Synplicity black box declaration
+attribute syn_black_box : boolean;
+attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : fifo_xlnx_512x36_2clk
+		port map (
+			din => din,
+			rd_clk => rd_clk,
+			rd_en => rd_en,
+			rst => rst,
+			wr_clk => wr_clk,
+			wr_en => wr_en,
+			dout => dout,
+			empty => empty,
+			full => full,
+			rd_data_count => rd_data_count,
+			wr_data_count => wr_data_count);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
+
+-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
+-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
+-- reference the XilinxCoreLib VHDL simulation library. For detailed
+-- instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
new file mode 100644
index 000000000..5934ef285
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Sep  3 17:24:24 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_512x36_2clk
+CSET data_count=false
+CSET data_count_width=10
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Block_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=511
+CSET full_threshold_negate_value=510
+CSET input_data_width=36
+CSET input_depth=512
+CSET output_data_width=36
+CSET output_depth=512
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=10
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=10
+# END Parameters
+GENERATE
+# CRC: b7f2a9ba
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
new file mode 100644
index 000000000..f1a6f7899
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso
@@ -0,0 +1,3 @@
+blkmemdp_v6_2
+blk_mem_gen_v2_6
+fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
new file mode 100644
index 000000000..d110a0158
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
@@ -0,0 +1,109 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.03">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Thu Sep  3 10:23:58 2009">
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
+        <item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="31">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+        <item dataType="int" stringID="XST_10BIT_REGISTER" value="2"/>
+        <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_36BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_9BIT_REGISTER" value="11"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="68">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="68"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="1"/>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
+        <item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2">
+        <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/>
+      </item>
+      <item dataType="int" stringID="XST_REGISTERS" value="165">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="165"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="68">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="68"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="192">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="192"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="180"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="223">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="1"/>
+          <item dataType="int" stringID="XST_LUT1" value="18"/>
+          <item dataType="int" stringID="XST_LUT2" value="50"/>
+          <item dataType="int" stringID="XST_LUT2D" value="1"/>
+          <item dataType="int" stringID="XST_LUT3" value="16"/>
+          <item dataType="int" stringID="XST_LUT3D" value="1"/>
+          <item dataType="int" stringID="XST_LUT3L" value="1"/>
+          <item dataType="int" stringID="XST_LUT4" value="45"/>
+          <item dataType="int" stringID="XST_MUXCY" value="52"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XORCY" value="36"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="192">
+          <item dataType="int" stringID="XST_FD" value="4"/>
+          <item dataType="int" stringID="XST_FDC" value="85"/>
+          <item dataType="int" stringID="XST_FDCE" value="78"/>
+          <item dataType="int" stringID="XST_FDP" value="10"/>
+          <item dataType="int" stringID="XST_FDPE" value="5"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="1">
+          <item dataType="int" stringID="XST_RAMB16S36S36" value="1"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+      <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="137"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="192"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="133"/>
+      <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="180"/>
+      <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+      <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="128"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="17"/>
+    </section>
+  </application>
+
+</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt
new file mode 100644
index 000000000..b0975be2d
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_flist.txt
@@ -0,0 +1,8 @@
+# Output products list for <fifo_xlnx_512x36_2clk>
+fifo_xlnx_512x36_2clk.ngc
+fifo_xlnx_512x36_2clk.v
+fifo_xlnx_512x36_2clk.veo
+fifo_xlnx_512x36_2clk.xco
+fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_512x36_2clk_flist.txt
+fifo_xlnx_512x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt
new file mode 100644
index 000000000..a250a74f5
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_readme.txt
@@ -0,0 +1,39 @@
+The following files were generated for 'fifo_xlnx_512x36_2clk' in directory 
+/home/matt/gnuradio.git/usrp2/fpga/coregen/:
+
+fifo_xlnx_512x36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_512x36_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_512x36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_512x36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+fifo_xlnx_512x36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+fifo_xlnx_512x36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_512x36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
new file mode 100644
index 000000000..8a0c0e3ff
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_512x36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_512x36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk
+}
+# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc
new file mode 100644
index 000000000..e8c55a1af
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.ngc
@@ -0,0 +1,3 @@
+XILINX-XDB 0.1 STUB 0.1 ASCII
+XILINX-XDM V1.4e
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p`>2`c94?7|@=2;7p`>2``94?7|@=2;7p`>2`a94?7|@=2;7p`>2`f94?7|@=2;7p`>2`g94?7|@=2;7p`>2`d94?7|@=2;7p`>2c294?7|@=2;7p`>2c394?7|@=2;7p`>2c094?7|@=2;7p`>2c194?7|@=2;7p`>2c694?7|@=2;7p`>2c794?7|@=2;7p`>2c494?7|@=2;7p`>2c594?7|@=2;7p`>2c:94?7|@=2;7p`>2c;94?7|@=2;7p`>2cc94?7|@=2;7p`>2c`94?7|@=2;7p`>2ca94?7|@=2;7p`>2cf94?7|@=2;7p`>2cg94?7|@=2;7p`>2cd94?7|@=2;7p`>2b294?7|@=2;7p`>2b394?7|@=2;7p`>2b094?7|@=2;7p`>2b194?7|@=2;7p`>2b694?7|@=2;7p`>2b794?7|@=2;7p`>2b494?7|@=2;7p`>2b594?7|@=2;7p`>2b:94?7|@=2;7p`>2b;94?7|@=2;7p`>2bc94?7|@=2;7p`>2b`94?7|@=2;7p`>2ba94?7|@=2;7p`>2bf94?7|@=2;7p`>2bg94?7|@=2;7p`>2bd94?7|@=2;7p`>2e294?7|@=2;7p`>2e394?7|@=2;7p`>2e094?7|@=2;7p`>2e194?7|@=2;7p`>2e694?7|@=2;7p`>2e794?7|@=2;7p`>2e494?7|@=2;7p`>2e594?7|@=2;7p`>2e:94?7|@=2;7p`>2e;94?7|@=2;7p`>2ec94?7|@=2;7p`>2e`94?7|@=2;7p`>2ea94?7|@=2;7p`>2ef94?7|@=2;7p`>2eg94?7|@=2;7p`>2ed94?7|@=2;7p`>2d294?7|@=2;7p`>2d394?7|@=2;7p`>2d094?7|@=2;7p`>2d194?7|@=2;7p`>2d694?7|@=2;7p`>2d794?7|@=2;7p`>2d494?7|@=2;7p`>2d594?7|@=2;7p`>2d:94?7|@=2;7p`>2d;94?7|@=2;7p`>2dc94?7|@=2;7p`>2d`94?7|@=2;7p`>2da94?7|@=2;7p`>2df94?7|@=2;7p`>2dg94?7|@=2;7p`>2dd94?7|@=2;7p`>2g294?7|@=2;7p`>2g394?7|@=2;7p`>2g094?7|@=2;7p`>2g194?7|@=2;7p`>2g694?7|@=2;7p`>2g794?7|@=2;7p`>2g494?7|@=2;7p`>2g594?7|@=2;7p`>2g:94?7|@=2;7p`>2g;94?7|@=2;7p`>2gc94?7|@=2;7p`>2g`94?7|@=2;7p`>2ga94?7|@=2;7p`>2gf94?7|@=2;7p`>2gg94?7|@=2;7p`>2gd94?7|@=2;7p`>31294?7|@=2;7p`>31394?7|@=2;7p`>31094?7|@=2;7p`>31194?7|@=2;7p`>31694?7|@=2;7p`>31794?7|@=2;7p`>31494?7|@=2;7p`>31594?7|@=2;7p`>31:94?7|@=2;7p`>31;94?7|@=2;7p`>31c94?7|@=2;7p`>31`94?7|@=2;7p`>31a94?7|@=2;7p`>31f94?7|@=2;7p`>31g94?7|@=2;7p`>31d94?7|@=2;7p`>30294?7|@=2;7p`>30394?7|@=2;7p`>30094?7|@=2;7p`>30194?7|@=2;7p`>30694?7|@=2;7p`>30794?7|@=2;7p`>30494?7|@=2;7p`>30594?7|@=2;7p`>30:94?7|@=2;7p`>30;94?7|@=2;7p`>30c94?7|@=2;7p`>30`94?7|@=2;7p`>30a94?7|@=2;7p`>30f94?7|@=2;7p`>30g94?7|@=2;7p`>30d94?7|@=2;7p`>33294?7|@=2;7p`>33394?7|@=2;7p`>33094?7|@=2;7p`>33194?7|@=2;7p`>33694?7|@=2;7p`>33794?7|@=2;7p`>33494?7|@=2;7p`>33594?7|@=2;7p`>33:94?7|@=2;7p`>33;94?7|@=2;7p`>33c94?7|@=2;7p`>33`94?7|@=2;7p`>33a94?7|@=2;7p`>33f94?7|@=2;7p`>33g94?7|@=2;7p`>33d94?7|@=2;7p`>32294?7|@=2;7p`>32394?7|@=2;7p`>32094?7|@=2;7p`>32194?7|@=2;7p`>32694?7|@=2;7p`>32794?7|@=2;7p`>32494?7|@=2;7p`>32594?7|@=2;7p`>32:94?7|@=2;7p`>32;94?7|@=2;7p`>32c94?7|@=2;7p`>32`94?7|@=2;7p`>32a94?7|@=2;7p`>32f94?7|@=2;7p`>32g94?7|@=2;7p`>32d94?7|@=2;7p`>35294?7|@=2;7p`>35394?7|@=2;7p`>35094?7|@=2;7p`>35194?7|@=2;7p`>35694?7|@=2;7p`>35794?7|@=2;7p`>35494?7|@=2;7p`>35594?7|@=2;7p`>35:94?7|@=2;7p`>35;94?7|@=2;7p`>35c94?7|@=2;7p`>35`94?7|@=2;7p`>35a94?7|@=2;7p`>35f94?7|@=2;7p`>35g94?7|@=2;7p`>35d94?7|@=2;7p`>34294?7|@=2;7p`>34394?7|@=2;7p`>34094?7|@=2;7p`>34194?7|@=2;7p`>34694?7|@=2;7p`>34794?7|@=2;7p`>34494?7|@=2;7p`>34594?7|@=2;7p`>34:94?7|@=2;7p`>34;94?7|@=2;7p`>34c94?7|@=2;7p`>34`94?7|@=2;7p`>34a94?7|@=2;7p`>34f94?7|@=2;7p`>34g94?7|@=2;7p`>34d94?7|@=2;7p`>37294?7|@=2;7p`>37394?7|@=2;7p`>37094?7|@=2;7p`>37194?7|@=2;7p`>37694?7|@=2;7p`>37794?7|@=2;7p`>37494?7|@=2;7p`>37594?7|@=2;7p`>37:94?7|@=2;7p`>37;94?7|@=2;7p`>37c94?7|@=2;7p`>37`94?7|@=2;7p`>37a94?7|@=2;7p`>37f94?7|@=2;7p`>37g94?7|@=2;7p`>37d94?7|@=2;7p`>36294?7|@=2;7p`>36394?7|@=2;7p`>36094?7|@=2;7p`>36194?7|@=2;7p`>36694?7|@=2;7p`>36794?7|@=2;7p`>36494?7|@=2;7p`>36594?7|@=2;7p`>36:94?7|@=2;7p`>36;94?7|@=2;7p`>36c94?7|@=2;7p`>36`94?7|@=2;7p`>36a94?7|@=2;7p`>36f94?7|@=2;7p`>36g94?7|@=2;7p`>36d94?7|@=2;7p`>39294?7|@=2;7p`>39394?7|@=2;7p`>39094?7|@=2;7p`>39194?7|@=2;7p`>39694?7|@=2;7p`>39794?7|@=2;7p`>39494?7|@=2;7p`>39594?7|@=2;7p`>39:94?7|@=2;7p`>39;94?7|@=2;7p`>39c94?7|@=2;7p`>39`94?7|@=2;7p`>39a94?7|@=2;7p`>39f94?7|@=2;7p`>39g94?7|@=2;7p`>39d94?7|@=2;7p`>38294?7|@=2;7p`>38394?7|@=2;7p`>38094?7|@=2;7p`>38194?7|@=2;7p`>38694?7|@=2;7p`>38794?7|@=2;7p`>38494?7|@=2;7p`>38594?7|@=2;7p`>38:94?7|@=2;7p`>38;94?7|@=2;7p`>38c94?7|@=2;7p`>38`94?7|@=2;7p`>38a94?7|@=2;7p`>38f94?7|@=2;7p`>38g94?7|@=2;7p`>38d94?7|@=2;7p`>3`294?7|@=2;7p`>3`394?7|@=2;7p`>3`094?7|@=2;7p`>3`194?7|@=2;7p`>3`694?7|@=2;7p`>3`794?7|@=2;7p`>3`494?7|@=2;7p`>3`594?7|@=2;7p`>3`:94?7|@=2;7p`>3`;94?7|@=2;7p`>3`c94?7|@=2;7p`>3``94?7|@=2;7p`>3`a94?7|@=2;7p`>3`f94?7|@=2;7p`>3`g94?7|@=2;7p`>3`d94?7|@=2;7p`>3c294?7|@=2;7p`>3c394?7|@=2;7p`>3c094?7|@=2;7p`>3c194?7|@=2;7p`>3c694?7|@=2;7p`>3c794?7|@=2;7p`>3c494?7|@=2;7p`>3c594?7|@=2;7p`>3c:94?7|@=2;7p`>3c;94?7|@=2;7p`>3cc94?7|@=2;7p`>3c`94?7|@=2;7p`>3ca94?7|@=2;7p`>3cf94?7|@=2;7p`>3cg94?7|@=2;7p`>3cd94?7|@=2;7p`>3b294?7|@=2;7p`>3b394?7|@=2;7p`>3b094?7|@=2;7p`>3b194?7|@=2;7p`>3b694?7|@=2;7p`>3b794?7|@=2;7p`>3b494?7|@=2;7p`>3b594?7|@=2;7p`>3b:94?7|@=2;7p`>3b;94?7|@=2;7p`>3bc94?7|@=2;7p`>3b`94?7|@=2;7p`>3ba94?7|@=2;7p`>3bf94?7|@=2;7p`>3bg94?7|@=2;7p`>3bd94?7|@=2;7p`>3e294?7|@=2;7psr}AB@40?l3;?hkh977CDG}7uIJ[wpNO
\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v
new file mode 100644
index 000000000..e84237689
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v
@@ -0,0 +1,169 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating
+// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+`timescale 1ns/1ps
+
+module fifo_xlnx_64x36_2clk(
+	din,
+	rd_clk,
+	rd_en,
+	rst,
+	wr_clk,
+	wr_en,
+	dout,
+	empty,
+	full,
+	rd_data_count,
+	wr_data_count);
+
+
+input [35 : 0] din;
+input rd_clk;
+input rd_en;
+input rst;
+input wr_clk;
+input wr_en;
+output [35 : 0] dout;
+output empty;
+output full;
+output [6 : 0] rd_data_count;
+output [6 : 0] wr_data_count;
+
+// synthesis translate_off
+
+      FIFO_GENERATOR_V4_3 #(
+		.C_COMMON_CLOCK(0),
+		.C_COUNT_TYPE(0),
+		.C_DATA_COUNT_WIDTH(7),
+		.C_DEFAULT_VALUE("BlankString"),
+		.C_DIN_WIDTH(36),
+		.C_DOUT_RST_VAL("0"),
+		.C_DOUT_WIDTH(36),
+		.C_ENABLE_RLOCS(0),
+		.C_FAMILY("spartan3"),
+		.C_FULL_FLAGS_RST_VAL(1),
+		.C_HAS_ALMOST_EMPTY(0),
+		.C_HAS_ALMOST_FULL(0),
+		.C_HAS_BACKUP(0),
+		.C_HAS_DATA_COUNT(0),
+		.C_HAS_INT_CLK(0),
+		.C_HAS_MEMINIT_FILE(0),
+		.C_HAS_OVERFLOW(0),
+		.C_HAS_RD_DATA_COUNT(1),
+		.C_HAS_RD_RST(0),
+		.C_HAS_RST(1),
+		.C_HAS_SRST(0),
+		.C_HAS_UNDERFLOW(0),
+		.C_HAS_VALID(0),
+		.C_HAS_WR_ACK(0),
+		.C_HAS_WR_DATA_COUNT(1),
+		.C_HAS_WR_RST(0),
+		.C_IMPLEMENTATION_TYPE(2),
+		.C_INIT_WR_PNTR_VAL(0),
+		.C_MEMORY_TYPE(2),
+		.C_MIF_FILE_NAME("BlankString"),
+		.C_MSGON_VAL(1),
+		.C_OPTIMIZATION_MODE(0),
+		.C_OVERFLOW_LOW(0),
+		.C_PRELOAD_LATENCY(0),
+		.C_PRELOAD_REGS(1),
+		.C_PRIM_FIFO_TYPE("512x36"),
+		.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+		.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+		.C_PROG_EMPTY_TYPE(0),
+		.C_PROG_FULL_THRESH_ASSERT_VAL(63),
+		.C_PROG_FULL_THRESH_NEGATE_VAL(62),
+		.C_PROG_FULL_TYPE(0),
+		.C_RD_DATA_COUNT_WIDTH(7),
+		.C_RD_DEPTH(64),
+		.C_RD_FREQ(1),
+		.C_RD_PNTR_WIDTH(6),
+		.C_UNDERFLOW_LOW(0),
+		.C_USE_DOUT_RST(1),
+		.C_USE_ECC(0),
+		.C_USE_EMBEDDED_REG(0),
+		.C_USE_FIFO16_FLAGS(0),
+		.C_USE_FWFT_DATA_COUNT(1),
+		.C_VALID_LOW(0),
+		.C_WR_ACK_LOW(0),
+		.C_WR_DATA_COUNT_WIDTH(7),
+		.C_WR_DEPTH(64),
+		.C_WR_FREQ(1),
+		.C_WR_PNTR_WIDTH(6),
+		.C_WR_RESPONSE_LATENCY(1))
+	inst (
+		.DIN(din),
+		.RD_CLK(rd_clk),
+		.RD_EN(rd_en),
+		.RST(rst),
+		.WR_CLK(wr_clk),
+		.WR_EN(wr_en),
+		.DOUT(dout),
+		.EMPTY(empty),
+		.FULL(full),
+		.RD_DATA_COUNT(rd_data_count),
+		.WR_DATA_COUNT(wr_data_count),
+		.CLK(),
+		.INT_CLK(),
+		.BACKUP(),
+		.BACKUP_MARKER(),
+		.PROG_EMPTY_THRESH(),
+		.PROG_EMPTY_THRESH_ASSERT(),
+		.PROG_EMPTY_THRESH_NEGATE(),
+		.PROG_FULL_THRESH(),
+		.PROG_FULL_THRESH_ASSERT(),
+		.PROG_FULL_THRESH_NEGATE(),
+		.RD_RST(),
+		.SRST(),
+		.WR_RST(),
+		.ALMOST_EMPTY(),
+		.ALMOST_FULL(),
+		.DATA_COUNT(),
+		.OVERFLOW(),
+		.PROG_EMPTY(),
+		.PROG_FULL(),
+		.VALID(),
+		.UNDERFLOW(),
+		.WR_ACK(),
+		.SBITERR(),
+		.DBITERR());
+
+
+// synthesis translate_on
+
+endmodule
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo
new file mode 100644
index 000000000..9c761370c
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.veo
@@ -0,0 +1,53 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used             *
+*     solely for design, simulation, implementation and creation of            *
+*     design files limited to Xilinx devices or technologies. Use              *
+*     with non-Xilinx devices or technologies is expressly prohibited          *
+*     and immediately terminates your license.                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"            *
+*     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                  *
+*     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION          *
+*     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION              *
+*     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                *
+*     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                  *
+*     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE         *
+*     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                 *
+*     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                  *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS          *
+*     FOR A PARTICULAR PURPOSE.                                                *
+*                                                                              *
+*     Xilinx products are not intended for use in life support                 *
+*     appliances, devices, or systems. Use in such applications are            *
+*     expressly prohibited.                                                    *
+*                                                                              *
+*     (c) Copyright 1995-2007 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// The following must be inserted into your Verilog file for this
+// core to be instantiated. Change the instance name and port connections
+// (in parentheses) to your own signal names.
+
+//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
+fifo_xlnx_64x36_2clk YourInstanceName (
+	.din(din), // Bus [35 : 0] 
+	.rd_clk(rd_clk),
+	.rd_en(rd_en),
+	.rst(rst),
+	.wr_clk(wr_clk),
+	.wr_en(wr_en),
+	.dout(dout), // Bus [35 : 0] 
+	.empty(empty),
+	.full(full),
+	.rd_data_count(rd_data_count), // Bus [6 : 0] 
+	.wr_data_count(wr_data_count)); // Bus [6 : 0] 
+
+// INST_TAG_END ------ End INSTANTIATION Template ---------
+
+// You must compile the wrapper file fifo_xlnx_64x36_2clk.v when simulating
+// the core, fifo_xlnx_64x36_2clk. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
new file mode 100644
index 000000000..c6e9aae27
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.xco
@@ -0,0 +1,82 @@
+##############################################################
+#
+# Xilinx Core Generator version K.39
+# Date: Thu Sep  3 17:22:56 2009
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = False
+SET asysymbol = False
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = False
+SET designentry = Verilog
+SET device = xc3s2000
+SET devicefamily = spartan3
+SET flowvendor = Other
+SET formalverification = False
+SET foundationsym = False
+SET implementationfiletype = Ngc
+SET package = fg456
+SET removerpms = False
+SET simulationfiles = Behavioral
+SET speedgrade = -5
+SET verilogsim = True
+SET vhdlsim = False
+# END Project Options
+# BEGIN Select
+SELECT Fifo_Generator family Xilinx,_Inc. 4.3
+# END Select
+# BEGIN Parameters
+CSET almost_empty_flag=false
+CSET almost_full_flag=false
+CSET component_name=fifo_xlnx_64x36_2clk
+CSET data_count=false
+CSET data_count_width=7
+CSET disable_timing_violations=false
+CSET dout_reset_value=0
+CSET empty_threshold_assert_value=4
+CSET empty_threshold_negate_value=5
+CSET enable_ecc=false
+CSET enable_int_clk=false
+CSET fifo_implementation=Independent_Clocks_Distributed_RAM
+CSET full_flags_reset_value=1
+CSET full_threshold_assert_value=63
+CSET full_threshold_negate_value=62
+CSET input_data_width=36
+CSET input_depth=64
+CSET output_data_width=36
+CSET output_depth=64
+CSET overflow_flag=false
+CSET overflow_sense=Active_High
+CSET performance_options=First_Word_Fall_Through
+CSET programmable_empty_type=No_Programmable_Empty_Threshold
+CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET read_clock_frequency=1
+CSET read_data_count=true
+CSET read_data_count_width=7
+CSET reset_pin=true
+CSET reset_type=Asynchronous_Reset
+CSET underflow_flag=false
+CSET underflow_sense=Active_High
+CSET use_dout_reset=true
+CSET use_embedded_registers=false
+CSET use_extra_logic=true
+CSET valid_flag=false
+CSET valid_sense=Active_High
+CSET write_acknowledge_flag=false
+CSET write_acknowledge_sense=Active_High
+CSET write_clock_frequency=1
+CSET write_data_count=true
+CSET write_data_count_width=7
+# END Parameters
+GENERATE
+# CRC: 2bb925ae
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
new file mode 100644
index 000000000..f1a6f7899
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.lso
@@ -0,0 +1,3 @@
+blkmemdp_v6_2
+blk_mem_gen_v2_6
+fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
new file mode 100644
index 000000000..a23402f56
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
@@ -0,0 +1,104 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<document OS="lin64" product="ISE" version="10.1.03">
+
+  <!--The data in this file is primarily intended for consumption by Xilinx tools.
+    The structure and the elements are likely to change over the next few releases.
+    This means code written to parse this file will need to be revisited each subsequent release.-->
+
+  <application stringID="Xst" timeStamp="Thu Sep  3 10:22:37 2009">
+    <section stringID="XST_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="32">
+        <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
+        <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
+        <item dataType="int" stringID="XST_36BIT_REGISTER" value="2"/>
+        <item dataType="int" stringID="XST_6BIT_REGISTER" value="11"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="44">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="44"/>
+      </item>
+    </section>
+    <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
+      <item dataType="int" stringID="XST_FSMS" value="1"/>
+      <item dataType="int" stringID="XST_RAMS" value="1"></item>
+      <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
+      <item dataType="int" stringID="XST_COUNTERS" value="2"></item>
+      <item dataType="int" stringID="XST_REGISTERS" value="165">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="165"/>
+      </item>
+      <item dataType="int" stringID="XST_XORS" value="44">
+        <item dataType="int" stringID="XST_1BIT_XOR2" value="44"/>
+      </item>
+    </section>
+    <section stringID="XST_FINAL_REGISTER_REPORT">
+      <item dataType="int" stringID="XST_REGISTERS" value="192">
+        <item dataType="int" stringID="XST_FLIPFLOPS" value="192"/>
+      </item>
+    </section>
+    <section stringID="XST_PARTITION_REPORT">
+      <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
+        <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+      </section>
+    </section>
+    <section stringID="XST_FINAL_REPORT">
+      <section stringID="XST_FINAL_RESULTS">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc"/>
+        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
+        <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
+        <item stringID="XST_KEEP_HIERARCHY" value="no"/>
+      </section>
+      <section stringID="XST_DESIGN_STATISTICS">
+        <item stringID="XST_IOS" value="153"/>
+      </section>
+      <section stringID="XST_CELL_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="227">
+          <item dataType="int" stringID="XST_GND" value="1"/>
+          <item dataType="int" stringID="XST_INV" value="3"/>
+          <item dataType="int" stringID="XST_LUT2" value="37"/>
+          <item dataType="int" stringID="XST_LUT2L" value="1"/>
+          <item dataType="int" stringID="XST_LUT3" value="86"/>
+          <item dataType="int" stringID="XST_LUT3D" value="1"/>
+          <item dataType="int" stringID="XST_LUT3L" value="3"/>
+          <item dataType="int" stringID="XST_LUT4" value="34"/>
+          <item dataType="int" stringID="XST_LUT4D" value="2"/>
+          <item dataType="int" stringID="XST_MUXCY" value="10"/>
+          <item dataType="int" stringID="XST_MUXF5" value="36"/>
+          <item dataType="int" stringID="XST_VCC" value="1"/>
+          <item dataType="int" stringID="XST_XORCY" value="12"/>
+        </item>
+        <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="192">
+          <item dataType="int" stringID="XST_FD" value="4"/>
+          <item dataType="int" stringID="XST_FDC" value="58"/>
+          <item dataType="int" stringID="XST_FDCE" value="108"/>
+          <item dataType="int" stringID="XST_FDP" value="10"/>
+          <item dataType="int" stringID="XST_FDPE" value="5"/>
+        </item>
+        <item dataType="int" stringID="XST_RAMS" value="144">
+          <item dataType="int" stringID="XST_RAM16X1D" value="144"/>
+        </item>
+      </section>
+    </section>
+    <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
+      <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
+      <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="188"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="192"/>
+      <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="455"/>
+      <item dataType="int" stringID="XST_NUMBER_USED_AS_LOGIC" value="167"/>
+      <item dataType="int" stringID="XST_NUMBER_USED_AS_RAMS" value="288"/>
+      <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="153"/>
+      <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
+    </section>
+    <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
+      <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
+    </section>
+    <section stringID="XST_ERRORS_STATISTICS">
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="73"/>
+      <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="10"/>
+    </section>
+  </application>
+
+</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt
new file mode 100644
index 000000000..44e31eb6c
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_flist.txt
@@ -0,0 +1,8 @@
+# Output products list for <fifo_xlnx_64x36_2clk>
+fifo_xlnx_64x36_2clk.ngc
+fifo_xlnx_64x36_2clk.v
+fifo_xlnx_64x36_2clk.veo
+fifo_xlnx_64x36_2clk.xco
+fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+fifo_xlnx_64x36_2clk_flist.txt
+fifo_xlnx_64x36_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt
new file mode 100644
index 000000000..7734c0087
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_readme.txt
@@ -0,0 +1,39 @@
+The following files were generated for 'fifo_xlnx_64x36_2clk' in directory 
+/home/matt/gnuradio.git/usrp2/fpga/coregen/:
+
+fifo_xlnx_64x36_2clk.ngc:
+   Binary Xilinx implementation netlist file containing the information
+   required to implement the module in a Xilinx (R) FPGA.
+
+fifo_xlnx_64x36_2clk.v:
+   Verilog wrapper file provided to support functional simulation.
+   This file contains simulation model customization data that is
+   passed to a parameterized simulation model for the core.
+
+fifo_xlnx_64x36_2clk.veo:
+   VEO template file containing code that can be used as a model for
+   instantiating a CORE Generator module in a Verilog design.
+
+fifo_xlnx_64x36_2clk.xco:
+   CORE Generator input file containing the parameters used to
+   regenerate a core.
+
+fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
+   Please see the core data sheet.
+
+fifo_xlnx_64x36_2clk_flist.txt:
+   Text file listing all of the output files produced when a customized
+   core was generated in the CORE Generator.
+
+fifo_xlnx_64x36_2clk_readme.txt:
+   Text file indicating the files generated and how they are used.
+
+fifo_xlnx_64x36_2clk_xmdf.tcl:
+   ISE Project Navigator interface file. ISE uses this file to determine
+   how the files output by CORE Generator for the core can be integrated
+   into your ISE project.
+
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+
diff --git a/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
new file mode 100644
index 000000000..ff5dfd3c2
--- /dev/null
+++ b/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk_xmdf.tcl
@@ -0,0 +1,68 @@
+# The package naming convention is <core_name>_xmdf
+package provide fifo_xlnx_64x36_2clk_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::fifo_xlnx_64x36_2clk_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_64x36_2clk
+}
+# ::fifo_xlnx_64x36_2clk_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::fifo_xlnx_64x36_2clk_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.v
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.veo
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_64x36_2clk_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_64x36_2clk
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/extram/.gitignore b/fpga/usrp2/extram/.gitignore
new file mode 100644
index 000000000..7fc71ccb6
--- /dev/null
+++ b/fpga/usrp2/extram/.gitignore
@@ -0,0 +1 @@
+/a.out
diff --git a/fpga/usrp2/extram/extram_interface.v b/fpga/usrp2/extram/extram_interface.v
new file mode 100644
index 000000000..7554592ba
--- /dev/null
+++ b/fpga/usrp2/extram/extram_interface.v
@@ -0,0 +1,53 @@
+
+// Temporary buffer pool storage, mostly useful for pre-generated data streams or
+//   for making more space to juggle packets in case of eth frames coming out of order
+
+module extram_interface
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+   
+   // Buffer pool interfaces
+   input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
+   input rd_sop_i, input rd_eop_i,
+   output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
+   input wr_ready_i, input wr_full_i,
+   
+   // RAM Interface
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   input RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn );
+
+   // Command format --
+   //    Read/_Write , start address[17:0]
+   wire [18:0] cmd_in;
+   wire        cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd;
+   wire        empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd;
+   
+   // Dummy logic
+   assign RAM_OEn = 1;
+   
+   setting_reg #(.my_addr(0)) 
+     sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+		 .in(set_data),.out(cmd_in),.changed(cmd_stb));
+   
+   reg 	  cmd_stb_d1;
+   always @(posedge clk) cmd_stb_d1 <= cmd_stb;
+   assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1;
+   assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1;   
+
+   shortfifo #(.WIDTH(19)) wr_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd),
+      .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) );
+
+   shortfifo #(.WIDTH(19)) rd_cmd_fifo
+     (.clk(clk),.rst(rst),.clear(1'b0),
+      .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd),
+      .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) );
+
+endmodule // extram_interface
diff --git a/fpga/usrp2/extram/extram_wb.v b/fpga/usrp2/extram/extram_wb.v
new file mode 100644
index 000000000..c8428783a
--- /dev/null
+++ b/fpga/usrp2/extram/extram_wb.v
@@ -0,0 +1,146 @@
+
+module extram_wb
+  #(parameter PAGE_SIZE = 10,
+    parameter ADDR_WIDTH = 16)
+    (input clk, input rst,
+     input wb_clk, input wb_rst,
+     input cyc_i, input stb_i,
+     input [ADDR_WIDTH-1:0] adr_i,
+     input we_i,
+     input [31:0] dat_i,
+     output reg [31:0] dat_o,
+     output reg ack_o,
+     
+     inout [17:0] RAM_D,
+     output [PAGE_SIZE-2:0] RAM_A,
+     output RAM_CE1n, output RAM_CENn,
+     output RAM_CLK, output RAM_WEn,
+     output RAM_OEn, output RAM_LDn );
+
+   wire     read_acc = stb_i & cyc_i & ~we_i;
+   wire     write_acc = stb_i & cyc_i & we_i;
+   wire     acc = stb_i & cyc_i;
+
+   assign   RAM_CLK = ~wb_clk;   // 50 MHz for now, eventually should be 200 MHz
+   assign   RAM_LDn = 0;        // No burst for now
+   assign   RAM_CENn = 0;       // Use CE1n as our main CE
+
+   reg [PAGE_SIZE-2:1] RAM_addr_reg;
+   always @(posedge wb_clk)
+     if(acc)
+       RAM_addr_reg[PAGE_SIZE-2:1] <= adr_i[PAGE_SIZE-1:2];
+   assign 	       RAM_A[PAGE_SIZE-2:1] = RAM_addr_reg; 
+
+   reg [31:0] 	       ram_out;
+   always @(posedge wb_clk)
+     if(write_acc)
+       ram_out <= dat_i;
+
+   // RAM access state machine
+   localparam RAM_idle = 0;
+   localparam RAM_read_1 = 1;
+   localparam RAM_read_2 = 2;
+   localparam RAM_read_3 = 3;
+   localparam RAM_read_4 = 4;
+   localparam RAM_write_1 = 6;
+   localparam RAM_write_2 = 7;
+   localparam RAM_write_3 = 8;
+   localparam RAM_write_4 = 9;
+
+   reg 	      myOE = 0;
+   reg 	      RAM_OE = 0;
+   reg 	      RAM_WE = 0;
+   reg 	      RAM_EN = 0;
+   reg 	      RAM_A0_reg;
+   reg [3:0]  RAM_state;
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       begin
+	  RAM_state <= RAM_idle;
+	  myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+       end
+     else
+       case(RAM_state)
+	 RAM_idle :
+	   if(read_acc & ~ack_o)
+	     begin
+		RAM_state <= RAM_read_1;
+		myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0;
+	     end
+	   else if(write_acc & ~ack_o)
+	     begin
+		RAM_state <= RAM_write_1;
+		myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0;
+	     end
+	   else
+	     begin
+		myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	     end
+	 RAM_read_1 : 
+	   begin
+	      RAM_state <= RAM_read_2;
+	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 1;
+	   end
+	 RAM_read_2 : 
+	   begin
+	      RAM_state <= RAM_read_3;
+	      myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_read_3 : 
+	   begin
+	      RAM_state <= RAM_read_4;
+	      myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_read_4 :
+	   begin
+	      RAM_state <= RAM_idle;
+	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_write_1 : 
+	   begin
+	      RAM_state <= RAM_write_2;
+	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1;
+	   end
+	 RAM_write_2 : 
+	   begin
+	      RAM_state <= RAM_write_3;
+	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_write_3 : 
+	   begin
+	      RAM_state <= RAM_write_4;
+	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 RAM_write_4 : 
+	   begin
+	      RAM_state <= RAM_idle;
+	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
+	   end
+	 default : RAM_state <= RAM_idle;
+       endcase // case(RAM_state)
+   
+   assign     RAM_A[0] = RAM_A0_reg;
+   assign     RAM_WEn = ~RAM_WE;  // ((RAM_state==RAM_write_1)||(RAM_state==RAM_write_2));
+   assign     RAM_OEn = ~RAM_OE;
+   assign     RAM_CE1n = ~RAM_EN;    // Active low     (RAM_state != RAM_idle);
+   
+   assign     RAM_D[17:16] = 2'bzz;
+   assign     RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) 
+	      : 16'bzzzz_zzzz_zzzz_zzzz;
+
+   always @(posedge wb_clk)
+     if(RAM_state == RAM_read_3)
+       dat_o[15:0] <= RAM_D[15:0];
+     else
+       dat_o[31:16] <= RAM_D[15:0];
+   
+   always @(posedge wb_clk)
+     if(wb_rst)
+       ack_o <= 0;
+     else if((RAM_state == RAM_write_4)||(RAM_state == RAM_read_4))
+       ack_o <= 1;
+     else
+       ack_o <= 0;
+   
+endmodule // extram_wb
diff --git a/fpga/usrp2/extram/wb_zbt16_b.v b/fpga/usrp2/extram/wb_zbt16_b.v
new file mode 100644
index 000000000..d93e21c99
--- /dev/null
+++ b/fpga/usrp2/extram/wb_zbt16_b.v
@@ -0,0 +1,63 @@
+
+module wb_zbt16_b
+  (input               clk,
+   input               rst,
+   // Wishbone bus A, highest priority, with prefetch
+   input      [19:0]   wb_adr_i,
+   input      [15:0]   wb_dat_i,
+   output reg [15:0]   wb_dat_o,
+   input      [ 1:0]   wb_sel_i,
+   input               wb_cyc_i,
+   input               wb_stb_i,
+   output reg          wb_ack_o,
+   input               wb_we_i,
+   // Memory connection
+   output              sram_clk,
+   output     [18:0]   sram_a,
+   inout      [15:0]   sram_d,
+   output              sram_we,
+   output     [ 1:0]   sram_bw,
+   output              sram_adv,
+   output              sram_ce,
+   output              sram_oe,
+   output              sram_mode,
+   output              sram_zz
+   );
+
+   assign 	       sram_clk = ~clk;
+   //assign 	       sram_oe = 1'b0;
+   assign 	       sram_ce = 1'b0;
+   assign 	       sram_adv = 1'b0;
+   assign 	       sram_mode = 1'b0;
+   assign 	       sram_zz = 1'b0;
+   assign 	       sram_bw = 2'b0;
+   
+   // need to drive wb_dat_o, wb_ack_o,
+   // sram_a, sram_d, sram_we
+   wire 	       myOE;
+   assign 	       sram_d = myOE ? wb_dat_i : 16'bzzzz;
+   assign 	       sram_a = wb_adr_i[19:1];
+
+   reg 		       read_d1, read_d2, read_d3, write_d1, write_d2, write_d3;
+   wire 	       acc = wb_cyc_i & wb_stb_i;
+   wire 	       read_acc = wb_cyc_i & wb_stb_i & ~wb_we_i & ~read_d1 & ~read_d2 & ~read_d3;
+   wire 	       write_acc = wb_cyc_i & wb_stb_i & wb_we_i & ~write_d1 & ~write_d2 & ~write_d3;
+
+   assign 	       sram_we = ~write_acc;
+   assign 	       sram_oe = ~(read_d2 | read_d3);
+   assign 	       myOE = write_d1 | write_d2;
+   wire 	       latch_now = read_d2;
+
+   always @(posedge clk)
+     if(latch_now)
+       wb_dat_o <= sram_d;
+
+   always @(posedge clk) wb_ack_o <= read_d2 | write_d2;
+   always @(posedge clk) read_d1 <= read_acc;
+   always @(posedge clk) read_d2 <= read_d1;
+   always @(posedge clk) read_d3 <= read_d2;
+   always @(posedge clk) write_d1 <= write_acc;
+   always @(posedge clk) write_d2 <= write_d1;
+   always @(posedge clk) write_d3 <= write_d2;
+endmodule // wb_zbt16_b
+
diff --git a/fpga/usrp2/models/BUFG.v b/fpga/usrp2/models/BUFG.v
new file mode 100644
index 000000000..a935c6285
--- /dev/null
+++ b/fpga/usrp2/models/BUFG.v
@@ -0,0 +1,33 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFG.v,v 1.5 2005/03/14 22:32:51 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 8.1i (I.13)
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Global Clock Buffer
+// /___/   /\     Filename : BUFG.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:14 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+// End Revision
+
+`timescale  100 ps / 10 ps
+
+
+module BUFG (O, I);
+
+    output O;
+
+    input  I;
+
+	buf B1 (O, I);
+
+
+endmodule
+
diff --git a/fpga/usrp2/models/CY7C1356C/cy1356.inp b/fpga/usrp2/models/CY7C1356C/cy1356.inp
new file mode 100644
index 000000000..a55ffac39
--- /dev/null
+++ b/fpga/usrp2/models/CY7C1356C/cy1356.inp
@@ -0,0 +1,140 @@
+/*Address inputs only		0=LOW						
+	"Data is in HEX, four bytes (LSB,MSB)"	1=HIGH						
+	ZZZZZZZZZZZZZZZZ=Tri-state				G-WRITE = Global Write						
+	XXXXXXXXXXXXXXXX= Don't care			B-WRITE = Byte Write						
+	YYYY=unknown				BG-WRITE = BURST GLOBAL WRITE						
+						BB-WRITE = BURST BYTE WRITE						
+
+*/						
+//		    				        CE3#  BW2# ADV/LD#
+//	     					 CEN# CE2 WE#   
+//    Add             IN                  OUT 	    CE1#    BW1#  
+0000000000000000_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0 
+0000000000000001_XXXXXXXXXXXXXXXX_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000000010_0000000000000000_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000000011_0000000000000001_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000000100_0000000000000010_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000000101_0000000000000011_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000000110_0000000000000100_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000000111_0000000000000101_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001000_0000000000000110_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001001_0000000000000111_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001010_0000000000001000_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001011_0000000000001001_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001100_0000000000001010_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001101_0000000000001011_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001110_0000000000001100_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000001111_0000000000001101_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_0_0
+0000000000000000_0000000000001110_ZZZZZZZZZZZZZZZZ_0_0_1_0_1_X_X_0
+0000000000000001_0000000000001111_ZZZZZZZZZZZZZZZZ_0_0_1_0_1_X_X_0
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+0000000000000010_01000100XXXXXXXX_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0
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+0000000000000100_xxxxxxxxxxxxxxxx_0000000000000010_0_0_1_0_1_X_X_0
+0000000000000001_xxxxxxxxxxxxxxxx_0011001100110011_0_0_1_0_0_0_0_0
+0000000000000010_xxxxxxxxxxxxxxxx_0100010001001001_0_0_1_0_0_0_0_0
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+0000000000000100_0010001000100010_xxxxxxxxxxxxxxxx_0_0_1_0_0_0_0_0
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+0000000000000010_0100010001000100_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0
+0000000000000011_xxxxxxxxxxxxxxxx_0001000100010001_0_0_1_0_1_X_X_0
+0000000000000100_xxxxxxxxxxxxxxxx_0010001000100010_0_0_1_0_1_X_X_0
+0000000000000101_xxxxxxxxxxxxxxxx_0011001100110011_0_0_1_0_0_0_0_0
+0000000000000110_xxxxxxxxxxxxxxxx_0100010001000100_0_X_X_X_X_0_0_1 
+0000000000000111_0101010101010101_xxxxxxxxxxxxxxxx_0_X_X_X_X_1_1_1 
+0000000000001000_0110011001100110_xxxxxxxxxxxxxxxx_0_X_X_X_X_0_0_1 
+0000000000000101_01110111XXXXXXXX_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0
+XXXXXXXXXXXXXXXX_XXXXXXXX10001000_xxxxxxxxxxxxxxxx_0_X_X_X_X_X_X_1 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0101010101010101_0_X_X_X_X_X_X_1 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0110011001100110_0_X_X_X_X_X_X_1 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0111011101110001_0_1_X_X_X_X_X_0 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0100010010001000_1_X_X_X_X_X_X_X 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0100010010001000_0_X_0_X_X_X_X_0 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_0_X_X_1_X_X_X_0 
+0000000000000101_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_0_0_1_0_1_X_X_0
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_1_X_X_X_X_X_X_X 
+0000000000001000_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_0_0_1_0_0_0_1_0 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0101010101010101_1_X_X_X_X_X_X_X 
+0000000000000111_xxxxxxxxxxxxxxxx_0101010101010101_0_0_1_0_1_X_X_0
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+0000000000000000_xxxxxxxxxxxxxxxx_0111011101110001_0_0_1_0_1_X_X_0
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+0000000000000000_XXXXXXXXXXXX0100_xxxxxxxxxxxxxxxx_0_0_1_0_1_X_X_0 
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0110011001100110_0_X_X_X_X_X_X_1
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0001001000110100_0_X_X_X_X_X_X_1
+XXXXXXXXXXXXXXXX_xxxxxxxxxxxxxxxx_0010001000100010_0_1_X_X_X_X_X_0
+xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_0011001100110011_0_1_x_x_x_x_x_x
+xxxxxxxxxxxxxxxx_xxxxxxxxxxxxxxxx_ZZZZZZZZZZZZZZZZ_0_1_x_x_x_x_x_x												
+//Lines =126
+
+
diff --git a/fpga/usrp2/models/CY7C1356C/cy1356.v b/fpga/usrp2/models/CY7C1356C/cy1356.v
new file mode 100644
index 000000000..9197eea6d
--- /dev/null
+++ b/fpga/usrp2/models/CY7C1356C/cy1356.v
@@ -0,0 +1,485 @@
+`define sb200  

+//************************************************************************

+//************************************************************************

+//** This model is the property of Cypress Semiconductor Corp and is    **

+//** protected by the US copyright laws, any unauthorized copying and   **

+//** distribution is prohibited. Cypress reserves the right to change   ** 

+//** any of the functional specifications without any prior notice.     ** 

+//** Cypress is not liable for any damages which may result from the    **

+//** use of this functional model.					**

+//**									**

+//** File Name	:   CY7C1356						**

+//**									**

+//** Revision	:   1.0 - 08/03/2004					**

+//**									**

+//** The timings are to be selected by the user depending upon the 	**

+//** frequency of operation from the datasheet.				**

+//**									**

+//** Model	:   CY7C1356C - NoBL Pipelined SRAM		**

+//** Queries	:   MPD Applications					**

+//** Website:    www.cypress.com/support              ** 		

+//************************************************************************

+//************************************************************************

+

+`timescale  1ns /  10ps

+

+//	NOTE :	Any setup/hold errors will force input signal to x state

+//		or if results indeterminant (write addr) core is reset x

+

+// define fixed values

+

+`define wordsize (18 -1)		//

+`define no_words (1048576  -1)		// 1M x 18 RAM

+

+module cy1356 ( d, clk, a, bws, we_b, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);

+

+inout	[`wordsize:0] 	d;

+input 			clk, 		// clock input (R)

+			we_b, 		// byte write enable(L)

+			adv_lb, 	// burst(H)/load(L) address

+			ce1b, 		// chip enable(L)

+			ce2, 		// chip enable(H)

+			ce3b, 		// chip enable(L)

+			oeb, 		// async output enable(L)(read)

+			cenb,		// clock enable(L)

+			mode;		// interleave(H)/linear(L) burst

+input 	[1:0] 		bws;		// byte write select(L)

+input 	[18:0] 		a;		// address bus

+

+//	*** 	NOTE DEVICE OPERATES #0.01 AFTER CLOCK   	***

+//	*** THEREFORE DELAYS HAVE TO TAKE THIS INTO ACCOUNT	***

+

+

+//**********************************************************************

+//  Timings for 225MHz

+//**********************************************************************

+`ifdef sb225

+  `define teohz #2.8

+  `define teolz #0

+  `define tchz #2.8

+  `define tclz #1.25

+  

+  `define tco   #2.8

+  `define tdoh  #1.25

+  `define tas 1.4			

+  `define tah 0.4		

+`endif

+//***********************************************************************

+//  Timings for 200MHz

+//**********************************************************************

+`ifdef sb200

+  `define teohz #3.2

+  `define teolz #0

+  `define tchz #3.2

+  `define tclz #1.5

+  

+  `define tco   #3.2

+  `define tdoh  #1.5

+

+  `define tas 1.5			

+  `define tah 0.5		

+`endif

+//***********************************************************************

+

+//**********************************************************************

+//  This model is configured for 166 MHz Operation (CY7C1356-166). 

+//**********************************************************************

+`ifdef sb166

+  `define teohz #3.5

+  `define teolz #0

+  `define tchz #3.5

+  `define tclz #1.5

+  

+  `define tco   #3.5

+  `define tdoh  #1.5

+

+  `define tas 1.5			

+  `define tah 0.5		

+`endif

+

+reg 		notifier;	// error support reg's

+reg 		noti1_0;

+reg 		noti1_1;

+reg 		noti1_2;

+reg 		noti1_3;

+reg 		noti1_4;

+reg 		noti1_5;

+reg 		noti1_6;

+reg 	 	noti2;

+

+

+wire chipen;     	// combined chip enable (high for an active chip)

+

+reg  chipen_d;		// _d = delayed

+reg  chipen_o;		// _o = operational = delayed sig or _d sig

+

+wire writestate;   	// holds 1 if any of writebus is low

+reg  writestate_d;

+reg  writestate_o;

+

+wire loadcyc;        	// holds 1 for load cycles (setup and hold checks)

+wire writecyc;     	// holds 1 for write cycles (setup and hold checks)

+wire [1:0] bws;     	// holds the bws values

+

+wire [1:0] writebusb; 	// holds the "internal" bws bus based on we_b

+reg  [1:0] writebusb_d;

+reg  [1:0] writebusb_o;

+

+wire [2:0] operation;	// holds chipen, adv_ld and writestate

+reg  [2:0] operation_d;

+reg  [2:0] operation_o;

+

+wire [18:0] a;       	// address input bus

+reg  [18:0] a_d;

+reg  [18:0] a_o;

+

+reg  [`wordsize:0] do;      	// data  output reg

+reg  [`wordsize:0] di;      	// data   input bus

+reg  [`wordsize:0] dd;      	// data delayed bus

+

+wire tristate;		// tristate output (on a bytewise basis) when asserted

+reg  cetri;       	// register set by chip disable which sets the tristate 

+reg  oetri;    		// register set by oe which sets the tristate

+reg  enable;         	// register to make the ram enabled when equal to 1

+reg  [18:0] addreg;   	// register to hold the input address

+reg  [`wordsize:0] pipereg; 	// register for the output data

+

+reg  [`wordsize:0] mem [0:`no_words];	// RAM array

+

+reg  [`wordsize:0] writeword;	// temporary holding register for the write data

+reg  burstinit;    	// register to hold a[0] for burst type

+reg  [18:0] i;  	// temporary register used to write to all mem locs.

+reg  writetri;		// tristate

+reg  lw, bw;		// pipelined write functions

+reg  we_bl;

+

+

+wire [`wordsize:0]  d =  !tristate ?  do[`wordsize:0] : 18'bz ;	//  data bus

+

+assign chipen 		= (adv_lb == 1 ) ? chipen_d :

+                                ~ce1b & ce2 & ~ce3b ;

+

+assign writestate 	= ~& writebusb;

+

+assign operation 	= {chipen, adv_lb, writestate};

+

+assign writebusb[1:0] 	= (  we_b  ==0 & adv_lb ==0) ? bws[1:0]:

+                          (  we_b  ==1 & adv_lb ==0) ? 2'b11 :

+                          (  we_bl ==0 & adv_lb ==1) ? bws[1:0]:

+                          (  we_bl ==1 & adv_lb ==1) ? 2'b11 :

+                                                       2'bxx ;

+

+assign loadcyc 		= chipen & !cenb;

+

+assign writecyc 	= writestate_d & enable & ~cenb & chipen; // check

+

+assign tristate 	= cetri | writetri | oetri;

+

+pullup    (mode); 

+

+// formers for notices/errors etc

+//

+//$display("NOTICE      : xxx :");

+//$display("WARNING     : xxx :");

+//$display("ERROR   *** : xxx :");

+

+

+// initialize the output to be tri-state, ram to be disabled

+

+initial

+	begin

+// signals

+

+	  writetri 	= 0;

+	  cetri 	= 1;

+	  enable 	= 0;

+	  lw		= 0;

+	  bw		= 0;

+

+// error signals 

+

+	  notifier 	= 0;

+	  noti1_0	= 0;

+	  noti1_1	= 0;

+	  noti1_2	= 0;

+	  noti1_3	= 0;

+	  noti1_4	= 0;

+	  noti1_5	= 0;

+	  noti1_6	= 0;

+	  noti2		= 0;  

+

+end

+

+

+

+// asynchronous OE

+

+always @(oeb)

+begin

+  if (oeb == 1)

+    oetri <= `teohz 1;

+  else

+    oetri <= `teolz 0;

+end

+

+//	***	SETUP / HOLD VIOLATIONS		***

+

+always @(noti2)

+begin

+$display("NOTICE      : 020 : Data bus    corruption");

+    force d =18'bx;

+    #1;

+    release d;

+end

+

+always @(noti1_0)

+begin

+$display("NOTICE      : 010 : Byte write  corruption");

+    force bws = 2'bx;

+    #1;

+    release bws;

+end

+

+always @(noti1_1)

+begin

+$display("NOTICE      : 011 : Byte enable corruption");

+    force we_b = 1'bx;

+    #1;

+    release we_b;

+end

+

+always @(noti1_2)

+begin

+$display("NOTICE      : 012 : CE1B       corruption");

+    force ce1b =1'bx;

+    #1;

+    release ce1b;

+end

+

+always @(noti1_3)

+begin

+$display("NOTICE      : 013 : CE2       corruption");

+    force ce2 =1'bx;

+    #1;

+   release ce2;

+end

+

+always @(noti1_4)

+begin

+$display("NOTICE      : 014 : CE3B      corruption");

+    force ce3b =1'bx;

+    #1;

+    release ce3b;

+end

+

+always @(noti1_5)

+begin

+$display("NOTICE      : 015 : CENB      corruption");

+    force cenb =1'bx;

+    #1;

+    release cenb;

+end

+

+always @(noti1_6)

+begin

+$display("NOTICE      : 016 : ADV_LB   corruption");

+    force adv_lb = 1'bx;

+    #1;

+    release adv_lb;

+end

+

+// synchronous functions from clk edge

+

+always @(posedge clk)

+if (!cenb)

+begin

+#0.01;  

+  // latch conditions on adv_lb

+

+  if (adv_lb) 

+   we_bl 		<=	we_bl;

+  else

+   we_bl 		<=	we_b;

+

+  chipen_d		<=	chipen;

+  

+

+      chipen_o	 	<=	chipen;

+      writestate_o	<= 	writestate;

+      writestate_d	<=	writestate_o;  

+      writebusb_o	<=	writebusb;

+      writebusb_d	<=	writebusb_o;

+      operation_o	<=	operation;

+      a_o		<=	a;

+      a_d		<=	a_o;

+      di		 =	d;

+

+  // execute previously pipelined fns

+

+  if (lw) begin			

+		loadwrite;

+		lw =0;

+	  end

+

+  if (bw) begin

+		burstwrite;

+		bw =0;

+	  end

+

+  // decode input/piplined state

+

+    casex (operation_o)

+    3'b0??	: turnoff;

+    3'b101	: setlw;

+    3'b111	: setbw;

+    3'b100	: loadread;

+    3'b110	: burstread;

+    default : unknown; // output unknown values and display an error message

+  endcase

+

+   do <= `tco  pipereg;

+

+end

+

+//			***	task section	***

+

+task read;

+begin

+  if (enable) cetri <= `tclz 0;

+  writetri <= `tchz 0;

+  do <= `tdoh 18'hx;

+  pipereg = mem[addreg];

+end

+endtask

+

+task write;

+begin

+  if (enable) cetri <= `tclz 0;

+  writeword = mem[addreg];  // set up a word to hold the data for the current location

+  /* overwrite the current word for the bytes being written to */

+  if (!writebusb_d[1]) writeword[17:9]  = di[17:9];

+  if (!writebusb_d[0]) writeword[8:0]   = di[8:0];

+  writeword = writeword &  writeword; //convert z to x states

+  mem[addreg] = writeword; // store the new word into the memory location

+  //writetri <= `tchz 1;    // tristate the outputs

+end

+endtask

+

+task setlw;

+begin

+    lw =1;

+    writetri <= `tchz 1;    // tristate the outputs

+end

+endtask

+

+task setbw;

+begin

+    bw =1;

+    writetri <= `tchz 1;    // tristate the outputs

+end

+endtask

+

+task loadread;

+begin

+  burstinit = a_o[0];

+  addreg = a_o;

+  enable = 1;

+  read;

+end

+endtask

+

+task loadwrite;

+begin

+  burstinit = a_d[0];

+  addreg = a_d;

+  enable = 1;

+  write;

+end

+endtask

+

+task burstread;

+begin

+  burst;

+  read;

+end

+endtask

+

+task burstwrite;

+begin

+  burst;

+  write;

+end

+endtask

+

+task unknown;

+begin

+  do = 18'bx;

+  // $display ("Unknown function:  Operation = %b\n", operation);

+end

+endtask

+

+task turnoff;

+begin

+  enable = 0;

+  cetri <= `tchz 1;

+  pipereg = 18'h0;

+end

+endtask

+

+task burst;

+begin

+  if (burstinit == 0 || mode == 0)

+  begin

+    case (addreg[1:0])

+      2'b00:   addreg[1:0] = 2'b01;

+      2'b01:   addreg[1:0] = 2'b10;

+      2'b10:   addreg[1:0] = 2'b11;

+      2'b11:   addreg[1:0] = 2'b00;

+      default: addreg[1:0] = 2'bxx;

+    endcase

+  end

+  else

+  begin

+    case (addreg[1:0])

+      2'b00:   addreg[1:0] = 2'b11;

+      2'b01:   addreg[1:0] = 2'b00;

+      2'b10:   addreg[1:0] = 2'b01;

+      2'b11:   addreg[1:0] = 2'b10;

+      default: addreg[1:0] = 2'bxx;

+    endcase

+  end

+end

+endtask

+

+// IO checks

+

+specify

+// specify the setup and hold checks

+

+// notifier will wipe memory as result is indeterminent

+

+$setuphold(posedge clk &&& loadcyc, a, `tas, `tah, notifier);

+

+// noti1 should make ip = 'bx;

+

+$setuphold(posedge clk, bws,  `tas, `tah, noti1_0);

+

+$setuphold(posedge clk, we_b, `tas, `tah, noti1_1);

+$setuphold(posedge clk, ce1b, `tas, `tah, noti1_2);

+$setuphold(posedge clk,  ce2, `tas, `tah, noti1_3);

+$setuphold(posedge clk, ce3b, `tas, `tah, noti1_4);

+

+// noti2 should make d = 18'hxxxxx;

+

+$setuphold(posedge clk &&& writecyc, d, `tas, `tah, noti2);

+

+// add extra tests here.

+

+$setuphold(posedge clk,   cenb, `tas, `tah, noti1_5);

+$setuphold(posedge clk, adv_lb, `tas, `tah, noti1_6);

+

+endspecify

+

+endmodule

+

+

diff --git a/fpga/usrp2/models/CY7C1356C/readme.txt b/fpga/usrp2/models/CY7C1356C/readme.txt
new file mode 100644
index 000000000..3578c80dc
--- /dev/null
+++ b/fpga/usrp2/models/CY7C1356C/readme.txt
@@ -0,0 +1,33 @@
+***************************

+Cypress Semiconductor

+MPD Applications

+Verilog  model for NoBL SRAM CY7C1356

+Created: August 04, 2004

+Rev: 1.0

+***************************

+

+This is the verilog model for the CY7C1356 along with the testbench and test vectors.

+

+Contact support@cypress.com if you have any questions.

+

+This directory has 4 files. including this readme.

+

+1)cy7c1356c.v -> Verilog model for CY7C1356c

+

+2)cy1356.inp -> Test Vector File used for testing the verilog model  

+

+3)testbench.v -> Test bench used for testing the verilog model

+

+

+COMPILING METHOD :

+------------------

+

+        	verilog  +define+<speed_bin>	<Main File>	<Test bench File>

+

+	Ex:

+		verilog  +define+sb133  	CY7C1356c.v 	testbench.v

+

+VERIFIED WITH:

+--------------

+

+VERILOG-XL 2.2
\ No newline at end of file
diff --git a/fpga/usrp2/models/CY7C1356C/testbench.v b/fpga/usrp2/models/CY7C1356C/testbench.v
new file mode 100644
index 000000000..5dde89e6c
--- /dev/null
+++ b/fpga/usrp2/models/CY7C1356C/testbench.v
@@ -0,0 +1,189 @@
+`timescale  1ns /  10ps

+

+

+//

+//				CY7C1356 

+//			Simulatiom of Verilog model 

+//

+//

+

+//

+//			test bench for US vector input

+//

+//

+

+//	define speed 166MHz

+

+`define tx10 #6 

+`define tx08 #4.8

+`define tx05 #3

+`define tx04 #2.4

+`define tx02 #1.2

+

+/*

+`define tx10 #4.0		//    period

+`define tx08 #3.2		//0.8 period

+`define tx05 #2.0		//0.5 period  250MHZ

+`define tx04 #1.6		//0.4 period

+`define tx02 #0.8		//0.2 period

+

+`define tx10 #4.4		//    period

+`define tx08 #3.52		//0.8 period

+`define tx05 #2.2		//0.5 period  225MHZ

+`define tx04 #1.76		//0.4 period

+`define tx02 #0.88		//0.2 period

+

+`define tx10 #5			//    period

+`define tx08 #4			//0.8 period

+`define tx05 #2.5		//0.5 period  200MHZ

+`define tx04 #2.0		//0.4 period

+`define tx02 #1.0		//0.2 period

+*/

+

+

+module rw_test;

+

+`define num_vectors    126

+`define	impi {a[15:0],io[15:0],tsti[15:0],cenb,ce1b,ce2,ce3b,bweb,bwb,adv_lb}

+

+

+reg	[57:1]	lsim_vectors	[1:`num_vectors];

+

+

+reg		clk;

+reg		adv_lb;

+reg		ce1b;		//cs1b

+reg		ce2;		//cs2

+reg		ce3b;		//cs3b

+reg	[1:0]	bwb;

+reg		bweb;

+reg		oeb;

+reg		ftb;

+reg		mode;		//lbob

+reg		cenb;		//zz

+reg		tp42;		//sclk

+reg		tp39;		//se

+reg		tp38;		//tm

+reg	[19:0]	a;

+reg	[17:0]	io;

+reg	[17:0]	tsti;

+reg		vddq;

+reg		vssqr;

+reg		iosel;

+

+

+wire	[17:0]	d = iosel ? io[17:0] : 18'bz;

+

+reg 		noti3;

+reg		strb,j;

+integer		vector,i;

+

+

+

+cy1356 testram ( d, clk, a, bwb, bweb, adv_lb, ce1b, ce2, ce3b, oeb, cenb, mode);

+

+initial

+begin

+  $dumpfile("dumpfile.dump");

+  $dumpvars(0,rw_test);

+end

+

+initial

+begin

+io	= 18'bz;

+ftb 	= 1;

+oeb 	= 0;

+a[19:16] = 4'h0;

+mode	= 0;

+strb 	= 0;

+tp38	= 0;

+tp39	= 0;

+tp42	= 0;

+`tx02;

+forever `tx05 strb = ~strb;

+end

+

+initial

+begin

+clk	= 0;

+forever `tx05 clk =~clk;

+end

+

+initial

+ begin

+ 

+ $readmemb("cy1356.inp", lsim_vectors);     //load input vector file

+

+ `impi = lsim_vectors[1];         //apply 1st test vector

+

+ for (vector = 2; vector <= `num_vectors; vector = vector + 1)

+   @(posedge strb)

+    begin

+

+ `impi = lsim_vectors[vector];

+ 

+

+      

+      io[16:13] = io[07:04];

+      io[12:09] = io[07:04];

+      io[07:04] = io[03:00];

+      io[03:00] = io[03:00];

+      

+      io[17] = io[16] ^^ io[15] ^^ io[14] ^^ io[13] ^^ io[11] ^^ io[11] ^^ io[10] ^^ io[9];

+      io[8] = io[7] ^^ io[6] ^^ io[5] ^^ io[4] ^^ io[3] ^^ io[2] ^^ io[1] ^^ io[0];

+

+      tsti[16:13] = tsti[07:04];

+      tsti[12:09] = tsti[07:04];

+      tsti[07:04] = tsti[03:00];

+      tsti[03:00] = tsti[03:00];

+      

+      tsti[17] = tsti[16] ^^ tsti[15] ^^ tsti[14] ^^ tsti[13] ^^ tsti[11] ^^ tsti[11] ^^ tsti[10] ^^ tsti[9];

+      tsti[8] = tsti[7] ^^ tsti[6] ^^ tsti[5] ^^ tsti[4] ^^ tsti[3] ^^ tsti[2] ^^ tsti[1] ^^ tsti[0];

+

+      if (io === 18'hxxxxx)

+       iosel = `tx05 0;

+      else

+       iosel = `tx05 1;

+

+    end

+   #15 $finish; // This prevents simulation beyond end of test patterns

+ end

+

+always@(posedge clk)

+begin

+  

+  if (io !== 18'hxxxxx) 	//input cycle

+  begin

+    $display("NOTICE      : 001 : line = %d OK",vector -1);

+  end

+  else				//do the test

+  begin

+    if (d == tsti)

+    begin

+    $display("NOTICE      : 002 : line = %d OK",vector -1);

+    end

+    else

+    begin

+      j =0;

+      for (i =0;i< 18; i=i+1)

+      begin

+        if(tsti[i] !== 1'bx)

+          begin

+           if (d[i] !== tsti[i]) j = 1;

+          end

+	else

+	  j = 0;

+      end

+      if (j) 

+    $display("ERROR   *** : 003 : line = %d data = %b test = %b",vector -1,d,tsti);

+      else

+    $display("NOTICE      : 003 : line = %d OK",vector -1);

+    end

+  end

+end

+

+endmodule

+

+

+

+

diff --git a/fpga/usrp2/models/FIFO_GENERATOR_V4_3.v b/fpga/usrp2/models/FIFO_GENERATOR_V4_3.v
new file mode 100644
index 000000000..bcb9af8a7
--- /dev/null
+++ b/fpga/usrp2/models/FIFO_GENERATOR_V4_3.v
@@ -0,0 +1,3494 @@
+/*
+ * $RDCfile: $ $Revision: 1.1.2.15 $ $Date: 2007/07/25 15:58:33 $
+ *******************************************************************************
+ *
+ * FIFO Generator v3.3 - Verilog Behavioral Model
+ *
+ *******************************************************************************
+ *
+ * Copyright(C) 2006 by Xilinx, Inc. All rights reserved.
+ * This text/file contains proprietary, confidential
+ * information of Xilinx, Inc., is distributed under
+ * license from Xilinx, Inc., and may be used, copied
+ * and/or disclosed only pursuant to the terms of a valid
+ * license agreement with Xilinx, Inc. Xilinx hereby
+ * grants you a license to use this text/file solely for
+ * design, simulation, implementation and creation of
+ * design files limited to Xilinx devices or technologies.
+ * Use with non-Xilinx devices or technologies is expressly
+ * prohibited and immediately terminates your license unless
+ * covered by a separate agreement.
+ *
+ * Xilinx is providing theis design, code, or information
+ * "as-is" solely for use in developing programs and
+ * solutions for Xilinx devices, with no obligation on the
+ * part of Xilinx to provide support. By providing this design,
+ * code, or information as one possible implementation of
+ * this feature, application or standard. Xilinx is making no
+ * representation that this implementation is free from any
+ * claims of infringement. You are responsible for obtaining
+ * any rights you may require for your implementation.
+ * Xilinx expressly disclaims any warranty whatsoever with
+ * respect to the adequacy of the implementation, including
+ * but not limited to any warranties or representations that this
+ * implementation is free from claims of infringement, implied
+ * warranties of merchantability or fitness for a particular
+ * purpose.
+ *
+ * Xilinx products are not intended for use in life support
+ * appliances, devices, or systems. Use in such applications is
+ * expressly prohibited.
+ *
+ * This copyright and support notice must be retained as part
+ * of this text at all times. (c)Copyright 1995-2006 Xilinx, Inc.
+ * All rights reserved.
+ *
+ *******************************************************************************
+ *
+ * Filename: fifo_generator_v4_3_bhv.v
+ *
+ * Description:
+ *  The verilog behavioral model for the FIFO generator core.
+ *
+ *******************************************************************************
+ */
+
+`timescale 1ps/1ps
+
+/*******************************************************************************
+ * Declaration of top-level module
+ ******************************************************************************/
+module FIFO_GENERATOR_V4_3
+(
+  BACKUP,
+  BACKUP_MARKER,
+  CLK,
+  DIN,
+  PROG_EMPTY_THRESH,
+  PROG_EMPTY_THRESH_ASSERT,
+  PROG_EMPTY_THRESH_NEGATE,
+  PROG_FULL_THRESH,
+  PROG_FULL_THRESH_ASSERT,
+  PROG_FULL_THRESH_NEGATE,
+  RD_CLK,
+  RD_EN,
+  RD_RST,
+  RST,
+  SRST,
+  WR_CLK,
+  WR_EN,
+  WR_RST,
+  INT_CLK,
+
+  ALMOST_EMPTY,
+  ALMOST_FULL,
+  DATA_COUNT,
+  DOUT,
+  EMPTY,
+  FULL,
+  OVERFLOW,
+  PROG_EMPTY,
+  PROG_FULL,
+  RD_DATA_COUNT,
+  UNDERFLOW,
+  VALID,
+  WR_ACK,
+  WR_DATA_COUNT,
+  SBITERR,
+  DBITERR
+  );
+
+  /****************************************************************************
+  * Definition of Ports
+  *
+  *
+  *****************************************************************************
+  * Definition of Parameters
+  *
+  *
+  *****************************************************************************/
+
+  /****************************************************************************
+  * Declare user parameters and their defaults
+  *****************************************************************************/
+  parameter  C_COMMON_CLOCK                 = 0;
+  parameter  C_COUNT_TYPE                   = 0;
+  parameter  C_DATA_COUNT_WIDTH             = 2;
+  parameter  C_DEFAULT_VALUE                = "";
+  parameter  C_DIN_WIDTH                    = 8;
+  parameter  C_DOUT_RST_VAL                 = "";
+  parameter  C_DOUT_WIDTH                   = 8;
+  parameter  C_ENABLE_RLOCS                 = 0;
+
+  parameter  C_FAMILY                       = "virtex2"; 
+  //Not allowed in Verilog model
+  
+  parameter  C_HAS_ALMOST_EMPTY             = 0;
+  parameter  C_HAS_ALMOST_FULL              = 0;
+  parameter  C_HAS_BACKUP                   = 0;
+  parameter  C_HAS_DATA_COUNT               = 0;
+  parameter  C_HAS_MEMINIT_FILE             = 0;
+  parameter  C_HAS_OVERFLOW                 = 0;
+  parameter  C_HAS_RD_DATA_COUNT            = 0;
+  parameter  C_HAS_RD_RST                   = 0;
+  parameter  C_HAS_RST                      = 0;
+  parameter  C_HAS_SRST                     = 0;
+  parameter  C_HAS_UNDERFLOW                = 0;
+  parameter  C_HAS_VALID                    = 0;
+  parameter  C_HAS_WR_ACK                   = 0;
+  parameter  C_HAS_WR_DATA_COUNT            = 0;
+  parameter  C_HAS_WR_RST                   = 0;
+  parameter  C_IMPLEMENTATION_TYPE          = 0;
+  parameter  C_INIT_WR_PNTR_VAL             = 0;
+  parameter  C_MEMORY_TYPE                  = 1;
+  parameter  C_MIF_FILE_NAME                = "";
+  parameter  C_OPTIMIZATION_MODE            = 0;
+  parameter  C_OVERFLOW_LOW                 = 0;
+  parameter  C_PRELOAD_LATENCY              = 1;
+  parameter  C_PRELOAD_REGS                 = 0;
+  parameter  C_PRIM_FIFO_TYPE               = 512;
+  parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0;
+  parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0;
+  parameter  C_PROG_EMPTY_TYPE              = 0;
+  parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0;
+  parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0;
+  parameter  C_PROG_FULL_TYPE               = 0;
+  parameter  C_RD_DATA_COUNT_WIDTH          = 2;
+  parameter  C_RD_DEPTH                     = 256;
+  parameter  C_RD_FREQ                      = 1;
+  parameter  C_RD_PNTR_WIDTH                = 8;
+  parameter  C_UNDERFLOW_LOW                = 0;
+  parameter  C_USE_FIFO16_FLAGS             = 0;
+  parameter  C_VALID_LOW                    = 0;
+  parameter  C_WR_ACK_LOW                   = 0;
+  parameter  C_WR_DATA_COUNT_WIDTH          = 2;
+  parameter  C_WR_DEPTH                     = 256;
+  parameter  C_WR_FREQ                      = 1;
+  parameter  C_WR_PNTR_WIDTH                = 8;
+  parameter  C_WR_RESPONSE_LATENCY          = 1;
+  parameter  C_USE_ECC                      = 0;
+  parameter  C_FULL_FLAGS_RST_VAL           = 1;
+  parameter  C_HAS_INT_CLK                  = 0;
+  parameter  C_USE_EMBEDDED_REG             = 0;
+  parameter  C_USE_FWFT_DATA_COUNT             = 0;
+
+  //There are 2 Verilog behavioral models
+  // 0 = Synchronous FIFO/ShiftRam FIFO
+  // 1 = Asynchronous FIFO
+  parameter  C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE==0 ? 0 :
+                               (C_IMPLEMENTATION_TYPE==1 ? 0 :
+                                (C_IMPLEMENTATION_TYPE==2 ? 1 : 0)));
+
+
+  /******************************************************************************
+   * Declare Input and Output Ports
+   *****************************************************************************/
+  input                              CLK;
+  input                              BACKUP;
+  input                              BACKUP_MARKER;
+  input [C_DIN_WIDTH-1:0]            DIN;
+  input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;
+  input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;
+  input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;
+  input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;
+  input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;
+  input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;
+  input                              RD_CLK;
+  input                              RD_EN;
+  input                              RD_RST;
+  input                              RST;
+  input                              SRST;
+  input                              WR_CLK;
+  input                              WR_EN;
+  input                              WR_RST;
+  input                              INT_CLK;
+
+  output                             ALMOST_EMPTY;
+  output                             ALMOST_FULL;
+  output [C_DATA_COUNT_WIDTH-1:0]    DATA_COUNT;
+  output [C_DOUT_WIDTH-1:0]          DOUT;
+  output                             EMPTY;
+  output                             FULL;
+  output                             OVERFLOW;
+  output                             PROG_EMPTY;
+  output                             PROG_FULL;
+  output                             VALID;
+  output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
+  output                             UNDERFLOW;
+  output                             WR_ACK;
+  output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
+  output                             SBITERR;
+  output                             DBITERR;
+
+
+  wire                               ALMOST_EMPTY;
+  wire                               ALMOST_FULL;
+  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT;
+  wire [C_DOUT_WIDTH-1:0]            DOUT;
+  wire                               EMPTY;
+  wire                               FULL;
+  wire                               OVERFLOW;
+  wire                               PROG_EMPTY;
+  wire                               PROG_FULL;
+  wire                               VALID;
+  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT;
+  wire                               UNDERFLOW;
+  wire                               WR_ACK;
+  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT;
+
+
+  wire                               RD_CLK_P0_IN;
+  wire                               RST_P0_IN;
+  wire                               RD_EN_FIFO_IN;
+  wire                               RD_EN_P0_IN;
+
+  wire                               ALMOST_EMPTY_FIFO_OUT;
+  wire                               ALMOST_FULL_FIFO_OUT;
+  wire [C_DATA_COUNT_WIDTH-1:0]      DATA_COUNT_FIFO_OUT;
+  wire [C_DOUT_WIDTH-1:0]            DOUT_FIFO_OUT;
+  wire                               EMPTY_FIFO_OUT;
+  wire                               FULL_FIFO_OUT;
+  wire                               OVERFLOW_FIFO_OUT;
+  wire                               PROG_EMPTY_FIFO_OUT;
+  wire                               PROG_FULL_FIFO_OUT;
+  wire                               VALID_FIFO_OUT;
+  wire [C_RD_DATA_COUNT_WIDTH-1:0]   RD_DATA_COUNT_FIFO_OUT;
+  wire                               UNDERFLOW_FIFO_OUT;
+  wire                               WR_ACK_FIFO_OUT;
+  wire [C_WR_DATA_COUNT_WIDTH-1:0]   WR_DATA_COUNT_FIFO_OUT;
+
+
+  //***************************************************************************
+  // Internal Signals
+  //   The core uses either the internal_ wires or the preload0_ wires depending
+  //     on whether the core uses Preload0 or not.
+  //   When using preload0, the internal signals connect the internal core to
+  //     the preload logic, and the external core's interfaces are tied to the
+  //     preload0 signals from the preload logic.
+  //***************************************************************************
+  wire [C_DOUT_WIDTH-1:0]            DATA_P0_OUT;
+  wire                               VALID_P0_OUT;
+  wire                               EMPTY_P0_OUT;
+  wire                               ALMOSTEMPTY_P0_OUT;
+  reg                                EMPTY_P0_OUT_Q;
+  reg                                ALMOSTEMPTY_P0_OUT_Q;
+  wire                               UNDERFLOW_P0_OUT;
+  wire                               RDEN_P0_OUT;
+  wire [C_DOUT_WIDTH-1:0]            DATA_P0_IN;
+  wire                               EMPTY_P0_IN;
+
+  assign SBITERR = 1'b0;
+  assign DBITERR = 1'b0;
+
+// choose the base FIFO implementation for simulation
+generate
+case (C_VERILOG_IMPL)
+0 : begin : block1
+  fifo_generator_v4_3_bhv_ver_ss
+  #(
+    C_COMMON_CLOCK,
+    C_COUNT_TYPE,
+    C_DATA_COUNT_WIDTH,
+    C_DEFAULT_VALUE,
+    C_DIN_WIDTH,
+    C_DOUT_RST_VAL,
+    C_DOUT_WIDTH,
+    C_ENABLE_RLOCS,
+    C_FAMILY,//Not allowed in Verilog model
+    C_HAS_ALMOST_EMPTY,
+    C_HAS_ALMOST_FULL,
+    C_HAS_BACKUP,
+    C_HAS_DATA_COUNT,
+    C_HAS_MEMINIT_FILE,
+    C_HAS_OVERFLOW,
+    C_HAS_RD_DATA_COUNT,
+    C_HAS_RD_RST,
+    C_HAS_RST,
+    C_HAS_SRST,
+    C_HAS_UNDERFLOW,
+    C_HAS_VALID,
+    C_HAS_WR_ACK,
+    C_HAS_WR_DATA_COUNT,
+    C_HAS_WR_RST,
+    C_IMPLEMENTATION_TYPE,
+    C_INIT_WR_PNTR_VAL,
+    C_MEMORY_TYPE,
+    C_MIF_FILE_NAME,
+    C_OPTIMIZATION_MODE,
+    C_OVERFLOW_LOW,
+    C_PRELOAD_LATENCY,
+    C_PRELOAD_REGS,
+    C_PROG_EMPTY_THRESH_ASSERT_VAL,
+    C_PROG_EMPTY_THRESH_NEGATE_VAL,
+    C_PROG_EMPTY_TYPE,
+    C_PROG_FULL_THRESH_ASSERT_VAL,
+    C_PROG_FULL_THRESH_NEGATE_VAL,
+    C_PROG_FULL_TYPE,
+    C_RD_DATA_COUNT_WIDTH,
+    C_RD_DEPTH,
+    C_RD_PNTR_WIDTH,
+    C_UNDERFLOW_LOW,
+    C_VALID_LOW,
+    C_WR_ACK_LOW,
+    C_WR_DATA_COUNT_WIDTH,
+    C_WR_DEPTH,
+    C_WR_PNTR_WIDTH,
+    C_WR_RESPONSE_LATENCY,
+    C_FULL_FLAGS_RST_VAL,
+    C_USE_EMBEDDED_REG
+  )
+  gen_ss
+  (
+    .CLK                      (CLK),
+    .RST                      (RST),
+    .SRST                     (SRST),
+    .DIN                      (DIN),
+    .WR_EN                    (WR_EN),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
+    .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
+    .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
+    .PROG_FULL_THRESH         (PROG_FULL_THRESH),
+    .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
+    .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .DATA_COUNT               (DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT)
+   );
+end
+1 : begin : block1
+  fifo_generator_v4_3_bhv_ver_as
+  #(
+    C_COMMON_CLOCK,
+    C_COUNT_TYPE,
+    C_DATA_COUNT_WIDTH,
+    C_DEFAULT_VALUE,
+    C_DIN_WIDTH,
+    C_DOUT_RST_VAL,
+    C_DOUT_WIDTH,
+    C_ENABLE_RLOCS,
+    C_FAMILY,//Not allowed in Verilog model
+    C_HAS_ALMOST_EMPTY,
+    C_HAS_ALMOST_FULL,
+    C_HAS_BACKUP,
+    C_HAS_DATA_COUNT,
+    C_HAS_MEMINIT_FILE,
+    C_HAS_OVERFLOW,
+    C_HAS_RD_DATA_COUNT,
+    C_HAS_RD_RST,
+    C_HAS_RST,
+    C_HAS_UNDERFLOW,
+    C_HAS_VALID,
+    C_HAS_WR_ACK,
+    C_HAS_WR_DATA_COUNT,
+    C_HAS_WR_RST,
+    C_IMPLEMENTATION_TYPE,
+    C_INIT_WR_PNTR_VAL,
+    C_MEMORY_TYPE,
+    C_MIF_FILE_NAME,
+    C_OPTIMIZATION_MODE,
+    C_OVERFLOW_LOW,
+    C_PRELOAD_LATENCY,
+    C_PRELOAD_REGS,
+    C_PROG_EMPTY_THRESH_ASSERT_VAL,
+    C_PROG_EMPTY_THRESH_NEGATE_VAL,
+    C_PROG_EMPTY_TYPE,
+    C_PROG_FULL_THRESH_ASSERT_VAL,
+    C_PROG_FULL_THRESH_NEGATE_VAL,
+    C_PROG_FULL_TYPE,
+    C_RD_DATA_COUNT_WIDTH,
+    C_RD_DEPTH,
+    C_RD_PNTR_WIDTH,
+    C_UNDERFLOW_LOW,
+    C_VALID_LOW,
+    C_WR_ACK_LOW,
+    C_WR_DATA_COUNT_WIDTH,
+    C_WR_DEPTH,
+    C_WR_PNTR_WIDTH,
+    C_WR_RESPONSE_LATENCY,
+    C_FULL_FLAGS_RST_VAL,
+    C_USE_FWFT_DATA_COUNT,
+    C_USE_EMBEDDED_REG
+  )
+  gen_as
+  (
+    .WR_CLK                   (WR_CLK),
+    .RD_CLK                   (RD_CLK),
+    .RST                      (RST),
+    .DIN                      (DIN),
+    .WR_EN                    (WR_EN),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
+    .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
+    .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
+    .PROG_FULL_THRESH         (PROG_FULL_THRESH),
+    .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
+    .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT)
+   );
+end
+
+default : begin : block1
+  fifo_generator_v4_3_bhv_ver_as
+  #(
+    C_COMMON_CLOCK,
+    C_COUNT_TYPE,
+    C_DATA_COUNT_WIDTH,
+    C_DEFAULT_VALUE,
+    C_DIN_WIDTH,
+    C_DOUT_RST_VAL,
+    C_DOUT_WIDTH,
+    C_ENABLE_RLOCS,
+    C_FAMILY,//Not allowed in Verilog model
+    C_HAS_ALMOST_EMPTY,
+    C_HAS_ALMOST_FULL,
+    C_HAS_BACKUP,
+    C_HAS_DATA_COUNT,
+    C_HAS_MEMINIT_FILE,
+    C_HAS_OVERFLOW,
+    C_HAS_RD_DATA_COUNT,
+    C_HAS_RD_RST,
+    C_HAS_RST,
+    C_HAS_UNDERFLOW,
+    C_HAS_VALID,
+    C_HAS_WR_ACK,
+    C_HAS_WR_DATA_COUNT,
+    C_HAS_WR_RST,
+    C_IMPLEMENTATION_TYPE,
+    C_INIT_WR_PNTR_VAL,
+    C_MEMORY_TYPE,
+    C_MIF_FILE_NAME,
+    C_OPTIMIZATION_MODE,
+    C_OVERFLOW_LOW,
+    C_PRELOAD_LATENCY,
+    C_PRELOAD_REGS,
+    C_PROG_EMPTY_THRESH_ASSERT_VAL,
+    C_PROG_EMPTY_THRESH_NEGATE_VAL,
+    C_PROG_EMPTY_TYPE,
+    C_PROG_FULL_THRESH_ASSERT_VAL,
+    C_PROG_FULL_THRESH_NEGATE_VAL,
+    C_PROG_FULL_TYPE,
+    C_RD_DATA_COUNT_WIDTH,
+    C_RD_DEPTH,
+    C_RD_PNTR_WIDTH,
+    C_UNDERFLOW_LOW,
+    C_VALID_LOW,
+    C_WR_ACK_LOW,
+    C_WR_DATA_COUNT_WIDTH,
+    C_WR_DEPTH,
+    C_WR_PNTR_WIDTH,
+    C_WR_RESPONSE_LATENCY,
+    C_FULL_FLAGS_RST_VAL,
+    C_USE_FWFT_DATA_COUNT,
+    C_USE_EMBEDDED_REG
+  )
+  gen_as
+  (
+    .WR_CLK                   (WR_CLK),
+    .RD_CLK                   (RD_CLK),
+    .RST                      (RST),
+    .DIN                      (DIN),
+    .WR_EN                    (WR_EN),
+    .RD_EN                    (RD_EN_FIFO_IN),
+    .PROG_EMPTY_THRESH        (PROG_EMPTY_THRESH),
+    .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
+    .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
+    .PROG_FULL_THRESH         (PROG_FULL_THRESH),
+    .PROG_FULL_THRESH_ASSERT  (PROG_FULL_THRESH_ASSERT),
+    .PROG_FULL_THRESH_NEGATE  (PROG_FULL_THRESH_NEGATE),
+    .DOUT                     (DOUT_FIFO_OUT),
+    .FULL                     (FULL_FIFO_OUT),
+    .ALMOST_FULL              (ALMOST_FULL_FIFO_OUT),
+    .WR_ACK                   (WR_ACK_FIFO_OUT),
+    .OVERFLOW                 (OVERFLOW_FIFO_OUT),
+    .EMPTY                    (EMPTY_FIFO_OUT),
+    .ALMOST_EMPTY             (ALMOST_EMPTY_FIFO_OUT),
+    .VALID                    (VALID_FIFO_OUT),
+    .UNDERFLOW                (UNDERFLOW_FIFO_OUT),
+    .RD_DATA_COUNT            (RD_DATA_COUNT_FIFO_OUT),
+    .WR_DATA_COUNT            (WR_DATA_COUNT_FIFO_OUT),
+    .PROG_FULL                (PROG_FULL_FIFO_OUT),
+    .PROG_EMPTY               (PROG_EMPTY_FIFO_OUT)
+   );
+end
+
+endcase
+endgenerate
+
+
+//**************************************************************************
+// Connect Internal Signals
+//   (Signals labeled internal_*)
+//  In the normal case, these signals tie directly to the FIFO's inputs and
+//    outputs.
+//  In the case of Preload Latency 0 or 1, there are intermediate
+//    signals between the internal FIFO and the preload logic.
+//**************************************************************************
+
+generate
+if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
+ begin : block2
+
+fifo_generator_v4_3_bhv_ver_preload0
+ #(
+    C_DOUT_RST_VAL,
+    C_DOUT_WIDTH,
+    C_HAS_RST,
+    C_VALID_LOW,
+    C_UNDERFLOW_LOW
+   )
+ fgpl0
+(
+ .RD_CLK           (RD_CLK_P0_IN),
+ .RD_RST           (RST_P0_IN),
+ .RD_EN            (RD_EN_P0_IN),
+ .FIFOEMPTY        (EMPTY_P0_IN),
+ .FIFODATA         (DATA_P0_IN),
+ .USERDATA         (DATA_P0_OUT),
+ .USERVALID        (VALID_P0_OUT),
+ .USEREMPTY        (EMPTY_P0_OUT),
+ .USERALMOSTEMPTY  (ALMOSTEMPTY_P0_OUT),
+ .USERUNDERFLOW    (UNDERFLOW_P0_OUT),
+ .RAMVALID         (RAMVALID_P0_OUT),
+ .FIFORDEN         (RDEN_P0_OUT)
+ );
+
+ assign RD_CLK_P0_IN       = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
+ assign RST_P0_IN          = RST;
+ assign RD_EN_P0_IN        = RD_EN;
+
+ assign RD_EN_FIFO_IN      = RDEN_P0_OUT;
+
+ assign DOUT               = DATA_P0_OUT;
+ assign DATA_P0_IN         = DOUT_FIFO_OUT;
+ assign VALID              = VALID_P0_OUT ;
+ assign EMPTY              = EMPTY_P0_OUT;
+ assign ALMOST_EMPTY       = ALMOSTEMPTY_P0_OUT;
+ assign EMPTY_P0_IN        = EMPTY_FIFO_OUT;
+ assign UNDERFLOW          = UNDERFLOW_P0_OUT ;
+
+ always @ (posedge RD_CLK or posedge RST)
+  begin
+   if (RST)
+    begin
+     EMPTY_P0_OUT_Q       <= 1;
+     ALMOSTEMPTY_P0_OUT_Q <= 1;
+    end
+   else
+    begin
+     EMPTY_P0_OUT_Q       <= EMPTY_P0_OUT;
+     ALMOSTEMPTY_P0_OUT_Q <= ALMOSTEMPTY_P0_OUT;
+    end
+  end
+
+ end
+else
+ begin : block2
+
+ assign RD_CLK_P0_IN       = 0;
+ assign RST_P0_IN          = 0;
+ assign RD_EN_P0_IN        = 0;
+
+ assign RD_EN_FIFO_IN      = RD_EN;
+
+ assign DOUT               = DOUT_FIFO_OUT;
+ assign DATA_P0_IN         = 0;
+ assign VALID              = VALID_FIFO_OUT;
+ assign EMPTY              = EMPTY_FIFO_OUT;
+ assign ALMOST_EMPTY       = ALMOST_EMPTY_FIFO_OUT;
+ assign EMPTY_P0_IN        = 0;
+ assign UNDERFLOW          = UNDERFLOW_FIFO_OUT;
+
+ end
+endgenerate
+
+
+//Connect Data Count Signals
+generate
+if (C_USE_FWFT_DATA_COUNT==1) begin : block3
+  assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
+end
+else begin : block3
+  assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
+end
+endgenerate
+
+generate
+if (C_USE_FWFT_DATA_COUNT==1) begin : block4
+  assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
+end
+else begin : block4
+  assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
+end
+endgenerate
+
+
+ assign FULL        = FULL_FIFO_OUT;
+ assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
+ assign WR_ACK      = WR_ACK_FIFO_OUT;
+ assign OVERFLOW    = OVERFLOW_FIFO_OUT;
+ assign PROG_FULL   = PROG_FULL_FIFO_OUT;
+ assign PROG_EMPTY  = PROG_EMPTY_FIFO_OUT;
+ assign DATA_COUNT  = DATA_COUNT_FIFO_OUT;
+
+
+ // if an asynchronous FIFO has been selected, display a message that the FIFO
+ //   will not be cycle-accurate in simulation
+ initial begin
+   //if (C_IMPLEMENTATION_TYPE == 1) begin //bug in v3.1
+   if (C_IMPLEMENTATION_TYPE == 2) begin   //fixed in v3.2 (IP2_Im)
+     $display("Warning in %m at time %t: When using an asynchronous configuration for the FIFO Generator, the behavioral model is not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time);
+   end else if (C_IMPLEMENTATION_TYPE == 3 || C_IMPLEMENTATION_TYPE == 4) begin
+     $display("Failure in %m at time %t: Use of Virtex-4 and Virtex-5 built-in FIFO configurations is currently not supported. Please use the structural simulation model. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information.", $time);
+     $finish;
+   end
+
+ end
+
+endmodule //fifo_generator_v4_3_bhv_ver
+
+
+
+
+
+
+/*******************************************************************************
+ * Declaration of asynchronous FIFO Module
+ ******************************************************************************/
+module fifo_generator_v4_3_bhv_ver_as
+  (
+    WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN,
+    PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE,
+    PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE,
+    DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID,
+    UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY
+  );
+
+  /*****************************************************************************
+  * Declare user parameters and their defaults
+  *****************************************************************************/
+  parameter  C_COMMON_CLOCK                 = 0;
+  parameter  C_COUNT_TYPE                   = 0;
+  parameter  C_DATA_COUNT_WIDTH             = 2;
+  parameter  C_DEFAULT_VALUE                = "";
+  parameter  C_DIN_WIDTH                    = 8;
+  parameter  C_DOUT_RST_VAL                 = "";
+  parameter  C_DOUT_WIDTH                   = 8;
+  parameter  C_ENABLE_RLOCS                 = 0;
+  parameter  C_FAMILY                       = "virtex2"; //Not allowed in Verilog model
+  parameter  C_HAS_ALMOST_EMPTY             = 0;
+  parameter  C_HAS_ALMOST_FULL              = 0;
+  parameter  C_HAS_BACKUP                   = 0;
+  parameter  C_HAS_DATA_COUNT               = 0;
+  parameter  C_HAS_MEMINIT_FILE             = 0;
+  parameter  C_HAS_OVERFLOW                 = 0;
+  parameter  C_HAS_RD_DATA_COUNT            = 0;
+  parameter  C_HAS_RD_RST                   = 0;
+  parameter  C_HAS_RST                      = 0;
+  parameter  C_HAS_UNDERFLOW                = 0;
+  parameter  C_HAS_VALID                    = 0;
+  parameter  C_HAS_WR_ACK                   = 0;
+  parameter  C_HAS_WR_DATA_COUNT            = 0;
+  parameter  C_HAS_WR_RST                   = 0;
+  parameter  C_IMPLEMENTATION_TYPE          = 0;
+  parameter  C_INIT_WR_PNTR_VAL             = 0;
+  parameter  C_MEMORY_TYPE                  = 1;
+  parameter  C_MIF_FILE_NAME                = "";
+  parameter  C_OPTIMIZATION_MODE            = 0;
+  parameter  C_OVERFLOW_LOW                 = 0;
+  parameter  C_PRELOAD_LATENCY              = 1;
+  parameter  C_PRELOAD_REGS                 = 0;
+  parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0;
+  parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0;
+  parameter  C_PROG_EMPTY_TYPE              = 0;
+  parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0;
+  parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0;
+  parameter  C_PROG_FULL_TYPE               = 0;
+  parameter  C_RD_DATA_COUNT_WIDTH          = 2;
+  parameter  C_RD_DEPTH                     = 256;
+  parameter  C_RD_PNTR_WIDTH                = 8;
+  parameter  C_UNDERFLOW_LOW                = 0;
+  parameter  C_VALID_LOW                    = 0;
+  parameter  C_WR_ACK_LOW                   = 0;
+  parameter  C_WR_DATA_COUNT_WIDTH          = 2;
+  parameter  C_WR_DEPTH                     = 256;
+  parameter  C_WR_PNTR_WIDTH                = 8;
+  parameter  C_WR_RESPONSE_LATENCY          = 1;
+  parameter  C_FULL_FLAGS_RST_VAL           = 1;
+  parameter  C_USE_FWFT_DATA_COUNT          = 0;
+  parameter  C_USE_EMBEDDED_REG             = 0;
+
+  /*****************************************************************************
+  * Declare Input and Output Ports
+  *****************************************************************************/
+  input [C_DIN_WIDTH-1:0]            DIN;
+  input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH;
+  input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_ASSERT;
+  input [C_RD_PNTR_WIDTH-1:0]        PROG_EMPTY_THRESH_NEGATE;
+  input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH;
+  input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_ASSERT;
+  input [C_WR_PNTR_WIDTH-1:0]        PROG_FULL_THRESH_NEGATE;
+  input                              RD_CLK;
+  input                              RD_EN;
+  input                              RST;
+  input                              WR_CLK;
+  input                              WR_EN;
+  output                             ALMOST_EMPTY;
+  output                             ALMOST_FULL;
+  output [C_DOUT_WIDTH-1:0]          DOUT;
+  output                             EMPTY;
+  output                             FULL;
+  output                             OVERFLOW;
+  output                             PROG_EMPTY;
+  output                             PROG_FULL;
+  output                             VALID;
+  output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
+  output                             UNDERFLOW;
+  output                             WR_ACK;
+  output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
+
+  /*******************************************************************************
+  * Input and output register declarations
+  ******************************************************************************/
+  /*******************************************************************************
+  * Parameters used as constants
+  ******************************************************************************/
+  //When RST is present, set FULL reset value to '1'.
+  //If core has no RST, make sure FULL powers-on as '0'.
+  parameter                      C_DEPTH_RATIO_WR =  
+    (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
+  parameter                      C_DEPTH_RATIO_RD =  
+    (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
+  parameter                      C_FIFO_WR_DEPTH = 
+    (C_COMMON_CLOCK) ? 
+    C_WR_DEPTH : C_WR_DEPTH - 1;
+  parameter                      C_FIFO_RD_DEPTH = 
+    (C_COMMON_CLOCK) ? 
+    C_RD_DEPTH : C_RD_DEPTH - 1;
+
+  
+  // EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
+  // WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1
+  // WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling)
+  // WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4
+  // WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8
+  parameter EXTRA_WORDS = (C_DEPTH_RATIO_RD > 1)? 1:(2 * C_DEPTH_RATIO_WR);
+  // extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD
+  //  C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH    | EXTRA_WORDS_DC
+  //  -----------------|------------------|-----------------|---------------
+  //  1                | 8                | C_RD_PNTR_WIDTH | 2
+  //  1                | 4                | C_RD_PNTR_WIDTH | 2
+  //  1                | 2                | C_RD_PNTR_WIDTH | 2
+  //  1                | 1                | C_WR_PNTR_WIDTH | 2
+  //  2                | 1                | C_WR_PNTR_WIDTH | 4
+  //  4                | 1                | C_WR_PNTR_WIDTH | 8
+  //  8                | 1                | C_WR_PNTR_WIDTH | 16
+  parameter EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR)?
+                             2:(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);  
+
+
+  //Memory which will be used to simulate a FIFO
+  reg [C_DIN_WIDTH-1:0]          memory[C_WR_DEPTH-1:0];
+  reg [31:0]                     num_wr_bits;
+  reg [31:0]                     num_rd_bits;
+  reg [31:0]                     next_num_wr_bits;
+  reg [31:0]                     next_num_rd_bits;
+  reg [31:0]                     wr_ptr;
+  reg [31:0]                     rd_ptr;
+  reg [31:0]                     wr_ptr_rdclk;
+  reg [31:0]                     wr_ptr_rdclk_next;
+  reg [31:0]                     rd_ptr_wrclk;
+  reg [31:0]                     rd_ptr_wrclk_next;
+  wire [31:0]                    num_read_words  = num_rd_bits/C_DOUT_WIDTH;
+  wire [31:0]                    num_read_words_dc_i; 
+  wire [31:0]                    num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
+  wire [31:0]                    num_read_words_fwft_dc = (num_rd_bits/C_DOUT_WIDTH+2);
+  wire [31:0]                    num_read_words_pe = 
+    num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
+  wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; 
+  wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized 
+    = num_read_words_dc_i[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; 
+  wire [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_fwft 
+    = num_read_words_dc_i[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; 
+  wire [31:0]                    num_write_words = num_wr_bits/C_DIN_WIDTH;
+  wire [31:0]                    num_write_words_dc_i;
+  wire [31:0]                    num_write_words_dc = 1+(num_wr_bits-1)/C_DIN_WIDTH;//roof of num_wr_bits/C_DIN_WIDTH
+  wire [31:0]                    num_write_words_fwft_dc = 
+    (num_wr_bits/C_DIN_WIDTH*C_DEPTH_RATIO_RD+2*C_DEPTH_RATIO_WR)/C_DEPTH_RATIO_RD;
+  wire [31:0]                    num_write_words_pf = 
+    num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
+  wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; 
+  wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized 
+    = num_write_words_dc_i[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; 
+  wire [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_fwft 
+    = num_write_words_dc_i[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; 
+  wire [31:0]                    reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
+  wire [31:0]                    log2_reads_per_write = log2_val(reads_per_write);
+  wire [31:0]                    writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
+  wire [31:0]                    log2_writes_per_read = log2_val(writes_per_read);
+
+  /*******************************************************************************
+   * Internal Registers and wires
+   ******************************************************************************/
+  wire                           wr_ack_i;
+  wire                           overflow_i;
+  wire                           underflow_i;
+  wire                           valid_i;
+  wire                           valid_out;
+  reg                            valid_d1;
+  /*******************************************************************************
+   * Internal registers and wires for internal reset logics 
+   ******************************************************************************/
+  reg                            rd_rst_asreg    =0;
+  reg                            rd_rst_asreg_d1 =0;
+  reg                            rd_rst_asreg_d2 =0;
+  reg                            rd_rst_reg      =0;
+  reg                            rd_rst_d1       =0;
+  reg                            wr_rst_asreg    =0;
+  reg                            wr_rst_asreg_d1 =0;
+  reg                            wr_rst_asreg_d2 =0;
+  reg                            wr_rst_reg      =0;
+  reg                            wr_rst_d1       =0;
+  wire                           rd_rst_comb;
+  wire                           rd_rst_i;
+  wire                           wr_rst_comb;
+  wire                           wr_rst_i;
+
+
+
+  //Special ideal FIFO signals
+  reg [C_DOUT_WIDTH-1:0]         ideal_dout;
+  wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;
+  reg [C_DOUT_WIDTH-1:0]         ideal_dout_d1;
+  reg                            ideal_wr_ack;
+  reg                            ideal_valid;
+  reg                            ideal_overflow;
+  reg                            ideal_underflow;
+  reg                            ideal_full;
+  reg                            ideal_empty;
+  reg                            ideal_almost_full;
+  reg                            ideal_almost_empty;
+  reg                            ideal_prog_full;
+  reg                            ideal_prog_empty;
+
+  //MSBs of the counts
+  reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count;
+  reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count;
+
+  //user specified value for reseting the size of the fifo
+  reg [C_DOUT_WIDTH-1:0]            dout_reset_val;
+
+  //temporary registers for WR_RESPONSE_LATENCY feature
+
+  integer                           tmp_wr_listsize;
+  integer                           tmp_rd_listsize;
+
+  //Signal for registered version of prog full and empty
+  reg                               prog_full_d;
+  reg                               prog_empty_d;
+
+  //Threshold values for Programmable Flags
+  integer                           prog_empty_actual_thresh_assert;
+  integer                           prog_empty_actual_thresh_negate;
+  integer                           prog_full_actual_thresh_assert;
+  integer                           prog_full_actual_thresh_negate;
+
+
+  /****************************************************************************
+   * Function Declarations
+   ***************************************************************************/
+
+  task write_fifo;
+    begin
+      memory[wr_ptr]     <= DIN;
+      if (wr_ptr == 0) begin
+        wr_ptr          <= C_WR_DEPTH - 1;
+      end else begin
+        wr_ptr          <= wr_ptr - 1;
+      end
+    end
+  endtask // write_fifo
+
+  task read_fifo;
+    integer i;
+    reg [C_DOUT_WIDTH-1:0] tmp_dout;
+    reg [C_DIN_WIDTH-1:0]  memory_read;
+    reg [31:0]             tmp_rd_ptr;
+    reg [31:0]             rd_ptr_high;
+    reg [31:0]             rd_ptr_low;
+    begin
+      // output is wider than input
+      if (reads_per_write == 0) begin
+        tmp_dout = 0;
+        tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
+        for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
+          tmp_dout = tmp_dout << C_DIN_WIDTH;
+          tmp_dout = tmp_dout | memory[tmp_rd_ptr];
+          if (tmp_rd_ptr == 0) begin
+            tmp_rd_ptr = C_WR_DEPTH - 1;
+          end else begin
+            tmp_rd_ptr = tmp_rd_ptr - 1;
+          end
+        end
+
+      // output is symmetric
+      end else if (reads_per_write == 1) begin
+        tmp_dout = memory[rd_ptr];
+
+      // input is wider than output
+      end else begin
+        rd_ptr_high = rd_ptr >> log2_reads_per_write;
+        rd_ptr_low  = rd_ptr & (reads_per_write - 1);
+        memory_read = memory[rd_ptr_high];
+        tmp_dout    = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
+      end
+      ideal_dout <= tmp_dout;
+      if (rd_ptr == 0) begin
+        rd_ptr <= C_RD_DEPTH - 1;
+      end else begin
+        rd_ptr <= rd_ptr - 1;
+      end
+    end
+  endtask
+
+  /****************************************************************************
+  * log2_val
+  *   Returns the 'log2' value for the input value for the supported ratios
+  ***************************************************************************/
+  function [31:0] log2_val;
+    input [31:0] binary_val;
+
+    begin
+      if (binary_val == 8) begin
+        log2_val = 3;
+      end else if (binary_val == 4) begin
+        log2_val = 2;
+      end else begin
+        log2_val = 1;
+      end
+    end
+  endfunction
+
+  /*************************************************************************
+  * hexstr_conv
+  *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+  ***********************************************************************/
+  function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_DOUT_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  /*************************************************************************
+  * Initialize Signals for clean power-on simulation
+  *************************************************************************/
+  initial
+    begin
+      num_wr_bits        = 0;
+      num_rd_bits        = 0;
+      next_num_wr_bits   = 0;
+      next_num_rd_bits   = 0;
+      rd_ptr             = C_RD_DEPTH - 1;
+      wr_ptr             = C_WR_DEPTH - 1;
+      rd_ptr_wrclk       = rd_ptr;
+      wr_ptr_rdclk       = wr_ptr;
+      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
+      ideal_dout         = dout_reset_val;
+      ideal_wr_ack       = 1'b0;
+      ideal_valid        = 1'b0;
+      ideal_overflow     = 1'b0;
+      ideal_underflow    = 1'b0;
+      //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im)
+      //ideal_full         = C_FULL_RESET_VAL; //was in v3.1
+      ideal_full         = 1'b0; //v3.2 
+      ideal_empty        = 1'b1;
+      //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im)
+      //ideal_almost_full  = C_ALMOST_FULL_RESET_VAL; //was in v3.1
+      ideal_almost_full  = 1'b0; //v3.2
+      ideal_almost_empty = 1'b1;
+      ideal_wr_count     = 0;
+      ideal_rd_count     = 0;
+      //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im)
+      //ideal_prog_full    = C_PROG_FULL_RESET_VAL; //was in v3.1
+      ideal_prog_full    = 1'b0; //v3.2
+      ideal_prog_empty   = 1'b1;
+      //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im)
+      //Therefore, prog_full_d has to start-up at '0' too
+      //prog_full_d        = C_PROG_FULL_RESET_VAL; //was in v3.1
+      prog_full_d        = 1'b0; //v3.2
+      prog_empty_d       = 1'b1;
+    end
+
+
+
+  /*************************************************************************
+   * Assign Internal ideal signals to output ports
+   *************************************************************************/
+  assign ideal_dout_out= (C_PRELOAD_LATENCY==2 &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
+                         ideal_dout_d1: ideal_dout;   
+  assign DOUT          = ideal_dout_out;
+  assign FULL          = ideal_full;
+  assign EMPTY         = ideal_empty;
+  assign ALMOST_FULL   = ideal_almost_full;
+  assign ALMOST_EMPTY  = ideal_almost_empty;
+  assign num_write_words_sized_i=C_USE_FWFT_DATA_COUNT?
+                                num_write_words_sized_fwft:num_write_words_sized;
+  assign num_read_words_sized_i=C_USE_FWFT_DATA_COUNT?
+                                num_read_words_sized_fwft:num_read_words_sized;
+  assign num_write_words_dc_i = C_USE_FWFT_DATA_COUNT?
+                               num_write_words_fwft_dc: num_write_words_dc;
+  assign num_read_words_dc_i = C_USE_FWFT_DATA_COUNT?
+                               num_read_words_fwft_dc: num_read_words_dc;
+  assign WR_DATA_COUNT = ideal_wr_count;
+  assign RD_DATA_COUNT = ideal_rd_count;
+  assign PROG_FULL     = ideal_prog_full;
+  assign PROG_EMPTY    = ideal_prog_empty;
+
+  //Handshaking signals can be active low, depending on _LOW parameters
+  assign valid_i       = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
+  assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;
+  assign valid_out     = (C_PRELOAD_LATENCY==2 &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
+                         valid_d1: valid_i;  
+  assign underflow_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
+  assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
+
+  assign WR_ACK        = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
+  assign wr_ack_i      = (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack :
+                            (WR_EN & !FULL);
+  assign OVERFLOW      = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
+  assign overflow_i    = (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow :
+                             (WR_EN & FULL);
+
+  /*******************************************************************************
+  * Internal reset logics 
+  ******************************************************************************/
+  assign wr_rst_comb      = !wr_rst_asreg_d2 && wr_rst_asreg;
+  assign rd_rst_comb      = !rd_rst_asreg_d2 && rd_rst_asreg;
+  assign wr_rst_i         = C_HAS_RST ? wr_rst_reg : 0;
+  assign rd_rst_i         = C_HAS_RST ? rd_rst_reg : 0;
+
+
+  always @(posedge RD_CLK or posedge rd_rst_i) begin
+    if (rd_rst_i == 1'b1) begin
+      valid_d1 <= 1'b0;
+    end else begin
+      valid_d1 <= valid_i;
+    end    
+  end   
+  always @(posedge RD_CLK or posedge rd_rst_i) begin
+    if (rd_rst_i == 1'b1) begin
+      ideal_dout_d1 <= dout_reset_val;
+    end else begin
+      ideal_dout_d1 <= ideal_dout;
+    end    
+  end   
+  
+  always @(posedge WR_CLK or posedge RST) begin
+    if (RST == 1'b1) begin
+      wr_rst_asreg <= 1'b1;
+    end else begin
+      if (wr_rst_asreg_d1 == 1'b1) begin
+        wr_rst_asreg <= 1'b0;
+      end else begin
+        wr_rst_asreg <= wr_rst_asreg;
+      end
+    end    
+  end   
+
+  always @(posedge WR_CLK) begin
+    wr_rst_asreg_d1 <= wr_rst_asreg;
+    wr_rst_asreg_d2 <= wr_rst_asreg_d1;
+  end
+  
+  always @(posedge WR_CLK or posedge wr_rst_comb) begin
+    if (wr_rst_comb == 1'b1) begin
+      wr_rst_reg <= 1'b1;
+    end else begin
+      wr_rst_reg <= 1'b0;
+    end    
+  end   
+
+  always @(posedge WR_CLK or posedge wr_rst_i) begin
+    if (wr_rst_i == 1'b1) begin
+      wr_rst_d1 <= 1'b1;
+    end else begin
+      wr_rst_d1 <= wr_rst_i;
+    end    
+  end   
+  always @(posedge RD_CLK or posedge RST) begin
+    if (RST == 1'b1) begin
+      rd_rst_asreg <= 1'b1;
+    end else begin
+      if (rd_rst_asreg_d1 == 1'b1) begin
+        rd_rst_asreg <= 1'b0;
+      end else begin
+        rd_rst_asreg <= rd_rst_asreg;
+      end
+    end    
+  end   
+
+  always @(posedge RD_CLK) begin
+    rd_rst_asreg_d1 <= rd_rst_asreg;
+    rd_rst_asreg_d2 <= rd_rst_asreg_d1;
+  end
+  
+  always @(posedge RD_CLK or posedge rd_rst_comb) begin
+    if (rd_rst_comb == 1'b1) begin
+      rd_rst_reg <= 1'b1;
+    end else begin
+      rd_rst_reg <= 1'b0;
+    end    
+  end   
+   
+   //Generate overflow and underflow flags seperately
+   //because they don't support async rst
+   always @(posedge WR_CLK) begin
+     ideal_overflow    <= WR_EN & ideal_full;
+   end
+   always @(posedge RD_CLK) begin
+     ideal_underflow    <= ideal_empty & RD_EN;
+   end
+
+   /*******************************************************************************
+   * Write and Read Logics 
+   ******************************************************************************/
+   always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
+
+     /****** Reset fifo (case 1)***************************************/
+     if (wr_rst_i == 1'b1) begin
+       num_wr_bits       <= 0;
+       next_num_wr_bits  <= 0;
+       wr_ptr            <= C_WR_DEPTH - 1;
+       rd_ptr_wrclk      <= C_RD_DEPTH - 1;
+       ideal_wr_ack      <= 0;
+       ideal_full        <= C_FULL_FLAGS_RST_VAL;
+       ideal_almost_full <= C_FULL_FLAGS_RST_VAL;
+       ideal_wr_count    <= 0;
+
+       ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;
+       prog_full_d       <= C_FULL_FLAGS_RST_VAL;
+
+     end else begin //wr_rst_i==0
+
+       //Determine the current number of words in the FIFO
+       tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
+                         num_wr_bits/C_DIN_WIDTH;
+       rd_ptr_wrclk_next = rd_ptr;
+       if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
+                                          - rd_ptr_wrclk_next);
+       end else begin
+         next_num_wr_bits = num_wr_bits -
+                            C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
+       end
+
+       //If this is a write, handle the write by adding the value
+       // to the linked list, and updating all outputs appropriately
+       if (WR_EN == 1'b1) begin
+         if (ideal_full == 1'b1) begin
+
+           //If the FIFO is full, do NOT perform the write,
+           // update flags accordingly
+           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD 
+             >= C_FIFO_WR_DEPTH) begin
+             //write unsuccessful - do not change contents
+
+             //Do not acknowledge the write
+             ideal_wr_ack      <= 0;
+             //Reminder that FIFO is still full
+             ideal_full        <= 1'b1;
+             ideal_almost_full <= 1'b1;
+
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           //If the FIFO is one from full, but reporting full
+           end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
+                        C_FIFO_WR_DEPTH-1) begin
+             //No change to FIFO
+
+             //Write not successful
+             ideal_wr_ack      <= 0;
+             //With DEPTH-1 words in the FIFO, it is almost_full
+             ideal_full        <= 1'b0;
+             ideal_almost_full <= 1'b1;
+
+             ideal_wr_count    <= num_write_words_sized_i;
+
+
+           //If the FIFO is completely empty, but it is
+           // reporting FULL for some reason (like reset)
+           end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
+                        C_FIFO_WR_DEPTH-2) begin
+             //No change to FIFO
+
+             //Write not successful
+             ideal_wr_ack      <= 0;
+             //FIFO is really not close to full, so change flag status.
+             ideal_full        <= 1'b0;
+             ideal_almost_full <= 1'b0;
+
+             ideal_wr_count    <= num_write_words_sized_i;
+           end //(tmp_wr_listsize == 0)
+
+         end else begin
+
+           //If the FIFO is full, do NOT perform the write,
+           // update flags accordingly
+           if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
+              C_FIFO_WR_DEPTH) begin
+             //write unsuccessful - do not change contents
+
+             //Do not acknowledge the write
+             ideal_wr_ack       <= 0;
+             //Reminder that FIFO is still full
+             ideal_full         <= 1'b1;
+             ideal_almost_full  <= 1'b1;
+
+             ideal_wr_count     <= num_write_words_sized_i;
+
+           //If the FIFO is one from full
+           end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
+                       C_FIFO_WR_DEPTH-1) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
+
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= 1;
+             //This write is CAUSING the FIFO to go full
+             ideal_full        <= 1'b1;
+             ideal_almost_full <= 1'b1;
+
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           //If the FIFO is 2 from full
+           end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
+                        C_FIFO_WR_DEPTH-2) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits =  next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= 1;
+             //Still 2 from full
+             ideal_full        <= 1'b0;
+             //2 from full, and writing, so set almost_full
+             ideal_almost_full <= 1'b1;
+
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           //If the FIFO is not close to being full
+           end else if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
+                       C_FIFO_WR_DEPTH-2) begin
+             //Add value on DIN port to FIFO
+             write_fifo;
+             next_num_wr_bits  = next_num_wr_bits + C_DIN_WIDTH;
+             //Write successful, so issue acknowledge
+             // and no error
+             ideal_wr_ack      <= 1;
+             //Not even close to full.
+             ideal_full        <= 1'b0;
+             ideal_almost_full <= 1'b0;
+
+             ideal_wr_count    <= num_write_words_sized_i;
+
+           end
+
+         end
+
+       end else begin //(WR_EN == 1'b1)
+
+         //If user did not attempt a write, then do not
+         // give ack or err
+         ideal_wr_ack   <= 0;
+
+         //Implied statements:
+         //ideal_empty <= ideal_empty;
+         //ideal_almost_empty <= ideal_almost_empty;
+
+         //Check for full
+         if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH)
+           ideal_full <= 1'b1;
+         else
+           ideal_full <= 1'b0;
+
+         //Check for almost_full
+         if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= C_FIFO_WR_DEPTH-1)
+           ideal_almost_full  <= 1'b1;
+         else
+           ideal_almost_full  <= 1'b0;
+
+         ideal_wr_count <= num_write_words_sized_i;
+       end
+
+       /*********************************************************
+        * Programmable FULL flags
+        *********************************************************/
+       //Single Programmable Full Constant Threshold
+       if (C_PROG_FULL_TYPE==1) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS;
+           prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS;
+         end else begin
+           prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL;
+           prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_ASSERT_VAL;
+         end
+
+       //Two Programmable Full Constant Thresholds
+       end else if (C_PROG_FULL_TYPE==2) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL-EXTRA_WORDS;
+           prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL-EXTRA_WORDS;
+         end else begin
+           prog_full_actual_thresh_assert = C_PROG_FULL_THRESH_ASSERT_VAL;
+           prog_full_actual_thresh_negate = C_PROG_FULL_THRESH_NEGATE_VAL;
+         end
+
+       //Single Programmable Full Threshold Input
+       end else if (C_PROG_FULL_TYPE==3) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_full_actual_thresh_assert = PROG_FULL_THRESH-EXTRA_WORDS;
+           prog_full_actual_thresh_negate = PROG_FULL_THRESH-EXTRA_WORDS;
+         end else begin
+           prog_full_actual_thresh_assert = PROG_FULL_THRESH;
+           prog_full_actual_thresh_negate = PROG_FULL_THRESH;
+         end
+
+       //Two Programmable Full Threshold Inputs
+       end else if (C_PROG_FULL_TYPE==4) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT-EXTRA_WORDS;
+           prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE-EXTRA_WORDS;
+         end else begin
+           prog_full_actual_thresh_assert = PROG_FULL_THRESH_ASSERT;
+           prog_full_actual_thresh_negate = PROG_FULL_THRESH_NEGATE;
+         end
+       end //C_PROG_FULL_TYPE
+       
+       if (num_write_words_pf==0) begin
+          prog_full_d <= 1'b0;
+       end else begin
+         if (((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) 
+              == prog_full_actual_thresh_assert-1) && WR_EN) begin
+            prog_full_d <= 1'b1;
+         end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) 
+                      >= prog_full_actual_thresh_assert) begin
+            prog_full_d <= 1'b1;
+         end else if ((1+(num_write_words_pf-1)/C_DEPTH_RATIO_RD) 
+                      < prog_full_actual_thresh_negate) begin
+            prog_full_d <= 1'b0;
+         end
+       end  
+
+       if (wr_rst_d1==1 && wr_rst_i==0) begin
+         ideal_prog_full   <= 0;
+       end else begin
+         ideal_prog_full   <= prog_full_d;
+       end
+       num_wr_bits       <= next_num_wr_bits;
+       rd_ptr_wrclk      <= rd_ptr;
+
+     end //wr_rst_i==0
+   end // write always
+
+   always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r
+
+     /****** Reset fifo (case 1)***************************************/
+     if (rd_rst_i) begin
+       num_rd_bits        <= 0;
+       next_num_rd_bits   <= 0;
+       rd_ptr             <= C_RD_DEPTH -1;
+       wr_ptr_rdclk       <= C_WR_DEPTH -1;
+       ideal_dout         <= dout_reset_val;
+       ideal_valid        <= 1'b0;
+       ideal_empty        <= 1'b1;
+       ideal_almost_empty <= 1'b1;
+       ideal_rd_count     <= 0;
+
+       ideal_prog_empty   <= 1'b1;
+       prog_empty_d       <= 1;
+
+
+     end else begin //rd_rst_i==0
+
+       //Determine the current number of words in the FIFO
+       tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
+                         num_rd_bits/C_DOUT_WIDTH;
+       wr_ptr_rdclk_next = wr_ptr;
+
+       if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
+         next_num_rd_bits = num_rd_bits +
+                            C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
+                                         - wr_ptr_rdclk_next);
+       end else begin
+         next_num_rd_bits = num_rd_bits +
+                             C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
+       end
+
+       /*****************************************************************/
+       // Read Operation - Read Latency 1
+       /*****************************************************************/
+       if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
+
+         if (RD_EN == 1'b1) begin
+
+           if (ideal_empty == 1'b1) begin
+
+             //If the FIFO is completely empty, and is reporting empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= 1'b0;
+                 //Reminder that FIFO is still empty
+                 ideal_empty        <= 1'b1;
+                 ideal_almost_empty <= 1'b1;
+
+                 ideal_rd_count     <= num_read_words_sized_i;
+               end // if (tmp_rd_listsize <= 0)
+
+             //If the FIFO is one from empty, but it is reporting empty
+             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= 1'b0;
+                 //Note that FIFO is no longer empty, but is almost empty (has one word left)
+                 ideal_empty        <= 1'b0;
+                 ideal_almost_empty <= 1'b1;
+
+                 ideal_rd_count     <= num_read_words_sized_i;
+
+               end // if (tmp_rd_listsize == 1)
+
+             //If the FIFO is two from empty, and is reporting empty
+             else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid        <= 1'b0;
+                 //Fifo has two words, so is neither empty or almost empty
+                 ideal_empty        <= 1'b0;
+                 ideal_almost_empty <= 1'b0;
+
+                 ideal_rd_count     <= num_read_words_sized_i;
+
+               end // if (tmp_rd_listsize == 2)
+
+             //If the FIFO is not close to empty, but is reporting that it is
+             // Treat the FIFO as empty this time, but unset EMPTY flags.
+             if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
+               begin
+                 //Do not change the contents of the FIFO
+
+                 //Do not acknowledge the read from empty FIFO
+                 ideal_valid <= 1'b0;
+                 //Note that the FIFO is No Longer Empty or Almost Empty
+                 ideal_empty  <= 1'b0;
+                 ideal_almost_empty <= 1'b0;
+
+                 ideal_rd_count <= num_read_words_sized_i;
+
+               end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+             end // else: if(ideal_empty == 1'b1)
+
+           else //if (ideal_empty == 1'b0)
+             begin
+
+               //If the FIFO is completely full, and we are successfully reading from it
+               if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= 1'b1;
+                   //Not close to empty
+                   ideal_empty        <= 1'b0;
+                   ideal_almost_empty <= 1'b0;
+
+                   ideal_rd_count     <= num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
+
+               //If the FIFO is not close to being empty
+               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= 1'b1;
+                   //Not close to empty
+                   ideal_empty        <= 1'b0;
+                   ideal_almost_empty <= 1'b0;
+
+                   ideal_rd_count     <= num_read_words_sized_i;
+
+                 end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+
+               //If the FIFO is two from empty
+               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= 1'b1;
+                   //Fifo is not yet empty. It is going almost_empty
+                   ideal_empty        <= 1'b0;
+                   ideal_almost_empty <= 1'b1;
+
+                   ideal_rd_count     <= num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 2)
+
+               //If the FIFO is one from empty
+               else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
+                 begin
+                   //Read the value from the FIFO
+                   read_fifo;
+                   next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+                   //Acknowledge the read from the FIFO, no error
+                   ideal_valid        <= 1'b1;
+                   //Note that FIFO is GOING empty
+                   ideal_empty        <= 1'b1;
+                   ideal_almost_empty <= 1'b1;
+
+                   ideal_rd_count     <= num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize == 1)
+
+
+               //If the FIFO is completely empty
+               else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+                 begin
+                   //Do not change the contents of the FIFO
+
+                   //Do not acknowledge the read from empty FIFO
+                   ideal_valid        <= 1'b0;
+                   //Reminder that FIFO is still empty
+                   ideal_empty        <= 1'b1;
+                   ideal_almost_empty <= 1'b1;
+
+                   ideal_rd_count     <= num_read_words_sized_i;
+
+                 end // if (tmp_rd_listsize <= 0)
+
+             end // if (ideal_empty == 1'b0)
+
+           end //(RD_EN == 1'b1)
+
+         else //if (RD_EN == 1'b0)
+           begin
+             //If user did not attempt a read, do not give an ack or err
+             ideal_valid          <= 1'b0;
+
+             //Check for empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+               ideal_empty        <= 1'b1;
+             else
+               ideal_empty        <= 1'b0;
+
+             //Check for almost_empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1)
+               ideal_almost_empty <= 1'b1;
+             else
+               ideal_almost_empty <= 1'b0;
+
+             ideal_rd_count       <= num_read_words_sized_i;
+
+           end // else: !if(RD_EN == 1'b1)
+
+       /*****************************************************************/
+       // Read Operation - Read Latency 0
+       /*****************************************************************/
+       end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+         if (RD_EN == 1'b1) begin
+
+           if (ideal_empty == 1'b1) begin
+
+             //If the FIFO is completely empty, and is reporting empty
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= 1'b0;
+               //Reminder that FIFO is still empty
+               ideal_empty        <= 1'b1;
+               ideal_almost_empty <= 1'b1;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             //If the FIFO is one from empty, but it is reporting empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= 1'b0;
+               //Note that FIFO is no longer empty, but is almost empty (has one word left)
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b1;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             //If the FIFO is two from empty, and is reporting empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= 1'b0;
+               //Fifo has two words, so is neither empty or almost empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+               //If the FIFO is not close to empty, but is reporting that it is
+             // Treat the FIFO as empty this time, but unset EMPTY flags.
+             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
+                         (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= 1'b0;
+               //Note that the FIFO is No Longer Empty or Almost Empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
+
+           end else begin
+
+             //If the FIFO is completely full, and we are successfully reading from it
+             if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= 1'b1;
+               //Not close to empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             //If the FIFO is not close to being empty
+             end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
+                          (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= 1'b1;
+               //Not close to empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             //If the FIFO is two from empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= 1'b1;
+               //Fifo is not yet empty. It is going almost_empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b1;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             //If the FIFO is one from empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
+               //Read the value from the FIFO
+               read_fifo;
+               next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
+
+               //Acknowledge the read from the FIFO, no error
+               ideal_valid        <= 1'b1;
+               //Note that FIFO is GOING empty
+               ideal_empty        <= 1'b1;
+               ideal_almost_empty <= 1'b1;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             //If the FIFO is completely empty
+             end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
+               //Do not change the contents of the FIFO
+
+               //Do not acknowledge the read from empty FIFO
+               ideal_valid        <= 1'b0;
+               //Reminder that FIFO is still empty
+               ideal_empty        <= 1'b1;
+               ideal_almost_empty <= 1'b1;
+
+               ideal_rd_count     <= num_read_words_sized_i;
+
+             end // if (tmp_rd_listsize <= 0)
+
+           end // if (ideal_empty == 1'b0)
+
+         end else begin//(RD_EN == 1'b0)
+
+         
+           //If user did not attempt a read, do not give an ack or err
+           ideal_valid           <= 1'b0;
+
+           //Check for empty
+           if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
+             ideal_empty         <= 1'b1;
+           else
+             ideal_empty         <= 1'b0;
+
+           //Check for almost_empty
+           if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 1)
+             ideal_almost_empty  <= 1'b1;
+           else
+             ideal_almost_empty  <= 1'b0;
+
+           ideal_rd_count        <= num_read_words_sized_i;
+
+         end // else: !if(RD_EN == 1'b1)
+       end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
+
+
+       /*********************************************************
+        * Programmable EMPTY flags
+        *********************************************************/
+       //Determine the Assert and Negate thresholds for Programmable Empty
+       //  (Subtract 2 read-sized words when using Preload 0)
+
+       //Single Programmable Empty Constant Threshold
+       if (C_PROG_EMPTY_TYPE==1) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2;
+           prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL-2;
+         end
+         else begin
+           prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL;
+           prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_ASSERT_VAL;
+         end
+
+       //Two Programmable Empty Constant Thresholds
+       end else if (C_PROG_EMPTY_TYPE==2) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL-2;
+           prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL-2;
+         end
+         else begin
+           prog_empty_actual_thresh_assert = C_PROG_EMPTY_THRESH_ASSERT_VAL;
+           prog_empty_actual_thresh_negate = C_PROG_EMPTY_THRESH_NEGATE_VAL;
+         end
+
+       //Single Programmable Empty Constant Threshold
+       end else if (C_PROG_EMPTY_TYPE==3) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH-2;
+           prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH-2;
+         end
+         else begin
+           prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH;
+           prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH;
+
+         end
+       //Two Programmable Empty Constant Thresholds
+       end else if (C_PROG_EMPTY_TYPE==4) begin
+         if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
+           prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT-2;
+           prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE-2;
+         end
+         else begin
+           prog_empty_actual_thresh_assert = PROG_EMPTY_THRESH_ASSERT;
+           prog_empty_actual_thresh_negate = PROG_EMPTY_THRESH_NEGATE;
+         end
+       end
+
+       if ((num_read_words_pe/C_DEPTH_RATIO_WR == prog_empty_actual_thresh_assert+1) 
+           && RD_EN) begin
+         prog_empty_d <= 1'b1;
+       end else if (num_read_words_pe/C_DEPTH_RATIO_WR 
+                    <= prog_empty_actual_thresh_assert) begin
+         prog_empty_d <= 1'b1;
+       end else if (num_read_words_pe/C_DEPTH_RATIO_WR 
+                    > prog_empty_actual_thresh_negate) begin
+         prog_empty_d <= 1'b0;
+       end
+
+
+       ideal_prog_empty <= prog_empty_d;
+       num_rd_bits      <= next_num_rd_bits;
+       wr_ptr_rdclk     <= wr_ptr;
+     end //rd_rst_i==0
+   end //always
+
+endmodule // fifo_generator_v4_3_bhv_ver_as
+
+
+/*******************************************************************************
+ * Declaration of top-level module
+ ******************************************************************************/
+module fifo_generator_v4_3_bhv_ver_ss
+  (
+    CLK, RST, SRST, DIN, WR_EN, RD_EN,
+    PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE,
+    PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE,
+    DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY,
+    ALMOST_EMPTY, VALID, UNDERFLOW, DATA_COUNT,
+    PROG_FULL, PROG_EMPTY
+   );
+
+/******************************************************************************
+ * Declare user parameters and their defaults
+ *****************************************************************************/
+ parameter  C_COMMON_CLOCK                 = 0;
+ parameter  C_COUNT_TYPE                   = 0;
+ parameter  C_DATA_COUNT_WIDTH             = 2;
+ parameter  C_DEFAULT_VALUE                = "";
+ parameter  C_DIN_WIDTH                    = 8;
+ parameter  C_DOUT_RST_VAL                 = "";
+ parameter  C_DOUT_WIDTH                   = 8;
+ parameter  C_ENABLE_RLOCS                 = 0;
+ parameter  C_FAMILY                       = "virtex2"; //Not allowed in Verilog model
+ parameter  C_HAS_ALMOST_EMPTY             = 0;
+ parameter  C_HAS_ALMOST_FULL              = 0;
+ parameter  C_HAS_BACKUP                   = 0;
+ parameter  C_HAS_DATA_COUNT               = 0;
+ parameter  C_HAS_MEMINIT_FILE             = 0;
+ parameter  C_HAS_OVERFLOW                 = 0;
+ parameter  C_HAS_RD_DATA_COUNT            = 0;
+ parameter  C_HAS_RD_RST                   = 0;
+ parameter  C_HAS_RST                      = 0;
+ parameter  C_HAS_SRST                     = 0;
+ parameter  C_HAS_UNDERFLOW                = 0;
+ parameter  C_HAS_VALID                    = 0;
+ parameter  C_HAS_WR_ACK                   = 0;
+ parameter  C_HAS_WR_DATA_COUNT            = 0;
+ parameter  C_HAS_WR_RST                   = 0;
+ parameter  C_IMPLEMENTATION_TYPE          = 0;
+ parameter  C_INIT_WR_PNTR_VAL             = 0;
+ parameter  C_MEMORY_TYPE                  = 1;
+ parameter  C_MIF_FILE_NAME                = "";
+ parameter  C_OPTIMIZATION_MODE            = 0;
+ parameter  C_OVERFLOW_LOW                 = 0;
+ parameter  C_PRELOAD_LATENCY              = 1;
+ parameter  C_PRELOAD_REGS                 = 0;
+ parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL = 0;
+ parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL = 0;
+ parameter  C_PROG_EMPTY_TYPE              = 0;
+ parameter  C_PROG_FULL_THRESH_ASSERT_VAL  = 0;
+ parameter  C_PROG_FULL_THRESH_NEGATE_VAL  = 0;
+ parameter  C_PROG_FULL_TYPE               = 0;
+ parameter  C_RD_DATA_COUNT_WIDTH          = 2;
+ parameter  C_RD_DEPTH                     = 256;
+ parameter  C_RD_PNTR_WIDTH                = 8;
+ parameter  C_UNDERFLOW_LOW                = 0;
+ parameter  C_VALID_LOW                    = 0;
+ parameter  C_WR_ACK_LOW                   = 0;
+ parameter  C_WR_DATA_COUNT_WIDTH          = 2;
+ parameter  C_WR_DEPTH                     = 256;
+ parameter  C_WR_PNTR_WIDTH                = 8;
+ parameter  C_WR_RESPONSE_LATENCY          = 1;
+ parameter  C_FULL_FLAGS_RST_VAL           = 1;
+ parameter  C_USE_EMBEDDED_REG             = 0;
+
+
+/******************************************************************************
+ * Declare Input and Output Ports
+ *****************************************************************************/
+ input                            CLK;
+ input [C_DIN_WIDTH-1:0]          DIN;
+ input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH;
+ input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_ASSERT;
+ input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_NEGATE;
+ input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH;
+ input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_ASSERT;
+ input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_NEGATE;
+ input                            RD_EN;
+ input                            RST;
+ input                            SRST;
+ input                            WR_EN;
+ output                           ALMOST_EMPTY;
+ output                           ALMOST_FULL;
+ output [C_DATA_COUNT_WIDTH-1:0]  DATA_COUNT;
+ output [C_DOUT_WIDTH-1:0]        DOUT;
+ output                           EMPTY;
+ output                           FULL;
+ output                           OVERFLOW;
+ output                           PROG_EMPTY;
+ output                           PROG_FULL;
+ output                           VALID;
+ output                           UNDERFLOW;
+ output                           WR_ACK;
+
+/*******************************************************************************
+ * Input and output register declarations
+ ******************************************************************************/
+/*******************************************************************************
+ * Parameters used as constants
+ ******************************************************************************/
+   //When RST is present, set FULL reset value to '1'.
+   //If core has no RST, make sure FULL powers-on as '0'.
+   //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not 
+   //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
+   // Therefore, during SRST, all the FULL flags reset to 0.
+   parameter                      C_HAS_FAST_FIFO = 0;
+   parameter                      C_FIFO_WR_DEPTH = (C_COMMON_CLOCK) ? C_WR_DEPTH : C_WR_DEPTH - 1;
+   parameter                      C_FIFO_RD_DEPTH = (C_COMMON_CLOCK) ? C_RD_DEPTH : C_RD_DEPTH - 1;
+
+   /****************************************************************************
+    * Internal Registers and wires
+    ***************************************************************************/
+   wire                           wr_ack_i;
+   wire                           overflow_i;
+   wire                           underflow_i;
+   wire                           valid_i;
+   wire                           valid_out;
+   reg                            valid_d1;
+   wire                           srst_i;
+   /*******************************************************************************
+    * Internal registers and wires for internal reset logics 
+    ******************************************************************************/
+   reg                            rst_asreg    =0;
+   reg                            rst_asreg_d1 =0;
+   reg                            rst_asreg_d2 =0;
+   reg                            rst_reg      =0;
+   reg                            rst_d1       =0;
+   wire                           rst_comb;
+   wire                           rst_i;
+
+
+   //Memory which will be used to simulate a FIFO
+   reg [C_DIN_WIDTH-1:0]          memory[C_WR_DEPTH-1:0];
+   reg [31:0]                     num_bits;
+   reg [31:0]                     wr_ptr;
+   reg [31:0]                     rd_ptr;
+   wire [31:0]                    num_read_words  = num_bits/C_DOUT_WIDTH;
+   reg [31:0]                     num_read_words_q;
+   wire [31:0]                    num_write_words = num_bits/C_DIN_WIDTH;
+   reg [31:0]                     num_write_words_q;
+   //Removed power_on_timer in v3.2 (IP2_Im). For all reset types (Async, Sync, or no reset), the power-on values of the flags in the core are modified so that the core is ready to use from the very first clock cycle.
+  //reg [3:0]                    power_on_timer;
+
+   //Special ideal FIFO signals
+   reg [C_DOUT_WIDTH-1:0]         ideal_dout;
+   reg [C_DOUT_WIDTH-1:0]         ideal_dout_d1;
+   wire [C_DOUT_WIDTH-1:0]        ideal_dout_out;
+   reg                            ideal_wr_ack;
+   reg                            ideal_valid;
+   reg                            ideal_overflow;
+   reg                            ideal_underflow;
+   reg                            ideal_full;
+   reg                            ideal_empty;
+   reg                            ideal_almost_full;
+   reg                            ideal_almost_empty;
+   reg                            ideal_prog_full;
+   reg                            ideal_prog_empty;
+
+
+   //MSBs of the counts
+   wire [C_DATA_COUNT_WIDTH-1:0]  ideal_d_count;
+
+   //user specified value for reseting the size of the fifo
+   reg [C_DOUT_WIDTH-1:0]          dout_reset_val;
+
+
+   //temporary registers for WR_RESPONSE_LATENCY feature
+   reg                             ideal_wr_ack_q;
+   reg                             ideal_overflow_q;
+
+   reg                             prog_full_d;
+   reg                             prog_empty_d;
+
+   //Delayed version of RST
+   reg                             rst_q;
+   reg                             rst_qq;
+
+   /****************************************************************************
+    * Function Declarations
+    ***************************************************************************/
+   task write_fifo;
+      begin
+         memory[wr_ptr]     <= DIN;
+         if (wr_ptr == 0) begin
+            wr_ptr          <= C_WR_DEPTH - 1;
+         end else begin
+            wr_ptr          <= wr_ptr - 1;
+         end
+      end
+   endtask // write_fifo
+
+   task  read_fifo;
+      begin
+         ideal_dout <= memory[rd_ptr];
+         if (rd_ptr == 0) begin
+            rd_ptr  <= C_RD_DEPTH - 1;
+         end else begin
+            rd_ptr  <= rd_ptr - 1;
+         end
+      end
+   endtask
+
+   /****************************************************************************
+    * log2_val
+    *   Returns the 'log2' value for the input value for the supported ratios
+    ***************************************************************************/
+    function [31:0] log2_val;
+    input [31:0] binary_val;
+
+    begin
+       if (binary_val == 8) begin
+          log2_val = 3;
+       end else if (binary_val == 4) begin
+          log2_val = 2;
+       end else begin
+          log2_val = 1;
+       end
+    end
+    endfunction
+
+   /****************************************************************************
+    * hexstr_conv
+    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+    ***************************************************************************/
+    function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_DOUT_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+  /*****************************************************************************
+   * Initialize Signals
+   ****************************************************************************/
+   initial begin
+      num_bits           = 0;
+      num_read_words_q   = 0;
+      num_write_words_q  = 0;
+      rd_ptr             = C_RD_DEPTH -1;
+      wr_ptr             = C_WR_DEPTH -1;
+      dout_reset_val     = hexstr_conv(C_DOUT_RST_VAL);
+      ideal_dout       = dout_reset_val;
+      ideal_wr_ack       = 1'b0;
+      ideal_valid        = 1'b0;
+      valid_d1           = 1'b0;
+      ideal_overflow     = 1'b0;
+      ideal_underflow    = 1'b0;
+      //Modified the start-up value of FULL to '0' in v3.2 (IP2_Im)
+      //ideal_full         = C_FULL_RESET_VAL; //was in v3.1
+      ideal_full         = 1'b0; //v3.2
+      ideal_empty        = 1'b1;
+      //Modified the start-up value of ALMOST_FULL to '0' in v3.2 (IP2_Im)
+      //ideal_almost_full  = C_ALMOST_FULL_RESET_VAL; //was in v3.1
+      ideal_almost_full  = 1'b0;
+      ideal_almost_empty = 1'b1;
+      //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im)
+      //ideal_prog_full    = C_PROG_FULL_RESET_VAL; //was in v3.1
+      ideal_prog_full    = 1'b0; //v3.2
+      ideal_prog_empty   = 1'b1;
+
+      //Modified the start-up value of PROG_FULL to '0' in v3.2 (IP2_Im)
+      //Therefore, prog_full_d is also changed
+      //prog_full_d        = C_PROG_FULL_RESET_VAL; //was in v3.1
+      prog_full_d        = 1'b0; //v3.2
+      prog_empty_d       = 1'b1;
+
+      //Removed in v3.2
+      //power_on_timer     = C_HAS_RST ? 4'h3 : 4'h0;
+  
+      //Added these initial values in v3.2 to make it consistent with the synchronization flop stages in the core.
+      rst_q              = 1'b0;
+      rst_qq             = 1'b0;    
+   end
+
+
+  /*****************************************************************************
+   * Assign Internal ideal signals to output ports
+   ****************************************************************************/
+  assign ideal_dout_out= (C_USE_EMBEDDED_REG==1 &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
+                         ideal_dout_d1: ideal_dout; 
+  assign DOUT          = ideal_dout_out;
+  //was in v3.1
+  //assign FULL          = (power_on_timer) ? C_FULL_RESET_VAL : ideal_full;
+  //v3.2
+  assign FULL          = ideal_full;
+
+  assign EMPTY         = ideal_empty;
+  //was in v3.1
+  //assign ALMOST_FULL   = (power_on_timer) ? C_ALMOST_FULL_RESET_VAL : ideal_almost_full;
+  //v3.2
+  assign ALMOST_FULL   = ideal_almost_full;
+
+  assign ALMOST_EMPTY  = ideal_almost_empty;
+
+  assign ideal_d_count = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
+  assign DATA_COUNT    = ideal_d_count;
+
+  //was in v3.1
+  //assign PROG_FULL     = (power_on_timer) ? C_PROG_FULL_RESET_VAL : ideal_prog_full;
+  //v3.2
+  assign PROG_FULL     = ideal_prog_full;
+
+  assign PROG_EMPTY    = ideal_prog_empty;
+
+  //Handshaking signals can be active low, depending on _LOW parameters
+  assign valid_i       = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
+  assign VALID         = valid_out ? !C_VALID_LOW : C_VALID_LOW;
+  assign valid_out     = (C_PRELOAD_LATENCY==2 &&
+                          (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
+                         valid_d1: valid_i; 
+  assign underflow_i   = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
+  assign UNDERFLOW     = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
+
+  assign WR_ACK        = wr_ack_i ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
+  assign wr_ack_i      = (C_WR_RESPONSE_LATENCY==2) ? ideal_wr_ack_q :
+                         (C_WR_RESPONSE_LATENCY==1) ? ideal_wr_ack :
+                         (WR_EN & !FULL);
+  assign OVERFLOW      = overflow_i ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
+  assign overflow_i    = (C_WR_RESPONSE_LATENCY==2) ? ideal_overflow_q :
+                         (C_WR_RESPONSE_LATENCY==1) ? ideal_overflow :
+                         (WR_EN & FULL);
+
+  assign srst_i         = C_HAS_SRST ? SRST : 0;
+
+  /*******************************************************************************
+   * Internal reset logics 
+   ******************************************************************************/
+  assign rst_comb      = !rst_asreg_d2 && rst_asreg;
+  assign rst_i         = C_HAS_RST ? rst_reg : 0;
+
+  always @(posedge CLK or posedge rst_i) begin
+    if (rst_i == 1'b1) begin
+      valid_d1 <= 1'b0;
+    end else begin
+      if (srst_i) begin
+        valid_d1 <= 1'b0;
+      end else begin
+        valid_d1 <= valid_i;
+      end
+    end    
+  end   
+  always @(posedge CLK or posedge rst_i) begin
+    if (rst_i == 1'b1) begin
+      ideal_dout_d1 <= dout_reset_val;
+    end else begin
+      if (srst_i) begin
+        ideal_dout_d1 <= dout_reset_val;
+      end else begin
+        ideal_dout_d1 <= ideal_dout;
+      end
+    end    
+  end   
+
+  always @(posedge CLK or posedge RST) begin
+     if (RST == 1'b1) begin
+       rst_asreg <= 1'b1;
+     end else begin
+       if (rst_asreg_d1 == 1'b1) begin
+         rst_asreg <= 1'b0;
+       end else begin
+         rst_asreg <= rst_asreg;
+       end
+     end    
+  end   
+
+  always @(posedge CLK) begin
+     rst_asreg_d1 <= rst_asreg;
+     rst_asreg_d2 <= rst_asreg_d1;
+  end
+  
+  always @(posedge CLK or posedge rst_comb) begin
+     if (rst_comb == 1'b1) begin
+       rst_reg <= 1'b1;
+     end else begin
+       rst_reg <= 1'b0;
+     end    
+  end   
+
+  
+  /*******************************************************************************
+   * Write and Read Logics 
+   ******************************************************************************/
+
+  always @(posedge CLK or posedge rst_i)
+   begin : gen_wr_ack_resp
+
+       //Register reset
+       rst_q   <= rst_i;
+       rst_qq  <= rst_q;
+
+       //Register output signals to achieve desired WR_RESPONSE latency
+       if (C_WR_RESPONSE_LATENCY == 2) begin
+          if (rst_i == 1) begin
+            ideal_wr_ack_q   <= 0;
+            ideal_overflow_q <= 0;
+          end else begin
+            ideal_wr_ack_q   <= ideal_wr_ack;
+            ideal_overflow_q <= ideal_overflow;
+          end
+       end
+  
+      //Removed in v3.2 
+      /*
+      if (rst_i == 1) begin
+         power_on_timer <= 0;
+      end else if (power_on_timer > 0) begin
+         power_on_timer <= power_on_timer -1;
+      end else begin
+         power_on_timer <= 0;
+      end
+      */
+    end // block: gen_wr_ack_resp
+
+   // block memory has a synchronous reset
+   always @(posedge CLK) begin : gen_fifo_blkmemdout
+      //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core.
+      //if (rst_i || rst_q || rst_qq) begin //was in v3.1
+      if (rst_i || rst_q || srst_i) begin //v3.2
+         /******Initialize Read Domain Signals************************************/
+         if (C_MEMORY_TYPE == 1) begin
+            ideal_dout <= dout_reset_val;
+         end
+     //v3.2
+     //end else begin
+         //if (C_MEMORY_TYPE == 1 && power_on_timer >= 2) begin //was in v3.1
+     //    if (C_MEMORY_TYPE == 1) begin //v3.2
+     //       ideal_dout <= dout_reset_val;
+     //    end
+     end
+   end
+
+   always @(posedge CLK or posedge rst_i) begin : gen_fifo
+
+      /****** Reset fifo - Asynchronous Reset*************************************/
+      //Changed the latency of during async reset to '1' instead of '2' to make it consistent with the core.
+      //if (rst_i || rst_q || rst_qq) begin //was in v3.1
+      //if (rst_i || rst_q) begin //v3.2
+      if (rst_i ) begin //v3.2
+         /******Initialize Generic FIFO constructs********************************/
+         num_bits           <= 0;
+         wr_ptr             <= C_WR_DEPTH - 1;
+         rd_ptr             <= C_RD_DEPTH - 1;
+         num_read_words_q   <= 0;
+         num_write_words_q  <= 0;
+
+
+         /******Initialize Write Domain Signals***********************************/
+         ideal_wr_ack       <= 0;
+         ideal_full         <= C_FULL_FLAGS_RST_VAL;
+         ideal_almost_full  <= C_FULL_FLAGS_RST_VAL;
+
+         /******Initialize Read Domain Signals************************************/
+         if (C_MEMORY_TYPE != 1) begin
+            ideal_dout      <= dout_reset_val;
+         end
+         ideal_valid        <= 1'b0;
+         ideal_empty        <= 1'b1;
+         ideal_almost_empty <= 1'b1;
+
+      end else begin   
+         if (srst_i) begin
+            // SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT.
+            if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin
+ 	       /******Initialize Generic FIFO constructs********************************/
+               num_bits           <= 0;
+               wr_ptr             <= C_WR_DEPTH - 1;
+               rd_ptr             <= C_RD_DEPTH - 1;
+               num_read_words_q   <= 0;
+               num_write_words_q  <= 0;
+
+               /******Initialize Write Domain Signals***********************************/
+               ideal_wr_ack       <= 0;
+               ideal_full         <= 0; //'0'
+               ideal_almost_full  <= 0; //'0'
+
+               /******Initialize Read Domain Signals************************************/
+               //Reset DOUT of Sync DRAM. Sync BRAM DOUT was reset in the above always block.
+	       if (C_MEMORY_TYPE == 2) begin  
+                  ideal_dout      <= dout_reset_val;
+               end
+               ideal_valid        <= 1'b0;
+               ideal_empty        <= 1'b1;
+               ideal_almost_empty <= 1'b1;
+            end
+
+         end else begin  //normal operating conditions
+         /**********************************************************************/
+         // Synchronous FIFO Condition #1 : Writing and not reading
+         /**********************************************************************/
+         if (WR_EN & ~RD_EN) begin
+
+            /*********************************/
+            //If the FIFO is full, do NOT perform the write,
+            // update flags accordingly
+            /*********************************/
+            if (num_write_words >= C_FIFO_WR_DEPTH) begin
+               ideal_wr_ack       <= 0;
+
+               //still full
+               ideal_full         <= 1'b1;
+               ideal_almost_full  <= 1'b1;
+
+               //write unsuccessful - do not change contents
+
+               // no read attempted
+               ideal_valid        <= 1'b0;
+
+               //Not near empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+
+            /*********************************/
+            //If the FIFO is reporting FULL
+            // (Startup condition)
+            /*********************************/
+            end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin
+               ideal_wr_ack       <= 0;
+
+               //still full
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //write unsuccessful - do not change contents
+
+               // no read attempted
+               ideal_valid        <= 1'b0;
+
+               //FIFO EMPTY in this state can not be determined
+               //ideal_empty        <= 1'b0;
+               //ideal_almost_empty <= 1'b0;
+
+
+               /*********************************/
+               //If the FIFO is one from full
+               /*********************************/
+            end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
+               //good write
+               ideal_wr_ack       <= 1;
+
+               //FIFO is one from FULL and going FULL
+               ideal_full         <= 1'b1;
+               ideal_almost_full  <= 1'b1;
+
+               //Add input data
+               write_fifo;
+
+               // no read attempted
+               ideal_valid        <= 1'b0;
+
+               //Not near empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               num_bits           <= num_bits + C_DIN_WIDTH;
+
+               /*********************************/
+               //If the FIFO is 2 from full
+               /*********************************/
+            end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin
+               //good write
+               ideal_wr_ack       <= 1;
+
+               //2 from full, and writing, so set almost_full
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b1;
+
+               //Add input data
+               write_fifo;
+
+               //no read attempted
+               ideal_valid        <= 1'b0;
+
+               //Not near empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               num_bits           <= num_bits + C_DIN_WIDTH;
+
+               /*********************************/
+               //If the FIFO is ALMOST EMPTY
+               /*********************************/
+            end else if (num_read_words == 1) begin
+               //good write
+               ideal_wr_ack       <= 1;
+
+               //Not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Add input data
+               write_fifo;
+
+               // no read attempted
+               ideal_valid        <= 1'b0;
+
+               //Leaving ALMOST_EMPTY
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               num_bits           <= num_bits + C_DIN_WIDTH;
+
+               /*********************************/
+               //If the FIFO is EMPTY
+               /*********************************/
+            end else if (num_read_words == 0) begin
+               // good write
+               ideal_wr_ack       <= 1;
+
+               //Not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Add input data
+               write_fifo;
+
+               // no read attempted
+               ideal_valid        <= 1'b0;
+
+               //Leaving EMPTY (still ALMOST_EMPTY)
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b1;
+
+               num_bits           <= num_bits + C_DIN_WIDTH;
+
+               /*********************************/
+               //If the FIFO is not near EMPTY or FULL
+               /*********************************/
+            end else begin
+               // good write
+               ideal_wr_ack       <= 1;
+
+               //Not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Add input data
+               write_fifo;
+
+               // no read attempted
+               ideal_valid        <= 1'b0;
+
+               //Not near EMPTY
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               num_bits           <= num_bits + C_DIN_WIDTH;
+
+            end // average case
+
+
+            /**********************************************************************/
+            // Synchronous FIFO Condition #2 : Reading and not writing
+            /**********************************************************************/
+         end else if (~WR_EN & RD_EN) begin
+
+            /*********************************/
+            //If the FIFO is EMPTY
+            /*********************************/
+            if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin
+               //no write attemped
+               ideal_wr_ack       <= 0;
+
+               //FIFO is not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Read will fail
+               ideal_valid        <= 1'b0;
+
+               //FIFO is still empty
+               ideal_empty        <= 1'b1;
+               ideal_almost_empty <= 1'b1;
+
+               //No read
+
+               /*********************************/
+               //If the FIFO is ALMOST EMPTY
+               /*********************************/
+            end else if (num_read_words == 1) begin
+               //no write attempted
+               ideal_wr_ack       <= 0;
+
+               //FIFO is not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Read successful
+               ideal_valid        <= 1'b1;
+
+               //This read will make FIFO go empty
+               ideal_empty        <= 1'b1;
+               ideal_almost_empty <= 1'b1;
+
+               //Get the data from the FIFO
+               read_fifo;
+               num_bits           <= num_bits - C_DIN_WIDTH;
+
+
+               /*********************************/
+               //If the FIFO is 2 from EMPTY
+               /*********************************/
+            end else if (num_read_words == 2) begin
+
+               //no write attempted
+               ideal_wr_ack       <= 0;
+
+               //FIFO is not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Read successful
+               ideal_valid        <= 1'b1;
+
+               //FIFO is going ALMOST_EMPTY
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b1;
+
+               //Get the data from the FIFO
+               read_fifo;
+               num_bits           <= num_bits - C_DOUT_WIDTH;
+
+
+
+               /*********************************/
+               //If the FIFO is one from full
+               /*********************************/
+            end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
+
+               //no write attempted
+               ideal_wr_ack       <= 0;
+
+               //FIFO is leaving ALMOST FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Read successful
+               ideal_valid        <= 1'b1;
+
+               //Not near empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               //Read from the FIFO
+               read_fifo;
+               num_bits           <= num_bits - C_DOUT_WIDTH;
+
+
+               /*********************************/
+               // FIFO is FULL
+               /*********************************/
+            end else if (num_write_words >= C_FIFO_WR_DEPTH)
+              begin
+                 //no write attempted
+                 ideal_wr_ack       <= 0;
+
+                 //FIFO is leaving FULL, but is still ALMOST_FULL
+                 ideal_full         <= 1'b0;
+                 ideal_almost_full  <= 1'b1;
+
+                 //Read successful
+                 ideal_valid        <= 1'b1;
+
+                 //Not near empty
+                 ideal_empty        <= 1'b0;
+                 ideal_almost_empty <= 1'b0;
+
+                 //Read from the FIFO
+                 read_fifo;
+                 num_bits           <= num_bits - C_DOUT_WIDTH;
+
+                 /*********************************/
+                 //If the FIFO is not near EMPTY or FULL
+                 /*********************************/
+              end else begin
+                 //no write attemped
+                 ideal_wr_ack       <= 0;
+
+                 //Not near empty
+                 ideal_full         <= 1'b0;
+                 ideal_almost_full  <= 1'b0;
+
+                 //Read successful
+                 ideal_valid        <= 1'b1;
+
+                 //Not near empty
+                 ideal_empty        <= 1'b0;
+                 ideal_almost_empty <= 1'b0;
+
+                 //Read from the FIFO
+                 read_fifo;
+                 num_bits           <= num_bits - C_DOUT_WIDTH;
+
+
+              end // average read
+
+
+            /**********************************************************************/
+            // Synchronous FIFO Condition #3 : Reading and writing
+            /**********************************************************************/
+         end else if (WR_EN & RD_EN) begin
+
+            /*********************************/
+            // FIFO is FULL
+            /*********************************/
+            if (num_write_words >= C_FIFO_WR_DEPTH) begin
+
+               ideal_wr_ack       <= 0;
+
+               //Read will be successful, so FIFO will leave FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b1;
+
+               //Read successful
+               ideal_valid        <= 1'b1;
+
+               //Not near empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               //Read from the FIFO
+               read_fifo;
+               num_bits           <= num_bits - C_DOUT_WIDTH;
+
+
+            /*********************************/
+            // FIFO is reporting FULL, but it is empty
+            // (This is a special case, when coming out of RST
+            /*********************************/
+            end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin
+
+               ideal_wr_ack       <= 0;
+
+               //Read will be successful, so FIFO will leave FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //Read unsuccessful
+               ideal_valid        <= 1'b0;
+
+               //Report empty condition
+               ideal_empty        <= 1'b1;
+               ideal_almost_empty <= 1'b1;
+
+               //Do not read from empty FIFO
+               // Read from the FIFO
+
+
+               /*********************************/
+               //If the FIFO is one from full
+               /*********************************/
+            end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
+
+               //Write successful
+               ideal_wr_ack       <= 1;
+
+               //FIFO will remain ALMOST_FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b1;
+
+               // put the data into the FIFO
+               write_fifo;
+
+               //Read successful
+               ideal_valid        <= 1'b1;
+
+               //Not near empty
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               //Read from the FIFO
+               read_fifo;
+               num_bits           <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH;
+
+               /*********************************/
+               //If the FIFO is ALMOST EMPTY
+               /*********************************/
+            end else if (num_read_words == 1) begin
+
+               //Write successful
+               ideal_wr_ack       <= 1;
+
+               // Not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               // put the data into the FIFO
+               write_fifo;
+
+               //Read successful
+               ideal_valid        <= 1'b1;
+
+               //FIFO will stay ALMOST_EMPTY
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b1;
+
+               //Read from the FIFO
+               read_fifo;
+               num_bits           <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH;
+
+
+               /*********************************/
+               //If the FIFO is EMPTY
+               /*********************************/
+            end else if (num_read_words == 0) begin
+
+               //Write successful
+               ideal_wr_ack       <= 1;
+
+               // Not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               // put the data into the FIFO
+               write_fifo;
+
+               //Read will fail
+               ideal_valid        <= 1'b0;
+
+               //FIFO will leave EMPTY
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b1;
+
+               // No read
+               num_bits           <= num_bits + C_DIN_WIDTH;
+
+
+               /*********************************/
+               //If the FIFO is not near EMPTY or FULL
+               /*********************************/
+            end else begin
+
+               //Write successful
+               ideal_wr_ack       <= 1;
+
+               // Not near FULL
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               // put the data into the FIFO
+               write_fifo;
+
+               //Read successful
+               ideal_valid        <= 1'b1;
+
+               // Not near EMPTY
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               //Read from the FIFO
+               read_fifo;
+               num_bits           <= num_bits + C_DIN_WIDTH - C_DOUT_WIDTH;
+
+            end // average case
+
+            /**********************************************************************/
+            // Synchronous FIFO Condition #4 : Not reading or writing
+            /***
+             *******************************************************************/
+         end else begin
+
+            /*********************************/
+            // FIFO is FULL
+            /*********************************/
+            if (num_write_words >= C_FIFO_WR_DEPTH) begin
+
+               //No write
+               ideal_wr_ack       <= 0;
+               ideal_full         <= 1'b1;
+               ideal_almost_full  <= 1'b1;
+
+               //No read
+               ideal_valid        <= 1'b0;
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               //No change to memory
+
+               /*********************************/
+               //If the FIFO is one from full
+               /*********************************/
+            end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin
+
+               //No write
+               ideal_wr_ack       <= 0;
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b1;
+
+               //No read
+               ideal_valid        <= 1'b0;
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b0;
+
+               //No change to memory
+
+               /*********************************/
+               //If the FIFO is ALMOST EMPTY
+               /*********************************/
+            end else if (num_read_words == 1) begin
+               //No write
+               ideal_wr_ack       <= 0;
+               ideal_full         <= 1'b0;
+               ideal_almost_full  <= 1'b0;
+
+               //No read
+               ideal_valid        <= 1'b0;
+               ideal_empty        <= 1'b0;
+               ideal_almost_empty <= 1'b1;
+
+               //No change to memory
+
+            end // almost empty
+
+
+            /*********************************/
+            //If the FIFO is EMPTY
+            /*********************************/
+            else if (num_read_words == 0)
+              begin
+                 //No write
+                 ideal_wr_ack       <= 0;
+                 ideal_full         <= 1'b0;
+                 ideal_almost_full  <= 1'b0;
+
+                 //No read
+                 ideal_valid        <= 1'b0;
+                 ideal_empty        <= 1'b1;
+                 ideal_almost_empty <= 1'b1;
+
+                 //No change to memory
+
+                 /*********************************/
+                 //If the FIFO is not near EMPTY or FULL
+                 /*********************************/
+              end else begin
+
+                 //No write
+                 ideal_wr_ack       <= 0;
+                 ideal_full         <= 1'b0;
+                 ideal_almost_full  <= 1'b0;
+
+                 //No read
+                 ideal_valid        <= 1'b0;
+                 ideal_empty        <= 1'b0;
+                 ideal_almost_empty <= 1'b0;
+
+                 //No change to memory
+
+              end //    average case
+
+         end // neither reading or writing
+
+         num_read_words_q  <= num_read_words;
+         num_write_words_q <= num_write_words;
+        
+         end //normal operating conditions
+      end 
+
+   end // block: gen_fifo
+
+   //Generate overflow and underflow flags seperately
+   //because they don't support async rst
+   always @(posedge CLK) begin
+     ideal_overflow    <= WR_EN & ideal_full;
+     ideal_underflow    <= ideal_empty & RD_EN;
+   end
+   
+   always @(posedge CLK or posedge rst_i) begin : gen_fifo_p
+
+      /****** Reset fifo - Async Reset****************************************/
+      //The latency of de-assertion of the flags is reduced by 1 to be consistent with the core.
+      //if (rst_i || rst_q) begin //was in v3.1 
+      if (rst_i) begin //v3.2 
+         ideal_prog_full   <= C_FULL_FLAGS_RST_VAL;
+         ideal_prog_empty  <= 1'b1;
+         prog_full_d       <= C_FULL_FLAGS_RST_VAL;
+         prog_empty_d      <= 1'b1;
+
+      end else begin
+         if (srst_i) begin
+            //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT.
+            if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2) begin
+               ideal_prog_full   <= 1'b0;
+               ideal_prog_empty  <= 1'b1;
+               prog_full_d       <= 1'b0;
+               prog_empty_d      <= 1'b1;
+            end
+         end else begin 
+
+	        /*****************************************************************
+            * Programmable FULL flags
+            ****************************************************************/
+            //Single constant threshold
+            if (C_PROG_FULL_TYPE == 1) begin
+               if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1)
+                             && WR_EN && !RD_EN) begin
+                  prog_full_d <= 1'b1;
+               end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL)
+                    && RD_EN && !WR_EN) || (rst_q && !rst_i)) begin //v3.2
+	              prog_full_d <= 1'b0;
+               end
+
+            //Dual constant thresholds
+            end else if (C_PROG_FULL_TYPE == 2) begin
+               if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1)
+                   && WR_EN && !RD_EN) begin
+                  prog_full_d <= 1'b1;
+               end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL)
+                            && RD_EN && !WR_EN) begin
+                  prog_full_d <= 1'b0;
+               end
+
+            //Single input threshold
+            end else if (C_PROG_FULL_TYPE == 3) begin
+              if ((num_write_words == PROG_FULL_THRESH-1)
+                    && WR_EN && !RD_EN) begin
+                  prog_full_d <= 1'b1;
+              end else if ((num_write_words == PROG_FULL_THRESH)
+                    && !WR_EN && RD_EN) begin
+                   prog_full_d <= 1'b0;
+              end else if (num_write_words >= PROG_FULL_THRESH) begin
+                  prog_full_d <= 1'b1;
+              end else if (num_write_words < PROG_FULL_THRESH) begin
+                   prog_full_d <= 1'b0;
+              end
+
+            //Dual input thresholds
+            end else begin
+              if ((num_write_words == PROG_FULL_THRESH_ASSERT-1)
+                    && WR_EN && !RD_EN) begin
+                  prog_full_d <= 1'b1;
+              end else if ((num_write_words == PROG_FULL_THRESH_NEGATE)
+                    && !WR_EN && RD_EN)begin
+                  prog_full_d <= 1'b0;
+              end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin
+                  prog_full_d <= 1'b1;
+              end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin 
+                  prog_full_d <= 1'b0;
+               end
+            end
+
+            /*****************************************************************
+             * Programmable EMPTY flags
+             ****************************************************************/
+            //Single constant threshold
+            if (C_PROG_EMPTY_TYPE == 1) begin
+               if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1)
+                   && RD_EN && !WR_EN) begin
+                  prog_empty_d <= 1'b1;
+               end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL)
+                   && WR_EN && !RD_EN) begin
+                  prog_empty_d <= 1'b0;
+               end
+            //Dual constant thresholds
+            end else if (C_PROG_EMPTY_TYPE == 2) begin
+               if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1)
+                   && RD_EN && !WR_EN) begin
+                  prog_empty_d <= 1'b1;
+               end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL)
+                            && !RD_EN && WR_EN) begin
+                  prog_empty_d <= 1'b0;
+               end
+
+            //Single input threshold
+            end else if (C_PROG_EMPTY_TYPE == 3) begin
+               if ((num_read_words == PROG_EMPTY_THRESH+1)
+                             && RD_EN && !WR_EN) begin
+                  prog_empty_d <= 1'b1;
+               end else if ((num_read_words == PROG_EMPTY_THRESH)
+                             && !RD_EN && WR_EN) begin
+                  prog_empty_d <= 1'b0;
+               end else if (num_read_words <= PROG_EMPTY_THRESH) begin
+                  prog_empty_d <= 1'b1;
+               end else if (num_read_words > PROG_EMPTY_THRESH)begin
+                  prog_empty_d <= 1'b0;
+               end
+
+            //Dual input thresholds
+            end else begin
+               if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin 
+                  prog_empty_d <= 1'b1;
+               end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1)
+                   && RD_EN && !WR_EN) begin
+                  prog_empty_d <= 1'b1;
+               end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin
+                  prog_empty_d <= 1'b0;
+               end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE)
+                   && !RD_EN && WR_EN) begin
+                  prog_empty_d <= 1'b0;
+               end
+            end
+
+            ideal_prog_empty  <= prog_empty_d;
+            if (rst_q && !rst_i) begin
+              ideal_prog_full   <= 1'b0;
+            end else begin
+              ideal_prog_full   <= prog_full_d;
+            end
+
+         end //if (srst_i) begin
+      end //if (rst_i) begin
+   end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p
+endmodule // fifo_generator_v4_3_bhv_ver_ss
+
+
+module fifo_generator_v4_3_bhv_ver_preload0
+ (
+  RD_CLK,
+  RD_RST,
+  RD_EN,
+  FIFOEMPTY,
+  FIFODATA,
+  USERDATA,
+  USERVALID,
+  USERUNDERFLOW,
+  USEREMPTY,
+  USERALMOSTEMPTY,
+  RAMVALID,
+  FIFORDEN
+  );
+
+
+ parameter  C_DOUT_RST_VAL            = "";
+ parameter  C_DOUT_WIDTH              = 8;
+ parameter  C_HAS_RST                 = 0;
+ parameter  C_USERVALID_LOW           = 0;
+ parameter  C_USERUNDERFLOW_LOW       = 0;
+
+
+ input                     RD_CLK;
+ input                     RD_RST;
+ input                     RD_EN;
+ input                     FIFOEMPTY;
+ input  [C_DOUT_WIDTH-1:0] FIFODATA;
+ output [C_DOUT_WIDTH-1:0] USERDATA;
+ output                    USERVALID;
+ output                    USERUNDERFLOW;
+ output                    USEREMPTY;
+ output                    USERALMOSTEMPTY;
+ output                    RAMVALID;
+ output                    FIFORDEN;
+
+ wire                      RD_CLK;
+ wire                      RD_RST;
+ wire                      RD_EN;
+ wire                      FIFOEMPTY;
+ wire [C_DOUT_WIDTH-1:0]   FIFODATA;
+ reg [C_DOUT_WIDTH-1:0]    USERDATA;
+ wire                      USERVALID;
+ wire                      USERUNDERFLOW;
+ wire                      USEREMPTY;
+ wire                      USERALMOSTEMPTY;
+ wire                      RAMVALID;
+ wire                      FIFORDEN;
+
+ wire                      preloadstage1;
+ wire                      preloadstage2;
+ reg                       ram_valid_i;
+ reg                       read_data_valid_i;
+ wire                      ram_regout_en;
+ wire                      ram_rd_en;
+ reg                       empty_i        = 1'b1;
+ reg                       empty_q        = 1'b1;
+ reg                       rd_en_q        = 1'b0; //Fix for CR:236270 in v3.2 //prasanna
+ reg                       almost_empty_i = 1'b1;
+ reg                       almost_empty_q = 1'b1;
+ wire rd_rst_i;
+
+
+/*************************************************************************
+* FUNCTIONS
+*************************************************************************/
+
+   /*************************************************************************
+    * hexstr_conv
+    *   Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
+    ***********************************************************************/
+    function [C_DOUT_WIDTH-1:0] hexstr_conv;
+    input [(C_DOUT_WIDTH*8)-1:0] def_data;
+
+    integer index,i,j;
+    reg [3:0] bin;
+
+    begin
+      index = 0;
+      hexstr_conv = 'b0;
+      for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
+      begin
+        case (def_data[7:0])
+          8'b00000000 :
+          begin
+            bin = 4'b0000;
+            i = -1;
+          end
+          8'b00110000 : bin = 4'b0000;
+          8'b00110001 : bin = 4'b0001;
+          8'b00110010 : bin = 4'b0010;
+          8'b00110011 : bin = 4'b0011;
+          8'b00110100 : bin = 4'b0100;
+          8'b00110101 : bin = 4'b0101;
+          8'b00110110 : bin = 4'b0110;
+          8'b00110111 : bin = 4'b0111;
+          8'b00111000 : bin = 4'b1000;
+          8'b00111001 : bin = 4'b1001;
+          8'b01000001 : bin = 4'b1010;
+          8'b01000010 : bin = 4'b1011;
+          8'b01000011 : bin = 4'b1100;
+          8'b01000100 : bin = 4'b1101;
+          8'b01000101 : bin = 4'b1110;
+          8'b01000110 : bin = 4'b1111;
+          8'b01100001 : bin = 4'b1010;
+          8'b01100010 : bin = 4'b1011;
+          8'b01100011 : bin = 4'b1100;
+          8'b01100100 : bin = 4'b1101;
+          8'b01100101 : bin = 4'b1110;
+          8'b01100110 : bin = 4'b1111;
+          default :
+          begin
+            bin = 4'bx;
+          end
+        endcase
+        for( j=0; j<4; j=j+1)
+        begin
+          if ((index*4)+j < C_DOUT_WIDTH)
+          begin
+            hexstr_conv[(index*4)+j] = bin[j];
+          end
+        end
+        index = index + 1;
+        def_data = def_data >> 8;
+      end
+    end
+  endfunction
+
+initial
+ begin
+    ram_valid_i       = 1'b0;
+    read_data_valid_i = 1'b0;
+    USERDATA          = hexstr_conv(C_DOUT_RST_VAL);
+  end
+
+
+ //******************************************************************************
+ //  connect up optional reset
+ //******************************************************************************
+ assign rd_rst_i = C_HAS_RST ? RD_RST : 0;
+
+
+ //******************************************************************************
+ //  preloadstage2 indicates that stage2 needs to be updated. This is true
+ //  whenever read_data_valid is false, and RAM_valid is true.
+ //******************************************************************************
+ assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN);
+
+ //******************************************************************************
+ //  preloadstage1 indicates that stage1 needs to be updated. This is true
+ //  whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
+ //  false (indicating that Stage1 needs updating), or preloadstage2 is active
+ //  (indicating that Stage2 is going to update, so Stage1, therefore, must
+ //  also be updated to keep it valid.
+ //******************************************************************************
+ assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
+
+ //******************************************************************************
+ // Calculate RAM_REGOUT_EN
+ //  The output registers are controlled by the ram_regout_en signal.
+ //  These registers should be updated either when the output in Stage2 is
+ //  invalid (preloadstage2), OR when the user is reading, in which case the
+ //  Stage2 value will go invalid unless it is replenished.
+ //******************************************************************************
+ assign ram_regout_en = preloadstage2;
+
+ //******************************************************************************
+ // Calculate RAM_RD_EN
+ //   RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
+ //  update the value in Stage1.
+ //   One case when this happens is when preloadstage1=true, which indicates
+ //  that the data in Stage1 or Stage2 is invalid, and needs to automatically
+ //  be updated.
+ //   The other case is when the user is reading from the FIFO, which guarantees
+ //  that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is
+ //  replinished by data from the memory. So, as long as the RAM has data in it,
+ //  a read of the RAM should occur.
+ //******************************************************************************
+ assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
+
+ //******************************************************************************
+ // Calculate RAMVALID_P0_OUT
+ //   RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
+ //
+ //   If the RAM is being read from on this clock cycle (ram_rd_en=1), then
+ //   RAMVALID_P0_OUT is certainly going to be true.
+ //   If the RAM is not being read from, but the output registers are being
+ //   updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
+ //   therefore causing RAMVALID_P0_OUT to be false.
+ //   Otherwise, RAMVALID_P0_OUT will remain unchanged.
+ //******************************************************************************
+ always @ (posedge RD_CLK or posedge rd_rst_i)
+  begin  // PROCESS regout_valid
+    if (rd_rst_i)                // asynchronous reset (active high)
+      ram_valid_i     <= 1'b0;
+    else
+    begin
+      if (ram_rd_en == 1'b1)
+        ram_valid_i   <= 1'b1;
+      else
+        if (ram_regout_en == 1'b1)
+          ram_valid_i <= 1'b0;
+        else
+          ram_valid_i <= ram_valid_i;
+    end //rd_rst_i
+  end //always
+
+ //******************************************************************************
+ // Calculate READ_DATA_VALID
+ //  READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
+ //  Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1,
+ //  such that the data in Stage1 is propogated into Stage2.
+ //******************************************************************************
+ always @ (posedge RD_CLK or posedge rd_rst_i)
+   begin
+    if (rd_rst_i)
+     read_data_valid_i <= 1'b0;
+    else
+     read_data_valid_i <= ram_valid_i | (read_data_valid_i & ~RD_EN);
+   end //always
+
+
+ //*****************************************************************************
+ // Calculate EMPTY
+ //  Defined as the inverse of READ_DATA_VALID
+ //
+ // Description:
+ //
+ //  If read_data_valid_i indicates that the output is not valid,
+ // and there is no valid data on the output of the ram to preload it
+ // with, then we will report empty.
+ //
+ //  If there is no valid data on the output of the ram and we are
+ // reading, then the FIFO will go empty.
+ //
+ //*****************************************************************************
+ always @ (posedge RD_CLK or posedge rd_rst_i)
+  begin
+   if (rd_rst_i)                // asynchronous reset (active high)
+   begin
+    empty_i <= 1'b1;
+    empty_q <= 1'b1;
+   end
+   else // rising clock edge
+    begin
+     empty_i <= (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
+     empty_q <= empty_i;
+    end
+  end //always
+
+  //Fix for CR:236270 //prasanna
+  //Register RD_EN from user to calculate USERUNDERFLOW.
+  always @ (posedge RD_CLK or posedge rd_rst_i)
+  begin
+   if (rd_rst_i)                // asynchronous reset (active high)
+   begin
+    rd_en_q <= 1'b0;
+   end
+   else // rising clock edge
+    begin
+     rd_en_q <= RD_EN;
+    end
+  end //always
+
+
+ //*****************************************************************************
+ // Calculate user_almost_empty
+ //  user_almost_empty is defined such that, unless more words are written
+ //  to the FIFO, the next read will cause the FIFO to go EMPTY.
+ //
+ //  In most cases, whenever the output registers are updated (due to a user
+ // read or a preload condition), then user_almost_empty will update to
+ // whatever RAM_EMPTY is.
+ //
+ //  The exception is when the output is valid, the user is not reading, and
+ // Stage1 is not empty. In this condition, Stage1 will be preloaded from the
+ // memory, so we need to make sure user_almost_empty deasserts properly under
+ // this condition.
+ //*****************************************************************************
+ always @ (posedge RD_CLK or posedge rd_rst_i)
+  begin
+   if (rd_rst_i)                // asynchronous reset (active high)
+   begin
+    almost_empty_i <= 1'b1;
+    almost_empty_q <= 1'b1;
+   end
+   else // rising clock edge
+    begin
+     if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN))
+      begin
+       almost_empty_i <= FIFOEMPTY;
+      end
+     almost_empty_q   <= empty_i;
+    end
+  end //always
+
+
+ assign USEREMPTY       = empty_i;
+ assign USERALMOSTEMPTY = almost_empty_i;
+ assign FIFORDEN        = ram_rd_en;
+ assign RAMVALID        = ram_valid_i;
+ assign USERVALID       = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i;
+ //assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & RD_EN) : empty_q & RD_EN; //Bug in v3.1 (CR:236270) 
+ assign USERUNDERFLOW   = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; //Fix for CR:236270 in v3.2 //prasanna 
+ 
+ always @ (posedge RD_CLK or posedge rd_rst_i)
+  begin
+    if (rd_rst_i)             // asynchronous reset (active high)
+      USERDATA   <= hexstr_conv(C_DOUT_RST_VAL);
+    else  // rising clock edge
+      if (ram_regout_en)
+        USERDATA <= FIFODATA;
+  end //always
+
+
+
+
+
+endmodule
diff --git a/fpga/usrp2/models/M24LC024B.v b/fpga/usrp2/models/M24LC024B.v
new file mode 100644
index 000000000..45e04b450
--- /dev/null
+++ b/fpga/usrp2/models/M24LC024B.v
@@ -0,0 +1,459 @@
+// Modified 11/14/07 to simulate the 24lc024, which responds to the address pins
+
+// *******************************************************************************************************
+// **                                                                           			**
+// **   M24LC024B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V)				**
+// **                                                                           			**
+// *******************************************************************************************************
+// **                                                                           			**
+// **                              COPYRIGHT (c) 2003 YOUNG ENGINEERING              			**
+// **                                      ALL RIGHTS RESERVED                         			**
+// **                                                                           			**
+// **   THIS PROGRAM IS CONFIDENTIAL AND  A  TRADE SECRET  OF  YOUNG  ENGINEERING.  THE RECEIPT OR	**
+// **	POSSESSION  OF THIS PROGRAM  DOES NOT  CONVEY  ANY  RIGHTS TO  REPRODUCE  OR  DISCLOSE ITS     	**
+// **	CONTENTS,  OR TO MANUFACTURE, USE, OR SELL  ANYTHING  THAT IT MAY DESCRIBE, IN WHOLE OR IN	**
+// **	PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING.    				**
+// **                                                                           			**
+// *******************************************************************************************************
+// **   Revision       : 1.1                                                    			**
+// **   Modified Date  : 07/19/2004                                             			**
+// **   Revision History:                                                       			**
+// **                                                                           			**
+// **   02/01/2003:  Initial design                                             			**
+// **   07/19/2004:  Fixed the timing checks and the open-drain modeling for SDA.			**
+// **                                                                           			**
+// *******************************************************************************************************
+// **                                       TABLE OF CONTENTS                          			**
+// *******************************************************************************************************
+// **---------------------------------------------------------------------------------------------------**
+// **   DECLARATIONS                                                          				**
+// **---------------------------------------------------------------------------------------------------**
+// **---------------------------------------------------------------------------------------------------**
+// **   INITIALIZATION                                              					**
+// **---------------------------------------------------------------------------------------------------**
+// **---------------------------------------------------------------------------------------------------**
+// **   CORE LOGIC                                                  					**
+// **---------------------------------------------------------------------------------------------------**
+// **   1.01:  START Bit Detection									**
+// **   1.02:  STOP Bit Detection									**
+// **   1.03:  Input Shift Register									**
+// **   1.04:  Input Bit Counter									**
+// **   1.05:  Control Byte Register									**
+// **   1.06:  Byte Address Register									**
+// **   1.07:  Write Data Buffer									**
+// **   1.08:  Acknowledge Generator									**
+// **   1.09:  Acknowledge Detect									**
+// **   1.10:  Write Cycle Timer									**
+// **   1.11:  Write Cycle Processor									**
+// **   1.12:  Read Data Multiplexor									**
+// **   1.13:  Read Data Processor									**
+// **   1.14:  SDA Data I/O Buffer									**
+// **                                                                           			**
+// **---------------------------------------------------------------------------------------------------**
+// **   DEBUG LOGIC                                                  					**
+// **---------------------------------------------------------------------------------------------------**
+// **   2.01:  Memory Data Bytes									**
+// **   2.02:  Write Data Buffer									**
+// **                                                                           			**
+// **---------------------------------------------------------------------------------------------------**
+// **   TIMING CHECKS                                                     				**
+// **---------------------------------------------------------------------------------------------------**
+// **                                                                           			**
+// *******************************************************************************************************
+
+
+`timescale 1ns/10ps
+
+module M24LC024B (A0, A1, A2, WP, SDA, SCL, RESET);
+
+   input 		A0;				// unconnected pin
+   input 		A1;				// unconnected pin
+   input 		A2;				// unconnected pin
+
+   input		WP;				// write protect pin
+
+   inout		SDA;				// serial data I/O
+   input		SCL;				// serial data clock
+
+   input		RESET;				// system reset
+
+
+// *******************************************************************************************************
+// **   DECLARATIONS                                                            			**
+// *******************************************************************************************************
+
+   reg			SDA_DO;				// serial data - output
+   reg			SDA_OE;				// serial data - output enable
+
+   wire			SDA_DriveEnable;		// serial data output enable
+   reg			SDA_DriveEnableDlyd;		// serial data output enable - delayed
+
+   reg	[03:00]		BitCounter;			// serial bit counter
+
+   reg			START_Rcvd;			// START bit received flag
+   reg			STOP_Rcvd;			// STOP bit received flag
+   reg			CTRL_Rcvd;			// control byte received flag
+   reg			ADDR_Rcvd;			// byte address received flag
+   reg			MACK_Rcvd;			// master acknowledge received flag
+
+   reg			WrCycle;			// memory write cycle
+   reg			RdCycle;			// memory read cycle
+
+   reg	[07:00]		ShiftRegister;			// input data shift register
+
+   reg  [07:00]		ControlByte;			// control byte register
+   wire			RdWrBit;			// read/write control bit
+
+   reg	[07:00]		StartAddress;			// memory access starting address
+   reg	[02:00]		PageAddress;			// memory page address
+
+   reg	[07:00]		WrDataByte [0:7];		// memory write data buffer
+   wire	[07:00]		RdDataByte;			// memory read data
+
+   reg	[15:00]		WrCounter;			// write buffer counter
+
+   reg	[02:00]		WrPointer;			// write buffer pointer
+   reg	[07:00]		RdPointer;			// read address pointer
+
+   reg			WriteActive;			// memory write cycle active
+
+   reg	[07:00]		MemoryBlock [0:255];		// EEPROM data memory array
+
+   integer		LoopIndex;			// iterative loop index
+
+   integer 		tAA;				// timing parameter
+   integer 		tWC;				// timing parameter
+
+
+// *******************************************************************************************************
+// **   INITIALIZATION                                                         				**
+// *******************************************************************************************************
+
+   initial tAA = 900;					// SCL to SDA output delay
+   initial tWC = 5000000;				// memory write cycle time
+   //initial tWC = 50000;				// shortened memory write cycle time to speed up sims
+
+   initial begin
+      SDA_DO = 0;
+      SDA_OE = 0;
+   end
+
+   initial begin
+      START_Rcvd = 0;
+      STOP_Rcvd  = 0;
+      CTRL_Rcvd  = 0;
+      ADDR_Rcvd  = 0;
+      MACK_Rcvd  = 0;
+   end
+
+   initial begin
+      BitCounter  = 0;
+      ControlByte = 0;
+   end
+
+   initial begin
+      WrCycle = 0;
+      RdCycle = 0;
+
+      WriteActive = 0;
+   end
+
+
+// *******************************************************************************************************
+// **   CORE LOGIC                                                    					**
+// *******************************************************************************************************
+// -------------------------------------------------------------------------------------------------------
+//      1.01:  START Bit Detection
+// -------------------------------------------------------------------------------------------------------
+
+   always @(negedge SDA) begin
+      if (SCL == 1) begin
+         START_Rcvd <= 1;
+         STOP_Rcvd  <= 0;
+         CTRL_Rcvd  <= 0;
+         ADDR_Rcvd  <= 0;
+         MACK_Rcvd  <= 0;
+
+         WrCycle <= #1 0;
+         RdCycle <= #1 0;
+
+         BitCounter <= 0;
+      end
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.02:  STOP Bit Detection
+// -------------------------------------------------------------------------------------------------------
+
+   always @(posedge SDA) begin
+      if (SCL == 1) begin
+         START_Rcvd <= 0;
+         STOP_Rcvd  <= 1;
+         CTRL_Rcvd  <= 0;
+         ADDR_Rcvd  <= 0;
+         MACK_Rcvd  <= 0;
+
+         WrCycle <= #1 0;
+         RdCycle <= #1 0;
+
+         BitCounter <= 10;
+      end
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.03:  Input Shift Register
+// -------------------------------------------------------------------------------------------------------
+
+   always @(posedge SCL) begin
+      ShiftRegister[00] <= SDA;
+      ShiftRegister[01] <= ShiftRegister[00];
+      ShiftRegister[02] <= ShiftRegister[01];
+      ShiftRegister[03] <= ShiftRegister[02];
+      ShiftRegister[04] <= ShiftRegister[03];
+      ShiftRegister[05] <= ShiftRegister[04];
+      ShiftRegister[06] <= ShiftRegister[05];
+      ShiftRegister[07] <= ShiftRegister[06];
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.04:  Input Bit Counter
+// -------------------------------------------------------------------------------------------------------
+
+   always @(posedge SCL) begin
+      if (BitCounter < 10) BitCounter <= BitCounter + 1;
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.05:  Control Byte Register
+// -------------------------------------------------------------------------------------------------------
+
+   always @(negedge SCL) begin
+      if (START_Rcvd & (BitCounter == 8)) begin
+         if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)
+	     & (ShiftRegister[3:1] == {A2,A1,A0})) begin
+            if (ShiftRegister[00] == 0) WrCycle <= 1;
+            if (ShiftRegister[00] == 1) RdCycle <= 1;
+
+            ControlByte <= ShiftRegister[07:00];
+
+            CTRL_Rcvd <= 1;
+         end
+
+         START_Rcvd <= 0;
+      end
+   end
+
+   assign RdWrBit     = ControlByte[00];
+
+// -------------------------------------------------------------------------------------------------------
+//      1.06:  Byte Address Register
+// -------------------------------------------------------------------------------------------------------
+
+   always @(negedge SCL) begin
+      if (CTRL_Rcvd & (BitCounter == 8)) begin
+         if (RdWrBit == 0) begin
+            StartAddress <= ShiftRegister[07:00];
+            RdPointer    <= ShiftRegister[07:00];
+
+            ADDR_Rcvd <= 1;
+         end
+
+         WrCounter <= 0;
+         WrPointer <= 0;
+
+         CTRL_Rcvd <= 0;
+      end
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.07:  Write Data Buffer
+// -------------------------------------------------------------------------------------------------------
+
+   always @(negedge SCL) begin
+      if (ADDR_Rcvd & (BitCounter == 8)) begin
+         if ((WP == 0) & (RdWrBit == 0)) begin
+            WrDataByte[WrPointer] <= ShiftRegister[07:00];
+
+            WrCounter <= WrCounter + 1;
+            WrPointer <= WrPointer + 1;
+         end
+      end
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.08:  Acknowledge Generator
+// -------------------------------------------------------------------------------------------------------
+
+   always @(negedge SCL) begin
+      if (!WriteActive) begin
+         if (BitCounter == 8) begin
+            if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin
+               SDA_DO <= 0;
+               SDA_OE <= 1;
+            end 
+         end
+         if (BitCounter == 9) begin
+            BitCounter <= 0;
+
+            if (!RdCycle) begin
+               SDA_DO <= 0;
+               SDA_OE <= 0;
+            end
+         end
+      end
+   end 
+
+// -------------------------------------------------------------------------------------------------------
+//      1.09:  Acknowledge Detect
+// -------------------------------------------------------------------------------------------------------
+
+   always @(posedge SCL) begin
+      if (RdCycle & (BitCounter == 8)) begin
+         if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1;
+      end
+   end
+
+   always @(negedge SCL) MACK_Rcvd <= 0;
+
+// -------------------------------------------------------------------------------------------------------
+//      1.10:  Write Cycle Timer
+// -------------------------------------------------------------------------------------------------------
+
+   always @(posedge STOP_Rcvd) begin
+      if (WrCycle & (WP == 0) & (WrCounter > 0)) begin
+         WriteActive = 1;
+         #(tWC);
+         WriteActive = 0;
+      end
+   end
+
+   always @(posedge STOP_Rcvd) begin
+      #(1.0);
+      STOP_Rcvd = 0;
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.11:  Write Cycle Processor
+// -------------------------------------------------------------------------------------------------------
+
+   always @(posedge WriteActive) begin
+      for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin
+         PageAddress = StartAddress[02:00] + LoopIndex;
+
+         MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]];
+      end
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.12:  Read Data Multiplexor
+// -------------------------------------------------------------------------------------------------------
+
+   always @(negedge SCL) begin
+      if (BitCounter == 8) begin
+         if (WrCycle & ADDR_Rcvd) begin
+            RdPointer <= StartAddress + WrPointer + 1;
+         end
+         if (RdCycle) begin
+            RdPointer <= RdPointer + 1;
+         end
+      end
+   end
+
+   assign RdDataByte = MemoryBlock[RdPointer[07:00]];
+
+// -------------------------------------------------------------------------------------------------------
+//      1.13:  Read Data Processor
+// -------------------------------------------------------------------------------------------------------
+
+   always @(negedge SCL) begin
+      if (RdCycle) begin
+         if (BitCounter == 8) begin
+            SDA_DO <= 0;
+            SDA_OE <= 0;
+         end
+         else if (BitCounter == 9) begin
+            SDA_DO <= RdDataByte[07];
+
+            if (MACK_Rcvd) SDA_OE <= 1;
+         end
+         else begin
+            SDA_DO <= RdDataByte[7-BitCounter];
+         end
+      end
+   end
+
+// -------------------------------------------------------------------------------------------------------
+//      1.14:  SDA Data I/O Buffer
+// -------------------------------------------------------------------------------------------------------
+
+   bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd);
+
+   assign SDA_DriveEnable = !SDA_DO & SDA_OE;
+   always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable;
+
+
+// *******************************************************************************************************
+// **   DEBUG LOGIC                                                           				**
+// *******************************************************************************************************
+// -------------------------------------------------------------------------------------------------------
+//      2.01:  Memory Data Bytes
+// -------------------------------------------------------------------------------------------------------
+
+   wire [07:00]	MemoryByte00 = MemoryBlock[00];
+   wire [07:00]	MemoryByte01 = MemoryBlock[01];
+   wire [07:00]	MemoryByte02 = MemoryBlock[02];
+   wire [07:00]	MemoryByte03 = MemoryBlock[03];
+   wire [07:00]	MemoryByte04 = MemoryBlock[04];
+   wire [07:00]	MemoryByte05 = MemoryBlock[05];
+   wire [07:00]	MemoryByte06 = MemoryBlock[06];
+   wire [07:00]	MemoryByte07 = MemoryBlock[07];
+
+   wire [07:00]	MemoryByte08 = MemoryBlock[08];
+   wire [07:00]	MemoryByte09 = MemoryBlock[09];
+   wire [07:00]	MemoryByte0A = MemoryBlock[10];
+   wire [07:00]	MemoryByte0B = MemoryBlock[11];
+   wire [07:00]	MemoryByte0C = MemoryBlock[12];
+   wire [07:00]	MemoryByte0D = MemoryBlock[13];
+   wire [07:00]	MemoryByte0E = MemoryBlock[14];
+   wire [07:00]	MemoryByte0F = MemoryBlock[15];
+
+// -------------------------------------------------------------------------------------------------------
+//      2.02:  Write Data Buffer
+// -------------------------------------------------------------------------------------------------------
+
+   wire [07:00]	WriteData_0 = WrDataByte[00];
+   wire [07:00]	WriteData_1 = WrDataByte[01];
+   wire [07:00]	WriteData_2 = WrDataByte[02];
+   wire [07:00]	WriteData_3 = WrDataByte[03];
+   wire [07:00]	WriteData_4 = WrDataByte[04];
+   wire [07:00]	WriteData_5 = WrDataByte[05];
+   wire [07:00]	WriteData_6 = WrDataByte[06];
+   wire [07:00]	WriteData_7 = WrDataByte[07];
+
+
+// *******************************************************************************************************
+// **   TIMING CHECKS                                                           			**
+// *******************************************************************************************************
+
+   wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0);
+
+   specify
+      specparam
+         tHI = 600,					// SCL pulse width - high
+         tLO = 1300,					// SCL pulse width - low
+         tSU_STA = 600,					// SCL to SDA setup time
+         tHD_STA = 600,					// SCL to SDA hold time
+         tSU_DAT = 100,					// SDA to SCL setup time
+         tSU_STO = 600;					// SCL to SDA setup time
+
+      $width (posedge SCL, tHI);
+      $width (negedge SCL, tLO);
+
+      $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA);
+      $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT);
+      $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO);
+
+      $hold  (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA);
+   endspecify
+
+endmodule
diff --git a/fpga/usrp2/models/M24LC02B.v b/fpga/usrp2/models/M24LC02B.v
new file mode 100644
index 000000000..4d9e2c6e2
--- /dev/null
+++ b/fpga/usrp2/models/M24LC02B.v
@@ -0,0 +1,455 @@
+// *******************************************************************************************************

+// **                                                                           			**

+// **   M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V)				**

+// **                                                                           			**

+// *******************************************************************************************************

+// **                                                                           			**

+// **                              COPYRIGHT (c) 2003 YOUNG ENGINEERING              			**

+// **                                      ALL RIGHTS RESERVED                         			**

+// **                                                                           			**

+// **   THIS PROGRAM IS CONFIDENTIAL AND  A  TRADE SECRET  OF  YOUNG  ENGINEERING.  THE RECEIPT OR	**

+// **	POSSESSION  OF THIS PROGRAM  DOES NOT  CONVEY  ANY  RIGHTS TO  REPRODUCE  OR  DISCLOSE ITS     	**

+// **	CONTENTS,  OR TO MANUFACTURE, USE, OR SELL  ANYTHING  THAT IT MAY DESCRIBE, IN WHOLE OR IN	**

+// **	PART, WITHOUT THE SPECIFIC WRITTEN CONSENT OF YOUNG ENGINEERING.    				**

+// **                                                                           			**

+// *******************************************************************************************************

+// **   Revision       : 1.1                                                    			**

+// **   Modified Date  : 07/19/2004                                             			**

+// **   Revision History:                                                       			**

+// **                                                                           			**

+// **   02/01/2003:  Initial design                                             			**

+// **   07/19/2004:  Fixed the timing checks and the open-drain modeling for SDA.			**

+// **                                                                           			**

+// *******************************************************************************************************

+// **                                       TABLE OF CONTENTS                          			**

+// *******************************************************************************************************

+// **---------------------------------------------------------------------------------------------------**

+// **   DECLARATIONS                                                          				**

+// **---------------------------------------------------------------------------------------------------**

+// **---------------------------------------------------------------------------------------------------**

+// **   INITIALIZATION                                              					**

+// **---------------------------------------------------------------------------------------------------**

+// **---------------------------------------------------------------------------------------------------**

+// **   CORE LOGIC                                                  					**

+// **---------------------------------------------------------------------------------------------------**

+// **   1.01:  START Bit Detection									**

+// **   1.02:  STOP Bit Detection									**

+// **   1.03:  Input Shift Register									**

+// **   1.04:  Input Bit Counter									**

+// **   1.05:  Control Byte Register									**

+// **   1.06:  Byte Address Register									**

+// **   1.07:  Write Data Buffer									**

+// **   1.08:  Acknowledge Generator									**

+// **   1.09:  Acknowledge Detect									**

+// **   1.10:  Write Cycle Timer									**

+// **   1.11:  Write Cycle Processor									**

+// **   1.12:  Read Data Multiplexor									**

+// **   1.13:  Read Data Processor									**

+// **   1.14:  SDA Data I/O Buffer									**

+// **                                                                           			**

+// **---------------------------------------------------------------------------------------------------**

+// **   DEBUG LOGIC                                                  					**

+// **---------------------------------------------------------------------------------------------------**

+// **   2.01:  Memory Data Bytes									**

+// **   2.02:  Write Data Buffer									**

+// **                                                                           			**

+// **---------------------------------------------------------------------------------------------------**

+// **   TIMING CHECKS                                                     				**

+// **---------------------------------------------------------------------------------------------------**

+// **                                                                           			**

+// *******************************************************************************************************

+

+

+`timescale 1ns/10ps

+

+module M24LC02B (A0, A1, A2, WP, SDA, SCL, RESET);

+

+   input 		A0;				// unconnected pin

+   input 		A1;				// unconnected pin

+   input 		A2;				// unconnected pin

+

+   input		WP;				// write protect pin

+

+   inout		SDA;				// serial data I/O

+   input		SCL;				// serial data clock

+

+   input		RESET;				// system reset

+

+

+// *******************************************************************************************************

+// **   DECLARATIONS                                                            			**

+// *******************************************************************************************************

+

+   reg			SDA_DO;				// serial data - output

+   reg			SDA_OE;				// serial data - output enable

+

+   wire			SDA_DriveEnable;		// serial data output enable

+   reg			SDA_DriveEnableDlyd;		// serial data output enable - delayed

+

+   reg	[03:00]		BitCounter;			// serial bit counter

+

+   reg			START_Rcvd;			// START bit received flag

+   reg			STOP_Rcvd;			// STOP bit received flag

+   reg			CTRL_Rcvd;			// control byte received flag

+   reg			ADDR_Rcvd;			// byte address received flag

+   reg			MACK_Rcvd;			// master acknowledge received flag

+

+   reg			WrCycle;			// memory write cycle

+   reg			RdCycle;			// memory read cycle

+

+   reg	[07:00]		ShiftRegister;			// input data shift register

+

+   reg  [07:00]		ControlByte;			// control byte register

+   wire			RdWrBit;			// read/write control bit

+

+   reg	[07:00]		StartAddress;			// memory access starting address

+   reg	[02:00]		PageAddress;			// memory page address

+

+   reg	[07:00]		WrDataByte [0:7];		// memory write data buffer

+   wire	[07:00]		RdDataByte;			// memory read data

+

+   reg	[15:00]		WrCounter;			// write buffer counter

+

+   reg	[02:00]		WrPointer;			// write buffer pointer

+   reg	[07:00]		RdPointer;			// read address pointer

+

+   reg			WriteActive;			// memory write cycle active

+

+   reg	[07:00]		MemoryBlock [0:255];		// EEPROM data memory array

+

+   integer		LoopIndex;			// iterative loop index

+

+   integer 		tAA;				// timing parameter

+   integer 		tWC;				// timing parameter

+

+

+// *******************************************************************************************************

+// **   INITIALIZATION                                                         				**

+// *******************************************************************************************************

+

+   initial tAA = 900;					// SCL to SDA output delay

+   initial tWC = 5000000;				// memory write cycle time

+

+   initial begin

+      SDA_DO = 0;

+      SDA_OE = 0;

+   end

+

+   initial begin

+      START_Rcvd = 0;

+      STOP_Rcvd  = 0;

+      CTRL_Rcvd  = 0;

+      ADDR_Rcvd  = 0;

+      MACK_Rcvd  = 0;

+   end

+

+   initial begin

+      BitCounter  = 0;

+      ControlByte = 0;

+   end

+

+   initial begin

+      WrCycle = 0;

+      RdCycle = 0;

+

+      WriteActive = 0;

+   end

+

+

+// *******************************************************************************************************

+// **   CORE LOGIC                                                    					**

+// *******************************************************************************************************

+// -------------------------------------------------------------------------------------------------------

+//      1.01:  START Bit Detection

+// -------------------------------------------------------------------------------------------------------

+

+   always @(negedge SDA) begin

+      if (SCL == 1) begin

+         START_Rcvd <= 1;

+         STOP_Rcvd  <= 0;

+         CTRL_Rcvd  <= 0;

+         ADDR_Rcvd  <= 0;

+         MACK_Rcvd  <= 0;

+

+         WrCycle <= #1 0;

+         RdCycle <= #1 0;

+

+         BitCounter <= 0;

+      end

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.02:  STOP Bit Detection

+// -------------------------------------------------------------------------------------------------------

+

+   always @(posedge SDA) begin

+      if (SCL == 1) begin

+         START_Rcvd <= 0;

+         STOP_Rcvd  <= 1;

+         CTRL_Rcvd  <= 0;

+         ADDR_Rcvd  <= 0;

+         MACK_Rcvd  <= 0;

+

+         WrCycle <= #1 0;

+         RdCycle <= #1 0;

+

+         BitCounter <= 10;

+      end

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.03:  Input Shift Register

+// -------------------------------------------------------------------------------------------------------

+

+   always @(posedge SCL) begin

+      ShiftRegister[00] <= SDA;

+      ShiftRegister[01] <= ShiftRegister[00];

+      ShiftRegister[02] <= ShiftRegister[01];

+      ShiftRegister[03] <= ShiftRegister[02];

+      ShiftRegister[04] <= ShiftRegister[03];

+      ShiftRegister[05] <= ShiftRegister[04];

+      ShiftRegister[06] <= ShiftRegister[05];

+      ShiftRegister[07] <= ShiftRegister[06];

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.04:  Input Bit Counter

+// -------------------------------------------------------------------------------------------------------

+

+   always @(posedge SCL) begin

+      if (BitCounter < 10) BitCounter <= BitCounter + 1;

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.05:  Control Byte Register

+// -------------------------------------------------------------------------------------------------------

+

+   always @(negedge SCL) begin

+      if (START_Rcvd & (BitCounter == 8)) begin

+         if (!WriteActive & (ShiftRegister[07:04] == 4'b1010)) begin

+            if (ShiftRegister[00] == 0) WrCycle <= 1;

+            if (ShiftRegister[00] == 1) RdCycle <= 1;

+

+            ControlByte <= ShiftRegister[07:00];

+

+            CTRL_Rcvd <= 1;

+         end

+

+         START_Rcvd <= 0;

+      end

+   end

+

+   assign RdWrBit     = ControlByte[00];

+

+// -------------------------------------------------------------------------------------------------------

+//      1.06:  Byte Address Register

+// -------------------------------------------------------------------------------------------------------

+

+   always @(negedge SCL) begin

+      if (CTRL_Rcvd & (BitCounter == 8)) begin

+         if (RdWrBit == 0) begin

+            StartAddress <= ShiftRegister[07:00];

+            RdPointer    <= ShiftRegister[07:00];

+

+            ADDR_Rcvd <= 1;

+         end

+

+         WrCounter <= 0;

+         WrPointer <= 0;

+

+         CTRL_Rcvd <= 0;

+      end

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.07:  Write Data Buffer

+// -------------------------------------------------------------------------------------------------------

+

+   always @(negedge SCL) begin

+      if (ADDR_Rcvd & (BitCounter == 8)) begin

+         if ((WP == 0) & (RdWrBit == 0)) begin

+            WrDataByte[WrPointer] <= ShiftRegister[07:00];

+

+            WrCounter <= WrCounter + 1;

+            WrPointer <= WrPointer + 1;

+         end

+      end

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.08:  Acknowledge Generator

+// -------------------------------------------------------------------------------------------------------

+

+   always @(negedge SCL) begin

+      if (!WriteActive) begin

+         if (BitCounter == 8) begin

+            if (WrCycle | (START_Rcvd & (ShiftRegister[07:04] == 4'b1010))) begin

+               SDA_DO <= 0;

+               SDA_OE <= 1;

+            end 

+         end

+         if (BitCounter == 9) begin

+            BitCounter <= 0;

+

+            if (!RdCycle) begin

+               SDA_DO <= 0;

+               SDA_OE <= 0;

+            end

+         end

+      end

+   end 

+

+// -------------------------------------------------------------------------------------------------------

+//      1.09:  Acknowledge Detect

+// -------------------------------------------------------------------------------------------------------

+

+   always @(posedge SCL) begin

+      if (RdCycle & (BitCounter == 8)) begin

+         if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1;

+      end

+   end

+

+   always @(negedge SCL) MACK_Rcvd <= 0;

+

+// -------------------------------------------------------------------------------------------------------

+//      1.10:  Write Cycle Timer

+// -------------------------------------------------------------------------------------------------------

+

+   always @(posedge STOP_Rcvd) begin

+      if (WrCycle & (WP == 0) & (WrCounter > 0)) begin

+         WriteActive = 1;

+         #(tWC);

+         WriteActive = 0;

+      end

+   end

+

+   always @(posedge STOP_Rcvd) begin

+      #(1.0);

+      STOP_Rcvd = 0;

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.11:  Write Cycle Processor

+// -------------------------------------------------------------------------------------------------------

+

+   always @(posedge WriteActive) begin

+      for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin

+         PageAddress = StartAddress[02:00] + LoopIndex;

+

+         MemoryBlock[{StartAddress[07:03],PageAddress[02:00]}] = WrDataByte[LoopIndex[02:00]];

+      end

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.12:  Read Data Multiplexor

+// -------------------------------------------------------------------------------------------------------

+

+   always @(negedge SCL) begin

+      if (BitCounter == 8) begin

+         if (WrCycle & ADDR_Rcvd) begin

+            RdPointer <= StartAddress + WrPointer + 1;

+         end

+         if (RdCycle) begin

+            RdPointer <= RdPointer + 1;

+         end

+      end

+   end

+

+   assign RdDataByte = MemoryBlock[RdPointer[07:00]];

+

+// -------------------------------------------------------------------------------------------------------

+//      1.13:  Read Data Processor

+// -------------------------------------------------------------------------------------------------------

+

+   always @(negedge SCL) begin

+      if (RdCycle) begin

+         if (BitCounter == 8) begin

+            SDA_DO <= 0;

+            SDA_OE <= 0;

+         end

+         else if (BitCounter == 9) begin

+            SDA_DO <= RdDataByte[07];

+

+            if (MACK_Rcvd) SDA_OE <= 1;

+         end

+         else begin

+            SDA_DO <= RdDataByte[7-BitCounter];

+         end

+      end

+   end

+

+// -------------------------------------------------------------------------------------------------------

+//      1.14:  SDA Data I/O Buffer

+// -------------------------------------------------------------------------------------------------------

+

+   bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd);

+

+   assign SDA_DriveEnable = !SDA_DO & SDA_OE;

+   always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable;

+

+

+// *******************************************************************************************************

+// **   DEBUG LOGIC                                                           				**

+// *******************************************************************************************************

+// -------------------------------------------------------------------------------------------------------

+//      2.01:  Memory Data Bytes

+// -------------------------------------------------------------------------------------------------------

+

+   wire [07:00]	MemoryByte00 = MemoryBlock[00];

+   wire [07:00]	MemoryByte01 = MemoryBlock[01];

+   wire [07:00]	MemoryByte02 = MemoryBlock[02];

+   wire [07:00]	MemoryByte03 = MemoryBlock[03];

+   wire [07:00]	MemoryByte04 = MemoryBlock[04];

+   wire [07:00]	MemoryByte05 = MemoryBlock[05];

+   wire [07:00]	MemoryByte06 = MemoryBlock[06];

+   wire [07:00]	MemoryByte07 = MemoryBlock[07];

+

+   wire [07:00]	MemoryByte08 = MemoryBlock[08];

+   wire [07:00]	MemoryByte09 = MemoryBlock[09];

+   wire [07:00]	MemoryByte0A = MemoryBlock[10];

+   wire [07:00]	MemoryByte0B = MemoryBlock[11];

+   wire [07:00]	MemoryByte0C = MemoryBlock[12];

+   wire [07:00]	MemoryByte0D = MemoryBlock[13];

+   wire [07:00]	MemoryByte0E = MemoryBlock[14];

+   wire [07:00]	MemoryByte0F = MemoryBlock[15];

+

+// -------------------------------------------------------------------------------------------------------

+//      2.02:  Write Data Buffer

+// -------------------------------------------------------------------------------------------------------

+

+   wire [07:00]	WriteData_0 = WrDataByte[00];

+   wire [07:00]	WriteData_1 = WrDataByte[01];

+   wire [07:00]	WriteData_2 = WrDataByte[02];

+   wire [07:00]	WriteData_3 = WrDataByte[03];

+   wire [07:00]	WriteData_4 = WrDataByte[04];

+   wire [07:00]	WriteData_5 = WrDataByte[05];

+   wire [07:00]	WriteData_6 = WrDataByte[06];

+   wire [07:00]	WriteData_7 = WrDataByte[07];

+

+

+// *******************************************************************************************************

+// **   TIMING CHECKS                                                           			**

+// *******************************************************************************************************

+

+   wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0);

+

+   specify

+      specparam

+         tHI = 600,					// SCL pulse width - high

+         tLO = 1300,					// SCL pulse width - low

+         tSU_STA = 600,					// SCL to SDA setup time

+         tHD_STA = 600,					// SCL to SDA hold time

+         tSU_DAT = 100,					// SDA to SCL setup time

+         tSU_STO = 600;					// SCL to SDA setup time

+

+      $width (posedge SCL, tHI);

+      $width (negedge SCL, tLO);

+

+      $setup (SCL, negedge SDA &&& TimingCheckEnable, tSU_STA);

+      $setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT);

+      $setup (SCL, posedge SDA &&& TimingCheckEnable, tSU_STO);

+

+      $hold  (negedge SDA &&& TimingCheckEnable, SCL, tHD_STA);

+   endspecify

+

+endmodule

diff --git a/fpga/usrp2/models/MULT18X18S.v b/fpga/usrp2/models/MULT18X18S.v
new file mode 100644
index 000000000..5d39eeaa6
--- /dev/null
+++ b/fpga/usrp2/models/MULT18X18S.v
@@ -0,0 +1,20 @@
+
+// Model of the Xilinx mult18x18s for signed 18x18 bit multiplies,
+// As in the Spartan 3 series
+
+module MULT18X18S
+  (output reg signed [35:0] P,
+   input signed [17:0] A,
+   input signed [17:0] B,
+   input C,    // Clock
+   input CE,   // Clock Enable
+   input R     // Synchronous Reset
+   );
+   
+   always @(posedge C)
+     if(R)
+       P <= 36'sd0;
+     else if(CE)
+       P <= A * B;
+
+endmodule // MULT18X18S
diff --git a/fpga/usrp2/models/RAMB16_S36_S36.v b/fpga/usrp2/models/RAMB16_S36_S36.v
new file mode 100644
index 000000000..f1a92c7ce
--- /dev/null
+++ b/fpga/usrp2/models/RAMB16_S36_S36.v
@@ -0,0 +1,2194 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2005 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
+// /___/   /\     Filename : RAMB16_S36_S36.v
+// \   \  /  \    Timestamp : Thu Mar 10 16:43:36 PST 2005
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+// End Revision
+
+`ifdef legacy_model
+
+`timescale  1 ps / 1 ps
+
+module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
+
+    parameter INIT_A = 36'h0;
+    parameter INIT_B = 36'h0;
+    parameter SRVAL_A = 36'h0;
+    parameter SRVAL_B = 36'h0;
+    parameter WRITE_MODE_A = "WRITE_FIRST";
+    parameter WRITE_MODE_B = "WRITE_FIRST";
+    parameter SIM_COLLISION_CHECK = "ALL";
+    localparam SETUP_ALL = 1000;
+    localparam SETUP_READ_FIRST = 3000;
+
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+    output [31:0] DOA;
+    output [3:0] DOPA;
+    reg [31:0] doa_out;
+    reg [3:0] dopa_out;
+    wire doa_out0, doa_out1, doa_out2, doa_out3, doa_out4, doa_out5, doa_out6, doa_out7, doa_out8, doa_out9, doa_out10, doa_out11, doa_out12, doa_out13, doa_out14, doa_out15, doa_out16, doa_out17, doa_out18, doa_out19, doa_out20, doa_out21, doa_out22, doa_out23, doa_out24, doa_out25, doa_out26, doa_out27, doa_out28, doa_out29, doa_out30, doa_out31;
+    wire dopa0_out, dopa1_out, dopa2_out, dopa3_out;
+
+    input [8:0] ADDRA;
+    input [31:0] DIA;
+    input [3:0] DIPA;
+    input ENA, CLKA, WEA, SSRA;
+
+    output [31:0] DOB;
+    output [3:0] DOPB;
+    reg [31:0] dob_out;
+    reg [3:0] dopb_out;
+    wire dob_out0, dob_out1, dob_out2, dob_out3, dob_out4, dob_out5, dob_out6, dob_out7, dob_out8, dob_out9, dob_out10, dob_out11, dob_out12, dob_out13, dob_out14, dob_out15, dob_out16, dob_out17, dob_out18, dob_out19, dob_out20, dob_out21, dob_out22, dob_out23, dob_out24, dob_out25, dob_out26, dob_out27, dob_out28, dob_out29, dob_out30, dob_out31;
+    wire dopb0_out, dopb1_out, dopb2_out, dopb3_out;
+
+    input [8:0] ADDRB;
+    input [31:0] DIB;
+    input [3:0] DIPB;
+    input ENB, CLKB, WEB, SSRB;
+
+    reg [18431:0] mem;
+    reg [8:0] count;
+    reg [1:0] wr_mode_a, wr_mode_b;
+
+    reg [5:0] dmi, dbi;
+    reg [5:0] pmi, pbi;
+
+    wire [8:0] addra_int;
+    reg [8:0] addra_reg;
+    wire [31:0] dia_int;
+    wire [3:0] dipa_int;
+    wire ena_int, clka_int, wea_int, ssra_int;
+    reg ena_reg, wea_reg, ssra_reg;
+    wire [8:0] addrb_int;
+    reg [8:0] addrb_reg;
+    wire [31:0] dib_int;
+    wire [3:0] dipb_int;
+    wire enb_int, clkb_int, web_int, ssrb_int;
+    reg display_flag;
+    reg enb_reg, web_reg, ssrb_reg;
+
+    time time_clka, time_clkb;
+    time time_clka_clkb;
+    time time_clkb_clka;
+
+    reg setup_all_a_b;
+    reg setup_all_b_a;
+    reg setup_zero;
+    reg setup_rf_a_b;
+    reg setup_rf_b_a;
+    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
+    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
+    reg address_collision, address_collision_a_b, address_collision_b_a;
+    reg change_clka;
+    reg change_clkb;
+
+    wire [14:0] data_addra_int;
+    wire [14:0] data_addra_reg;
+    wire [14:0] data_addrb_int;
+    wire [14:0] data_addrb_reg;
+    wire [15:0] parity_addra_int;
+    wire [15:0] parity_addra_reg;
+    wire [15:0] parity_addrb_int;
+    wire [15:0] parity_addrb_reg;
+
+    tri0 GSR = glbl.GSR;
+
+    always @(GSR)
+	if (GSR) begin
+	    assign doa_out = INIT_A[31:0];
+	    assign dopa_out = INIT_A[35:32];
+	    assign dob_out = INIT_B[31:0];
+	    assign dopb_out = INIT_B[35:32];
+	end
+	else begin
+	    deassign doa_out;
+	    deassign dopa_out;
+	    deassign dob_out;
+	    deassign dopb_out;
+	end
+
+    buf b_doa_out0 (doa_out0, doa_out[0]);
+    buf b_doa_out1 (doa_out1, doa_out[1]);
+    buf b_doa_out2 (doa_out2, doa_out[2]);
+    buf b_doa_out3 (doa_out3, doa_out[3]);
+    buf b_doa_out4 (doa_out4, doa_out[4]);
+    buf b_doa_out5 (doa_out5, doa_out[5]);
+    buf b_doa_out6 (doa_out6, doa_out[6]);
+    buf b_doa_out7 (doa_out7, doa_out[7]);
+    buf b_doa_out8 (doa_out8, doa_out[8]);
+    buf b_doa_out9 (doa_out9, doa_out[9]);
+    buf b_doa_out10 (doa_out10, doa_out[10]);
+    buf b_doa_out11 (doa_out11, doa_out[11]);
+    buf b_doa_out12 (doa_out12, doa_out[12]);
+    buf b_doa_out13 (doa_out13, doa_out[13]);
+    buf b_doa_out14 (doa_out14, doa_out[14]);
+    buf b_doa_out15 (doa_out15, doa_out[15]);
+    buf b_doa_out16 (doa_out16, doa_out[16]);
+    buf b_doa_out17 (doa_out17, doa_out[17]);
+    buf b_doa_out18 (doa_out18, doa_out[18]);
+    buf b_doa_out19 (doa_out19, doa_out[19]);
+    buf b_doa_out20 (doa_out20, doa_out[20]);
+    buf b_doa_out21 (doa_out21, doa_out[21]);
+    buf b_doa_out22 (doa_out22, doa_out[22]);
+    buf b_doa_out23 (doa_out23, doa_out[23]);
+    buf b_doa_out24 (doa_out24, doa_out[24]);
+    buf b_doa_out25 (doa_out25, doa_out[25]);
+    buf b_doa_out26 (doa_out26, doa_out[26]);
+    buf b_doa_out27 (doa_out27, doa_out[27]);
+    buf b_doa_out28 (doa_out28, doa_out[28]);
+    buf b_doa_out29 (doa_out29, doa_out[29]);
+    buf b_doa_out30 (doa_out30, doa_out[30]);
+    buf b_doa_out31 (doa_out31, doa_out[31]);
+    buf b_dopa_out0 (dopa_out0, dopa_out[0]);
+    buf b_dopa_out1 (dopa_out1, dopa_out[1]);
+    buf b_dopa_out2 (dopa_out2, dopa_out[2]);
+    buf b_dopa_out3 (dopa_out3, dopa_out[3]);
+    buf b_dob_out0 (dob_out0, dob_out[0]);
+    buf b_dob_out1 (dob_out1, dob_out[1]);
+    buf b_dob_out2 (dob_out2, dob_out[2]);
+    buf b_dob_out3 (dob_out3, dob_out[3]);
+    buf b_dob_out4 (dob_out4, dob_out[4]);
+    buf b_dob_out5 (dob_out5, dob_out[5]);
+    buf b_dob_out6 (dob_out6, dob_out[6]);
+    buf b_dob_out7 (dob_out7, dob_out[7]);
+    buf b_dob_out8 (dob_out8, dob_out[8]);
+    buf b_dob_out9 (dob_out9, dob_out[9]);
+    buf b_dob_out10 (dob_out10, dob_out[10]);
+    buf b_dob_out11 (dob_out11, dob_out[11]);
+    buf b_dob_out12 (dob_out12, dob_out[12]);
+    buf b_dob_out13 (dob_out13, dob_out[13]);
+    buf b_dob_out14 (dob_out14, dob_out[14]);
+    buf b_dob_out15 (dob_out15, dob_out[15]);
+    buf b_dob_out16 (dob_out16, dob_out[16]);
+    buf b_dob_out17 (dob_out17, dob_out[17]);
+    buf b_dob_out18 (dob_out18, dob_out[18]);
+    buf b_dob_out19 (dob_out19, dob_out[19]);
+    buf b_dob_out20 (dob_out20, dob_out[20]);
+    buf b_dob_out21 (dob_out21, dob_out[21]);
+    buf b_dob_out22 (dob_out22, dob_out[22]);
+    buf b_dob_out23 (dob_out23, dob_out[23]);
+    buf b_dob_out24 (dob_out24, dob_out[24]);
+    buf b_dob_out25 (dob_out25, dob_out[25]);
+    buf b_dob_out26 (dob_out26, dob_out[26]);
+    buf b_dob_out27 (dob_out27, dob_out[27]);
+    buf b_dob_out28 (dob_out28, dob_out[28]);
+    buf b_dob_out29 (dob_out29, dob_out[29]);
+    buf b_dob_out30 (dob_out30, dob_out[30]);
+    buf b_dob_out31 (dob_out31, dob_out[31]);
+    buf b_dopb_out0 (dopb_out0, dopb_out[0]);
+    buf b_dopb_out1 (dopb_out1, dopb_out[1]);
+    buf b_dopb_out2 (dopb_out2, dopb_out[2]);
+    buf b_dopb_out3 (dopb_out3, dopb_out[3]);
+
+    buf b_doa0 (DOA[0], doa_out0);
+    buf b_doa1 (DOA[1], doa_out1);
+    buf b_doa2 (DOA[2], doa_out2);
+    buf b_doa3 (DOA[3], doa_out3);
+    buf b_doa4 (DOA[4], doa_out4);
+    buf b_doa5 (DOA[5], doa_out5);
+    buf b_doa6 (DOA[6], doa_out6);
+    buf b_doa7 (DOA[7], doa_out7);
+    buf b_doa8 (DOA[8], doa_out8);
+    buf b_doa9 (DOA[9], doa_out9);
+    buf b_doa10 (DOA[10], doa_out10);
+    buf b_doa11 (DOA[11], doa_out11);
+    buf b_doa12 (DOA[12], doa_out12);
+    buf b_doa13 (DOA[13], doa_out13);
+    buf b_doa14 (DOA[14], doa_out14);
+    buf b_doa15 (DOA[15], doa_out15);
+    buf b_doa16 (DOA[16], doa_out16);
+    buf b_doa17 (DOA[17], doa_out17);
+    buf b_doa18 (DOA[18], doa_out18);
+    buf b_doa19 (DOA[19], doa_out19);
+    buf b_doa20 (DOA[20], doa_out20);
+    buf b_doa21 (DOA[21], doa_out21);
+    buf b_doa22 (DOA[22], doa_out22);
+    buf b_doa23 (DOA[23], doa_out23);
+    buf b_doa24 (DOA[24], doa_out24);
+    buf b_doa25 (DOA[25], doa_out25);
+    buf b_doa26 (DOA[26], doa_out26);
+    buf b_doa27 (DOA[27], doa_out27);
+    buf b_doa28 (DOA[28], doa_out28);
+    buf b_doa29 (DOA[29], doa_out29);
+    buf b_doa30 (DOA[30], doa_out30);
+    buf b_doa31 (DOA[31], doa_out31);
+    buf b_dopa0 (DOPA[0], dopa_out0);
+    buf b_dopa1 (DOPA[1], dopa_out1);
+    buf b_dopa2 (DOPA[2], dopa_out2);
+    buf b_dopa3 (DOPA[3], dopa_out3);
+    buf b_dob0 (DOB[0], dob_out0);
+    buf b_dob1 (DOB[1], dob_out1);
+    buf b_dob2 (DOB[2], dob_out2);
+    buf b_dob3 (DOB[3], dob_out3);
+    buf b_dob4 (DOB[4], dob_out4);
+    buf b_dob5 (DOB[5], dob_out5);
+    buf b_dob6 (DOB[6], dob_out6);
+    buf b_dob7 (DOB[7], dob_out7);
+    buf b_dob8 (DOB[8], dob_out8);
+    buf b_dob9 (DOB[9], dob_out9);
+    buf b_dob10 (DOB[10], dob_out10);
+    buf b_dob11 (DOB[11], dob_out11);
+    buf b_dob12 (DOB[12], dob_out12);
+    buf b_dob13 (DOB[13], dob_out13);
+    buf b_dob14 (DOB[14], dob_out14);
+    buf b_dob15 (DOB[15], dob_out15);
+    buf b_dob16 (DOB[16], dob_out16);
+    buf b_dob17 (DOB[17], dob_out17);
+    buf b_dob18 (DOB[18], dob_out18);
+    buf b_dob19 (DOB[19], dob_out19);
+    buf b_dob20 (DOB[20], dob_out20);
+    buf b_dob21 (DOB[21], dob_out21);
+    buf b_dob22 (DOB[22], dob_out22);
+    buf b_dob23 (DOB[23], dob_out23);
+    buf b_dob24 (DOB[24], dob_out24);
+    buf b_dob25 (DOB[25], dob_out25);
+    buf b_dob26 (DOB[26], dob_out26);
+    buf b_dob27 (DOB[27], dob_out27);
+    buf b_dob28 (DOB[28], dob_out28);
+    buf b_dob29 (DOB[29], dob_out29);
+    buf b_dob30 (DOB[30], dob_out30);
+    buf b_dob31 (DOB[31], dob_out31);
+    buf b_dopb0 (DOPB[0], dopb_out0);
+    buf b_dopb1 (DOPB[1], dopb_out1);
+    buf b_dopb2 (DOPB[2], dopb_out2);
+    buf b_dopb3 (DOPB[3], dopb_out3);
+
+    buf b_addra_0 (addra_int[0], ADDRA[0]);
+    buf b_addra_1 (addra_int[1], ADDRA[1]);
+    buf b_addra_2 (addra_int[2], ADDRA[2]);
+    buf b_addra_3 (addra_int[3], ADDRA[3]);
+    buf b_addra_4 (addra_int[4], ADDRA[4]);
+    buf b_addra_5 (addra_int[5], ADDRA[5]);
+    buf b_addra_6 (addra_int[6], ADDRA[6]);
+    buf b_addra_7 (addra_int[7], ADDRA[7]);
+    buf b_addra_8 (addra_int[8], ADDRA[8]);
+    buf b_dia_0 (dia_int[0], DIA[0]);
+    buf b_dia_1 (dia_int[1], DIA[1]);
+    buf b_dia_2 (dia_int[2], DIA[2]);
+    buf b_dia_3 (dia_int[3], DIA[3]);
+    buf b_dia_4 (dia_int[4], DIA[4]);
+    buf b_dia_5 (dia_int[5], DIA[5]);
+    buf b_dia_6 (dia_int[6], DIA[6]);
+    buf b_dia_7 (dia_int[7], DIA[7]);
+    buf b_dia_8 (dia_int[8], DIA[8]);
+    buf b_dia_9 (dia_int[9], DIA[9]);
+    buf b_dia_10 (dia_int[10], DIA[10]);
+    buf b_dia_11 (dia_int[11], DIA[11]);
+    buf b_dia_12 (dia_int[12], DIA[12]);
+    buf b_dia_13 (dia_int[13], DIA[13]);
+    buf b_dia_14 (dia_int[14], DIA[14]);
+    buf b_dia_15 (dia_int[15], DIA[15]);
+    buf b_dia_16 (dia_int[16], DIA[16]);
+    buf b_dia_17 (dia_int[17], DIA[17]);
+    buf b_dia_18 (dia_int[18], DIA[18]);
+    buf b_dia_19 (dia_int[19], DIA[19]);
+    buf b_dia_20 (dia_int[20], DIA[20]);
+    buf b_dia_21 (dia_int[21], DIA[21]);
+    buf b_dia_22 (dia_int[22], DIA[22]);
+    buf b_dia_23 (dia_int[23], DIA[23]);
+    buf b_dia_24 (dia_int[24], DIA[24]);
+    buf b_dia_25 (dia_int[25], DIA[25]);
+    buf b_dia_26 (dia_int[26], DIA[26]);
+    buf b_dia_27 (dia_int[27], DIA[27]);
+    buf b_dia_28 (dia_int[28], DIA[28]);
+    buf b_dia_29 (dia_int[29], DIA[29]);
+    buf b_dia_30 (dia_int[30], DIA[30]);
+    buf b_dia_31 (dia_int[31], DIA[31]);
+    buf b_dipa_0 (dipa_int[0], DIPA[0]);
+    buf b_dipa_1 (dipa_int[1], DIPA[1]);
+    buf b_dipa_2 (dipa_int[2], DIPA[2]);
+    buf b_dipa_3 (dipa_int[3], DIPA[3]);
+    buf b_ena (ena_int, ENA);
+    buf b_clka (clka_int, CLKA);
+    buf b_ssra (ssra_int, SSRA);
+    buf b_wea (wea_int, WEA);
+    buf b_addrb_0 (addrb_int[0], ADDRB[0]);
+    buf b_addrb_1 (addrb_int[1], ADDRB[1]);
+    buf b_addrb_2 (addrb_int[2], ADDRB[2]);
+    buf b_addrb_3 (addrb_int[3], ADDRB[3]);
+    buf b_addrb_4 (addrb_int[4], ADDRB[4]);
+    buf b_addrb_5 (addrb_int[5], ADDRB[5]);
+    buf b_addrb_6 (addrb_int[6], ADDRB[6]);
+    buf b_addrb_7 (addrb_int[7], ADDRB[7]);
+    buf b_addrb_8 (addrb_int[8], ADDRB[8]);
+    buf b_dib_0 (dib_int[0], DIB[0]);
+    buf b_dib_1 (dib_int[1], DIB[1]);
+    buf b_dib_2 (dib_int[2], DIB[2]);
+    buf b_dib_3 (dib_int[3], DIB[3]);
+    buf b_dib_4 (dib_int[4], DIB[4]);
+    buf b_dib_5 (dib_int[5], DIB[5]);
+    buf b_dib_6 (dib_int[6], DIB[6]);
+    buf b_dib_7 (dib_int[7], DIB[7]);
+    buf b_dib_8 (dib_int[8], DIB[8]);
+    buf b_dib_9 (dib_int[9], DIB[9]);
+    buf b_dib_10 (dib_int[10], DIB[10]);
+    buf b_dib_11 (dib_int[11], DIB[11]);
+    buf b_dib_12 (dib_int[12], DIB[12]);
+    buf b_dib_13 (dib_int[13], DIB[13]);
+    buf b_dib_14 (dib_int[14], DIB[14]);
+    buf b_dib_15 (dib_int[15], DIB[15]);
+    buf b_dib_16 (dib_int[16], DIB[16]);
+    buf b_dib_17 (dib_int[17], DIB[17]);
+    buf b_dib_18 (dib_int[18], DIB[18]);
+    buf b_dib_19 (dib_int[19], DIB[19]);
+    buf b_dib_20 (dib_int[20], DIB[20]);
+    buf b_dib_21 (dib_int[21], DIB[21]);
+    buf b_dib_22 (dib_int[22], DIB[22]);
+    buf b_dib_23 (dib_int[23], DIB[23]);
+    buf b_dib_24 (dib_int[24], DIB[24]);
+    buf b_dib_25 (dib_int[25], DIB[25]);
+    buf b_dib_26 (dib_int[26], DIB[26]);
+    buf b_dib_27 (dib_int[27], DIB[27]);
+    buf b_dib_28 (dib_int[28], DIB[28]);
+    buf b_dib_29 (dib_int[29], DIB[29]);
+    buf b_dib_30 (dib_int[30], DIB[30]);
+    buf b_dib_31 (dib_int[31], DIB[31]);
+    buf b_dipb_0 (dipb_int[0], DIPB[0]);
+    buf b_dipb_1 (dipb_int[1], DIPB[1]);
+    buf b_dipb_2 (dipb_int[2], DIPB[2]);
+    buf b_dipb_3 (dipb_int[3], DIPB[3]);
+    buf b_enb (enb_int, ENB);
+    buf b_clkb (clkb_int, CLKB);
+    buf b_ssrb (ssrb_int, SSRB);
+    buf b_web (web_int, WEB);
+
+    initial begin
+	for (count = 0; count < 256; count = count + 1) begin
+	    mem[count]		  <= INIT_00[count];
+	    mem[256 * 1 + count]  <= INIT_01[count];
+	    mem[256 * 2 + count]  <= INIT_02[count];
+	    mem[256 * 3 + count]  <= INIT_03[count];
+	    mem[256 * 4 + count]  <= INIT_04[count];
+	    mem[256 * 5 + count]  <= INIT_05[count];
+	    mem[256 * 6 + count]  <= INIT_06[count];
+	    mem[256 * 7 + count]  <= INIT_07[count];
+	    mem[256 * 8 + count]  <= INIT_08[count];
+	    mem[256 * 9 + count]  <= INIT_09[count];
+	    mem[256 * 10 + count] <= INIT_0A[count];
+	    mem[256 * 11 + count] <= INIT_0B[count];
+	    mem[256 * 12 + count] <= INIT_0C[count];
+	    mem[256 * 13 + count] <= INIT_0D[count];
+	    mem[256 * 14 + count] <= INIT_0E[count];
+	    mem[256 * 15 + count] <= INIT_0F[count];
+	    mem[256 * 16 + count] <= INIT_10[count];
+	    mem[256 * 17 + count] <= INIT_11[count];
+	    mem[256 * 18 + count] <= INIT_12[count];
+	    mem[256 * 19 + count] <= INIT_13[count];
+	    mem[256 * 20 + count] <= INIT_14[count];
+	    mem[256 * 21 + count] <= INIT_15[count];
+	    mem[256 * 22 + count] <= INIT_16[count];
+	    mem[256 * 23 + count] <= INIT_17[count];
+	    mem[256 * 24 + count] <= INIT_18[count];
+	    mem[256 * 25 + count] <= INIT_19[count];
+	    mem[256 * 26 + count] <= INIT_1A[count];
+	    mem[256 * 27 + count] <= INIT_1B[count];
+	    mem[256 * 28 + count] <= INIT_1C[count];
+	    mem[256 * 29 + count] <= INIT_1D[count];
+	    mem[256 * 30 + count] <= INIT_1E[count];
+	    mem[256 * 31 + count] <= INIT_1F[count];
+	    mem[256 * 32 + count] <= INIT_20[count];
+	    mem[256 * 33 + count] <= INIT_21[count];
+	    mem[256 * 34 + count] <= INIT_22[count];
+	    mem[256 * 35 + count] <= INIT_23[count];
+	    mem[256 * 36 + count] <= INIT_24[count];
+	    mem[256 * 37 + count] <= INIT_25[count];
+	    mem[256 * 38 + count] <= INIT_26[count];
+	    mem[256 * 39 + count] <= INIT_27[count];
+	    mem[256 * 40 + count] <= INIT_28[count];
+	    mem[256 * 41 + count] <= INIT_29[count];
+	    mem[256 * 42 + count] <= INIT_2A[count];
+	    mem[256 * 43 + count] <= INIT_2B[count];
+	    mem[256 * 44 + count] <= INIT_2C[count];
+	    mem[256 * 45 + count] <= INIT_2D[count];
+	    mem[256 * 46 + count] <= INIT_2E[count];
+	    mem[256 * 47 + count] <= INIT_2F[count];
+	    mem[256 * 48 + count] <= INIT_30[count];
+	    mem[256 * 49 + count] <= INIT_31[count];
+	    mem[256 * 50 + count] <= INIT_32[count];
+	    mem[256 * 51 + count] <= INIT_33[count];
+	    mem[256 * 52 + count] <= INIT_34[count];
+	    mem[256 * 53 + count] <= INIT_35[count];
+	    mem[256 * 54 + count] <= INIT_36[count];
+	    mem[256 * 55 + count] <= INIT_37[count];
+	    mem[256 * 56 + count] <= INIT_38[count];
+	    mem[256 * 57 + count] <= INIT_39[count];
+	    mem[256 * 58 + count] <= INIT_3A[count];
+	    mem[256 * 59 + count] <= INIT_3B[count];
+	    mem[256 * 60 + count] <= INIT_3C[count];
+	    mem[256 * 61 + count] <= INIT_3D[count];
+	    mem[256 * 62 + count] <= INIT_3E[count];
+	    mem[256 * 63 + count] <= INIT_3F[count];
+	    mem[256 * 64 + count] <= INITP_00[count];
+	    mem[256 * 65 + count] <= INITP_01[count];
+	    mem[256 * 66 + count] <= INITP_02[count];
+	    mem[256 * 67 + count] <= INITP_03[count];
+	    mem[256 * 68 + count] <= INITP_04[count];
+	    mem[256 * 69 + count] <= INITP_05[count];
+	    mem[256 * 70 + count] <= INITP_06[count];
+	    mem[256 * 71 + count] <= INITP_07[count];
+	end
+	address_collision <= 0;
+	address_collision_a_b <= 0;
+	address_collision_b_a <= 0;
+	change_clka <= 0;
+	change_clkb <= 0;
+	data_collision <= 0;
+	data_collision_a_b <= 0;
+	data_collision_b_a <= 0;
+	memory_collision <= 0;
+	memory_collision_a_b <= 0;
+	memory_collision_b_a <= 0;
+	setup_all_a_b <= 0;
+	setup_all_b_a <= 0;
+	setup_zero <= 0;
+	setup_rf_a_b <= 0;
+	setup_rf_b_a <= 0;
+    end
+
+    assign data_addra_int = addra_int * 32;
+    assign data_addra_reg = addra_reg * 32;
+    assign data_addrb_int = addrb_int * 32;
+    assign data_addrb_reg = addrb_reg * 32;
+    assign parity_addra_int = 16384 + addra_int * 4;
+    assign parity_addra_reg = 16384 + addra_reg * 4;
+    assign parity_addrb_int = 16384 + addrb_int * 4;
+    assign parity_addrb_reg = 16384 + addrb_reg * 4;
+
+
+    initial begin
+
+	display_flag = 1;
+
+	case (SIM_COLLISION_CHECK)
+
+	    "NONE" : begin
+		         assign setup_all_a_b = 1'b0;
+	                 assign setup_all_b_a = 1'b0;
+	                 assign setup_zero = 1'b0;
+	                 assign setup_rf_a_b = 1'b0;
+	                 assign setup_rf_b_a = 1'b0;
+	                 assign display_flag = 0;
+	             end
+	    "WARNING_ONLY" : begin
+		                 assign data_collision = 2'b00;
+	                         assign data_collision_a_b = 2'b00;
+	                         assign data_collision_b_a = 2'b00;
+	                         assign memory_collision = 1'b0;
+	                         assign memory_collision_a_b = 1'b0;
+	                         assign memory_collision_b_a = 1'b0;
+	                     end
+	    "GENERATE_X_ONLY" : begin
+		                    assign display_flag = 0;
+	                        end
+	    "ALL" : ;
+	    default : begin
+		          $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
+		          $finish;
+	              end
+
+	endcase // case(SIM_COLLISION_CHECK)
+
+    end // initial begin
+
+
+    always @(posedge clka_int) begin
+	time_clka = $time;
+	#0 time_clkb_clka = time_clka - time_clkb;
+	change_clka = ~change_clka;
+    end
+
+    always @(posedge clkb_int) begin
+	time_clkb = $time;
+	#0 time_clka_clkb = time_clkb - time_clka;
+	change_clkb = ~change_clkb;
+    end
+
+    always @(change_clkb) begin
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
+	    setup_all_a_b = 1;
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
+	    setup_rf_a_b = 1;
+    end
+
+    always @(change_clka) begin
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
+	    setup_all_b_a = 1;
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
+	    setup_rf_b_a = 1;
+    end
+
+    always @(change_clkb or change_clka) begin
+	if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
+	    setup_zero = 1;
+    end
+
+    always @(posedge setup_zero) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_int[14:5] == data_addrb_int[14:5]))
+	    memory_collision <= 1;
+    end
+
+    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
+	if ((ena_reg == 1) && (wea_reg == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_reg[14:5] == data_addrb_int[14:5]))
+	    memory_collision_a_b <= 1;
+    end
+
+    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_reg == 1) && (web_reg == 1) &&
+	    (data_addra_int[14:5] == data_addrb_reg[14:5]))
+	    memory_collision_b_a <= 1;
+    end
+
+    always @(posedge setup_all_a_b) begin
+	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+		6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_a_b <= 0;
+    end
+
+
+    always @(posedge setup_all_b_a) begin
+	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+		6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_b_a <= 0;
+    end
+
+
+    always @(posedge setup_zero) begin
+	if (data_addra_int[14:5] == data_addrb_int[14:5]) begin
+	if ((ena_int == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_int})
+		6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_zero <= 0;
+    end
+
+    task display_ra_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
+    end
+    endtask
+
+    task display_wa_rb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
+    end
+    endtask
+
+    task display_wa_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
+    end
+    endtask
+
+
+    always @(posedge setup_rf_a_b) begin
+	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+//		6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_a_b <= 0;
+    end
+
+
+    always @(posedge setup_rf_b_a) begin
+	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+//		6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+//		6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_b_a <= 0;
+    end
+
+
+    always @(posedge clka_int) begin
+	addra_reg <= addra_int;
+	ena_reg <= ena_int;
+	ssra_reg <= ssra_int;
+	wea_reg <= wea_int;
+    end
+
+    always @(posedge clkb_int) begin
+	addrb_reg <= addrb_int;
+	enb_reg <= enb_int;
+	ssrb_reg <= ssrb_int;
+	web_reg <= web_int;
+    end
+
+    // Data
+    always @(posedge memory_collision) begin
+	for (dmi = 0; dmi < 32; dmi = dmi + 1) begin
+	    mem[data_addra_int + dmi] <= 1'bX;
+	end
+	memory_collision <= 0;
+    end
+
+    always @(posedge memory_collision_a_b) begin
+	for (dmi = 0; dmi < 32; dmi = dmi + 1) begin
+	    mem[data_addra_reg + dmi] <= 1'bX;
+	end
+	memory_collision_a_b <= 0;
+    end
+
+    always @(posedge memory_collision_b_a) begin
+	for (dmi = 0; dmi < 32; dmi = dmi + 1) begin
+	    mem[data_addra_int + dmi] <= 1'bX;
+	end
+	memory_collision_b_a <= 0;
+    end
+
+    always @(posedge data_collision[1]) begin
+	if (ssra_int == 0) begin
+	    doa_out <= 32'bX;
+	end
+	data_collision[1] <= 0;
+    end
+
+    always @(posedge data_collision[0]) begin
+	if (ssrb_int == 0) begin
+	    dob_out <= 32'bX;
+	end
+	data_collision[0] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[1]) begin
+	if (ssra_reg == 0) begin
+	    doa_out <= 32'bX;
+	end
+	data_collision_a_b[1] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[0]) begin
+	if (ssrb_int == 0) begin
+	    dob_out <= 32'bX;
+	end
+	data_collision_a_b[0] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[1]) begin
+	if (ssra_int == 0) begin
+	    doa_out <= 32'bX;
+	end
+	data_collision_b_a[1] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[0]) begin
+	if (ssrb_reg == 0) begin
+	dob_out <= 32'bX;
+	end
+	data_collision_b_a[0] <= 0;
+    end
+
+
+    // Parity
+    always @(posedge memory_collision) begin
+	for (pmi = 0; pmi < 4; pmi = pmi + 1) begin
+	    mem[parity_addra_int + pmi] <= 1'bX;
+	end
+    end
+
+    always @(posedge memory_collision_a_b) begin
+	for (pmi = 0; pmi < 4; pmi = pmi + 1) begin
+	    mem[parity_addra_reg + pmi] <= 1'bX;
+	end
+    end
+
+    always @(posedge memory_collision_b_a) begin
+	for (pmi = 0; pmi < 4; pmi = pmi + 1) begin
+	    mem[parity_addra_int + pmi] <= 1'bX;
+	end
+    end
+
+    always @(posedge data_collision[1]) begin
+	if (ssra_int == 0) begin
+	    dopa_out <= 4'bX;
+	end
+    end
+
+    always @(posedge data_collision[0]) begin
+	if (ssrb_int == 0) begin
+	    dopb_out <= 4'bX;
+	end
+    end
+
+    always @(posedge data_collision_a_b[1]) begin
+	if (ssra_reg == 0) begin
+	    dopa_out <= 4'bX;
+	end
+    end
+
+    always @(posedge data_collision_a_b[0]) begin
+	if (ssrb_int == 0) begin
+	dopb_out <= 4'bX;
+	end
+    end
+
+    always @(posedge data_collision_b_a[1]) begin
+	if (ssra_int == 0) begin
+	    dopa_out <= 4'bX;
+	end
+    end
+
+    always @(posedge data_collision_b_a[0]) begin
+	if (ssrb_reg == 0) begin
+	    dopb_out <= 4'bX;
+	end
+    end
+
+
+    initial begin
+	case (WRITE_MODE_A)
+	    "WRITE_FIRST" : wr_mode_a <= 2'b00;
+	    "READ_FIRST"  : wr_mode_a <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_a <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
+				$finish;
+			    end
+	endcase
+    end
+
+    initial begin
+	case (WRITE_MODE_B)
+	    "WRITE_FIRST" : wr_mode_b <= 2'b00;
+	    "READ_FIRST"  : wr_mode_b <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_b <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
+				$finish;
+			    end
+	endcase
+    end
+
+    // Port A
+    always @(posedge clka_int) begin
+	if (ena_int == 1'b1) begin
+	    if (ssra_int == 1'b1) begin
+		doa_out[0] <= SRVAL_A[0];
+		doa_out[1] <= SRVAL_A[1];
+		doa_out[2] <= SRVAL_A[2];
+		doa_out[3] <= SRVAL_A[3];
+		doa_out[4] <= SRVAL_A[4];
+		doa_out[5] <= SRVAL_A[5];
+		doa_out[6] <= SRVAL_A[6];
+		doa_out[7] <= SRVAL_A[7];
+		doa_out[8] <= SRVAL_A[8];
+		doa_out[9] <= SRVAL_A[9];
+		doa_out[10] <= SRVAL_A[10];
+		doa_out[11] <= SRVAL_A[11];
+		doa_out[12] <= SRVAL_A[12];
+		doa_out[13] <= SRVAL_A[13];
+		doa_out[14] <= SRVAL_A[14];
+		doa_out[15] <= SRVAL_A[15];
+		doa_out[16] <= SRVAL_A[16];
+		doa_out[17] <= SRVAL_A[17];
+		doa_out[18] <= SRVAL_A[18];
+		doa_out[19] <= SRVAL_A[19];
+		doa_out[20] <= SRVAL_A[20];
+		doa_out[21] <= SRVAL_A[21];
+		doa_out[22] <= SRVAL_A[22];
+		doa_out[23] <= SRVAL_A[23];
+		doa_out[24] <= SRVAL_A[24];
+		doa_out[25] <= SRVAL_A[25];
+		doa_out[26] <= SRVAL_A[26];
+		doa_out[27] <= SRVAL_A[27];
+		doa_out[28] <= SRVAL_A[28];
+		doa_out[29] <= SRVAL_A[29];
+		doa_out[30] <= SRVAL_A[30];
+		doa_out[31] <= SRVAL_A[31];
+		dopa_out[0] <= SRVAL_A[32];
+		dopa_out[1] <= SRVAL_A[33];
+		dopa_out[2] <= SRVAL_A[34];
+		dopa_out[3] <= SRVAL_A[35];
+	    end
+	    else begin
+		if (wea_int == 1'b1) begin
+		    if (wr_mode_a == 2'b00) begin
+			doa_out <= dia_int;
+			dopa_out <= dipa_int;
+		    end
+		    else if (wr_mode_a == 2'b01) begin
+			doa_out[0] <= mem[data_addra_int + 0];
+			doa_out[1] <= mem[data_addra_int + 1];
+			doa_out[2] <= mem[data_addra_int + 2];
+			doa_out[3] <= mem[data_addra_int + 3];
+			doa_out[4] <= mem[data_addra_int + 4];
+			doa_out[5] <= mem[data_addra_int + 5];
+			doa_out[6] <= mem[data_addra_int + 6];
+			doa_out[7] <= mem[data_addra_int + 7];
+			doa_out[8] <= mem[data_addra_int + 8];
+			doa_out[9] <= mem[data_addra_int + 9];
+			doa_out[10] <= mem[data_addra_int + 10];
+			doa_out[11] <= mem[data_addra_int + 11];
+			doa_out[12] <= mem[data_addra_int + 12];
+			doa_out[13] <= mem[data_addra_int + 13];
+			doa_out[14] <= mem[data_addra_int + 14];
+			doa_out[15] <= mem[data_addra_int + 15];
+			doa_out[16] <= mem[data_addra_int + 16];
+			doa_out[17] <= mem[data_addra_int + 17];
+			doa_out[18] <= mem[data_addra_int + 18];
+			doa_out[19] <= mem[data_addra_int + 19];
+			doa_out[20] <= mem[data_addra_int + 20];
+			doa_out[21] <= mem[data_addra_int + 21];
+			doa_out[22] <= mem[data_addra_int + 22];
+			doa_out[23] <= mem[data_addra_int + 23];
+			doa_out[24] <= mem[data_addra_int + 24];
+			doa_out[25] <= mem[data_addra_int + 25];
+			doa_out[26] <= mem[data_addra_int + 26];
+			doa_out[27] <= mem[data_addra_int + 27];
+			doa_out[28] <= mem[data_addra_int + 28];
+			doa_out[29] <= mem[data_addra_int + 29];
+			doa_out[30] <= mem[data_addra_int + 30];
+			doa_out[31] <= mem[data_addra_int + 31];
+			dopa_out[0] <= mem[parity_addra_int + 0];
+			dopa_out[1] <= mem[parity_addra_int + 1];
+			dopa_out[2] <= mem[parity_addra_int + 2];
+			dopa_out[3] <= mem[parity_addra_int + 3];
+		    end
+		end
+		else begin
+		    doa_out[0] <= mem[data_addra_int + 0];
+		    doa_out[1] <= mem[data_addra_int + 1];
+		    doa_out[2] <= mem[data_addra_int + 2];
+		    doa_out[3] <= mem[data_addra_int + 3];
+		    doa_out[4] <= mem[data_addra_int + 4];
+		    doa_out[5] <= mem[data_addra_int + 5];
+		    doa_out[6] <= mem[data_addra_int + 6];
+		    doa_out[7] <= mem[data_addra_int + 7];
+		    doa_out[8] <= mem[data_addra_int + 8];
+		    doa_out[9] <= mem[data_addra_int + 9];
+		    doa_out[10] <= mem[data_addra_int + 10];
+		    doa_out[11] <= mem[data_addra_int + 11];
+		    doa_out[12] <= mem[data_addra_int + 12];
+		    doa_out[13] <= mem[data_addra_int + 13];
+		    doa_out[14] <= mem[data_addra_int + 14];
+		    doa_out[15] <= mem[data_addra_int + 15];
+		    doa_out[16] <= mem[data_addra_int + 16];
+		    doa_out[17] <= mem[data_addra_int + 17];
+		    doa_out[18] <= mem[data_addra_int + 18];
+		    doa_out[19] <= mem[data_addra_int + 19];
+		    doa_out[20] <= mem[data_addra_int + 20];
+		    doa_out[21] <= mem[data_addra_int + 21];
+		    doa_out[22] <= mem[data_addra_int + 22];
+		    doa_out[23] <= mem[data_addra_int + 23];
+		    doa_out[24] <= mem[data_addra_int + 24];
+		    doa_out[25] <= mem[data_addra_int + 25];
+		    doa_out[26] <= mem[data_addra_int + 26];
+		    doa_out[27] <= mem[data_addra_int + 27];
+		    doa_out[28] <= mem[data_addra_int + 28];
+		    doa_out[29] <= mem[data_addra_int + 29];
+		    doa_out[30] <= mem[data_addra_int + 30];
+		    doa_out[31] <= mem[data_addra_int + 31];
+		    dopa_out[0] <= mem[parity_addra_int + 0];
+		    dopa_out[1] <= mem[parity_addra_int + 1];
+		    dopa_out[2] <= mem[parity_addra_int + 2];
+		    dopa_out[3] <= mem[parity_addra_int + 3];
+		end
+	    end
+	end
+    end
+
+    always @(posedge clka_int) begin
+	if (ena_int == 1'b1 && wea_int == 1'b1) begin
+	    mem[data_addra_int + 0] <= dia_int[0];
+	    mem[data_addra_int + 1] <= dia_int[1];
+	    mem[data_addra_int + 2] <= dia_int[2];
+	    mem[data_addra_int + 3] <= dia_int[3];
+	    mem[data_addra_int + 4] <= dia_int[4];
+	    mem[data_addra_int + 5] <= dia_int[5];
+	    mem[data_addra_int + 6] <= dia_int[6];
+	    mem[data_addra_int + 7] <= dia_int[7];
+	    mem[data_addra_int + 8] <= dia_int[8];
+	    mem[data_addra_int + 9] <= dia_int[9];
+	    mem[data_addra_int + 10] <= dia_int[10];
+	    mem[data_addra_int + 11] <= dia_int[11];
+	    mem[data_addra_int + 12] <= dia_int[12];
+	    mem[data_addra_int + 13] <= dia_int[13];
+	    mem[data_addra_int + 14] <= dia_int[14];
+	    mem[data_addra_int + 15] <= dia_int[15];
+	    mem[data_addra_int + 16] <= dia_int[16];
+	    mem[data_addra_int + 17] <= dia_int[17];
+	    mem[data_addra_int + 18] <= dia_int[18];
+	    mem[data_addra_int + 19] <= dia_int[19];
+	    mem[data_addra_int + 20] <= dia_int[20];
+	    mem[data_addra_int + 21] <= dia_int[21];
+	    mem[data_addra_int + 22] <= dia_int[22];
+	    mem[data_addra_int + 23] <= dia_int[23];
+	    mem[data_addra_int + 24] <= dia_int[24];
+	    mem[data_addra_int + 25] <= dia_int[25];
+	    mem[data_addra_int + 26] <= dia_int[26];
+	    mem[data_addra_int + 27] <= dia_int[27];
+	    mem[data_addra_int + 28] <= dia_int[28];
+	    mem[data_addra_int + 29] <= dia_int[29];
+	    mem[data_addra_int + 30] <= dia_int[30];
+	    mem[data_addra_int + 31] <= dia_int[31];
+	    mem[parity_addra_int + 0] <= dipa_int[0];
+	    mem[parity_addra_int + 1] <= dipa_int[1];
+	    mem[parity_addra_int + 2] <= dipa_int[2];
+	    mem[parity_addra_int + 3] <= dipa_int[3];
+	end
+    end
+
+    // Port B
+    always @(posedge clkb_int) begin
+	if (enb_int == 1'b1) begin
+	    if (ssrb_int == 1'b1) begin
+		dob_out[0] <= SRVAL_B[0];
+		dob_out[1] <= SRVAL_B[1];
+		dob_out[2] <= SRVAL_B[2];
+		dob_out[3] <= SRVAL_B[3];
+		dob_out[4] <= SRVAL_B[4];
+		dob_out[5] <= SRVAL_B[5];
+		dob_out[6] <= SRVAL_B[6];
+		dob_out[7] <= SRVAL_B[7];
+		dob_out[8] <= SRVAL_B[8];
+		dob_out[9] <= SRVAL_B[9];
+		dob_out[10] <= SRVAL_B[10];
+		dob_out[11] <= SRVAL_B[11];
+		dob_out[12] <= SRVAL_B[12];
+		dob_out[13] <= SRVAL_B[13];
+		dob_out[14] <= SRVAL_B[14];
+		dob_out[15] <= SRVAL_B[15];
+		dob_out[16] <= SRVAL_B[16];
+		dob_out[17] <= SRVAL_B[17];
+		dob_out[18] <= SRVAL_B[18];
+		dob_out[19] <= SRVAL_B[19];
+		dob_out[20] <= SRVAL_B[20];
+		dob_out[21] <= SRVAL_B[21];
+		dob_out[22] <= SRVAL_B[22];
+		dob_out[23] <= SRVAL_B[23];
+		dob_out[24] <= SRVAL_B[24];
+		dob_out[25] <= SRVAL_B[25];
+		dob_out[26] <= SRVAL_B[26];
+		dob_out[27] <= SRVAL_B[27];
+		dob_out[28] <= SRVAL_B[28];
+		dob_out[29] <= SRVAL_B[29];
+		dob_out[30] <= SRVAL_B[30];
+		dob_out[31] <= SRVAL_B[31];
+		dopb_out[0] <= SRVAL_B[32];
+		dopb_out[1] <= SRVAL_B[33];
+		dopb_out[2] <= SRVAL_B[34];
+		dopb_out[3] <= SRVAL_B[35];
+	    end
+	    else begin
+		if (web_int == 1'b1) begin
+		    if (wr_mode_b == 2'b00) begin
+			dob_out <= dib_int;
+			dopb_out <= dipb_int;
+		    end
+		    else if (wr_mode_b == 2'b01) begin
+			dob_out[0] <= mem[data_addrb_int + 0];
+			dob_out[1] <= mem[data_addrb_int + 1];
+			dob_out[2] <= mem[data_addrb_int + 2];
+			dob_out[3] <= mem[data_addrb_int + 3];
+			dob_out[4] <= mem[data_addrb_int + 4];
+			dob_out[5] <= mem[data_addrb_int + 5];
+			dob_out[6] <= mem[data_addrb_int + 6];
+			dob_out[7] <= mem[data_addrb_int + 7];
+			dob_out[8] <= mem[data_addrb_int + 8];
+			dob_out[9] <= mem[data_addrb_int + 9];
+			dob_out[10] <= mem[data_addrb_int + 10];
+			dob_out[11] <= mem[data_addrb_int + 11];
+			dob_out[12] <= mem[data_addrb_int + 12];
+			dob_out[13] <= mem[data_addrb_int + 13];
+			dob_out[14] <= mem[data_addrb_int + 14];
+			dob_out[15] <= mem[data_addrb_int + 15];
+			dob_out[16] <= mem[data_addrb_int + 16];
+			dob_out[17] <= mem[data_addrb_int + 17];
+			dob_out[18] <= mem[data_addrb_int + 18];
+			dob_out[19] <= mem[data_addrb_int + 19];
+			dob_out[20] <= mem[data_addrb_int + 20];
+			dob_out[21] <= mem[data_addrb_int + 21];
+			dob_out[22] <= mem[data_addrb_int + 22];
+			dob_out[23] <= mem[data_addrb_int + 23];
+			dob_out[24] <= mem[data_addrb_int + 24];
+			dob_out[25] <= mem[data_addrb_int + 25];
+			dob_out[26] <= mem[data_addrb_int + 26];
+			dob_out[27] <= mem[data_addrb_int + 27];
+			dob_out[28] <= mem[data_addrb_int + 28];
+			dob_out[29] <= mem[data_addrb_int + 29];
+			dob_out[30] <= mem[data_addrb_int + 30];
+			dob_out[31] <= mem[data_addrb_int + 31];
+			dopb_out[0] <= mem[parity_addrb_int + 0];
+			dopb_out[1] <= mem[parity_addrb_int + 1];
+			dopb_out[2] <= mem[parity_addrb_int + 2];
+			dopb_out[3] <= mem[parity_addrb_int + 3];
+		    end
+		end
+		else begin
+		    dob_out[0] <= mem[data_addrb_int + 0];
+		    dob_out[1] <= mem[data_addrb_int + 1];
+		    dob_out[2] <= mem[data_addrb_int + 2];
+		    dob_out[3] <= mem[data_addrb_int + 3];
+		    dob_out[4] <= mem[data_addrb_int + 4];
+		    dob_out[5] <= mem[data_addrb_int + 5];
+		    dob_out[6] <= mem[data_addrb_int + 6];
+		    dob_out[7] <= mem[data_addrb_int + 7];
+		    dob_out[8] <= mem[data_addrb_int + 8];
+		    dob_out[9] <= mem[data_addrb_int + 9];
+		    dob_out[10] <= mem[data_addrb_int + 10];
+		    dob_out[11] <= mem[data_addrb_int + 11];
+		    dob_out[12] <= mem[data_addrb_int + 12];
+		    dob_out[13] <= mem[data_addrb_int + 13];
+		    dob_out[14] <= mem[data_addrb_int + 14];
+		    dob_out[15] <= mem[data_addrb_int + 15];
+		    dob_out[16] <= mem[data_addrb_int + 16];
+		    dob_out[17] <= mem[data_addrb_int + 17];
+		    dob_out[18] <= mem[data_addrb_int + 18];
+		    dob_out[19] <= mem[data_addrb_int + 19];
+		    dob_out[20] <= mem[data_addrb_int + 20];
+		    dob_out[21] <= mem[data_addrb_int + 21];
+		    dob_out[22] <= mem[data_addrb_int + 22];
+		    dob_out[23] <= mem[data_addrb_int + 23];
+		    dob_out[24] <= mem[data_addrb_int + 24];
+		    dob_out[25] <= mem[data_addrb_int + 25];
+		    dob_out[26] <= mem[data_addrb_int + 26];
+		    dob_out[27] <= mem[data_addrb_int + 27];
+		    dob_out[28] <= mem[data_addrb_int + 28];
+		    dob_out[29] <= mem[data_addrb_int + 29];
+		    dob_out[30] <= mem[data_addrb_int + 30];
+		    dob_out[31] <= mem[data_addrb_int + 31];
+		    dopb_out[0] <= mem[parity_addrb_int + 0];
+		    dopb_out[1] <= mem[parity_addrb_int + 1];
+		    dopb_out[2] <= mem[parity_addrb_int + 2];
+		    dopb_out[3] <= mem[parity_addrb_int + 3];
+		end
+	    end
+	end
+    end
+
+    always @(posedge clkb_int) begin
+	if (enb_int == 1'b1 && web_int == 1'b1) begin
+	    mem[data_addrb_int + 0] <= dib_int[0];
+	    mem[data_addrb_int + 1] <= dib_int[1];
+	    mem[data_addrb_int + 2] <= dib_int[2];
+	    mem[data_addrb_int + 3] <= dib_int[3];
+	    mem[data_addrb_int + 4] <= dib_int[4];
+	    mem[data_addrb_int + 5] <= dib_int[5];
+	    mem[data_addrb_int + 6] <= dib_int[6];
+	    mem[data_addrb_int + 7] <= dib_int[7];
+	    mem[data_addrb_int + 8] <= dib_int[8];
+	    mem[data_addrb_int + 9] <= dib_int[9];
+	    mem[data_addrb_int + 10] <= dib_int[10];
+	    mem[data_addrb_int + 11] <= dib_int[11];
+	    mem[data_addrb_int + 12] <= dib_int[12];
+	    mem[data_addrb_int + 13] <= dib_int[13];
+	    mem[data_addrb_int + 14] <= dib_int[14];
+	    mem[data_addrb_int + 15] <= dib_int[15];
+	    mem[data_addrb_int + 16] <= dib_int[16];
+	    mem[data_addrb_int + 17] <= dib_int[17];
+	    mem[data_addrb_int + 18] <= dib_int[18];
+	    mem[data_addrb_int + 19] <= dib_int[19];
+	    mem[data_addrb_int + 20] <= dib_int[20];
+	    mem[data_addrb_int + 21] <= dib_int[21];
+	    mem[data_addrb_int + 22] <= dib_int[22];
+	    mem[data_addrb_int + 23] <= dib_int[23];
+	    mem[data_addrb_int + 24] <= dib_int[24];
+	    mem[data_addrb_int + 25] <= dib_int[25];
+	    mem[data_addrb_int + 26] <= dib_int[26];
+	    mem[data_addrb_int + 27] <= dib_int[27];
+	    mem[data_addrb_int + 28] <= dib_int[28];
+	    mem[data_addrb_int + 29] <= dib_int[29];
+	    mem[data_addrb_int + 30] <= dib_int[30];
+	    mem[data_addrb_int + 31] <= dib_int[31];
+	    mem[parity_addrb_int + 0] <= dipb_int[0];
+	    mem[parity_addrb_int + 1] <= dipb_int[1];
+	    mem[parity_addrb_int + 2] <= dipb_int[2];
+	    mem[parity_addrb_int + 3] <= dipb_int[3];
+	end
+    end
+
+    specify
+	(CLKA *> DOA) = (100, 100);
+	(CLKA *> DOPA) = (100, 100);
+	(CLKB *> DOB) = (100, 100);
+	(CLKB *> DOPB) = (100, 100);
+    endspecify
+
+endmodule
+
+`else
+
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/RAMB16_S36_S36.v,v 1.10 2007/02/22 01:58:06 wloo Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2005 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Timing Simulation Library Component
+//  /   /                  16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
+// /___/   /\     Filename : RAMB16_S36_S36.v
+// \   \  /  \    Timestamp : Thu Mar 10 16:44:01 PST 2005
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+//    03/10/05 - Initialized outputs.
+//    02/21/07 - Fixed parameter SIM_COLLISION_CHECK (CR 433281).
+// End Revision
+
+`timescale 1 ps/1 ps
+
+module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB);
+
+    parameter INIT_A = 36'h0;
+    parameter INIT_B = 36'h0;
+    parameter SRVAL_A = 36'h0;
+    parameter SRVAL_B = 36'h0;
+    parameter WRITE_MODE_A = "WRITE_FIRST";
+    parameter WRITE_MODE_B = "WRITE_FIRST";
+    parameter SIM_COLLISION_CHECK = "ALL";
+    localparam SETUP_ALL = 1000;
+    localparam SETUP_READ_FIRST = 3000;
+
+    parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+    parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+
+    output [31:0] DOA;
+    output [3:0] DOPA;
+    output [31:0] DOB;
+    output [3:0] DOPB;
+
+    input [8:0] ADDRA;
+    input [31:0] DIA;
+    input [3:0] DIPA;
+    input ENA, CLKA, WEA, SSRA;
+    input [8:0] ADDRB;
+    input [31:0] DIB;
+    input [3:0] DIPB;
+    input ENB, CLKB, WEB, SSRB;
+
+    reg [31:0] doa_out = INIT_A[31:0];
+    reg [3:0] dopa_out = INIT_A[35:32];
+    reg [31:0] dob_out = INIT_B[31:0];
+    reg [3:0] dopb_out = INIT_B[35:32];
+    
+    reg [31:0] mem [511:0];
+    reg [3:0] memp [511:0];
+    
+    reg [8:0] count, countp;
+    reg [1:0] wr_mode_a, wr_mode_b;
+
+    reg [5:0] dmi, dbi;
+    reg [5:0] pmi, pbi;
+
+    wire [8:0] addra_int;
+    reg [8:0] addra_reg;
+    wire [31:0] dia_int;
+    wire [3:0] dipa_int;
+    wire ena_int, clka_int, wea_int, ssra_int;
+    reg ena_reg, wea_reg, ssra_reg;
+    wire [8:0] addrb_int;
+    reg [8:0] addrb_reg;
+    wire [31:0] dib_int;
+    wire [3:0] dipb_int;
+    wire enb_int, clkb_int, web_int, ssrb_int;
+    reg display_flag, output_flag;
+    reg enb_reg, web_reg, ssrb_reg;
+
+    time time_clka, time_clkb;
+    time time_clka_clkb;
+    time time_clkb_clka;
+
+    reg setup_all_a_b;
+    reg setup_all_b_a;
+    reg setup_zero;
+    reg setup_rf_a_b;
+    reg setup_rf_b_a;
+    reg [1:0] data_collision, data_collision_a_b, data_collision_b_a;
+    reg memory_collision, memory_collision_a_b, memory_collision_b_a;
+    reg change_clka;
+    reg change_clkb;
+
+    wire [14:0] data_addra_int;
+    wire [14:0] data_addra_reg;
+    wire [14:0] data_addrb_int;
+    wire [14:0] data_addrb_reg;
+
+    wire dia_enable = ena_int && wea_int;
+    wire dib_enable = enb_int && web_int;
+
+    tri0 GSR = glbl.GSR;
+    wire gsr_int;
+
+    buf b_gsr (gsr_int, GSR);
+
+    buf b_doa [31:0] (DOA, doa_out);
+    buf b_dopa [3:0] (DOPA, dopa_out);
+    buf b_addra [8:0] (addra_int, ADDRA);
+    buf b_dia [31:0] (dia_int, DIA);
+    buf b_dipa [3:0] (dipa_int, DIPA);
+    buf b_ena (ena_int, ENA);
+    buf b_clka (clka_int, CLKA);
+    buf b_ssra (ssra_int, SSRA);
+    buf b_wea (wea_int, WEA);
+
+    buf b_dob [31:0] (DOB, dob_out);
+    buf b_dopb [3:0] (DOPB, dopb_out);
+    buf b_addrb [8:0] (addrb_int, ADDRB);
+    buf b_dib [31:0] (dib_int, DIB);
+    buf b_dipb [3:0] (dipb_int, DIPB);
+    buf b_enb (enb_int, ENB);
+    buf b_clkb (clkb_int, CLKB);
+    buf b_ssrb (ssrb_int, SSRB);
+    buf b_web (web_int, WEB);
+
+    
+    always @(gsr_int)
+	if (gsr_int) begin
+	    assign {dopa_out, doa_out} = INIT_A;
+	    assign {dopb_out, dob_out} = INIT_B;
+	end
+	else begin
+	    deassign doa_out;
+	    deassign dopa_out;
+	    deassign dob_out;
+	    deassign dopb_out;
+	end
+
+    
+    initial begin
+
+	for (count = 0; count < 8; count = count + 1) begin
+	    mem[count]          = INIT_00[(count * 32) +: 32];
+	    mem[8 * 1 + count]  = INIT_01[(count * 32) +: 32];
+	    mem[8 * 2 + count]  = INIT_02[(count * 32) +: 32];
+	    mem[8 * 3 + count]  = INIT_03[(count * 32) +: 32];
+	    mem[8 * 4 + count]  = INIT_04[(count * 32) +: 32];
+	    mem[8 * 5 + count]  = INIT_05[(count * 32) +: 32];
+	    mem[8 * 6 + count]  = INIT_06[(count * 32) +: 32];
+	    mem[8 * 7 + count]  = INIT_07[(count * 32) +: 32];
+	    mem[8 * 8 + count]  = INIT_08[(count * 32) +: 32];
+	    mem[8 * 9 + count]  = INIT_09[(count * 32) +: 32];
+	    mem[8 * 10 + count] = INIT_0A[(count * 32) +: 32];
+	    mem[8 * 11 + count] = INIT_0B[(count * 32) +: 32];
+	    mem[8 * 12 + count] = INIT_0C[(count * 32) +: 32];
+	    mem[8 * 13 + count] = INIT_0D[(count * 32) +: 32];
+	    mem[8 * 14 + count] = INIT_0E[(count * 32) +: 32];
+	    mem[8 * 15 + count] = INIT_0F[(count * 32) +: 32];
+	    mem[8 * 16 + count] = INIT_10[(count * 32) +: 32];
+	    mem[8 * 17 + count] = INIT_11[(count * 32) +: 32];
+	    mem[8 * 18 + count] = INIT_12[(count * 32) +: 32];
+	    mem[8 * 19 + count] = INIT_13[(count * 32) +: 32];
+	    mem[8 * 20 + count] = INIT_14[(count * 32) +: 32];
+	    mem[8 * 21 + count] = INIT_15[(count * 32) +: 32];
+	    mem[8 * 22 + count] = INIT_16[(count * 32) +: 32];
+	    mem[8 * 23 + count] = INIT_17[(count * 32) +: 32];
+	    mem[8 * 24 + count] = INIT_18[(count * 32) +: 32];
+	    mem[8 * 25 + count] = INIT_19[(count * 32) +: 32];
+	    mem[8 * 26 + count] = INIT_1A[(count * 32) +: 32];
+	    mem[8 * 27 + count] = INIT_1B[(count * 32) +: 32];
+	    mem[8 * 28 + count] = INIT_1C[(count * 32) +: 32];
+	    mem[8 * 29 + count] = INIT_1D[(count * 32) +: 32];
+	    mem[8 * 30 + count] = INIT_1E[(count * 32) +: 32];
+	    mem[8 * 31 + count] = INIT_1F[(count * 32) +: 32];
+	    mem[8 * 32 + count] = INIT_20[(count * 32) +: 32];
+	    mem[8 * 33 + count] = INIT_21[(count * 32) +: 32];
+	    mem[8 * 34 + count] = INIT_22[(count * 32) +: 32];
+	    mem[8 * 35 + count] = INIT_23[(count * 32) +: 32];
+	    mem[8 * 36 + count] = INIT_24[(count * 32) +: 32];
+	    mem[8 * 37 + count] = INIT_25[(count * 32) +: 32];
+	    mem[8 * 38 + count] = INIT_26[(count * 32) +: 32];
+	    mem[8 * 39 + count] = INIT_27[(count * 32) +: 32];
+	    mem[8 * 40 + count] = INIT_28[(count * 32) +: 32];
+	    mem[8 * 41 + count] = INIT_29[(count * 32) +: 32];
+	    mem[8 * 42 + count] = INIT_2A[(count * 32) +: 32];
+	    mem[8 * 43 + count] = INIT_2B[(count * 32) +: 32];
+	    mem[8 * 44 + count] = INIT_2C[(count * 32) +: 32];
+	    mem[8 * 45 + count] = INIT_2D[(count * 32) +: 32];
+	    mem[8 * 46 + count] = INIT_2E[(count * 32) +: 32];
+	    mem[8 * 47 + count] = INIT_2F[(count * 32) +: 32];
+	    mem[8 * 48 + count] = INIT_30[(count * 32) +: 32];
+	    mem[8 * 49 + count] = INIT_31[(count * 32) +: 32];
+	    mem[8 * 50 + count] = INIT_32[(count * 32) +: 32];
+	    mem[8 * 51 + count] = INIT_33[(count * 32) +: 32];
+	    mem[8 * 52 + count] = INIT_34[(count * 32) +: 32];
+	    mem[8 * 53 + count] = INIT_35[(count * 32) +: 32];
+	    mem[8 * 54 + count] = INIT_36[(count * 32) +: 32];
+	    mem[8 * 55 + count] = INIT_37[(count * 32) +: 32];
+	    mem[8 * 56 + count] = INIT_38[(count * 32) +: 32];
+	    mem[8 * 57 + count] = INIT_39[(count * 32) +: 32];
+	    mem[8 * 58 + count] = INIT_3A[(count * 32) +: 32];
+	    mem[8 * 59 + count] = INIT_3B[(count * 32) +: 32];
+	    mem[8 * 60 + count] = INIT_3C[(count * 32) +: 32];
+	    mem[8 * 61 + count] = INIT_3D[(count * 32) +: 32];
+	    mem[8 * 62 + count] = INIT_3E[(count * 32) +: 32];
+	    mem[8 * 63 + count] = INIT_3F[(count * 32) +: 32];
+	end
+
+// initiate parity start
+	for (countp = 0; countp < 64; countp = countp + 1) begin
+	    memp[countp]          = INITP_00[(countp * 4) +: 4];
+	    memp[64 * 1 + countp] = INITP_01[(countp * 4) +: 4];
+	    memp[64 * 2 + countp] = INITP_02[(countp * 4) +: 4];
+	    memp[64 * 3 + countp] = INITP_03[(countp * 4) +: 4];
+	    memp[64 * 4 + countp] = INITP_04[(countp * 4) +: 4];
+	    memp[64 * 5 + countp] = INITP_05[(countp * 4) +: 4];
+	    memp[64 * 6 + countp] = INITP_06[(countp * 4) +: 4];
+	    memp[64 * 7 + countp] = INITP_07[(countp * 4) +: 4];
+	end
+// initiate parity end
+	
+	change_clka <= 0;
+	change_clkb <= 0;
+	data_collision <= 0;
+	data_collision_a_b <= 0;
+	data_collision_b_a <= 0;
+	memory_collision <= 0;
+	memory_collision_a_b <= 0;
+	memory_collision_b_a <= 0;
+	setup_all_a_b <= 0;
+	setup_all_b_a <= 0;
+	setup_zero <= 0;
+	setup_rf_a_b <= 0;
+	setup_rf_b_a <= 0;
+    end
+
+    assign data_addra_int = addra_int * 32;
+    assign data_addra_reg = addra_reg * 32;
+    assign data_addrb_int = addrb_int * 32;
+    assign data_addrb_reg = addrb_reg * 32;
+
+
+    initial begin
+
+	display_flag = 1;
+	output_flag = 1;
+	
+	case (SIM_COLLISION_CHECK)
+
+	    "NONE" : begin
+		         output_flag = 0;
+	                 display_flag = 0;
+	             end
+	    "WARNING_ONLY" : output_flag = 0;
+	    "GENERATE_X_ONLY" : display_flag = 0;
+	    "ALL" : ;
+
+	    default : begin
+		          $display("Attribute Syntax Error : The Attribute SIM_COLLISION_CHECK on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are ALL, NONE, WARNING_ONLY or GENERATE_X_ONLY.", SIM_COLLISION_CHECK);
+		          $finish;
+	              end
+
+	endcase // case(SIM_COLLISION_CHECK)
+
+    end // initial begin
+
+    
+    always @(posedge clka_int) begin
+	if ((output_flag || display_flag)) begin
+	    time_clka = $time;
+	    #0 time_clkb_clka = time_clka - time_clkb;
+	    change_clka = ~change_clka;
+	end
+    end
+    
+    always @(posedge clkb_int) begin
+	if ((output_flag || display_flag)) begin
+	    time_clkb = $time;
+	    #0 time_clka_clkb = time_clkb - time_clka;
+	    change_clkb = ~change_clkb;
+	end
+    end
+    
+    always @(change_clkb) begin
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_ALL))
+	    setup_all_a_b = 1;
+	if ((0 < time_clka_clkb) && (time_clka_clkb < SETUP_READ_FIRST))
+	    setup_rf_a_b = 1;
+    end
+
+    always @(change_clka) begin
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_ALL))
+	    setup_all_b_a = 1;
+	if ((0 < time_clkb_clka) && (time_clkb_clka < SETUP_READ_FIRST))
+	    setup_rf_b_a = 1;
+    end
+
+    always @(change_clkb or change_clka) begin
+	if ((time_clkb_clka == 0) && (time_clka_clkb == 0))
+	    setup_zero = 1;
+    end
+
+    always @(posedge setup_zero) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_int[14:5] == data_addrb_int[14:5]))
+	    memory_collision <= 1;
+    end
+
+    always @(posedge setup_all_a_b or posedge setup_rf_a_b) begin
+	if ((ena_reg == 1) && (wea_reg == 1) &&
+	    (enb_int == 1) && (web_int == 1) &&
+	    (data_addra_reg[14:5] == data_addrb_int[14:5]))
+	    memory_collision_a_b <= 1;
+    end
+
+    always @(posedge setup_all_b_a or posedge setup_rf_b_a) begin
+	if ((ena_int == 1) && (wea_int == 1) &&
+	    (enb_reg == 1) && (web_reg == 1) &&
+	    (data_addra_int[14:5] == data_addrb_reg[14:5]))
+	    memory_collision_b_a <= 1;
+    end
+
+    always @(posedge setup_all_a_b) begin
+	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+		6'b000011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b010011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b010111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b011011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b100011 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_a_b <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision_a_b <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_a_b <= 0;
+    end
+
+
+    always @(posedge setup_all_b_a) begin
+	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+		6'b000011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b000111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b001011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b010111 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b011011 : begin data_collision_b_a <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b001001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b011001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b101001 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision_b_a <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_all_b_a <= 0;
+    end
+
+
+    always @(posedge setup_zero) begin
+	if (data_addra_int[14:5] == data_addrb_int[14:5]) begin
+	if ((ena_int == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_int})
+		6'b000011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b000111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b001011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b010011 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision <= 2'b10; display_wa_wb; end
+		6'b100011 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b100111 : begin data_collision <= 2'b01; display_wa_wb; end
+		6'b101011 : begin display_wa_wb; end
+		6'b000001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b000101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b001001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b010001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b010101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b011001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b100001 : begin data_collision <= 2'b10; display_ra_wb; end
+//		6'b100101 : begin data_collision <= 2'b00; display_ra_wb; end
+		6'b101001 : begin data_collision <= 2'b10; display_ra_wb; end
+		6'b000010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b000110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b001010 : begin data_collision <= 2'b01; display_wa_rb; end
+//		6'b010010 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision <= 2'b00; display_wa_rb; end
+		6'b100010 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b100110 : begin data_collision <= 2'b01; display_wa_rb; end
+		6'b101010 : begin data_collision <= 2'b01; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_zero <= 0;
+    end
+
+    task display_ra_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle.", $time/1000.0, addra_int);
+    end
+    endtask
+
+    task display_wa_rb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA read was performed on address %h (hex) of Port B while a write was requested to the same address on Port A. The write will be successful however the read value on Port B is unknown until the next CLKB cycle.", $time/1000.0, addrb_int);
+    end
+    endtask
+
+    task display_wa_wb;
+    begin
+	if (display_flag)
+        $display("Memory Collision Error on RAMB16_S36_S36:%m at simulation time %.3f ns\nA write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location %h (hex) of Port A and address location %h (hex) of Port B are unknown.", $time/1000.0, addra_int, addrb_int);
+    end
+    endtask
+
+
+    always @(posedge setup_rf_a_b) begin
+	if (data_addra_reg[14:5] == data_addrb_int[14:5]) begin
+	if ((ena_reg == 1) && (enb_int == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_reg, web_int})
+//		6'b000011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b001011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+		6'b010011 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b010111 : begin data_collision_a_b <= 2'b11; display_wa_wb; end
+		6'b011011 : begin data_collision_a_b <= 2'b10; display_wa_wb; end
+//		6'b100011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b100111 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b101011 : begin data_collision_a_b <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b001001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b010101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b011001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b100101 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b101001 : begin data_collision_a_b <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+		6'b010010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b010110 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+		6'b011010 : begin data_collision_a_b <= 2'b01; display_wa_rb; end
+//		6'b100010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_a_b <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_a_b <= 0;
+    end
+
+
+    always @(posedge setup_rf_b_a) begin
+	if (data_addra_int[14:5] == data_addrb_reg[14:5]) begin
+	if ((ena_int == 1) && (enb_reg == 1)) begin
+	    case ({wr_mode_a, wr_mode_b, wea_int, web_reg})
+//		6'b000011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b000111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b001011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b010011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b010111 : begin data_collision_b_a <= 2'b11; display_wa_wb; end
+//		6'b011011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b100011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+		6'b100111 : begin data_collision_b_a <= 2'b01; display_wa_wb; end
+//		6'b101011 : begin data_collision_b_a <= 2'b00; display_wa_wb; end
+//		6'b000001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b000101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b001001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b010001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b010101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b011001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b100001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+		6'b100101 : begin data_collision_b_a <= 2'b10; display_ra_wb; end
+//		6'b101001 : begin data_collision_b_a <= 2'b00; display_ra_wb; end
+//		6'b000010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b000110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b001010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b010110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b011010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b100110 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+//		6'b101010 : begin data_collision_b_a <= 2'b00; display_wa_rb; end
+	    endcase
+	end
+	end
+	setup_rf_b_a <= 0;
+    end
+
+
+    always @(posedge clka_int) begin
+	if ((output_flag || display_flag)) begin
+	    addra_reg <= addra_int;
+	    ena_reg <= ena_int;
+	    ssra_reg <= ssra_int;
+	    wea_reg <= wea_int;
+	end
+    end
+    
+    always @(posedge clkb_int) begin
+	if ((output_flag || display_flag)) begin
+	    addrb_reg <= addrb_int;
+	    enb_reg <= enb_int;
+	    ssrb_reg <= ssrb_int;
+	    web_reg <= web_int;
+	end
+    end
+    
+	    
+    // Data
+    always @(posedge memory_collision) begin
+	if ((output_flag || display_flag)) begin
+	    mem[addra_int] <= 32'bx;
+	    memory_collision <= 0;
+	end
+	
+    end
+
+    always @(posedge memory_collision_a_b) begin
+	if ((output_flag || display_flag)) begin
+	    mem[addra_reg] <= 32'bx;
+	    memory_collision_a_b <= 0;
+	end
+    end
+    
+    always @(posedge memory_collision_b_a) begin
+	if ((output_flag || display_flag)) begin
+	    mem[addra_int] <= 32'bx;
+	    memory_collision_b_a <= 0;
+	end
+    end
+    
+    always @(posedge data_collision[1]) begin
+	if (ssra_int == 0 && output_flag) begin
+	    doa_out <= #100 32'bX;
+	end
+	data_collision[1] <= 0;
+    end
+
+    always @(posedge data_collision[0]) begin
+	if (ssrb_int == 0 && output_flag) begin
+	    dob_out <= #100 32'bX;
+	end
+	data_collision[0] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[1]) begin
+	if (ssra_reg == 0 && output_flag) begin
+	    doa_out <= #100 32'bX;
+	end
+	data_collision_a_b[1] <= 0;
+    end
+
+    always @(posedge data_collision_a_b[0]) begin
+	if (ssrb_int == 0 && output_flag) begin
+	    dob_out <= #100 32'bX;
+	end
+	data_collision_a_b[0] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[1]) begin
+	if (ssra_int == 0 && output_flag) begin
+	    doa_out <= #100 32'bX;
+	end
+	data_collision_b_a[1] <= 0;
+    end
+
+    always @(posedge data_collision_b_a[0]) begin
+	if (ssrb_reg == 0 && output_flag) begin
+	    dob_out <= #100 32'bX;
+	end
+	data_collision_b_a[0] <= 0;
+    end
+
+// x parity start
+    always @(posedge memory_collision) begin
+	if ((output_flag || display_flag))
+	    memp[addra_int] <= 4'bx;
+    end
+
+    always @(posedge memory_collision_a_b) begin
+	if ((output_flag || display_flag))
+	    memp[addra_reg] <= 4'bx;
+    end
+
+    always @(posedge memory_collision_b_a) begin
+	if ((output_flag || display_flag))
+	    memp[addra_int] <= 4'bx;
+    end
+    
+    always @(posedge data_collision[1]) begin
+	if (ssra_int == 0 && output_flag) begin
+	    dopa_out <= #100 4'bX;
+	end
+    end
+
+    always @(posedge data_collision_a_b[1]) begin
+	if (ssra_reg == 0 && output_flag) begin
+	    dopa_out <= #100 4'bX;
+	end
+    end
+
+    
+    always @(posedge data_collision_b_a[1]) begin
+	if (ssra_int == 0 && output_flag) begin
+	    dopa_out <= #100 4'bX;
+	end
+    end
+
+    always @(posedge data_collision[0]) begin
+	if (ssrb_int == 0 && output_flag) begin
+	    dopb_out <= #100 4'bx;
+	end
+    end
+
+    always @(posedge data_collision_a_b[0]) begin
+	if (ssrb_int == 0 && output_flag) begin
+	    dopb_out <= #100 4'bx;
+	end
+    end
+
+    always @(posedge data_collision_b_a[0]) begin
+	if (ssrb_reg == 0 && output_flag) begin
+	    dopb_out <= #100 4'bx;
+	end
+    end
+// x parity end
+
+    initial begin
+	case (WRITE_MODE_A)
+	    "WRITE_FIRST" : wr_mode_a <= 2'b00;
+	    "READ_FIRST"  : wr_mode_a <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_a <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_A on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_A);
+				$finish;
+			    end
+	endcase
+    end
+
+    initial begin
+	case (WRITE_MODE_B)
+	    "WRITE_FIRST" : wr_mode_b <= 2'b00;
+	    "READ_FIRST"  : wr_mode_b <= 2'b01;
+	    "NO_CHANGE"   : wr_mode_b <= 2'b10;
+	    default       : begin
+				$display("Attribute Syntax Error : The Attribute WRITE_MODE_B on RAMB16_S36_S36 instance %m is set to %s.  Legal values for this attribute are WRITE_FIRST, READ_FIRST or NO_CHANGE.", WRITE_MODE_B);
+				$finish;
+			    end
+	endcase
+    end
+
+
+    // Port A
+    always @(posedge clka_int) begin
+
+	if (ena_int == 1'b1) begin
+
+	    if (ssra_int == 1'b1) begin
+		{dopa_out, doa_out} <= #100 SRVAL_A;
+	    end
+	    else begin
+		if (wea_int == 1'b1) begin
+		    if (wr_mode_a == 2'b00) begin
+			doa_out <= #100 dia_int;
+			dopa_out <= #100 dipa_int;
+		    end
+		    else if (wr_mode_a == 2'b01) begin
+
+			doa_out <= #100 mem[addra_int];
+			dopa_out <= #100 memp[addra_int];
+
+		    end
+		end
+		else begin
+
+		    doa_out <= #100 mem[addra_int];
+		    dopa_out <= #100 memp[addra_int];
+		    
+		end
+	    end
+
+	    // memory
+	    if (wea_int == 1'b1) begin
+		mem[addra_int] <= dia_int;
+		memp[addra_int] <= dipa_int;
+	    end
+	    
+	end
+    end
+
+
+    // Port B
+    always @(posedge clkb_int) begin
+
+	if (enb_int == 1'b1) begin
+
+	    if (ssrb_int == 1'b1) begin
+		{dopb_out, dob_out} <= #100 SRVAL_B;
+	    end
+	    else begin
+		if (web_int == 1'b1) begin
+		    if (wr_mode_b == 2'b00) begin
+			dob_out <= #100 dib_int;
+			dopb_out <= #100 dipb_int;
+		    end
+		    else if (wr_mode_b == 2'b01) begin
+			dob_out <= #100 mem[addrb_int];
+			dopb_out <= #100 memp[addrb_int];
+		    end
+		end
+		else begin
+		    dob_out <= #100 mem[addrb_int];
+		    dopb_out <= #100 memp[addrb_int];
+		end
+	    end
+
+	    // memory
+	    if (web_int == 1'b1) begin
+		mem[addrb_int] <= dib_int;
+		memp[addrb_int] <= dipb_int;
+	    end
+
+	end
+    end
+
+
+endmodule
+
+`endif
diff --git a/fpga/usrp2/models/SRL16E.v b/fpga/usrp2/models/SRL16E.v
new file mode 100644
index 000000000..e71a419ac
--- /dev/null
+++ b/fpga/usrp2/models/SRL16E.v
@@ -0,0 +1,53 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 8.1i (I.13)
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  16-Bit Shift Register Look-Up-Table with Clock Enable
+// /___/   /\     Filename : SRL16E.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:43:40 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+// End Revision
+
+`timescale  1 ps / 1 ps
+
+
+module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
+
+    parameter INIT = 16'h0000;
+
+    output Q;
+
+    input  A0, A1, A2, A3, CE, CLK, D;
+
+    reg  [15:0] data;
+
+
+    assign Q = data[{A3, A2, A1, A0}];
+
+    initial
+    begin
+          assign  data = INIT;
+          while (CLK === 1'b1 || CLK===1'bX) 
+            #10; 
+          deassign data;
+    end
+
+    always @(posedge CLK)
+    begin
+	if (CE == 1'b1) begin
+	    {data[15:0]} <= #100 {data[14:0], D};
+	end
+    end
+
+
+endmodule
+
diff --git a/fpga/usrp2/models/SRLC16E.v b/fpga/usrp2/models/SRLC16E.v
new file mode 100644
index 000000000..a68bbe9e9
--- /dev/null
+++ b/fpga/usrp2/models/SRLC16E.v
@@ -0,0 +1,61 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRLC16E.v,v 1.6.158.1 2007/03/09 18:13:20 patrickp Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 8.1i (I.13)
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  16-Bit Shift Register Look-Up-Table with Carry and Clock Enable
+// /___/   /\     Filename : SRLC16E.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:43:40 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+// End Revision
+
+`timescale  1 ps / 1 ps
+
+
+module SRLC16E (Q, Q15, A0, A1, A2, A3, CE, CLK, D);
+
+    parameter INIT = 16'h0000;
+
+    output Q, Q15;
+
+    input  A0, A1, A2, A3, CE, CLK, D;
+
+    reg  [15:0] data;
+    wire [3:0]  addr;
+    wire	q_int;
+
+    buf b_a3 (addr[3], A3);
+    buf b_a2 (addr[2], A2);
+    buf b_a1 (addr[1], A1);
+    buf b_a0 (addr[0], A0);
+
+    buf b_q_int (q_int, data[addr]);
+    buf b_q (Q, q_int);
+    buf b_q15_int (q15_int, data[15]);
+    buf b_q15 (Q15, q15_int);
+
+    initial
+    begin
+          assign  data = INIT;
+          while (CLK === 1'b1 || CLK===1'bX) 
+            #10; 
+          deassign data;
+    end
+
+    always @(posedge CLK) begin
+	if (CE == 1'b1) begin
+	    {data[15:0]} <= #100 {data[14:0], D};
+	end
+    end
+
+
+endmodule
+
diff --git a/fpga/usrp2/models/adc_model.v b/fpga/usrp2/models/adc_model.v
new file mode 100644
index 000000000..e5a3ee0d8
--- /dev/null
+++ b/fpga/usrp2/models/adc_model.v
@@ -0,0 +1,48 @@
+
+module adc_model
+  (input clk, input rst,
+   output [13:0] adc_a,
+   output adc_ovf_a,
+   input adc_on_a,
+   input adc_oe_a,
+   output [13:0] adc_b,
+   output adc_ovf_b,
+   input adc_on_b,
+   input adc_oe_b
+   );
+   
+   math_real math ( ) ;
+
+   reg [13:0] adc_a_int = 0;
+   reg [13:0] adc_b_int = 0;
+   
+   assign     adc_a = adc_oe_a ? adc_a_int : 14'bz;
+   assign     adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz;
+   assign     adc_b = adc_oe_b ? adc_b_int : 14'bz;
+   assign     adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz;
+   
+   real       phase = 0;
+   real       freq = 330000/100000000;
+
+   real       scale = 8190; // math.pow(2,13)-2;
+   always @(posedge clk)
+     if(rst)
+       begin
+	  adc_a_int <= 0;
+	  adc_b_int <= 0;
+       end
+     else 
+       begin
+	  if(adc_on_a)
+	    //adc_a_int <= $rtoi(math.round(math.sin(phase*math.MATH_2_PI)*scale)) ;
+	    adc_a_int <= adc_a_int + 3;
+	  if(adc_on_b)
+	    adc_b_int <= adc_b_int - 7;
+	  //adc_b_int <= $rtoi(math.round(math.cos(phase*math.MATH_2_PI)*scale)) ;
+	  if(phase > 1)
+	    phase <= phase + freq - 1;
+	  else
+	    phase <= phase + freq;
+       end
+   
+endmodule // adc_model
diff --git a/fpga/usrp2/models/cpld_model.v b/fpga/usrp2/models/cpld_model.v
new file mode 100644
index 000000000..c886433ae
--- /dev/null
+++ b/fpga/usrp2/models/cpld_model.v
@@ -0,0 +1,96 @@
+ 
+module cpld_model
+  (input aux_clk, input start, input mode, input done,
+   output dout, output reg sclk, output detached);
+
+   reg [7:0] rom[0:65535];
+
+   reg [15:0] addr;
+   reg [7:0]  data;
+   assign     dout = data[7];
+
+   reg [2:0]  state, bitcnt;
+   
+   localparam IDLE = 3'd0;
+   localparam READ = 3'd1;
+   localparam BIT1 = 3'd2;
+   localparam BIT2 = 3'd3;
+   localparam DONE = 3'd4;
+   localparam DETACHED = 3'd5;
+   localparam ERROR = 3'd7;
+   
+   integer i; 
+   reg [1023:0] ROMFile;
+   
+   initial begin
+      for (i=0;i<65536;i=i+1) begin
+	 rom[i] <= 32'h0;
+      end       
+      if ( !$value$plusargs( "rom=%s", ROMFile ) )
+        begin
+           $display( "Using default ROM file, 'flash.rom'" );
+           ROMFile = "flash.rom";
+        end
+      else
+	$display( "Using %s as ROM file.", ROMFile);
+      
+      #1 $readmemh( ROMFile,rom );     
+   end
+
+   initial addr = 16'd0;
+   initial data = 8'd0;
+   initial state = IDLE;
+   initial bitcnt = 3'd0;
+   initial sclk = 1'b0;
+   
+   always @(posedge aux_clk)
+     case(state)
+       IDLE :
+	 if(start)
+	   if(~mode)
+	     state <= READ;
+	   else
+	     state <= ERROR;
+       READ :
+	 if(done)
+	   state <= DONE;
+       	 else
+	   begin
+	      data <= rom[addr];
+	      addr <= addr + 1;
+	      bitcnt <= 3'd0;
+	      if(addr==16'hFFFF)
+		state <= ERROR;
+	      else
+		state <= BIT1;
+	   end // else: !if(start)
+       BIT1 :
+	 begin
+	    sclk <= 1'b1;
+	    state <= BIT2;
+	 end
+       BIT2 :
+	 begin
+	    sclk <= 1'b0;
+	    data <= {data[6:0],1'b0};
+	    bitcnt <= bitcnt + 1;
+	    if(bitcnt==7)
+	      state <= READ;
+	    else
+	      state <=BIT1;
+	 end
+       DONE :
+	 begin
+	    if(start)
+	      state <= ERROR;
+	    else
+	      state <= DETACHED;
+	 end
+       DETACHED :
+	 if(start)
+	   state <= ERROR;
+     endcase // case(state)
+   
+   assign detached = (state == DETACHED) || (state == IDLE);
+   
+endmodule // cpld_model
diff --git a/fpga/usrp2/models/math_real.v b/fpga/usrp2/models/math_real.v
new file mode 100644
index 000000000..e30f68ee7
--- /dev/null
+++ b/fpga/usrp2/models/math_real.v
@@ -0,0 +1,495 @@
+/*

+ * This is a general recreation of the VHDL ieee.math_real package.

+ */

+ 

+module math_real ;

+   // Constants for use below and for general reference

+   // TODO: Bring it out to 12 (or more???) places beyond the decimal?

+   localparam MATH_E            =  2.7182818284;

+   localparam MATH_1_OVER_E     =  0.3678794411;

+   localparam MATH_PI           =  3.1415926536;

+   localparam MATH_2_PI         =  6.2831853071;

+   localparam MATH_1_OVER_PI    =  0.3183098861;

+   localparam MATH_PI_OVER_2    =  1.5707963267;

+   localparam MATH_PI_OVER_3    =  1.0471975511;

+   localparam MATH_PI_OVER_4    =  0.7853981633;

+   localparam MATH_3_PI_OVER_2  =  4.7123889803;

+   localparam MATH_LOG_OF_2     =  0.6931471805;

+   localparam MATH_LOG_OF_10    =  2.3025850929;

+   localparam MATH_LOG2_OF_E    =  1.4426950408;

+   localparam MATH_LOG10_OF_E   =  0.4342944819;

+   localparam MATH_SQRT_2       =  1.4142135623;

+   localparam MATH_1_OVER_SQRT_2=  0.7071067811;

+   localparam MATH_SQRT_PI      =  1.7724538509;

+   localparam MATH_DEG_TO_RAD   =  0.0174532925;

+   localparam MATH_RAD_TO_DEG   =  57.2957795130;

+

+   // The number of iterations to do for the Taylor series approximations

+   localparam EXPLOG_ITERATIONS =  19;

+   localparam COS_ITERATIONS    =  8;

+   

+   /* Conversion Routines */

+    

+   // Return the sign of a particular number.

+   function real sign ;

+      input real x ;

+      begin

+         sign = x < 0.0 ? 1.0 : 0.0 ;

+      end

+   endfunction

+   

+   // Return the trunc function of a number

+   function real trunc ;

+      input real x ;

+      begin

+         trunc = x - mod(x,1.0) ;

+      end

+   endfunction

+   

+   // Return the ceiling function of a number.

+   function real ceil ;

+      input real x ;

+      real retval ;

+      begin

+         retval = mod(x,1.0) ;

+         if( retval != 0.0 && x > 0.0 )  retval = x+1.0 ;

+         else retval = x ;

+         ceil = trunc(retval) ;

+      end

+   endfunction

+   

+   // Return the floor function of a number

+   function real floor ;

+      input real x ;

+      real retval ;

+      begin

+         retval = mod(x,1.0) ;

+         if( retval != 0.0 && x < 0.0 ) retval = x - 1.0 ;

+         else retval = x ;

+         floor = trunc(retval) ;

+      end

+   endfunction

+   

+   // Return the round function of a number

+   function real round ;

+      input real x ;

+      real retval ;

+      begin

+         retval = x > 0.0 ? x + 0.5 : x - 0.5 ;

+         round = trunc(retval) ;

+      end

+   endfunction

+   

+   // Return the fractional remainder of (x mod m)

+   function real mod ;

+      input real x ;

+      input real m ;

+      real retval ;

+      begin

+         retval = x ;

+         if( retval > m ) begin

+            while( retval > m ) begin

+               retval = retval - m ;

+            end

+         end

+         else begin

+            while( retval < -m ) begin

+               retval = retval + m ;

+            end

+         end

+         mod = retval ;

+      end

+   endfunction

+   

+   // Return the max between two real numbers

+   function real realmax ;

+      input real x ;

+      input real y ;

+      begin

+         realmax = x > y ? x : y ;

+      end

+   endfunction

+   

+   // Return the min between two real numbers

+   function real realmin ;

+      input real x ;

+      input real y ;

+      begin

+         realmin = x > y ? y : x ;

+      end

+   endfunction

+   

+   /* Random Numbers */

+   

+   // Generate Gaussian distributed variables

+   function real gaussian ;

+      input real mean ;

+      input real var ;

+      real u1, u2, v1, v2, s ;

+      begin

+         s = 1.0 ;

+         while( s >= 1.0  ) begin

+            // Two random numbers between 0 and 1

+            u1 = $random/4294967296.0 + 0.5 ;

+            u2 = $random/4294967296.0 + 0.5 ;

+            // Adjust to be between -1,1

+            v1 = 2*u1-1.0 ;

+            v2 = 2*u2-1.0 ;

+            // Polar mag squared

+            s = (v1*v1 + v2*v2) ;

+         end

+         gaussian = mean + sqrt((-2.0*log(s))/s) * v1 * sqrt(var) ;

+         // gaussian2 = mean + sqrt(-2*log(s)/s)*v2 * sqrt(var) ;

+      end

+   endfunction

+   

+   /* Roots and Log Functions */

+   

+   // Return the square root of a number

+   function real sqrt ;

+      input real x ;

+      real retval ;

+      begin

+         sqrt = (x == 0.0) ? 0.0 : powr(x,0.5) ;

+      end

+   endfunction

+   

+   // Return the cube root of a number

+   function real cbrt ;

+      input real x ;

+      real retval ;

+      begin

+         cbrt = (x == 0.0) ? 0.0 : powr(x,1.0/3.0) ;

+      end

+   endfunction

+   

+   // Return the absolute value of a real value

+   function real abs ;

+      input real x ;

+      begin

+         abs = (x > 0.0) ? x : -x ;

+      end

+   endfunction 

+   

+   // Return a real value raised to an integer power

+   function real pow ;

+      input real b ;

+      input integer x ;

+      integer absx ;

+      real retval ;

+      begin

+         retval = 1.0 ;

+         absx = abs(x) ;

+         repeat(absx) begin

+            retval = b*retval ;

+         end

+         pow = x < 0 ? (1.0/retval) : retval ;

+      end

+   endfunction

+   

+   // Return a real value raised to a real power

+   function real powr ;

+      input real b ;

+      input real x ;

+      begin

+         powr = exp(x*log(b)) ;

+      end

+   endfunction

+   

+   // Return the evaluation of e^x where e is the natural logarithm base

+   // NOTE: This is the Taylor series expansion of e^x

+   function real exp ;

+      input real x ;

+      real retval ;

+      integer i ;

+      real nm1_fact ;

+      real powm1 ;

+      begin

+         nm1_fact = 1.0 ;

+         powm1 = 1.0 ;

+         retval = 1.0 ;

+         for( i = 1 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin

+            powm1 = x*powm1 ;

+            nm1_fact = nm1_fact * i ;

+            retval = retval + powm1/nm1_fact ;

+         end

+         exp = retval ;

+      end

+   endfunction

+   

+   // Return the evaluation log(x)

+   function real log ;

+      input real x ;

+      integer i ;

+      real whole ;

+      real xm1oxp1 ;

+      real retval ;

+      real newx ;

+      begin

+         retval = 0.0 ;

+         whole = 0.0 ;

+         newx = x ;

+         while( newx > MATH_E ) begin

+            whole = whole + 1.0 ;

+            newx = newx / MATH_E ;

+         end

+         xm1oxp1 = (newx-1.0)/(newx+1.0) ;

+         for( i = 0 ; i < EXPLOG_ITERATIONS ; i = i + 1 ) begin

+            retval = retval + pow(xm1oxp1,2*i+1)/(2.0*i+1.0) ;

+         end

+         log = whole+2.0*retval ;

+      end

+   endfunction

+   

+   // Return the evaluation ln(x) (same as log(x))

+   function real ln ;

+      input real x ;

+      begin

+         ln = log(x) ;

+      end

+   endfunction

+   

+   // Return the evaluation log_2(x)

+   function real log2 ;

+      input real x ;

+      begin

+         log2 = log(x)/MATH_LOG_OF_2 ;

+      end

+   endfunction

+   

+   function real log10 ;

+      input real x ;

+      begin

+         log10 = log(x)/MATH_LOG_OF_10 ;

+      end

+   endfunction

+   

+   function real log_base ;

+      input real x ;

+      input real b ;

+      begin

+         log_base = log(x)/log(b) ;

+      end

+   endfunction

+   

+   /* Trigonometric Functions */

+   

+   // Internal function to reduce a value to be between [-pi:pi]

+   function real reduce ;

+      input real x ;

+      real retval ;

+      begin

+         retval = x ;

+         while( abs(retval) > MATH_PI ) begin

+            retval = retval > MATH_PI ? 

+                     (retval - MATH_2_PI) : 

+                     (retval + MATH_2_PI) ;

+         end

+         reduce = retval ;

+      end

+   endfunction

+   

+   // Return the cos of a number in radians

+   function real cos ;

+      input real x ;

+      integer i ;

+      integer sign ;

+      real newx ;

+      real retval ;

+      real xsqnm1 ;

+      real twonm1fact ;

+      begin

+         newx = reduce(x) ;

+         xsqnm1 = 1.0 ;

+         twonm1fact = 1.0 ;

+         retval = 1.0 ;

+         for( i = 1 ; i < COS_ITERATIONS ; i = i + 1 ) begin

+            sign = -2*(i % 2)+1 ;

+            xsqnm1 = xsqnm1*newx*newx ;

+            twonm1fact = twonm1fact * (2.0*i) * (2.0*i-1.0) ;

+            retval = retval + sign*(xsqnm1/twonm1fact) ; 

+         end

+         cos = retval ;

+      end

+   endfunction

+   

+   // Return the sin of a number in radians

+   function real sin ;

+      input real x ;

+      begin

+         sin = cos(x - MATH_PI_OVER_2) ;

+      end

+   endfunction

+   

+   // Return the tan of a number in radians

+   function real tan ;

+      input real x ;

+      begin

+         tan = sin(x) / cos(x) ;

+      end

+   endfunction

+   

+   // Return the arcsin in radians of a number

+   function real arcsin ;

+      input real x ;

+      begin

+         arcsin = 2.0*arctan(x/(1.0+sqrt(1.0-x*x))) ;

+      end

+   endfunction

+   

+   // Return the arccos in radians of a number

+   function real arccos ;

+      input real x ;

+      begin

+         arccos = MATH_PI_OVER_2-arcsin(x) ;

+      end

+   endfunction

+   

+   // Return the arctan in radians of a number

+   // TODO: Make sure this REALLY does work as it is supposed to!

+   function real arctan ;

+      input real x ;

+      real retval ;

+      real y ;

+      real newx ;

+      real twoiotwoip1 ;

+      integer i ;

+      integer mult ;

+      begin

+         retval = 1.0 ;

+         twoiotwoip1 = 1.0 ;

+         mult = 1 ;

+         newx = abs(x) ;

+         while( newx > 1.0 ) begin

+            mult = mult*2 ;

+            newx = newx/(1.0+sqrt(1.0+newx*newx)) ;

+         end

+         y = 1.0 ;

+         for( i = 1 ; i < 2*COS_ITERATIONS ; i = i + 1 ) begin

+            y = y*((newx*newx)/(1+newx*newx)) ;

+            twoiotwoip1 = twoiotwoip1 * (2.0*i)/(2.0*i+1.0) ;

+            retval = retval + twoiotwoip1*y ;

+         end

+         retval = retval * (newx/(1+newx*newx)) ;

+         retval = retval * mult ;

+         

+         arctan = (x > 0.0) ? retval : -retval ;

+      end

+   endfunction

+   

+   // Return the arctan in radians of a ratio x/y

+   // TODO: Test to make sure this works as it is supposed to!

+   function real arctan_xy ;

+      input real x ;

+      input real y ;

+      real retval ;

+      begin

+         retval = 0.0 ;

+         if( x < 0.0 ) retval = MATH_PI - arctan(-abs(y)/x) ;

+         else if( x > 0.0 ) retval = arctan(abs(y)/x) ;

+         else if( x == 0.0 ) retval = MATH_PI_OVER_2 ;

+         arctan_xy = (y < 0.0) ? -retval : retval ;

+      end

+   endfunction

+   

+   /* Hyperbolic Functions */

+   

+   // Return the sinh of a number

+   function real sinh ;

+      input real x ;

+      begin

+         sinh = (exp(x) - exp(-x))/2.0 ;

+      end

+   endfunction

+   

+   // Return the cosh of a number

+   function real cosh ;

+      input real x ;

+      begin

+         cosh = (exp(x) + exp(-x))/2.0 ;

+      end

+   endfunction

+   

+   // Return the tanh of a number

+   function real tanh ;

+      input real x ;

+      real e2x ;

+      begin

+         e2x = exp(2.0*x) ;

+         tanh = (e2x+1.0)/(e2x-1.0) ;

+      end

+   endfunction

+   

+   // Return the arcsinh of a number

+   function real arcsinh ;

+      input real x ;

+      begin

+         arcsinh = log(x+sqrt(x*x+1.0)) ;

+      end

+   endfunction

+   

+   // Return the arccosh of a number

+   function real arccosh ;

+      input real x ;

+      begin

+         arccosh = ln(x+sqrt(x*x-1.0)) ;

+      end

+   endfunction

+   

+   // Return the arctanh of a number

+   function real arctanh ;

+      input real x ;

+      begin

+         arctanh = 0.5*ln((1.0+x)/(1.0-x)) ;

+      end

+   endfunction

+   /*

+    initial begin

+    $display( "cos(MATH_PI_OVER_3): %f", cos(MATH_PI_OVER_3) ) ;

+    $display( "sin(MATH_PI_OVER_3): %f", sin(MATH_PI_OVER_3) ) ;

+    $display( "sign(-10): %f", sign(-10) ) ;

+    $display( "realmax(MATH_PI,MATH_E): %f", realmax(MATH_PI,MATH_E) ) ;

+    $display( "realmin(MATH_PI,MATH_E): %f", realmin(MATH_PI,MATH_E) ) ;

+    $display( "mod(MATH_PI,MATH_E): %f", mod(MATH_PI,MATH_E) ) ;

+    $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ;

+    $display( "ceil(4.0): %f", ceil(4.0) ) ;

+    $display( "ceil(3.99999999999999): %f", ceil(3.99999999999999) ) ;

+    $display( "pow(MATH_PI,2): %f", pow(MATH_PI,2) ) ;

+    $display( "gaussian(1.0,1.0): %f", gaussian(1.0,1.0) ) ;

+    $display( "round(MATH_PI): %f", round(MATH_PI) ) ;

+    $display( "trunc(-MATH_PI): %f", trunc(-MATH_PI) ) ;

+    $display( "ceil(-MATH_PI): %f", ceil(-MATH_PI) ) ;

+    $display( "floor(MATH_PI): %f", floor(MATH_PI) ) ;

+    $display( "round(e): %f", round(MATH_E)) ;

+    $display( "ceil(-e): %f", ceil(-MATH_E)) ;

+    $display( "exp(MATH_PI): %f", exp(MATH_PI) ) ;

+    $display( "log2(MATH_PI): %f", log2(MATH_PI) ) ;

+    $display( "log_base(pow(2,32),2): %f", log_base(pow(2,32),2) ) ;

+    $display( "ln(0.1): %f", log(0.1) ) ;

+    $display( "cbrt(7): %f", cbrt(7) ) ;

+    $display( "cos(MATH_2_PI): %f", cos(20*MATH_2_PI) ) ;

+    $display( "sin(-MATH_2_PI): %f", sin(-50*MATH_2_PI) ) ;

+    $display( "sinh(MATH_E): %f", sinh(MATH_E) ) ;

+    $display( "cosh(MATH_2_PI): %f", cosh(MATH_2_PI) ) ;

+    $display( "arctan_xy(-4,3): %f", arctan_xy(-4,3) ) ;

+    $display( "arctan(MATH_PI): %f", arctan(MATH_PI) ) ;

+    $display( "arctan(-MATH_E/2): %f", arctan(-MATH_E/2) ) ;

+    $display( "arctan(MATH_PI_OVER_2): %f", arctan(MATH_PI_OVER_2) ) ;

+    $display( "arctan(1/7) = %f", arctan(1.0/7.0) ) ;

+    $display( "arctan(3/79) = %f", arctan(3.0/79.0) ) ;

+    $display( "pi/4 ?= %f", 5*arctan(1.0/7.0)+2*arctan(3.0/79.0) ) ;

+    $display( "arcsin(1.0): %f", arcsin(1.0) ) ;

+    $display( "cos(pi/2): %f", cos(MATH_PI_OVER_2)) ;

+    $display( "arccos(cos(pi/2)): %f", arccos(cos(MATH_PI_OVER_2)) ) ;

+    $display( "cos(0): %f", cos(0) ) ;

+    $display( "cos(MATH_PI_OVER_4): %f", cos(MATH_PI_OVER_4) ) ;

+    $display( "cos(MATH_PI_OVER_2): %f", cos(MATH_PI_OVER_2) ) ;

+    $display( "cos(3*MATH_PI_OVER_4): %f", cos(3*MATH_PI_OVER_4) ) ;

+    $display( "cos(MATH_PI): %f", cos(MATH_PI) ) ;

+    $display( "cos(5*MATH_PI_OVER_4): %f", cos(5*MATH_PI_OVER_4) ) ;

+    $display( "cos(6*MATH_PI_OVER_4): %f", cos(6*MATH_PI_OVER_4) ) ;

+    $display( "cos(7*MATH_PI_OVER_4): %f", cos(7*MATH_PI_OVER_4) ) ;

+    $display( "cos(8*MATH_PI_OVER_4): %f", cos(8*MATH_PI_OVER_4) ) ;

+    end*/

+   

+endmodule

diff --git a/fpga/usrp2/models/miim_model.v b/fpga/usrp2/models/miim_model.v
new file mode 100644
index 000000000..936d99a80
--- /dev/null
+++ b/fpga/usrp2/models/miim_model.v
@@ -0,0 +1,14 @@
+
+// Skeleton PHY interface simulator
+
+module miim_model(input mdc_i, 
+		  inout mdio, 
+		  input phy_resetn_i, 
+		  input phy_clk_i, 
+		  output phy_intn_o,
+		  output [2:0] speed_o);
+
+   assign 		       phy_intn_o = 1;    // No interrupts
+   assign 		       speed_o = 3'b100;  // 1G mode
+   
+endmodule // miim_model
diff --git a/fpga/usrp2/models/phy_sim.v b/fpga/usrp2/models/phy_sim.v
new file mode 100644
index 000000000..b3de19b04
--- /dev/null
+++ b/fpga/usrp2/models/phy_sim.v
@@ -0,0 +1,113 @@
+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+////  Phy_sim.v                                                   ////

+////                                                              ////

+////  This file is part of the Ethernet IP core project           ////

+////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////

+////                                                              ////

+////  Author(s):                                                  ////

+////      - Jon Gao (gaojon@yahoo.com)                            ////

+////                                                              ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+//// Copyright (C) 2001 Authors                                   ////

+////                                                              ////

+//// This source file may be used and distributed without         ////

+//// restriction provided that this copyright statement is not    ////

+//// removed from the file and that any derivative work contains  ////

+//// the original copyright notice and the associated disclaimer. ////

+////                                                              ////

+//// This source file is free software; you can redistribute it   ////

+//// and/or modify it under the terms of the GNU Lesser General   ////

+//// Public License as published by the Free Software Foundation; ////

+//// either version 2.1 of the License, or (at your option) any   ////

+//// later version.                                               ////

+////                                                              ////

+//// This source is distributed in the hope that it will be       ////

+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

+//// PURPOSE.  See the GNU Lesser General Public License for more ////

+//// details.                                                     ////

+////                                                              ////

+//// You should have received a copy of the GNU Lesser General    ////

+//// Public License along with this source; if not, download it   ////

+//// from http://www.opencores.org/lgpl.shtml                     ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+//                                                                    

+// CVS Revision History                                               

+//                                                                    

+// $Log: Phy_sim.v,v $

+// Revision 1.3  2006/11/17 17:53:07  maverickist

+// no message

+//

+// Revision 1.2  2006/01/19 14:07:50  maverickist

+// verification is complete.

+//

+// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator

+// no message

+// 

+

+`timescale 1ns/100ps 

+

+module phy_sim(

+  input        Gtx_clk, // Used only in GMII mode

+  output       Rx_clk,

+  output       Tx_clk, // Used only in MII mode

+  input        Tx_er,

+  input        Tx_en,

+  input  [7:0] Txd,

+  output       Rx_er,

+  output       Rx_dv,

+  output [7:0] Rxd,

+  output       Crs,

+  output       Col,

+  input  [2:0] Speed,

+  input        Done

+);

+

+//////////////////////////////////////////////////////////////////////

+// this file used to simulate Phy.

+// generate clk and loop the Tx data to Rx data

+// full duplex mode can be verified on loop mode.

+//////////////////////////////////////////////////////////////////////

+//////////////////////////////////////////////////////////////////////

+// internal signals

+//////////////////////////////////////////////////////////////////////

+reg Clk_25m;  // Used for 100 Mbps mode

+reg Clk_2_5m; // Used for 10 Mbps mode

+

+//wire Rx_clk;

+//wire Tx_clk; // Used only in MII mode

+

+  initial 

+    begin

+      #10;

+      while ( !Done )

+        begin

+          #20 Clk_25m = 0;

+          #20 Clk_25m = 1;

+        end

+    end

+

+  initial 

+    begin

+      #10;

+      while ( !Done )

+        begin

+          #200 Clk_2_5m = 0;

+          #200 Clk_2_5m = 1;

+        end

+    end

+

+  assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;        

+  assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;

+

+  assign Rx_dv = Tx_en;

+  assign Rxd   = Txd;

+  assign Rx_er = Tx_er;

+  assign Crs   = Tx_en;

+  assign Col   = 0;

+

+endmodule

diff --git a/fpga/usrp2/models/serdes_model.v b/fpga/usrp2/models/serdes_model.v
new file mode 100644
index 000000000..f10e55554
--- /dev/null
+++ b/fpga/usrp2/models/serdes_model.v
@@ -0,0 +1,34 @@
+
+module serdes_model
+  (input ser_tx_clk,
+   input ser_tkmsb,
+   input ser_tklsb,
+   input [15:0] ser_t,
+   
+   output ser_rx_clk,
+   output ser_rkmsb,
+   output ser_rklsb,
+   output [15:0] ser_r,
+   
+   input even,
+   input error);
+   
+   wire [15:0] ser_r_odd;
+   wire  ser_rklsb_odd, ser_rkmsb_odd;   
+   
+   reg [7:0] hold_dat;
+   reg 	     hold_k;
+   
+   always @(posedge ser_tx_clk) hold_k <= ser_tklsb;
+   always @(posedge ser_tx_clk) hold_dat <= ser_t[15:8];
+   assign    ser_rklsb_odd = hold_k;
+   assign    ser_rkmsb_odd = ser_tklsb;
+   assign    ser_r_odd = {ser_t[7:0], hold_dat};
+   
+   // Set outputs
+   assign    ser_rx_clk = ser_tx_clk;
+   assign    ser_rkmsb = even ? ser_tkmsb : ser_rkmsb_odd;
+   assign    ser_rklsb = even ? ser_tklsb : ser_rklsb_odd;
+   assign    ser_r = error ^ (even ? ser_t : ser_r_odd);
+   
+endmodule // serdes_model
diff --git a/fpga/usrp2/models/uart_rx.v b/fpga/usrp2/models/uart_rx.v
new file mode 100644
index 000000000..f698a50fe
--- /dev/null
+++ b/fpga/usrp2/models/uart_rx.v
@@ -0,0 +1,48 @@
+
+
+// Simple printout of characters from the UART
+//   Only does 8N1, requires the baud clock
+
+module uart_rx (input baudclk, input rxd);
+   reg [8:0] sr = 9'b0;
+   reg [3:0]  baud_ctr = 4'b0;
+
+   /*
+   wire       byteclk = baud_ctr[3];
+   reg 	      rxd_d1 = 0;
+   always @(posedge baudclk)
+     rxd_d1 <= rxd;
+   
+   always @(posedge baudclk)
+     if(rxd_d1 != rxd)
+       baud_ctr <= 0;
+     else
+       baud_ctr <= baud_ctr + 1;
+*/
+
+   wire       byteclk = baudclk;
+   
+   always @(posedge byteclk)
+     sr <= { rxd, sr[8:1] };
+
+   reg [3:0]  state = 0;
+   always @(posedge byteclk)
+     case(state)
+       0 : 
+	 if(~sr[8] & sr[7])  // found start bit
+	   state  <= 1;
+       1, 2, 3, 4, 5, 6, 7, 8 :
+	 state <= state + 1;
+       9 : 
+	 begin
+	    state <= 0;
+	    $write("%c",sr[7:0]);
+	    if(~sr[8])
+	      $display("Error, no stop bit\n");
+	 end
+       default :
+	 state <= 0;
+     endcase // case(state)
+
+endmodule // uart_rx
+
diff --git a/fpga/usrp2/models/xlnx_glbl.v b/fpga/usrp2/models/xlnx_glbl.v
new file mode 100644
index 000000000..662a60e35
--- /dev/null
+++ b/fpga/usrp2/models/xlnx_glbl.v
@@ -0,0 +1,29 @@
+module xlnx_glbl

+(

+  GSR,

+  GTS

+);

+

+  //--------------------------------------------------------------------------

+  // Parameters

+  //--------------------------------------------------------------------------

+

+  //--------------------------------------------------------------------------

+  // IO declarations

+  //--------------------------------------------------------------------------

+

+  output GSR;

+  output GTS;

+

+  //--------------------------------------------------------------------------

+  // Local declarations

+  //--------------------------------------------------------------------------

+

+  //--------------------------------------------------------------------------

+  // Internal declarations

+  //--------------------------------------------------------------------------

+

+  assign GSR = 0;

+  assign GTS = 0;

+  

+endmodule

diff --git a/fpga/usrp2/opencores/8b10b/.gitignore b/fpga/usrp2/opencores/8b10b/.gitignore
new file mode 100644
index 000000000..548539d61
--- /dev/null
+++ b/fpga/usrp2/opencores/8b10b/.gitignore
@@ -0,0 +1,2 @@
+/dump.vcd
+/a.out
diff --git a/fpga/usrp2/opencores/8b10b/8b10b_a.mem b/fpga/usrp2/opencores/8b10b/8b10b_a.mem
new file mode 100644
index 000000000..1761d74f6
--- /dev/null
+++ b/fpga/usrp2/opencores/8b10b/8b10b_a.mem
@@ -0,0 +1,268 @@
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+011010011110010011011001001100
+011010100001011011000101101100
+011010101101010011010101001100
+011010110011010011001101001100
+011010111111010011000010101101
+011011000110011011000110001101
+011011001100110011010011001100
+011011010010110011001011001100
+011011011110110011000100101101
+011011100001110011000111001100
+011011101101110011001000101101
+011011110011110011010000101101
+011011111101011011001010001101
+011100000100111000101100011100
+011100001011101000110001011100
+011100010101101000101001011100
+011100011110001111011000100011
+011100100110101000100101011100
+011100101101001111010100100011
+011100110011001111001100100011
+011100111111000111000011100011
+011101000111001000100011011100
+011101001100101111010010100011
+011101010010101111001010100011
+011101011110100111011010010001
+011101100001101111000110100011
+011101101101100111010110010001
+011101110011100111001110010001
+011101111010111000110100011100
+011110000011011000110010011100
+011110001100011011110001100011
+011110010010011011101001100011
+011110011110010111011001000011
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+011111101101110000101000111100
+011111110011110000110000111100
+011111111101011000101010011100
+100011100001111010011000010110
+100111100001111100111000001101
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+101111100001111001111000011001
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+111011100001111011011000010011
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diff --git a/fpga/usrp2/opencores/8b10b/README b/fpga/usrp2/opencores/8b10b/README
new file mode 100644
index 000000000..7bce294ac
--- /dev/null
+++ b/fpga/usrp2/opencores/8b10b/README
@@ -0,0 +1,4 @@
+These files are not actually from OpenCores.  They are from 
+Chuck Benz.  See http://asics.chuckbenz.com
+
+
diff --git a/fpga/usrp2/opencores/8b10b/decode_8b10b.v b/fpga/usrp2/opencores/8b10b/decode_8b10b.v
new file mode 100644
index 000000000..0b2a8ac59
--- /dev/null
+++ b/fpga/usrp2/opencores/8b10b/decode_8b10b.v
@@ -0,0 +1,165 @@
+// Chuck Benz, Hollis, NH   Copyright (c)2002
+//
+// The information and description contained herein is the
+// property of Chuck Benz.
+//
+// Permission is granted for any reuse of this information
+// and description as long as this copyright notice is
+// preserved.  Modifications may be made as long as this
+// notice is preserved.
+
+// per Widmer and Franaszek
+
+module decode_8b10b (datain, dispin, dataout, dispout, code_err, disp_err) ;
+  input [9:0]   datain ;
+  input		dispin ;
+  output [8:0]	dataout ;
+  output	dispout ;
+  output	code_err ;
+  output	disp_err ;
+
+  wire ai = datain[0] ;
+  wire bi = datain[1] ;
+  wire ci = datain[2] ;
+  wire di = datain[3] ;
+  wire ei = datain[4] ;
+  wire ii = datain[5] ;
+  wire fi = datain[6] ;
+  wire gi = datain[7] ;
+  wire hi = datain[8] ;
+  wire ji = datain[9] ;
+
+  wire aeqb = (ai & bi) | (!ai & !bi) ;
+  wire ceqd = (ci & di) | (!ci & !di) ;
+  wire p22 = (ai & bi & !ci & !di) |
+	     (ci & di & !ai & !bi) |
+	     ( !aeqb & !ceqd) ;
+  wire p13 = ( !aeqb & !ci & !di) |
+	     ( !ceqd & !ai & !bi) ;
+  wire p31 = ( !aeqb & ci & di) |
+	     ( !ceqd & ai & bi) ;
+
+  wire p40 = ai & bi & ci & di ;
+  wire p04 = !ai & !bi & !ci & !di ;
+
+  wire disp6a = p31 | (p22 & dispin) ; // pos disp if p22 and was pos, or p31.
+   wire disp6a2 = p31 & dispin ;  // disp is ++ after 4 bits
+   wire disp6a0 = p13 & ! dispin ; // -- disp after 4 bits
+    
+  wire disp6b = (((ei & ii & ! disp6a0) | (disp6a & (ei | ii)) | disp6a2 |
+		  (ei & ii & di)) & (ei | ii | di)) ;
+
+  // The 5B/6B decoding special cases where ABCDE != abcde
+
+  wire p22bceeqi = p22 & bi & ci & (ei == ii) ;
+  wire p22bncneeqi = p22 & !bi & !ci & (ei == ii) ;
+  wire p13in = p13 & !ii ;
+  wire p31i = p31 & ii ;
+  wire p13dei = p13 & di & ei & ii ;
+  wire p22aceeqi = p22 & ai & ci & (ei == ii) ;
+  wire p22ancneeqi = p22 & !ai & !ci & (ei == ii) ;
+  wire p13en = p13 & !ei ;
+  wire anbnenin = !ai & !bi & !ei & !ii ;
+  wire abei = ai & bi & ei & ii ;
+  wire cdei = ci & di & ei & ii ;
+  wire cndnenin = !ci & !di & !ei & !ii ;
+
+  // non-zero disparity cases:
+  wire p22enin = p22 & !ei & !ii ;
+  wire p22ei = p22 & ei & ii ;
+  //wire p13in = p12 & !ii ;
+  //wire p31i = p31 & ii ;
+  wire p31dnenin = p31 & !di & !ei & !ii ;
+  //wire p13dei = p13 & di & ei & ii ;
+  wire p31e = p31 & ei ;
+
+  wire compa = p22bncneeqi | p31i | p13dei | p22ancneeqi | 
+		p13en | abei | cndnenin ;
+  wire compb = p22bceeqi | p31i | p13dei | p22aceeqi | 
+		p13en | abei | cndnenin ;
+  wire compc = p22bceeqi | p31i | p13dei | p22ancneeqi | 
+		p13en | anbnenin | cndnenin ;
+  wire compd = p22bncneeqi | p31i | p13dei | p22aceeqi |
+		p13en | abei | cndnenin ;
+  wire compe = p22bncneeqi | p13in | p13dei | p22ancneeqi | 
+		p13en | anbnenin | cndnenin ;
+
+  wire ao = ai ^ compa ;
+  wire bo = bi ^ compb ;
+  wire co = ci ^ compc ;
+  wire do = di ^ compd ;
+  wire eo = ei ^ compe ;
+
+  wire feqg = (fi & gi) | (!fi & !gi) ;
+  wire heqj = (hi & ji) | (!hi & !ji) ;
+  wire fghj22 = (fi & gi & !hi & !ji) |
+		(!fi & !gi & hi & ji) |
+		( !feqg & !heqj) ;
+  wire fghjp13 = ( !feqg & !hi & !ji) |
+		 ( !heqj & !fi & !gi) ;
+  wire fghjp31 = ( (!feqg) & hi & ji) |
+		 ( !heqj & fi & gi) ;
+
+  wire dispout = (fghjp31 | (disp6b & fghj22) | (hi & ji)) & (hi | ji) ;
+
+  wire ko = ( (ci & di & ei & ii) | ( !ci & !di & !ei & !ii) |
+		(p13 & !ei & ii & gi & hi & ji) |
+		(p31 & ei & !ii & !gi & !hi & !ji)) ;
+
+  wire alt7 =   (fi & !gi & !hi & // 1000 cases, where disp6b is 1
+		 ((dispin & ci & di & !ei & !ii) | ko |
+		  (dispin & !ci & di & !ei & !ii))) |
+		(!fi & gi & hi & // 0111 cases, where disp6b is 0
+		 (( !dispin & !ci & !di & ei & ii) | ko |
+		  ( !dispin & ci & !di & ei & ii))) ;
+
+  wire k28 = (ci & di & ei & ii) | ! (ci | di | ei | ii) ;
+  // k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
+  wire k28p = ! (ci | di | ei | ii) ;
+  wire fo = (ji & !fi & (hi | !gi | k28p)) |
+	    (fi & !ji & (!hi | gi | !k28p)) |
+	    (k28p & gi & hi) |
+	    (!k28p & !gi & !hi) ;
+  wire go = (ji & !fi & (hi | !gi | !k28p)) |
+	    (fi & !ji & (!hi | gi |k28p)) |
+	    (!k28p & gi & hi) |
+	    (k28p & !gi & !hi) ;
+  wire ho = ((ji ^ hi) & ! ((!fi & gi & !hi & ji & !k28p) | (!fi & gi & hi & !ji & k28p) | 
+			    (fi & !gi & !hi & ji & !k28p) | (fi & !gi & hi & !ji & k28p))) |
+	    (!fi & gi & hi & ji) | (fi & !gi & !hi & !ji) ;
+
+  wire disp6p = (p31 & (ei | ii)) | (p22 & ei & ii) ;
+  wire disp6n = (p13 & ! (ei & ii)) | (p22 & !ei & !ii) ;
+  wire disp4p = fghjp31 ;
+  wire disp4n = fghjp13 ;
+
+  assign code_err = p40 | p04 | (fi & gi & hi & ji) | (!fi & !gi & !hi & !ji) |
+		    (p13 & !ei & !ii) | (p31 & ei & ii) | 
+		    (ei & ii & fi & gi & hi) | (!ei & !ii & !fi & !gi & !hi) | 
+		    (ei & !ii & gi & hi & ji) | (!ei & ii & !gi & !hi & !ji) |
+		    (!p31 & ei & !ii & !gi & !hi & !ji) |
+		    (!p13 & !ei & ii & gi & hi & ji) |
+		    (((ei & ii & !gi & !hi & !ji) | 
+		      (!ei & !ii & gi & hi & ji)) &
+		     ! ((ci & di & ei) | (!ci & !di & !ei))) |
+		    (disp6p & disp4p) | (disp6n & disp4n) |
+		    (ai & bi & ci & !ei & !ii & ((!fi & !gi) | fghjp13)) |
+		    (!ai & !bi & !ci & ei & ii & ((fi & gi) | fghjp31)) |
+		    (fi & gi & !hi & !ji & disp6p) |
+		    (!fi & !gi & hi & ji & disp6n) |
+		    (ci & di & ei & ii & !fi & !gi & !hi) |
+		    (!ci & !di & !ei & !ii & fi & gi & hi) ;
+
+  assign dataout = {ko, ho, go, fo, eo, do, co, bo, ao} ;
+
+  // my disp err fires for any legal codes that violate disparity, may fire for illegal codes
+   assign disp_err = ((dispin & disp6p) | (disp6n & !dispin) |
+		      (dispin & !disp6n & fi & gi) |
+		      (dispin & ai & bi & ci) |
+		      (dispin & !disp6n & disp4p) |
+		      (!dispin & !disp6p & !fi & !gi) |
+		      (!dispin & !ai & !bi & !ci) |
+		      (!dispin & !disp6p & disp4n) |
+		      (disp6p & disp4p) | (disp6n & disp4n)) ;
+
+endmodule
diff --git a/fpga/usrp2/opencores/8b10b/encode_8b10b.v b/fpga/usrp2/opencores/8b10b/encode_8b10b.v
new file mode 100644
index 000000000..c1f09b9ce
--- /dev/null
+++ b/fpga/usrp2/opencores/8b10b/encode_8b10b.v
@@ -0,0 +1,120 @@
+// Chuck Benz, Hollis, NH   Copyright (c)2002
+//
+// The information and description contained herein is the
+// property of Chuck Benz.
+//
+// Permission is granted for any reuse of this information
+// and description as long as this copyright notice is
+// preserved.  Modifications may be made as long as this
+// notice is preserved.
+
+// per Widmer and Franaszek
+
+module encode_8b10b (datain, dispin, dataout, dispout) ;
+  input [8:0]   datain ;
+  input 	dispin ;  // 0 = neg disp; 1 = pos disp
+  output [9:0]	dataout ;
+  output	dispout ;
+
+
+  wire ai = datain[0] ;
+  wire bi = datain[1] ;
+  wire ci = datain[2] ;
+  wire di = datain[3] ;
+  wire ei = datain[4] ;
+  wire fi = datain[5] ;
+  wire gi = datain[6] ;
+  wire hi = datain[7] ;
+  wire ki = datain[8] ;
+
+  wire aeqb = (ai & bi) | (!ai & !bi) ;
+  wire ceqd = (ci & di) | (!ci & !di) ;
+  wire l22 = (ai & bi & !ci & !di) |
+	     (ci & di & !ai & !bi) |
+	     ( !aeqb & !ceqd) ;
+  wire l40 = ai & bi & ci & di ;
+  wire l04 = !ai & !bi & !ci & !di ;
+  wire l13 = ( !aeqb & !ci & !di) |
+	     ( !ceqd & !ai & !bi) ;
+  wire l31 = ( !aeqb & ci & di) |
+	     ( !ceqd & ai & bi) ;
+
+  // The 5B/6B encoding
+
+  wire ao = ai ;
+  wire bo = (bi & !l40) | l04 ;
+  wire co = l04 | ci | (ei & di & !ci & !bi & !ai) ;
+  wire do = di & ! (ai & bi & ci) ;
+  wire eo = (ei | l13) & ! (ei & di & !ci & !bi & !ai) ;
+  wire io = (l22 & !ei) |
+	    (ei & !di & !ci & !(ai&bi)) |  // D16, D17, D18
+	    (ei & l40) |
+	    (ki & ei & di & ci & !bi & !ai) | // K.28
+	    (ei & !di & ci & !bi & !ai) ;
+
+  // pds16 indicates cases where d-1 is assumed + to get our encoded value
+  wire pd1s6 = (ei & di & !ci & !bi & !ai) | (!ei & !l22 & !l31) ;
+  // nds16 indicates cases where d-1 is assumed - to get our encoded value
+  wire nd1s6 = ki | (ei & !l22 & !l13) | (!ei & !di & ci & bi & ai) ;
+
+  // ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
+  wire ndos6 = pd1s6 ;
+  // pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
+  wire pdos6 = ki | (ei & !l22 & !l13) ;
+
+
+  // some Dx.7 and all Kx.7 cases result in run length of 5 case unless
+  // an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
+  // specifically, D11, D13, D14, D17, D18, D19.
+  wire alt7 = fi & gi & hi & (ki | 
+			      (dispin ? (!ei & di & l31) : (ei & !di & l13))) ;
+
+   
+  wire fo = fi & ! alt7 ;
+  wire go = gi | (!fi & !gi & !hi) ;
+  wire ho = hi ;
+  wire jo = (!hi & (gi ^ fi)) | alt7 ;
+
+  // nd1s4 is cases where d-1 is assumed - to get our encoded value
+  wire nd1s4 = fi & gi ;
+  // pd1s4 is cases where d-1 is assumed + to get our encoded value
+  wire pd1s4 = (!fi & !gi) | (ki & ((fi & !gi) | (!fi & gi))) ;
+
+  // ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
+  wire ndos4 = (!fi & !gi) ;
+  // pdos4 is nd1s4 cases where d-1 is - yields + disp out 
+  wire pdos4 = fi & gi & hi ;
+
+  // only legal K codes are K28.0->.7, K23/27/29/30.7
+  //	K28.0->7 is ei=di=ci=1,bi=ai=0
+  //	K23 is 10111
+  //	K27 is 11011
+  //	K29 is 11101
+  //	K30 is 11110 - so K23/27/29/30 are ei & l31
+  wire illegalk = ki & 
+		  (ai | bi | !ci | !di | !ei) & // not K28.0->7
+		  (!fi | !gi | !hi | !ei | !l31) ; // not K23/27/29/30.7
+
+  // now determine whether to do the complementing
+  // complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
+  wire compls6 = (pd1s6 & !dispin) | (nd1s6 & dispin) ;
+
+  // disparity out of 5b6b is disp in with pdso6 and ndso6
+  // pds16 indicates cases where d-1 is assumed + to get our encoded value
+  // ndos6 is cases where d-1 is + yields - disp out
+  // nds16 indicates cases where d-1 is assumed - to get our encoded value
+  // pdos6 is cases where d-1 is - yields + disp out
+  // disp toggles in all ndis16 cases, and all but that 1 nds16 case
+
+  wire disp6 = dispin ^ (ndos6 | pdos6) ;
+
+  wire compls4 = (pd1s4 & !disp6) | (nd1s4 & disp6) ;
+  assign dispout = disp6 ^ (ndos4 | pdos4) ;
+
+  assign dataout = {(jo ^ compls4), (ho ^ compls4),
+		    (go ^ compls4), (fo ^ compls4),
+		    (io ^ compls6), (eo ^ compls6),
+		    (do ^ compls6), (co ^ compls6),
+		    (bo ^ compls6), (ao ^ compls6)} ;
+
+endmodule
diff --git a/fpga/usrp2/opencores/8b10b/validate_8b10b.v b/fpga/usrp2/opencores/8b10b/validate_8b10b.v
new file mode 100644
index 000000000..926b1081d
--- /dev/null
+++ b/fpga/usrp2/opencores/8b10b/validate_8b10b.v
@@ -0,0 +1,168 @@
+// Chuck Benz, Hollis, NH   Copyright (c)2002
+//
+// The information and description contained herein is the
+// property of Chuck Benz.
+//
+// Permission is granted for any reuse of this information
+// and description as long as this copyright notice is
+// preserved.  Modifications may be made as long as this
+// notice is preserved.
+
+// 11-OCT-2002: updated with clearer messages, and checking decodeout
+
+`timescale 1ns / 1ns
+module test_8b10b ;
+   reg [29:0]	code8b10b [0:267] ;
+   reg [8:0] 	testin ;
+   reg 		dispin ;
+   reg [10:0] 	i ;
+   wire [9:0] 	testout ;
+   wire 	dispout, decodedisp, decodeerr, disperr ;
+   wire [8:0] 	decodeout ;
+   // My data file is 30 columns. Column 1 becomes [29], 2 becomes [28], etc..
+   // code[0] is last Column (30)
+   // First column, [29] is K indication
+   // columns 2:9, [28:21], are data byte, aka 'm' and 'n' of Dm.n
+   // columns 10:19, [20:11] are 10b symbol if starting disparity was negative, 0
+   // columns 20:29, [10:1] are 10b symbol if starting disparity was positive, 1
+   // column 30, [0], is a 1 if symbol results in a disparity flip
+   //   0 for a balanced symbol (5 '1's, 5 '0's).
+
+   wire [29:0] 	code = code8b10b[i] ;
+   wire [9:0] 	expect_0_disp = {code[11], code[12], code[13], code[14], code[15],
+				 code[16], code[17], code[18], code[19], code[20]} ;
+   wire [9:0] 	expect_1_disp = {code[1], code[2], code[3], code[4], code[5],
+				 code[6], code[7], code[8], code[9], code[10]} ;
+
+   reg [1023:0] legal ;  // mark every used 10b symbol as legal, leave rest marked as not
+   reg [2047:0] okdisp ; // now mark every used combination of symbol and starting disparity
+   reg [8:0] 	mapcode [1023:0] ;
+   reg [10:0] 	codedisp0, codedisp1 ;
+   reg [9:0] 	decodein ;
+   reg 		decdispin ;
+   integer 	errors ;
+
+   encode_8b10b DUTE (testin, dispin, testout, dispout) ;
+   decode_8b10b DUTD (decodein, decdispin, decodeout, decodedisp, decodeerr, disperr) ;
+
+   always @ (code) testin = code[29:21] ;
+   
+   initial begin 
+      errors = 0 ;
+      $readmemb ("8b10b_a.mem", code8b10b) ;
+      //$vcdpluson ;
+      $dumpvars (0);
+      $display ("\n\nFirst, test by trying all 268 (256 Dx.y and 12 Kx.y)") ;
+      $display ("valid inputs, with both + and - starting disparity.");
+      $display ("We check that the encoder output and ending disparity is correct.");
+      $display ("We also check that the decoder matches.");
+      for (i = 0 ; i < 268 ; i = i + 1) begin
+	 // testin = code[29:21] ;
+	 dispin = 0 ;
+	 #1
+	   decodein = testout ;
+	 decdispin = dispin ;
+	 #1
+//	   $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ;
+	 if (testout != expect_0_disp) 
+	   $display ("bad code0 %b %b %b %b %b", dispin, testin,  dispout, testout, expect_0_disp) ;
+	 if (dispout != (dispin ^ code[0]))
+	   $display ("bad disp0 %b %b %b %b %b", dispin, testin, dispout, testout, (dispin ^ code[0])) ;
+	 if (0 != (9'b1_1111_1111 & (testin ^ decodeout)))
+	   $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin,  dispout, testout, decodeout) ;
+	 if (decodedisp != dispout)
+	   $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin,  dispout, testout, decodeout) ;
+	 if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin,  dispout, testout, decodeout) ;
+	 if ((testout != expect_0_disp) | decodeerr |
+	     (dispout != (dispin ^ code[0])) | (decodedisp != dispout))
+	   errors = errors + 1 ;
+
+	 dispin = 1 ;
+	 #1
+	 decodein = testout ;
+	 decdispin = dispin ;
+	 #1
+//	   $display ("%b %b %b %b *%b*", dispin, testin, testout, {dispout, DUTD.disp6a, DUTD.disp6a2, DUTD.disp6a0, DUTD.disp6a2, DUTD.fghjp31, DUTD.feqg, DUTD.heqj, DUTD.fghj22, DUTD.fi, DUTD.gi, DUTD.hi, DUTD.ji, DUTD.dispout}, decodeout,, decodedisp,, DUTD.k28,, DUTD.disp6b) ;
+	 if (testout != expect_1_disp) 
+	   $display ("bad code1 %b %b %b %b %b", dispin, testin, dispout, testout, expect_1_disp) ;
+	 if (dispout != (dispin ^ code[0]))
+	   $display ("bad disp1 %b %b %b %b %b", dispin, testin,  dispout, testout, (dispin ^ code[0])) ;
+	 if (0 != (9'b1_1111_1111 & (testin ^ decodeout)))
+	   $display ("diff in abcdefghk decode, %b %b %b %b %b", dispin, testin,  dispout, testout, decodeout) ;
+	 if (decodedisp != dispout)
+	   $display ("diff in decoder disp out, %b %b %b %b %b", dispin, testin,  dispout, testout, decodeout) ;
+	 if (decodeerr) $display ("decode error asserted improperly, %b %b %b %b %b", dispin, testin,  dispout, testout, decodeout) ;
+	 if ((testout != expect_1_disp) | decodeerr |
+	     (dispout != (dispin ^ code[0])) | (decodedisp != dispout))
+	   errors = errors + 1 ;
+      end
+      $display ("%d errors in that testing.\n", errors) ;
+
+      // Now, having verified all legal codes, lets run some illegal codes
+      // at the decoder... how to figure illegal codes ?  2048 possible cases,
+      // lets mark the OK ones...
+      legal = 0 ;
+      okdisp = 0 ;
+      for (i = 0 ; i < 268 ; i = i + 1) begin
+	 #1
+//	   $display ("i=%d: %b %b %d %d %x %x", i, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp, expect_0_disp, expect_1_disp) ;
+	 legal[expect_0_disp] = 1 ;
+	 legal[expect_1_disp] = 1 ;
+	 codedisp0 = expect_0_disp ;
+	 codedisp1 = {1'b1, expect_1_disp} ;
+	 okdisp[codedisp0] = 1 ;
+	 okdisp[codedisp1] = 1 ;
+	 mapcode[expect_0_disp] = code[29:21] ;
+	 mapcode[expect_1_disp] = code[29:21] ;
+      end
+
+      $display ("Now lets test all (legal and illegal) codes into the decoder.");
+      $display ("checking all possible decode inputs") ;
+      for (i = 0 ; i < 1024 ; i = i + 1) begin
+	 decodein = i ;
+	 decdispin = 0 ;
+	 codedisp1 = 1024 | i ;
+	 #1
+	 if (((legal[i] == 0) & (decodeerr != 1)) |
+	     (legal[i] & (mapcode[i] != decodeout)) |
+	     (legal[i] & (disperr != !okdisp[i])))
+	   $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", 
+		     decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i]) ;
+	 if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ;
+	 if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ;
+	 if (legal[i] & (disperr != 1) & !okdisp[i]) $display ("ERR: disp err should be asserted") ;
+	 else if (legal[i] & (disperr != 0) & okdisp[i])
+	   $display ("ERR: disp err should not be asserted") ;
+
+	 if (((legal[i] == 0) & (decodeerr != 1)) |
+	     (legal[i] & !disperr & !okdisp[i]) |
+	     (legal[i] & (mapcode[i] != decodeout)) |
+	     (legal[i] & disperr & okdisp[i]))
+	   errors = errors + 1 ;
+
+	 decdispin = 1 ;
+	 #1
+	 if (((legal[i] == 0) & (decodeerr != 1)) |
+	     (legal[i] & (mapcode[i] != decodeout)) |
+	     (legal[i] & (disperr != !okdisp[i|1024])))
+	   $display ("10b:%b start disp:%b 8b:%b end disp:%b codevio:%b dispvio:%b known code:%b used disp:", 
+		     decodein, decdispin, decodeout, decodedisp, decodeerr, disperr, legal[i], okdisp[i|1024]) ;
+	 if ((legal[i] == 0) & (decodeerr != 1)) $display ("ERR: decoderr should be 1") ;
+	 if (legal[i] & (mapcode[i] != decodeout)) $display ("ERR: decode output incorrect") ;
+	 if (legal[i] & (disperr != 1) & !okdisp[i|1024]) $display ("ERR: disp err should be asserted") ;
+	 else if (legal[i] & (disperr != 0) & okdisp[i|1024])
+	   $display ("ERR: disp err should not be asserted") ;
+	 if (((legal[i] == 0) & (decodeerr != 1)) |
+	     (legal[i] & !disperr & !okdisp[i|1024]) |
+	     (legal[i] & (mapcode[i] != decodeout)) |
+	     (legal[i] & disperr & okdisp[i|1024]))
+	   errors = errors + 1 ;
+      end // for (i = 0 ; i < 1024 ; i = i + 1)
+
+      $display ("\nDone testing decoder.\n") ;
+      $display ("Total error count: %d", errors);
+      if (errors == 0) $display ("Congratulations!\n");
+      $finish ;
+   end // initial begin
+   
+endmodule
diff --git a/fpga/usrp2/opencores/README b/fpga/usrp2/opencores/README
new file mode 100644
index 000000000..d63b7cbdb
--- /dev/null
+++ b/fpga/usrp2/opencores/README
@@ -0,0 +1,11 @@
+All the subdirectories of this directory contain code from the OpenCores
+project, checked out directly from the OpenCores CVS server.  You can update
+any directory to the latest OpenCores code by doing "cvs up" in that.
+This is not recommended unless you know what you are doing.  
+
+
+Each directory contains its own copyright and licensing information.  We 
+believe that we have the right to distribute all of these files in the form
+in which we provide them.  If this is not the case, please notify Matt Ettus,
+matt@ettus.com.
+
diff --git a/fpga/usrp2/opencores/aemb/CVS/.gitignore b/fpga/usrp2/opencores/aemb/CVS/.gitignore
new file mode 100644
index 000000000..b693d7c72
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/CVS/.gitignore
@@ -0,0 +1 @@
+/Entries.Log
diff --git a/fpga/usrp2/opencores/aemb/CVS/Entries b/fpga/usrp2/opencores/aemb/CVS/Entries
new file mode 100644
index 000000000..093a9a86a
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/CVS/Entries
@@ -0,0 +1,4 @@
+D/rtl////
+D/sim////
+D/sw////
+D/doc////
diff --git a/fpga/usrp2/opencores/aemb/CVS/Repository b/fpga/usrp2/opencores/aemb/CVS/Repository
new file mode 100644
index 000000000..967f2cedf
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/CVS/Repository
@@ -0,0 +1 @@
+aemb
diff --git a/fpga/usrp2/opencores/aemb/CVS/Root b/fpga/usrp2/opencores/aemb/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/CVS/Template b/fpga/usrp2/opencores/aemb/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/doc/CVS/Entries b/fpga/usrp2/opencores/aemb/doc/CVS/Entries
new file mode 100644
index 000000000..16bb46ac6
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/doc/CVS/Entries
@@ -0,0 +1,2 @@
+/aeMB_datasheet.pdf/1.3/Tue Jan 15 18:38:57 2008/-kb/
+D
diff --git a/fpga/usrp2/opencores/aemb/doc/CVS/Repository b/fpga/usrp2/opencores/aemb/doc/CVS/Repository
new file mode 100644
index 000000000..41df302a9
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/doc/CVS/Repository
@@ -0,0 +1 @@
+aemb/doc
diff --git a/fpga/usrp2/opencores/aemb/doc/CVS/Root b/fpga/usrp2/opencores/aemb/doc/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/doc/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/doc/CVS/Template b/fpga/usrp2/opencores/aemb/doc/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/doc/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf b/fpga/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf
new file mode 100644
index 000000000..5b26ac319
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/doc/aeMB_datasheet.pdf
diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Entries b/fpga/usrp2/opencores/aemb/rtl/CVS/Entries
new file mode 100644
index 000000000..428c5622d
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/CVS/Entries
@@ -0,0 +1 @@
+D/verilog////
diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Repository b/fpga/usrp2/opencores/aemb/rtl/CVS/Repository
new file mode 100644
index 000000000..e2c1eab77
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/CVS/Repository
@@ -0,0 +1 @@
+aemb/rtl
diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Root b/fpga/usrp2/opencores/aemb/rtl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/rtl/CVS/Template b/fpga/usrp2/opencores/aemb/rtl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/.gitignore b/fpga/usrp2/opencores/aemb/rtl/verilog/.gitignore
new file mode 100644
index 000000000..6b09f5cc9
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/.gitignore
@@ -0,0 +1 @@
+/aeMB2*
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Entries b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Entries
new file mode 100644
index 000000000..f17d70235
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Entries
@@ -0,0 +1,38 @@
+/aeMB2_aslu.v/1.10/Tue May 20 18:13:50 2008//
+/aeMB2_bpcu.v/1.5/Tue May 20 18:13:50 2008//
+/aeMB2_brcc.v/1.3/Tue May 20 18:13:50 2008//
+/aeMB2_bsft.v/1.3/Tue May 20 18:13:50 2008//
+/aeMB2_ctrl.v/1.7/Tue May 20 18:13:51 2008//
+/aeMB2_dparam.v/1.1/Tue May 20 18:13:51 2008//
+/aeMB2_dwbif.v/1.7/Tue May 20 18:13:51 2008//
+/aeMB2_edk32.v/1.8/Tue May 20 18:13:51 2008//
+/aeMB2_edk62.v/1.8/Tue May 20 18:13:51 2008//
+/aeMB2_exec.v/1.4/Tue May 20 18:13:51 2008//
+/aeMB2_gprf.v/1.4/Tue May 20 18:13:51 2008//
+/aeMB2_iche.v/1.5/Tue May 20 18:13:51 2008//
+/aeMB2_idmx.v/1.5/Tue May 20 18:13:51 2008//
+/aeMB2_intu.v/1.7/Tue May 20 18:13:51 2008//
+/aeMB2_iwbif.v/1.5/Tue May 20 18:13:51 2008//
+/aeMB2_memif.v/1.3/Tue May 20 18:13:51 2008//
+/aeMB2_mult.v/1.5/Tue May 20 18:13:51 2008//
+/aeMB2_ofid.v/1.2/Tue May 20 18:13:51 2008//
+/aeMB2_opmx.v/1.3/Tue May 20 18:13:51 2008//
+/aeMB2_pipe.v/1.4/Tue May 20 18:13:51 2008//
+/aeMB2_regf.v/1.3/Tue May 20 18:13:51 2008//
+/aeMB2_regs.v/1.4/Tue May 20 18:13:51 2008//
+/aeMB2_sfrf.v/1.2/Tue May 20 18:13:51 2008//
+/aeMB2_sim.v/1.2/Tue May 20 18:13:51 2008//
+/aeMB2_sparam.v/1.2/Tue May 20 18:13:51 2008//
+/aeMB2_spsram.v/1.1/Tue May 20 18:13:51 2008//
+/aeMB2_sysc.v/1.5/Tue May 20 18:13:51 2008//
+/aeMB2_tpsram.v/1.3/Tue May 20 18:13:51 2008//
+/aeMB2_xslif.v/1.7/Tue May 20 18:13:52 2008//
+/aeMB_bpcu.v/1.4/Thu Sep 11 02:11:12 2008//
+/aeMB_core.v/1.9/Thu Sep 11 02:11:12 2008//
+/aeMB_ctrl.v/1.10/Thu Sep 11 02:11:12 2008//
+/aeMB_edk32.v/1.14/Thu Sep 11 02:11:12 2008//
+/aeMB_ibuf.v/1.10/Thu Sep 11 02:11:12 2008//
+/aeMB_regf.v/1.3/Thu Sep 11 02:11:12 2008//
+/aeMB_sim.v/1.2/Thu Jan 22 05:50:30 2009//
+/aeMB_xecu.v/1.12/Thu Sep 11 02:11:12 2008//
+D
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Repository b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Repository
new file mode 100644
index 000000000..a9de19556
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Repository
@@ -0,0 +1 @@
+aemb/rtl/verilog
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Root b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Template b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
new file mode 100644
index 000000000..a7c686e7e
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_bpcu.v
@@ -0,0 +1,184 @@
+// $Id: aeMB_bpcu.v,v 1.4 2007/11/14 22:14:34 sybreon Exp $
+//
+// AEMB BRANCH PROGRAMME COUNTER UNIT
+// 
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+//  
+// This file is part of AEMB.
+//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+// Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+//
+// $Log: aeMB_bpcu.v,v $
+// Revision 1.4  2007/11/14 22:14:34  sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
+// Revision 1.3  2007/11/10 16:39:38  sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.2  2007/11/02 19:20:58  sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1  2007/11/02 03:25:39  sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_bpcu (/*AUTOARG*/
+   // Outputs
+   iwb_adr_o, rPC, rPCLNK, rBRA, rDLY,
+   // Inputs
+   rMXALT, rOPC, rRD, rRA, rRESULT, rDWBDI, rREGA, gclk, grst, gena
+   );
+   parameter IW = 24;
+
+   // INST WISHBONE
+   output [IW-1:2] iwb_adr_o;
+
+   // INTERNAL
+   output [31:2]   rPC, rPCLNK;
+   output 	   rBRA;
+   output 	   rDLY;
+   //output [1:0]    rATOM;
+   //output [1:0]    xATOM;
+   
+   input [1:0] 	   rMXALT;   
+   input [5:0] 	   rOPC;
+   input [4:0] 	   rRD, rRA;  
+   input [31:0]    rRESULT; // ALU
+   input [31:0]    rDWBDI; // RAM
+   input [31:0]    rREGA;
+   //input [1:0] 	   rXCE;   
+   
+   // SYSTEM
+   input 	   gclk, grst, gena;
+
+   // --- BRANCH CONTROL --------------------------------------------
+   // Controls the branch and delay flags
+   
+   wire 	   fRTD = (rOPC == 6'o55);
+   wire 	   fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
+   wire 	   fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
+
+   wire [31:0] 	   wREGA;
+   assign 	   wREGA = (rMXALT == 2'o2) ? rDWBDI :
+			   (rMXALT == 2'o1) ? rRESULT :
+			   rREGA;   
+   
+   wire 	   wBEQ = (wREGA == 32'd0);
+   wire 	   wBNE = ~wBEQ;
+   wire 	   wBLT = wREGA[31];
+   wire 	   wBLE = wBLT | wBEQ;   
+   wire 	   wBGE = ~wBLT;
+   wire 	   wBGT = ~wBLE;   
+
+   reg 		   xXCC;
+   always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT
+	    or wBNE)
+     case (rRD[2:0])
+       3'o0: xXCC <= wBEQ;
+       3'o1: xXCC <= wBNE;
+       3'o2: xXCC <= wBLT;
+       3'o3: xXCC <= wBLE;
+       3'o4: xXCC <= wBGT;
+       3'o5: xXCC <= wBGE;
+       default: xXCC <= 1'bX;
+     endcase // case (rRD[2:0])
+
+   reg 		   rBRA, xBRA;
+   reg 		   rDLY, xDLY;
+   wire 	   fSKIP = rBRA & !rDLY;   
+   
+   always @(/*AUTOSENSE*/fBCC or fBRU or fRTD or rBRA or rRA or rRD
+	    or xXCC)
+     //if (rBRA | |rXCE) begin
+     if (rBRA) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	xBRA <= 1'h0;
+	xDLY <= 1'h0;
+	// End of automatics
+     end else begin
+	xDLY <= (fBRU & rRA[4]) | (fBCC & rRD[4]) | fRTD;      
+	xBRA <= (fRTD | fBRU) ? 1'b1 :
+		(fBCC) ? xXCC :
+		1'b0;
+     end
+
+   // --- PC PIPELINE ------------------------------------------------
+   // PC and related changes
+   
+   reg [31:2] 	   rIPC, xIPC;
+   reg [31:2] 	   rPC, xPC;
+   reg [31:2] 	   rPCLNK, xPCLNK;
+   
+   assign 	   iwb_adr_o = rIPC[IW-1:2];
+   
+   always @(/*AUTOSENSE*/rBRA or rIPC or rPC or rRESULT) begin
+      //xPCLNK <= (^rATOM) ? rPC : rPC;
+      xPCLNK <= rPC;
+      //xPC <= (^rATOM) ? rIPC : rRESULT[31:2];	
+      xPC <= rIPC;
+      //xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
+      /*
+     case (rXCE)
+       2'o1: xIPC <= 30'h2;       
+       2'o2: xIPC <= 30'h4;       
+       2'o3: xIPC <= 30'h6;       
+       default: xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
+     endcase // case (rXCE)      
+       */
+      xIPC <= (rBRA) ? rRESULT[31:2] : (rIPC + 1);
+   end   			   
+
+   // --- ATOMIC CONTROL ---------------------------------------------
+   // This is used to indicate 'safe' instruction borders.
+   
+   wire 	wIMM = (rOPC == 6'o54) & !fSKIP;
+   wire 	wRTD = (rOPC == 6'o55) & !fSKIP;
+   wire 	wBCC = xXCC & ((rOPC == 6'o47) | (rOPC == 6'o57)) & !fSKIP;
+   wire 	wBRU = ((rOPC == 6'o46) | (rOPC == 6'o56)) & !fSKIP;   
+   
+   wire 	fATOM = ~(wIMM | wRTD | wBCC | wBRU | rBRA);   
+   reg [1:0] 	rATOM, xATOM;
+
+   always @(/*AUTOSENSE*/fATOM or rATOM)
+     xATOM <= {rATOM[0], (rATOM[0] ^ fATOM)};   
+     
+   
+   // --- SYNC PIPELINE ----------------------------------------------
+    
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rATOM <= 2'h0;
+	rBRA <= 1'h0;
+	rDLY <= 1'h0;
+	rIPC <= 30'h0;
+	rPC <= 30'h0;
+	rPCLNK <= 30'h0;
+	// End of automatics
+     end else if (gena) begin
+	rIPC <= #1 xIPC;
+	rBRA <= #1 xBRA;
+	rPC <= #1 xPC;
+	rPCLNK <= #1 xPCLNK;
+	rDLY <= #1 xDLY;
+	rATOM <= #1 xATOM;	
+     end
+      
+endmodule // aeMB_bpcu
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v
new file mode 100644
index 000000000..20ce9852e
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v
@@ -0,0 +1,137 @@
+// $Id: aeMB_core.v,v 1.9 2007/11/23 14:06:41 sybreon Exp $
+//
+// AEMB 32'bit RISC MICROPROCESSOR CORE
+//
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+//  
+// This file is part of AEMB.
+//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+// Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+//
+// HISTORY
+// $Log: aeMB_core.v,v $
+// Revision 1.9  2007/11/23 14:06:41  sybreon
+// Old version deprecated.
+//
+// Revision 1.8  2007/10/22 19:12:59  sybreon
+// Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.
+//
+// Revision 1.7  2007/05/30 18:44:30  sybreon
+// Added interrupt support.
+//
+// Revision 1.6  2007/05/17 09:08:21  sybreon
+// Removed asynchronous reset signal.
+//
+// Revision 1.5  2007/04/27 00:23:55  sybreon
+// Added code documentation.
+// Improved size & speed of rtl/verilog/aeMB_aslu.v
+//
+// Revision 1.4  2007/04/25 22:15:04  sybreon
+// Added support for 8-bit and 16-bit data types.
+//
+// Revision 1.3  2007/04/11 04:30:43  sybreon
+// Added pipeline stalling from incomplete bus cycles.
+// Separated sync and async portions of code.
+//
+// Revision 1.2  2007/04/04 06:13:23  sybreon
+// Removed unused signals
+//
+// Revision 1.1  2007/03/09 17:52:17  sybreon
+// initial import
+//
+
+
+module aeMB_core (/*AUTOARG*/
+   // Outputs
+   iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
+   fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
+   // Inputs
+   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
+   fsl_ack_i, dwb_dat_i, dwb_ack_i
+   );
+   // Instruction WB address space
+   parameter ISIZ = 32;
+   // Data WB address space
+   parameter DSIZ = 32;
+   // Multiplier
+   parameter MUL = 1;
+   // Barrel Shifter
+   parameter BSF = 1;   
+
+   /*AUTOOUTPUT*/
+   // Beginning of automatic outputs (from unused autoinst outputs)
+   output [DSIZ-1:2]	dwb_adr_o;		// From edk32 of aeMB_edk32.v
+   output [31:0]	dwb_dat_o;		// From edk32 of aeMB_edk32.v
+   output [3:0]		dwb_sel_o;		// From edk32 of aeMB_edk32.v
+   output		dwb_stb_o;		// From edk32 of aeMB_edk32.v
+   output		dwb_wre_o;		// From edk32 of aeMB_edk32.v
+   output [6:2]		fsl_adr_o;		// From edk32 of aeMB_edk32.v
+   output [31:0]	fsl_dat_o;		// From edk32 of aeMB_edk32.v
+   output		fsl_stb_o;		// From edk32 of aeMB_edk32.v
+   output [1:0]		fsl_tag_o;		// From edk32 of aeMB_edk32.v
+   output		fsl_wre_o;		// From edk32 of aeMB_edk32.v
+   output [ISIZ-1:2]	iwb_adr_o;		// From edk32 of aeMB_edk32.v
+   output		iwb_stb_o;		// From edk32 of aeMB_edk32.v
+   // End of automatics
+   /*AUTOINPUT*/
+   // Beginning of automatic inputs (from unused autoinst inputs)
+   input		dwb_ack_i;		// To edk32 of aeMB_edk32.v
+   input [31:0]		dwb_dat_i;		// To edk32 of aeMB_edk32.v
+   input		fsl_ack_i;		// To edk32 of aeMB_edk32.v
+   input [31:0]		fsl_dat_i;		// To edk32 of aeMB_edk32.v
+   input		iwb_ack_i;		// To edk32 of aeMB_edk32.v
+   input [31:0]		iwb_dat_i;		// To edk32 of aeMB_edk32.v
+   input		sys_clk_i;		// To edk32 of aeMB_edk32.v
+   input		sys_int_i;		// To edk32 of aeMB_edk32.v
+   input		sys_rst_i;		// To edk32 of aeMB_edk32.v
+   // End of automatics
+   /*AUTOWIRE*/
+
+   // INSTANTIATIONS /////////////////////////////////////////////////////////////////
+
+   /* 
+    aeMB_edk32 AUTO_TEMPLATE (
+    .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
+    .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
+    );
+    */
+   
+   aeMB_edk32 #(ISIZ, DSIZ, MUL, BSF)
+   edk32 (/*AUTOINST*/
+	  // Outputs
+	  .dwb_adr_o			(dwb_adr_o[DSIZ-1:2]),	 // Templated
+	  .dwb_dat_o			(dwb_dat_o[31:0]),
+	  .dwb_sel_o			(dwb_sel_o[3:0]),
+	  .dwb_stb_o			(dwb_stb_o),
+	  .dwb_wre_o			(dwb_wre_o),
+	  .fsl_adr_o			(fsl_adr_o[6:2]),
+	  .fsl_dat_o			(fsl_dat_o[31:0]),
+	  .fsl_stb_o			(fsl_stb_o),
+	  .fsl_tag_o			(fsl_tag_o[1:0]),
+	  .fsl_wre_o			(fsl_wre_o),
+	  .iwb_adr_o			(iwb_adr_o[ISIZ-1:2]),	 // Templated
+	  .iwb_stb_o			(iwb_stb_o),
+	  // Inputs
+	  .dwb_ack_i			(dwb_ack_i),
+	  .dwb_dat_i			(dwb_dat_i[31:0]),
+	  .fsl_ack_i			(fsl_ack_i),
+	  .fsl_dat_i			(fsl_dat_i[31:0]),
+	  .iwb_ack_i			(iwb_ack_i),
+	  .iwb_dat_i			(iwb_dat_i[31:0]),
+	  .sys_int_i			(sys_int_i),
+	  .sys_clk_i			(sys_clk_i),
+	  .sys_rst_i			(sys_rst_i));
+   
+   
+endmodule // aeMB_core
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
new file mode 100644
index 000000000..9ffa20ff2
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v
@@ -0,0 +1,62 @@
+
+// Wrapper for aeMB core:
+//    Drive wb_cyc_o  (just tied to wb_stb_o for now)
+//    Make input reset active high (like the signal name makes it sound....)
+// No longer needed
+//    Make it big-endian like the standard MicroBlaze
+
+module aeMB_core_BE
+  #(parameter ISIZ=32, parameter DSIZ=32, 
+    parameter MUL=0, parameter BSF=0)
+    (input sys_clk_i,
+     input sys_rst_i,
+
+     output iwb_stb_o,
+     output [ISIZ-1:0] iwb_adr_o,
+     input [31:0] iwb_dat_i,
+     input iwb_ack_i,
+
+     output dwb_we_o,
+     output dwb_stb_o,
+     output [DSIZ-1:0] dwb_adr_o,
+     output [31:0] dwb_dat_o,
+     input [31:0] dwb_dat_i,
+     input dwb_ack_i,
+     output [3:0] dwb_sel_o,
+     output dwb_cyc_o,
+     
+     input sys_int_i, 
+     input sys_exc_i);
+
+   assign  dwb_cyc_o = dwb_stb_o;
+
+   aeMB_edk32 #(.IW(ISIZ),.DW(DSIZ),.MUL(MUL),.BSF(BSF))
+     aeMB_edk32 (.sys_clk_i(sys_clk_i), 
+		 .sys_rst_i(sys_rst_i),
+		 
+		 .iwb_stb_o(iwb_stb_o),
+		 .iwb_adr_o(iwb_adr_o[ISIZ-1:2]),
+		 .iwb_ack_i(iwb_ack_i),
+		 .iwb_dat_i(iwb_dat_i),
+		 
+		 .dwb_wre_o(dwb_we_o),
+		 .dwb_stb_o(dwb_stb_o),
+		 .dwb_adr_o(dwb_adr_o[DSIZ-1:2]),
+		 .dwb_ack_i(dwb_ack_i),
+		 .dwb_sel_o(dwb_sel_o),
+		 .dwb_dat_i(dwb_dat_i),
+		 .dwb_dat_o(dwb_dat_o),
+	
+		 .fsl_wre_o(),
+		 .fsl_tag_o(),
+		 .fsl_stb_o(),
+		 .fsl_dat_o(),
+		 .fsl_adr_o(),
+		 .fsl_dat_i(32'b0),
+		 .fsl_ack_i(1'b0),
+		 .sys_int_i(sys_int_i) );
+   
+   assign  iwb_adr_o[1:0] = 2'b0;
+   assign  dwb_adr_o[1:0] = 2'b0;
+
+endmodule // aeMB_core_BE
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v
new file mode 100644
index 000000000..88d4e51ce
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ctrl.v
@@ -0,0 +1,336 @@
+// $Id: aeMB_ctrl.v,v 1.10 2007/11/30 16:44:40 sybreon Exp $
+//
+// AEMB CONTROL UNIT
+// 
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+//  
+// This file is part of AEMB.
+//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+// Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+//
+// $Log: aeMB_ctrl.v,v $
+// Revision 1.10  2007/11/30 16:44:40  sybreon
+// Minor code cleanup.
+//
+// Revision 1.9  2007/11/15 09:26:43  sybreon
+// Fixed minor typo causing synthesis failure.
+//
+// Revision 1.8  2007/11/14 23:19:24  sybreon
+// Fixed minor typo.
+//
+// Revision 1.7  2007/11/14 22:14:34  sybreon
+// Changed interrupt handling system (reported by M. Ettus).
+//
+// Revision 1.6  2007/11/10 16:39:38  sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.5  2007/11/09 20:51:52  sybreon
+// Added GET/PUT support through a FSL bus.
+//
+// Revision 1.4  2007/11/08 17:48:14  sybreon
+// Fixed data WISHBONE arbitration problem (reported by J Lee).
+//
+// Revision 1.3  2007/11/08 14:17:47  sybreon
+// Parameterised optional components.
+//
+// Revision 1.2  2007/11/02 19:20:58  sybreon
+// Added better (beta) interrupt support.
+// Changed MSR_IE to disabled at reset as per MB docs.
+//
+// Revision 1.1  2007/11/02 03:25:40  sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_ctrl (/*AUTOARG*/
+   // Outputs
+   rMXDST, rMXSRC, rMXTGT, rMXALT, rMXALU, rRW, dwb_stb_o, dwb_wre_o,
+   fsl_stb_o, fsl_wre_o,
+   // Inputs
+   rDLY, rIMM, rALT, rOPC, rRD, rRA, rRB, rPC, rBRA, rMSR_IE, xIREG,
+   dwb_ack_i, iwb_ack_i, fsl_ack_i, gclk, grst, gena
+   );
+   // INTERNAL   
+   //output [31:2] rPCLNK;
+   output [1:0]  rMXDST;
+   output [1:0]  rMXSRC, rMXTGT, rMXALT;
+   output [2:0]  rMXALU;   
+   output [4:0]  rRW;
+   
+   input 	 rDLY;
+   input [15:0]  rIMM;
+   input [10:0]  rALT;
+   input [5:0] 	 rOPC;
+   input [4:0] 	 rRD, rRA, rRB;
+   input [31:2]  rPC;
+   input 	 rBRA;
+   input 	 rMSR_IE;
+   input [31:0]  xIREG;   
+   
+   // DATA WISHBONE
+   output 	 dwb_stb_o;
+   output 	 dwb_wre_o;
+   input 	 dwb_ack_i;
+
+   // INST WISHBONE
+   input 	 iwb_ack_i;
+   
+   // FSL WISHBONE
+   output 	 fsl_stb_o;
+   output 	 fsl_wre_o;
+   input 	 fsl_ack_i;   
+   
+   // SYSTEM
+   input 	 gclk, grst, gena;
+
+   // --- DECODE INSTRUCTIONS
+   // TODO: Simplify
+
+   wire [5:0] 	 wOPC;
+   wire [4:0] 	 wRD, wRA, wRB;
+   wire [10:0] 	 wALT;   
+   
+   assign 	 {wOPC, wRD, wRA, wRB, wALT} = xIREG; // FIXME: Endian
+
+   wire 	 fSFT = (rOPC == 6'o44);
+   wire 	 fLOG = ({rOPC[5:4],rOPC[2]} == 3'o4);   
+
+   wire 	 fMUL = (rOPC == 6'o20) | (rOPC == 6'o30);
+   wire 	 fBSF = (rOPC == 6'o21) | (rOPC == 6'o31);
+   wire 	 fDIV = (rOPC == 6'o22);   
+   
+   wire 	 fRTD = (rOPC == 6'o55);
+   wire 	 fBCC = (rOPC == 6'o47) | (rOPC == 6'o57);
+   wire 	 fBRU = (rOPC == 6'o46) | (rOPC == 6'o56);
+   wire 	 fBRA = fBRU & rRA[3];   
+
+   wire 	 fIMM = (rOPC == 6'o54);
+   wire 	 fMOV = (rOPC == 6'o45);   
+   
+   wire 	 fLOD = ({rOPC[5:4],rOPC[2]} == 3'o6);
+   wire 	 fSTR = ({rOPC[5:4],rOPC[2]} == 3'o7);
+   wire 	 fLDST = (&rOPC[5:4]);   
+
+   wire          fPUT = (rOPC == 6'o33) & rRB[4];
+   wire 	 fGET = (rOPC == 6'o33) & !rRB[4];   
+
+
+   wire 	 wSFT = (wOPC == 6'o44);
+   wire 	 wLOG = ({wOPC[5:4],wOPC[2]} == 3'o4);   
+
+   wire 	 wMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
+   wire 	 wBSF = (wOPC == 6'o21) | (wOPC == 6'o31);
+   wire 	 wDIV = (wOPC == 6'o22);   
+   
+   wire 	 wRTD = (wOPC == 6'o55);
+   wire 	 wBCC = (wOPC == 6'o47) | (wOPC == 6'o57);
+   wire 	 wBRU = (wOPC == 6'o46) | (wOPC == 6'o56);
+   wire 	 wBRA = wBRU & wRA[3];   
+
+   wire 	 wIMM = (wOPC == 6'o54);
+   wire 	 wMOV = (wOPC == 6'o45);   
+   
+   wire 	 wLOD = ({wOPC[5:4],wOPC[2]} == 3'o6);
+   wire 	 wSTR = ({wOPC[5:4],wOPC[2]} == 3'o7);
+   wire 	 wLDST = (&wOPC[5:4]);   
+
+   wire          wPUT = (wOPC == 6'o33) & wRB[4];
+   wire 	 wGET = (wOPC == 6'o33) & !wRB[4];   
+
+   
+   // --- BRANCH SLOT REGISTERS ---------------------------
+
+   reg [31:2] 	 rPCLNK, xPCLNK;
+   reg [1:0] 	 rMXDST, xMXDST;
+   reg [4:0] 	 rRW, xRW;   
+
+   reg [1:0] 	 rMXSRC, xMXSRC;
+   reg [1:0] 	 rMXTGT, xMXTGT;
+   reg [1:0] 	 rMXALT, xMXALT;
+   
+   
+   // --- OPERAND SELECTOR ---------------------------------
+
+   wire 	 wRDWE = |xRW;
+   wire 	 wAFWD_M = (xRW == wRA) & (xMXDST == 2'o2) & wRDWE;
+   wire 	 wBFWD_M = (xRW == wRB) & (xMXDST == 2'o2) & wRDWE;
+   wire 	 wAFWD_R = (xRW == wRA) & (xMXDST == 2'o0) & wRDWE;   
+   wire 	 wBFWD_R = (xRW == wRB) & (xMXDST == 2'o0) & wRDWE;
+
+   always @(/*AUTOSENSE*/rBRA or wAFWD_M or wAFWD_R or wBCC or wBFWD_M
+	    or wBFWD_R or wBRU or wOPC) 
+     //if (rBRA | |rXCE) begin
+     if (rBRA) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	xMXALT <= 2'h0;
+	xMXSRC <= 2'h0;
+	xMXTGT <= 2'h0;
+	// End of automatics
+     end else begin
+	xMXSRC <= (wBRU | wBCC) ? 2'o3 : // PC
+		  (wAFWD_M) ? 2'o2 : // RAM
+		  (wAFWD_R) ? 2'o1 : // FWD
+		  2'o0; // REG
+	xMXTGT <= (wOPC[3]) ? 2'o3 : // IMM
+		  (wBFWD_M) ? 2'o2 : // RAM
+		  (wBFWD_R) ? 2'o1 : // FWD
+		  2'o0; // REG
+	xMXALT <= (wAFWD_M) ? 2'o2 : // RAM
+		  (wAFWD_R) ? 2'o1 : // FWD
+		  2'o0; // REG	
+     end // else: !if(rBRA)
+   
+   // --- ALU CONTROL ---------------------------------------
+
+   reg [2:0]     rMXALU, xMXALU;
+
+   always @(/*AUTOSENSE*/rBRA or wBRA or wBSF or wDIV or wLOG or wMOV
+	    or wMUL or wSFT)
+     //if (rBRA | |rXCE) begin
+     if (rBRA) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	xMXALU <= 3'h0;
+	// End of automatics
+     end else begin
+	xMXALU <= (wBRA | wMOV) ? 3'o3 :
+		  (wSFT) ? 3'o2 :
+		  (wLOG) ? 3'o1 :
+		  (wMUL) ? 3'o4 :
+		  (wBSF) ? 3'o5 :
+		  (wDIV) ? 3'o6 :
+		  3'o0;      	
+     end // else: !if(rBRA)
+   
+   // --- DELAY SLOT REGISTERS ------------------------------
+   
+   wire 	 fSKIP = (rBRA & !rDLY);
+   
+   always @(/*AUTOSENSE*/fBCC or fBRU or fGET or fLOD or fRTD or fSKIP
+	    or fSTR or rRD)
+     if (fSKIP) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	xMXDST <= 2'h0;
+	xRW <= 5'h0;
+	// End of automatics
+     end else begin
+	xMXDST <= (fSTR | fRTD | fBCC) ? 2'o3 :
+		  (fLOD | fGET) ? 2'o2 :
+		  (fBRU) ? 2'o1 :
+		  2'o0;
+	xRW <= rRD;
+     end // else: !if(fSKIP)
+
+
+   // --- DATA WISHBONE ----------------------------------
+
+   wire 	 fDACK = !(dwb_stb_o ^ dwb_ack_i);
+   
+   reg 		 rDWBSTB, xDWBSTB;
+   reg 		 rDWBWRE, xDWBWRE;
+
+   assign 	 dwb_stb_o = rDWBSTB;
+   assign 	 dwb_wre_o = rDWBWRE;
+   
+   
+   always @(/*AUTOSENSE*/fLOD or fSKIP or fSTR or iwb_ack_i)
+     //if (fSKIP | |rXCE) begin
+     if (fSKIP) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	xDWBSTB <= 1'h0;
+	xDWBWRE <= 1'h0;
+	// End of automatics
+     end else begin
+	xDWBSTB <= (fLOD | fSTR) & iwb_ack_i;
+	xDWBWRE <= fSTR & iwb_ack_i;	
+     end
+   
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rDWBSTB <= 1'h0;
+	rDWBWRE <= 1'h0;
+	// End of automatics
+     end else if (fDACK) begin
+	rDWBSTB <= #1 xDWBSTB;
+	rDWBWRE <= #1 xDWBWRE;	
+     end
+   
+
+   // --- FSL WISHBONE -----------------------------------
+
+   wire 	 fFACK = !(fsl_stb_o ^ fsl_ack_i);   
+	 
+   reg 		 rFSLSTB, xFSLSTB;
+   reg 		 rFSLWRE, xFSLWRE;
+
+   assign 	 fsl_stb_o = rFSLSTB;
+   assign 	 fsl_wre_o = rFSLWRE;   
+
+   always @(/*AUTOSENSE*/fGET or fPUT or fSKIP or iwb_ack_i) 
+     //if (fSKIP | |rXCE) begin
+     if (fSKIP) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	xFSLSTB <= 1'h0;
+	xFSLWRE <= 1'h0;
+	// End of automatics
+     end else begin
+	xFSLSTB <= (fPUT | fGET) & iwb_ack_i;
+	xFSLWRE <= fPUT & iwb_ack_i;	
+     end
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rFSLSTB <= 1'h0;
+	rFSLWRE <= 1'h0;
+	// End of automatics
+     end else if (fFACK) begin
+	rFSLSTB <= #1 xFSLSTB;
+	rFSLWRE <= #1 xFSLWRE;	
+     end
+   
+   // --- PIPELINE CONTROL DELAY ----------------------------
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rMXALT <= 2'h0;
+	rMXALU <= 3'h0;
+	rMXDST <= 2'h0;
+	rMXSRC <= 2'h0;
+	rMXTGT <= 2'h0;
+	rRW <= 5'h0;
+	// End of automatics
+     end else if (gena) begin // if (grst)
+	//rPCLNK <= #1 xPCLNK;
+	rMXDST <= #1 xMXDST;
+	rRW <= #1 xRW;
+	rMXSRC <= #1 xMXSRC;
+	rMXTGT <= #1 xMXTGT;
+	rMXALT <= #1 xMXALT;	
+	rMXALU <= #1 xMXALU;	
+     end
+
+   
+endmodule // aeMB_ctrl
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v
new file mode 100644
index 000000000..8bf4f7cac
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_edk32.v
@@ -0,0 +1,289 @@
+/* $Id: aeMB_edk32.v,v 1.14 2008/01/19 16:01:22 sybreon Exp $
+**
+** AEMB EDK 3.2 Compatible Core
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+module aeMB_edk32 (/*AUTOARG*/
+   // Outputs
+   iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
+   fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
+   // Inputs
+   sys_int_i, iwb_dat_i, iwb_ack_i, fsl_dat_i, fsl_ack_i, dwb_dat_i,
+   dwb_ack_i, sys_clk_i, sys_rst_i
+   );
+   // Bus widths
+   parameter IW = 32; /// Instruction bus address width
+   parameter DW = 32; /// Data bus address width
+
+   // Optional functions
+   parameter MUL = 0; // Multiplier
+   parameter BSF = 1; // Barrel Shifter
+   
+   /*AUTOOUTPUT*/
+   // Beginning of automatic outputs (from unused autoinst outputs)
+   output [DW-1:2]	dwb_adr_o;		// From xecu of aeMB_xecu.v
+   output [31:0]	dwb_dat_o;		// From regf of aeMB_regf.v
+   output [3:0]		dwb_sel_o;		// From xecu of aeMB_xecu.v
+   output		dwb_stb_o;		// From ctrl of aeMB_ctrl.v
+   output		dwb_wre_o;		// From ctrl of aeMB_ctrl.v
+   output [6:2]		fsl_adr_o;		// From xecu of aeMB_xecu.v
+   output [31:0]	fsl_dat_o;		// From regf of aeMB_regf.v
+   output		fsl_stb_o;		// From ctrl of aeMB_ctrl.v
+   output [1:0]		fsl_tag_o;		// From xecu of aeMB_xecu.v
+   output		fsl_wre_o;		// From ctrl of aeMB_ctrl.v
+   output [IW-1:2]	iwb_adr_o;		// From bpcu of aeMB_bpcu.v
+   output		iwb_stb_o;		// From ibuf of aeMB_ibuf.v
+   // End of automatics
+   /*AUTOINPUT*/
+   // Beginning of automatic inputs (from unused autoinst inputs)
+   input		dwb_ack_i;		// To ctrl of aeMB_ctrl.v
+   input [31:0]		dwb_dat_i;		// To regf of aeMB_regf.v
+   input		fsl_ack_i;		// To ctrl of aeMB_ctrl.v
+   input [31:0]		fsl_dat_i;		// To regf of aeMB_regf.v
+   input		iwb_ack_i;		// To ibuf of aeMB_ibuf.v, ...
+   input [31:0]		iwb_dat_i;		// To ibuf of aeMB_ibuf.v
+   input		sys_int_i;		// To ibuf of aeMB_ibuf.v
+   // End of automatics
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [10:0]		rALT;			// From ibuf of aeMB_ibuf.v
+   wire			rBRA;			// From bpcu of aeMB_bpcu.v
+   wire			rDLY;			// From bpcu of aeMB_bpcu.v
+   wire [31:0]		rDWBDI;			// From regf of aeMB_regf.v
+   wire [3:0]		rDWBSEL;		// From xecu of aeMB_xecu.v
+   wire [15:0]		rIMM;			// From ibuf of aeMB_ibuf.v
+   wire			rMSR_BIP;		// From xecu of aeMB_xecu.v
+   wire			rMSR_IE;		// From xecu of aeMB_xecu.v
+   wire [1:0]		rMXALT;			// From ctrl of aeMB_ctrl.v
+   wire [2:0]		rMXALU;			// From ctrl of aeMB_ctrl.v
+   wire [1:0]		rMXDST;			// From ctrl of aeMB_ctrl.v
+   wire [1:0]		rMXSRC;			// From ctrl of aeMB_ctrl.v
+   wire [1:0]		rMXTGT;			// From ctrl of aeMB_ctrl.v
+   wire [5:0]		rOPC;			// From ibuf of aeMB_ibuf.v
+   wire [31:2]		rPC;			// From bpcu of aeMB_bpcu.v
+   wire [31:2]		rPCLNK;			// From bpcu of aeMB_bpcu.v
+   wire [4:0]		rRA;			// From ibuf of aeMB_ibuf.v
+   wire [4:0]		rRB;			// From ibuf of aeMB_ibuf.v
+   wire [4:0]		rRD;			// From ibuf of aeMB_ibuf.v
+   wire [31:0]		rREGA;			// From regf of aeMB_regf.v
+   wire [31:0]		rREGB;			// From regf of aeMB_regf.v
+   wire [31:0]		rRESULT;		// From xecu of aeMB_xecu.v
+   wire [4:0]		rRW;			// From ctrl of aeMB_ctrl.v
+   wire [31:0]		rSIMM;			// From ibuf of aeMB_ibuf.v
+   wire			rSTALL;			// From ibuf of aeMB_ibuf.v
+   wire [31:0]		xIREG;			// From ibuf of aeMB_ibuf.v
+   // End of automatics
+
+   input 		sys_clk_i;
+   input 		sys_rst_i;
+
+   wire 		grst = sys_rst_i;
+   wire 		gclk = sys_clk_i;
+   wire 		gena = !((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i) & !rSTALL;   
+   wire 		oena = ((dwb_stb_o ^ dwb_ack_i) | (fsl_stb_o ^ fsl_ack_i) | !iwb_ack_i);   
+   
+   // --- INSTANTIATIONS -------------------------------------
+          
+   aeMB_ibuf
+     ibuf (/*AUTOINST*/
+	   // Outputs
+	   .rIMM			(rIMM[15:0]),
+	   .rRA				(rRA[4:0]),
+	   .rRD				(rRD[4:0]),
+	   .rRB				(rRB[4:0]),
+	   .rALT			(rALT[10:0]),
+	   .rOPC			(rOPC[5:0]),
+	   .rSIMM			(rSIMM[31:0]),
+	   .xIREG			(xIREG[31:0]),
+	   .rSTALL			(rSTALL),
+	   .iwb_stb_o			(iwb_stb_o),
+	   // Inputs
+	   .rBRA			(rBRA),
+	   .rMSR_IE			(rMSR_IE),
+	   .rMSR_BIP			(rMSR_BIP),
+	   .iwb_dat_i			(iwb_dat_i[31:0]),
+	   .iwb_ack_i			(iwb_ack_i),
+	   .sys_int_i			(sys_int_i),
+	   .gclk			(gclk),
+	   .grst			(grst),
+	   .gena			(gena),
+	   .oena			(oena));   
+   
+   aeMB_ctrl
+     ctrl (/*AUTOINST*/
+	   // Outputs
+	   .rMXDST			(rMXDST[1:0]),
+	   .rMXSRC			(rMXSRC[1:0]),
+	   .rMXTGT			(rMXTGT[1:0]),
+	   .rMXALT			(rMXALT[1:0]),
+	   .rMXALU			(rMXALU[2:0]),
+	   .rRW				(rRW[4:0]),
+	   .dwb_stb_o			(dwb_stb_o),
+	   .dwb_wre_o			(dwb_wre_o),
+	   .fsl_stb_o			(fsl_stb_o),
+	   .fsl_wre_o			(fsl_wre_o),
+	   // Inputs
+	   .rDLY			(rDLY),
+	   .rIMM			(rIMM[15:0]),
+	   .rALT			(rALT[10:0]),
+	   .rOPC			(rOPC[5:0]),
+	   .rRD				(rRD[4:0]),
+	   .rRA				(rRA[4:0]),
+	   .rRB				(rRB[4:0]),
+	   .rPC				(rPC[31:2]),
+	   .rBRA			(rBRA),
+	   .rMSR_IE			(rMSR_IE),
+	   .xIREG			(xIREG[31:0]),
+	   .dwb_ack_i			(dwb_ack_i),
+	   .iwb_ack_i			(iwb_ack_i),
+	   .fsl_ack_i			(fsl_ack_i),
+	   .gclk			(gclk),
+	   .grst			(grst),
+	   .gena			(gena));
+
+   aeMB_bpcu #(IW)
+     bpcu (/*AUTOINST*/
+	   // Outputs
+	   .iwb_adr_o			(iwb_adr_o[IW-1:2]),
+	   .rPC				(rPC[31:2]),
+	   .rPCLNK			(rPCLNK[31:2]),
+	   .rBRA			(rBRA),
+	   .rDLY			(rDLY),
+	   // Inputs
+	   .rMXALT			(rMXALT[1:0]),
+	   .rOPC			(rOPC[5:0]),
+	   .rRD				(rRD[4:0]),
+	   .rRA				(rRA[4:0]),
+	   .rRESULT			(rRESULT[31:0]),
+	   .rDWBDI			(rDWBDI[31:0]),
+	   .rREGA			(rREGA[31:0]),
+	   .gclk			(gclk),
+	   .grst			(grst),
+	   .gena			(gena));
+
+   aeMB_regf
+     regf (/*AUTOINST*/
+	   // Outputs
+	   .rREGA			(rREGA[31:0]),
+	   .rREGB			(rREGB[31:0]),
+	   .rDWBDI			(rDWBDI[31:0]),
+	   .dwb_dat_o			(dwb_dat_o[31:0]),
+	   .fsl_dat_o			(fsl_dat_o[31:0]),
+	   // Inputs
+	   .rOPC			(rOPC[5:0]),
+	   .rRA				(rRA[4:0]),
+	   .rRB				(rRB[4:0]),
+	   .rRW				(rRW[4:0]),
+	   .rRD				(rRD[4:0]),
+	   .rMXDST			(rMXDST[1:0]),
+	   .rPCLNK			(rPCLNK[31:2]),
+	   .rRESULT			(rRESULT[31:0]),
+	   .rDWBSEL			(rDWBSEL[3:0]),
+	   .rBRA			(rBRA),
+	   .rDLY			(rDLY),
+	   .dwb_dat_i			(dwb_dat_i[31:0]),
+	   .fsl_dat_i			(fsl_dat_i[31:0]),
+	   .gclk			(gclk),
+	   .grst			(grst),
+	   .gena			(gena));   
+
+   aeMB_xecu #(DW, MUL, BSF)
+     xecu (/*AUTOINST*/
+	   // Outputs
+	   .dwb_adr_o			(dwb_adr_o[DW-1:2]),
+	   .dwb_sel_o			(dwb_sel_o[3:0]),
+	   .fsl_adr_o			(fsl_adr_o[6:2]),
+	   .fsl_tag_o			(fsl_tag_o[1:0]),
+	   .rRESULT			(rRESULT[31:0]),
+	   .rDWBSEL			(rDWBSEL[3:0]),
+	   .rMSR_IE			(rMSR_IE),
+	   .rMSR_BIP			(rMSR_BIP),
+	   // Inputs
+	   .rREGA			(rREGA[31:0]),
+	   .rREGB			(rREGB[31:0]),
+	   .rMXSRC			(rMXSRC[1:0]),
+	   .rMXTGT			(rMXTGT[1:0]),
+	   .rRA				(rRA[4:0]),
+	   .rRB				(rRB[4:0]),
+	   .rMXALU			(rMXALU[2:0]),
+	   .rBRA			(rBRA),
+	   .rDLY			(rDLY),
+	   .rALT			(rALT[10:0]),
+	   .rSTALL			(rSTALL),
+	   .rSIMM			(rSIMM[31:0]),
+	   .rIMM			(rIMM[15:0]),
+	   .rOPC			(rOPC[5:0]),
+	   .rRD				(rRD[4:0]),
+	   .rDWBDI			(rDWBDI[31:0]),
+	   .rPC				(rPC[31:2]),
+	   .gclk			(gclk),
+	   .grst			(grst),
+	   .gena			(gena));
+   
+      
+endmodule // aeMB_edk32
+
+/*
+ $Log: aeMB_edk32.v,v $
+ Revision 1.14  2008/01/19 16:01:22  sybreon
+ Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)
+
+ Revision 1.13  2007/12/25 22:15:09  sybreon
+ Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
+
+ Revision 1.12  2007/12/23 20:40:44  sybreon
+ Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
+
+ Revision 1.11  2007/11/30 17:08:29  sybreon
+ Moved simulation kernel into code.
+ 
+ Revision 1.10  2007/11/16 21:52:03  sybreon
+ Added fsl_tag_o to FSL bus (tag either address or data).
+
+ Revision 1.9  2007/11/14 23:19:24  sybreon
+ Fixed minor typo.
+
+ Revision 1.8  2007/11/14 22:14:34  sybreon
+ Changed interrupt handling system (reported by M. Ettus).
+
+ Revision 1.7  2007/11/10 16:39:38  sybreon
+ Upgraded license to LGPLv3.
+ Significant performance optimisations.
+
+ Revision 1.6  2007/11/09 20:51:52  sybreon
+ Added GET/PUT support through a FSL bus.
+
+ Revision 1.5  2007/11/08 17:48:14  sybreon
+ Fixed data WISHBONE arbitration problem (reported by J Lee).
+
+ Revision 1.4  2007/11/08 14:17:47  sybreon
+ Parameterised optional components.
+
+ Revision 1.3  2007/11/03 08:34:55  sybreon
+ Minor code cleanup.
+
+ Revision 1.2  2007/11/02 19:20:58  sybreon
+ Added better (beta) interrupt support.
+ Changed MSR_IE to disabled at reset as per MB docs.
+
+ Revision 1.1  2007/11/02 03:25:40  sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+*/ 
\ No newline at end of file
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v
new file mode 100644
index 000000000..a4edf1d90
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_ibuf.v
@@ -0,0 +1,192 @@
+/* $Id: aeMB_ibuf.v,v 1.10 2008/01/21 01:02:26 sybreon Exp $
+**
+** AEMB INSTRUCTION BUFFER
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+module aeMB_ibuf (/*AUTOARG*/
+   // Outputs
+   rIMM, rRA, rRD, rRB, rALT, rOPC, rSIMM, xIREG, rSTALL, iwb_stb_o,
+   // Inputs
+   rBRA, rMSR_IE, rMSR_BIP, iwb_dat_i, iwb_ack_i, sys_int_i, gclk,
+   grst, gena, oena
+   );
+   // INTERNAL
+   output [15:0] rIMM;
+   output [4:0]  rRA, rRD, rRB;
+   output [10:0] rALT;
+   output [5:0]  rOPC;
+   output [31:0] rSIMM;
+   output [31:0] xIREG;
+   output 	 rSTALL;   
+   
+   input 	 rBRA;
+   //input [1:0] 	 rXCE;
+   input 	 rMSR_IE;
+   input 	 rMSR_BIP;   
+   
+   // INST WISHBONE
+   output 	 iwb_stb_o;
+   input [31:0]  iwb_dat_i;
+   input 	 iwb_ack_i;
+
+   // SYSTEM
+   input 	 sys_int_i;   
+
+   // SYSTEM
+   input 	 gclk, grst, gena, oena;
+
+   reg [15:0] 	 rIMM;
+   reg [4:0] 	 rRA, rRD;
+   reg [5:0] 	 rOPC;
+
+   // FIXME: Endian
+   wire [31:0] 	 wIDAT = iwb_dat_i;
+   assign 	 {rRB, rALT} = rIMM;   
+   
+   // TODO: Assign to FIFO not full.
+   assign 	iwb_stb_o = 1'b1;
+
+   reg [31:0] 	rSIMM, xSIMM;
+   reg 		rSTALL;   
+
+   wire [31:0] 	wXCEOP = 32'hBA2D0008; // Vector 0x08
+   wire [31:0] 	wINTOP = 32'hB9CE0010; // Vector 0x10
+   wire [31:0] 	wBRKOP = 32'hBA0C0018; // Vector 0x18
+   wire [31:0] 	wBRAOP = 32'h88000000; // NOP for branches
+   
+   wire [31:0] 	wIREG = {rOPC, rRD, rRA, rRB, rALT};   
+   reg [31:0] 	xIREG;
+
+
+   // --- INTERRUPT LATCH --------------------------------------
+   // Debounce and latch onto the positive level. This is independent
+   // of the pipeline so that stalls do not affect it.
+   
+   reg 		rFINT;
+   reg [1:0] 	rDINT;
+   wire 	wSHOT = rDINT[0];	
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rDINT <= 2'h0;
+	rFINT <= 1'h0;
+	// End of automatics
+     end else begin
+	if (rMSR_IE)
+	  rDINT <= #1 
+		   {rDINT[0], sys_int_i};
+	
+	rFINT <= #1 
+		 //(wIREG == wINTOP) ? 1'b0 : 
+		 (rFINT | wSHOT) & rMSR_IE;
+     end
+
+   wire 	fIMM = (rOPC == 6'o54);
+   wire 	fRTD = (rOPC == 6'o55);
+   wire 	fBRU = ((rOPC == 6'o46) | (rOPC == 6'o56));
+   wire 	fBCC = ((rOPC == 6'o47) | (rOPC == 6'o57));   
+   
+   // --- DELAY SLOT -------------------------------------------
+   
+   always @(/*AUTOSENSE*/fBCC or fBRU or fIMM or fRTD or rBRA or rFINT
+	    or wBRAOP or wIDAT or wINTOP) begin
+      xIREG <= (rBRA) ? wBRAOP : 
+	       (!fIMM & rFINT & !fRTD & !fBRU & !fBCC) ? wINTOP :
+	       wIDAT;
+   end
+   
+   always @(/*AUTOSENSE*/fIMM or rBRA or rIMM or wIDAT or xIREG) begin
+      xSIMM <= (!fIMM | rBRA) ? { {(16){xIREG[15]}}, xIREG[15:0]} :
+	       {rIMM, wIDAT[15:0]};
+   end   
+
+   // --- PIPELINE --------------------------------------------
+   
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rIMM <= 16'h0;
+	rOPC <= 6'h0;
+	rRA <= 5'h0;
+	rRD <= 5'h0;
+	rSIMM <= 32'h0;
+	// End of automatics
+     end else if (gena) begin
+	{rOPC, rRD, rRA, rIMM} <= #1 xIREG;
+	rSIMM <= #1 xSIMM;	
+     end
+
+   // --- STALL FOR MUL/BSF -----------------------------------
+
+   wire [5:0] wOPC = xIREG[31:26];   
+   
+   wire       fMUL = (wOPC == 6'o20) | (wOPC == 6'o30);
+   wire       fBSF = (wOPC == 6'o21) | (wOPC == 6'o31);   
+   
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rSTALL <= 1'h0;
+	// End of automatics
+     end else begin
+	rSTALL <= #1 (gena & !rSTALL & (fMUL | fBSF)) | (oena & rSTALL);	
+     end
+   
+endmodule // aeMB_ibuf
+
+/*
+ $Log: aeMB_ibuf.v,v $
+ Revision 1.10  2008/01/21 01:02:26  sybreon
+ Patch interrupt bug.
+
+ Revision 1.9  2008/01/19 16:01:22  sybreon
+ Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)
+
+ Revision 1.8  2007/12/25 22:15:09  sybreon
+ Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
+
+ Revision 1.7  2007/11/22 15:11:15  sybreon
+ Change interrupt to positive level triggered interrupts.
+
+ Revision 1.6  2007/11/14 23:39:51  sybreon
+ Fixed interrupt signal synchronisation.
+
+ Revision 1.5  2007/11/14 22:14:34  sybreon
+ Changed interrupt handling system (reported by M. Ettus).
+
+ Revision 1.4  2007/11/10 16:39:38  sybreon
+ Upgraded license to LGPLv3.
+ Significant performance optimisations.
+
+ Revision 1.3  2007/11/03 08:34:55  sybreon
+ Minor code cleanup.
+
+ Revision 1.2  2007/11/02 19:20:58  sybreon
+ Added better (beta) interrupt support.
+ Changed MSR_IE to disabled at reset as per MB docs.
+
+ Revision 1.1  2007/11/02 03:25:40  sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+*/
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
new file mode 100644
index 000000000..9ac45299b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_regf.v
@@ -0,0 +1,241 @@
+// $Id: aeMB_regf.v,v 1.3 2007/11/10 16:39:38 sybreon Exp $
+//
+// AEMB REGISTER FILE
+// 
+// Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+//  
+// This file is part of AEMB.
+//
+// AEMB is free software: you can redistribute it and/or modify it
+// under the terms of the GNU Lesser General Public License as
+// published by the Free Software Foundation, either version 3 of the
+// License, or (at your option) any later version.
+//
+// AEMB is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+// Public License for more details.
+//
+// You should have received a copy of the GNU Lesser General Public
+// License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+//
+// $Log: aeMB_regf.v,v $
+// Revision 1.3  2007/11/10 16:39:38  sybreon
+// Upgraded license to LGPLv3.
+// Significant performance optimisations.
+//
+// Revision 1.2  2007/11/09 20:51:52  sybreon
+// Added GET/PUT support through a FSL bus.
+//
+// Revision 1.1  2007/11/02 03:25:41  sybreon
+// New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+// Fixed various minor data hazard bugs.
+// Code compatible with -O0/1/2/3/s generated code.
+//
+
+module aeMB_regf (/*AUTOARG*/
+   // Outputs
+   rREGA, rREGB, rDWBDI, dwb_dat_o, fsl_dat_o,
+   // Inputs
+   rOPC, rRA, rRB, rRW, rRD, rMXDST, rPCLNK, rRESULT, rDWBSEL, rBRA,
+   rDLY, dwb_dat_i, fsl_dat_i, gclk, grst, gena
+   );
+   // INTERNAL
+   output [31:0] rREGA, rREGB;
+   output [31:0] rDWBDI;
+   input [5:0] 	 rOPC;   
+   input [4:0] 	 rRA, rRB, rRW, rRD;
+   input [1:0] 	 rMXDST;
+   input [31:2]  rPCLNK;
+   input [31:0]  rRESULT;
+   input [3:0] 	 rDWBSEL;   
+   input 	 rBRA, rDLY;   
+   
+   // DATA WISHBONE
+   output [31:0] dwb_dat_o;   
+   input [31:0]  dwb_dat_i;   
+
+   // FSL WISHBONE
+   output [31:0] fsl_dat_o;
+   input [31:0]	 fsl_dat_i;   
+   
+   // SYSTEM
+   input 	 gclk, grst, gena;   
+
+   // --- LOAD SIZER ----------------------------------------------
+   // Moves the data bytes around depending on the size of the
+   // operation.
+
+   wire [31:0] 	 wDWBDI = dwb_dat_i; // FIXME: Endian
+   wire [31:0] 	 wFSLDI = fsl_dat_i; // FIXME: Endian
+    
+   reg [31:0] 	 rDWBDI;
+   reg [1:0] 	 rSIZ;
+   
+   always @(/*AUTOSENSE*/rDWBSEL or wDWBDI or wFSLDI) begin
+      /* 51.2
+       case (rSIZ)
+        // FSL
+        2'o3: rDWBDI <= wFSLDI;	
+        // 32'bit
+        2'o2: rDWBDI <= wDWBDI;
+	// 16'bit
+	2'o1: case (rRESULT[1])
+		1'b0: rDWBDI <= {16'd0, wDWBDI[31:16]};
+		1'b1: rDWBDI <= {16'd0, wDWBDI[15:0]};		
+	      endcase // case (rRESULT[1])
+	// 8'bit
+	2'o0: case (rRESULT[1:0])
+		2'o0: rDWBDI <= {24'd0, wDWBDI[31:24]};
+		2'o1: rDWBDI <= {24'd0, wDWBDI[23:16]};
+		2'o2: rDWBDI <= {24'd0, wDWBDI[15:8]};
+		2'o3: rDWBDI <= {24'd0, wDWBDI[7:0]};
+	      endcase // case (rRESULT[1:0])
+      endcase // case (rSIZ)
+      */
+      
+      /* 50.6
+      case ({rSIZ, rRESULT[1:0]})
+	// FSL
+	4'hC, 4'hD, 4'hE, 4'hF: rDWBDI <= wFSLDI;	
+	// 32'bit
+	4'h8: rDWBDI <= wDWBDI;
+	// 16'bit
+	4'h4: rDWBDI <= {16'd0, wDWBDI[31:16]};
+	4'h6: rDWBDI <= {16'd0, wDWBDI[15:0]};		
+	// 8'bit
+	4'h0: rDWBDI <= {24'd0, wDWBDI[31:24]};
+	4'h1: rDWBDI <= {24'd0, wDWBDI[23:16]};
+	4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
+	4'h3: rDWBDI <= {24'd0, wDWBDI[7:0]};
+	default: rDWBDI <= 32'hX;	
+      endcase // case (rSIZ)
+      */
+
+      // 52.0
+      case (rDWBSEL)
+	// 8'bit
+	4'h8: rDWBDI <= {24'd0, wDWBDI[31:24]};
+	4'h4: rDWBDI <= {24'd0, wDWBDI[23:16]};
+	4'h2: rDWBDI <= {24'd0, wDWBDI[15:8]};
+	4'h1: rDWBDI <= {24'd0, wDWBDI[7:0]};
+	// 16'bit
+	4'hC: rDWBDI <= {16'd0, wDWBDI[31:16]};
+	4'h3: rDWBDI <= {16'd0, wDWBDI[15:0]};
+	// 32'bit
+	4'hF: rDWBDI <= wDWBDI;
+	// FSL
+	4'h0: rDWBDI <= wFSLDI;       
+	// Undefined
+	default: rDWBDI <= 32'hX;       
+      endcase
+       
+   end
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rSIZ <= 2'h0;
+	// End of automatics
+     end else if (gena) begin
+	rSIZ <= rOPC[1:0];	
+     end
+   
+   // --- GENERAL PURPOSE REGISTERS (R0-R31) -----------------------
+   // LUT RAM implementation is smaller and faster. R0 gets written
+   // during reset with 0x00 and doesn't change after.
+   
+   reg [31:0] 	 mARAM[0:31],
+		 mBRAM[0:31],
+		 mDRAM[0:31];
+
+   wire [31:0] 	 rREGW = mDRAM[rRW];   
+   wire [31:0] 	 rREGD = mDRAM[rRD];   
+   assign 	 rREGA = mARAM[rRA];
+   assign 	 rREGB = mBRAM[rRB];
+
+   wire 	 fRDWE = |rRW;   
+   
+   reg [31:0] 	 xWDAT;
+
+   always @(/*AUTOSENSE*/rDWBDI or rMXDST or rPCLNK or rREGW
+	    or rRESULT)
+     case (rMXDST)
+       2'o2: xWDAT <= rDWBDI;
+       2'o1: xWDAT <= {rPCLNK, 2'o0};
+       2'o0: xWDAT <= rRESULT;       
+       2'o3: xWDAT <= rREGW; // No change       
+     endcase // case (rMXDST)
+   
+   always @(posedge gclk)
+     if (grst | fRDWE) begin
+	mARAM[rRW] <= xWDAT;
+	mBRAM[rRW] <= xWDAT;
+	mDRAM[rRW] <= xWDAT;	
+     end
+
+   // --- STORE SIZER ---------------------------------------------
+   // Replicates the data bytes across depending on the size of the
+   // operation.
+
+   reg [31:0] 	 rDWBDO, xDWBDO;
+   
+   wire [31:0] 	 xFSL;   
+   wire 	 fFFWD_M = (rRA == rRW) & (rMXDST == 2'o2) & fRDWE;
+   wire 	 fFFWD_R = (rRA == rRW) & (rMXDST == 2'o0) & fRDWE;   
+   
+   assign 	 fsl_dat_o = rDWBDO;
+   assign 	 xFSL = (fFFWD_M) ? rDWBDI :
+			(fFFWD_R) ? rRESULT :
+			rREGA;   
+
+   wire [31:0] 	 xDST;   
+   wire 	 fDFWD_M = (rRW == rRD) & (rMXDST == 2'o2) & fRDWE;
+   wire 	 fDFWD_R = (rRW == rRD) & (rMXDST == 2'o0) & fRDWE;   
+   
+   assign 	 dwb_dat_o = rDWBDO;
+   assign 	 xDST = (fDFWD_M) ? rDWBDI :
+			(fDFWD_R) ? rRESULT :
+			rREGD;   
+   
+   always @(/*AUTOSENSE*/rOPC or xDST or xFSL)
+     case (rOPC[1:0])
+       // 8'bit
+       2'h0: xDWBDO <= {(4){xDST[7:0]}};
+       // 16'bit
+       2'h1: xDWBDO <= {(2){xDST[15:0]}};
+       // 32'bit
+       2'h2: xDWBDO <= xDST;
+       // FSL
+       2'h3: xDWBDO <= xFSL;       
+       //default: xDWBDO <= 32'hX;       
+     endcase // case (rOPC[1:0])   
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rDWBDO <= 32'h0;
+	// End of automatics
+     end else if (gena) begin
+	rDWBDO <= #1 xDWBDO;	
+     end
+   
+   // --- SIMULATION ONLY ------------------------------------------
+   // Randomise memory to simulate real-world memory
+   // synopsys translate_off
+   
+   integer i;
+   initial begin
+      for (i=0; i<32; i=i+1) begin
+	 mARAM[i] <= $random;
+	 mBRAM[i] <= $random;
+	 mDRAM[i] <= $random;
+      end
+   end
+   
+   // synopsys translate_on
+   
+   
+endmodule // aeMB_regf
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v
new file mode 100644
index 000000000..83248e4ba
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_sim.v
@@ -0,0 +1,312 @@
+/* $Id: aeMB_sim.v,v 1.2 2008/06/06 09:36:02 sybreon Exp $
+**
+** AEMB EDK 3.2 Compatible Core
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+module aeMB_sim (/*AUTOARG*/
+   // Outputs
+   iwb_stb_o, iwb_adr_o, fsl_wre_o, fsl_tag_o, fsl_stb_o, fsl_dat_o,
+   fsl_adr_o, dwb_wre_o, dwb_stb_o, dwb_sel_o, dwb_dat_o, dwb_adr_o,
+   // Inputs
+   sys_rst_i, sys_int_i, sys_clk_i, iwb_dat_i, iwb_ack_i, fsl_dat_i,
+   fsl_ack_i, dwb_dat_i, dwb_ack_i
+   );
+   // Bus widths
+   parameter IW = 32; /// Instruction bus address width
+   parameter DW = 32; /// Data bus address width
+
+   // Optional functions
+   parameter MUL = 1; // Multiplier
+   parameter BSF = 1; // Barrel Shifter
+      
+   /*AUTOOUTPUT*/
+   // Beginning of automatic outputs (from unused autoinst outputs)
+   output [DW-1:2]	dwb_adr_o;		// From cpu of aeMB_edk32.v
+   output [31:0]	dwb_dat_o;		// From cpu of aeMB_edk32.v
+   output [3:0]		dwb_sel_o;		// From cpu of aeMB_edk32.v
+   output		dwb_stb_o;		// From cpu of aeMB_edk32.v
+   output		dwb_wre_o;		// From cpu of aeMB_edk32.v
+   output [6:2]		fsl_adr_o;		// From cpu of aeMB_edk32.v
+   output [31:0]	fsl_dat_o;		// From cpu of aeMB_edk32.v
+   output		fsl_stb_o;		// From cpu of aeMB_edk32.v
+   output [1:0]		fsl_tag_o;		// From cpu of aeMB_edk32.v
+   output		fsl_wre_o;		// From cpu of aeMB_edk32.v
+   output [IW-1:2]	iwb_adr_o;		// From cpu of aeMB_edk32.v
+   output		iwb_stb_o;		// From cpu of aeMB_edk32.v
+   // End of automatics
+   /*AUTOINPUT*/
+   // Beginning of automatic inputs (from unused autoinst inputs)
+   input		dwb_ack_i;		// To cpu of aeMB_edk32.v
+   input [31:0]		dwb_dat_i;		// To cpu of aeMB_edk32.v
+   input		fsl_ack_i;		// To cpu of aeMB_edk32.v
+   input [31:0]		fsl_dat_i;		// To cpu of aeMB_edk32.v
+   input		iwb_ack_i;		// To cpu of aeMB_edk32.v
+   input [31:0]		iwb_dat_i;		// To cpu of aeMB_edk32.v
+   input		sys_clk_i;		// To cpu of aeMB_edk32.v
+   input		sys_int_i;		// To cpu of aeMB_edk32.v
+   input		sys_rst_i;		// To cpu of aeMB_edk32.v
+   // End of automatics
+   /*AUTOWIRE*/
+
+   aeMB_edk32
+     #(/*AUTOINSTPARAM*/
+       // Parameters
+       .IW				(IW),
+       .DW				(DW),
+       .MUL				(MUL),
+       .BSF				(BSF))
+   cpu
+     (/*AUTOINST*/
+      // Outputs
+      .dwb_adr_o			(dwb_adr_o[DW-1:2]),
+      .dwb_dat_o			(dwb_dat_o[31:0]),
+      .dwb_sel_o			(dwb_sel_o[3:0]),
+      .dwb_stb_o			(dwb_stb_o),
+      .dwb_wre_o			(dwb_wre_o),
+      .fsl_adr_o			(fsl_adr_o[6:2]),
+      .fsl_dat_o			(fsl_dat_o[31:0]),
+      .fsl_stb_o			(fsl_stb_o),
+      .fsl_tag_o			(fsl_tag_o[1:0]),
+      .fsl_wre_o			(fsl_wre_o),
+      .iwb_adr_o			(iwb_adr_o[IW-1:2]),
+      .iwb_stb_o			(iwb_stb_o),
+      // Inputs
+      .dwb_ack_i			(dwb_ack_i),
+      .dwb_dat_i			(dwb_dat_i[31:0]),
+      .fsl_ack_i			(fsl_ack_i),
+      .fsl_dat_i			(fsl_dat_i[31:0]),
+      .iwb_ack_i			(iwb_ack_i),
+      .iwb_dat_i			(iwb_dat_i[31:0]),
+      .sys_int_i			(sys_int_i),
+      .sys_clk_i			(sys_clk_i),
+      .sys_rst_i			(sys_rst_i));
+   
+   // --- SIMULATION KERNEL ----------------------------------
+   // synopsys translate_off
+   
+   wire [IW-1:0] 	iwb_adr = {iwb_adr_o, 2'd0};
+   wire [DW-1:0] 	dwb_adr = {dwb_adr_o,2'd0};   
+   wire [1:0] 		wBRA = {cpu.rBRA, cpu.rDLY};   
+   wire [3:0] 		wMSR = {cpu.xecu.rMSR_BIP, cpu.xecu.rMSR_C, cpu.xecu.rMSR_IE, cpu.xecu.rMSR_BE};
+
+
+   `ifdef AEMB_SIM_KERNEL
+   always @(posedge cpu.gclk) begin
+      if (cpu.gena) begin
+	 
+	 $write ("\n", ($stime/10));
+	 $writeh (" PC=", iwb_adr );
+	 $writeh ("\t");
+	 
+	 case (wBRA)
+	   2'b00: $write(" ");
+	   2'b01: $write(".");	
+	   2'b10: $write("-");
+	   2'b11: $write("+");	
+	 endcase // case (cpu.wBRA)
+      
+	 case (cpu.rOPC)
+	   6'o00: if (cpu.rRD == 0) $write("   "); else $write("ADD");
+	   6'o01: $write("RSUB");	
+	   6'o02: $write("ADDC");	
+	   6'o03: $write("RSUBC");	
+	   6'o04: $write("ADDK");	
+	   6'o05: case (cpu.rIMM[1:0])
+		    2'o0: $write("RSUBK");	
+		    2'o1: $write("CMP");	
+		    2'o3: $write("CMPU");	
+		    default: $write("XXX");
+		  endcase // case (cpu.rIMM[1:0])
+	   6'o06: $write("ADDKC");	
+	   6'o07: $write("RSUBKC");	
+	   
+	   6'o10: $write("ADDI");	
+	   6'o11: $write("RSUBI");	
+	   6'o12: $write("ADDIC");	
+	   6'o13: $write("RSUBIC");	
+	   6'o14: $write("ADDIK");	
+	   6'o15: $write("RSUBIK");	
+	   6'o16: $write("ADDIKC");	
+	   6'o17: $write("RSUBIKC");	
+	   
+	   6'o20: $write("MUL");	
+	   6'o21: case (cpu.rALT[10:9])
+		    2'o0: $write("BSRL");		 
+		    2'o1: $write("BSRA");		 
+		    2'o2: $write("BSLL");		 
+		    default: $write("XXX");		 
+		  endcase // case (cpu.rALT[10:9])
+	   6'o22: $write("IDIV");	
+	   
+	   6'o30: $write("MULI");	
+	   6'o31: case (cpu.rALT[10:9])
+		    2'o0: $write("BSRLI");		 
+		    2'o1: $write("BSRAI");		 
+		    2'o2: $write("BSLLI");		 
+		    default: $write("XXX");		 
+		  endcase // case (cpu.rALT[10:9])
+	   6'o33: case (cpu.rRB[4:2])
+		    3'o0: $write("GET");
+		    3'o4: $write("PUT");		 
+		    3'o2: $write("NGET");
+		    3'o6: $write("NPUT");		 
+		    3'o1: $write("CGET");
+		    3'o5: $write("CPUT");		 
+		    3'o3: $write("NCGET");
+		    3'o7: $write("NCPUT");		 
+		  endcase // case (cpu.rRB[4:2])
+	   
+	   6'o40: $write("OR");
+	   6'o41: $write("AND");	
+	   6'o42: if (cpu.rRD == 0) $write("   "); else $write("XOR");
+	   6'o43: $write("ANDN");	
+	   6'o44: case (cpu.rIMM[6:5])
+		    2'o0: $write("SRA");
+		    2'o1: $write("SRC");
+		    2'o2: $write("SRL");
+		    2'o3: if (cpu.rIMM[0]) $write("SEXT16"); else $write("SEXT8");		 
+		  endcase // case (cpu.rIMM[6:5])
+	   
+	   6'o45: $write("MOV");	
+	   6'o46: case (cpu.rRA[3:2])
+		    3'o0: $write("BR");		 
+		    3'o1: $write("BRL");		 
+		    3'o2: $write("BRA");		 
+		    3'o3: $write("BRAL");		 
+		  endcase // case (cpu.rRA[3:2])
+	   
+	   6'o47: case (cpu.rRD[2:0])
+		    3'o0: $write("BEQ");	
+		    3'o1: $write("BNE");	
+		    3'o2: $write("BLT");	
+		    3'o3: $write("BLE");	
+		    3'o4: $write("BGT");	
+		    3'o5: $write("BGE");
+		    default: $write("XXX");		 
+		  endcase // case (cpu.rRD[2:0])
+	   
+	   6'o50: $write("ORI");	
+	   6'o51: $write("ANDI");	
+	   6'o52: $write("XORI");	
+	   6'o53: $write("ANDNI");	
+	   6'o54: $write("IMMI");	
+	   6'o55: case (cpu.rRD[1:0])
+		    2'o0: $write("RTSD");
+		    2'o1: $write("RTID");
+		    2'o2: $write("RTBD");
+		    default: $write("XXX");		 
+		  endcase // case (cpu.rRD[1:0])
+	   6'o56: case (cpu.rRA[3:2])
+		    3'o0: $write("BRI");		 
+		    3'o1: $write("BRLI");		 
+		    3'o2: $write("BRAI");		 
+		    3'o3: $write("BRALI");		 
+		  endcase // case (cpu.rRA[3:2])
+	   6'o57: case (cpu.rRD[2:0])
+		    3'o0: $write("BEQI");	
+		    3'o1: $write("BNEI");	
+		    3'o2: $write("BLTI");	
+		    3'o3: $write("BLEI");	
+		    3'o4: $write("BGTI");	
+		    3'o5: $write("BGEI");	
+		    default: $write("XXX");		 
+		  endcase // case (cpu.rRD[2:0])
+	   
+	   6'o60: $write("LBU");	
+	   6'o61: $write("LHU");	
+	   6'o62: $write("LW");	
+	   6'o64: $write("SB");	
+	   6'o65: $write("SH");	
+	   6'o66: $write("SW");	
+	   
+	   6'o70: $write("LBUI");	
+	   6'o71: $write("LHUI");	
+	   6'o72: $write("LWI");	
+	   6'o74: $write("SBI");	
+	   6'o75: $write("SHI");	
+	   6'o76: $write("SWI");
+	   
+	   default: $write("XXX");	
+	 endcase // case (cpu.rOPC)
+	 
+	 case (cpu.rOPC[3])
+	   1'b1: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", h",cpu.rIMM);
+	   1'b0: $writeh("\tr",cpu.rRD,", r",cpu.rRA,", r",cpu.rRB,"  ");	
+	 endcase // case (cpu.rOPC[3])
+	 
+	 
+	 // ALU
+	 $write("\t");
+	 $writeh(" A=",cpu.xecu.rOPA);
+	 $writeh(" B=",cpu.xecu.rOPB);
+	 
+	 case (cpu.rMXALU)
+	   3'o0: $write(" ADD");
+	   3'o1: $write(" LOG");
+	   3'o2: $write(" SFT");
+	   3'o3: $write(" MOV");
+	   3'o4: $write(" MUL");
+	   3'o5: $write(" BSF");
+	   default: $write(" XXX");
+	 endcase // case (cpu.rMXALU)
+	 $writeh("=h",cpu.xecu.xRESULT);
+	 
+	 // WRITEBACK
+	 $writeh("\tSR=", wMSR," ");
+	 
+	 if (cpu.regf.fRDWE) begin
+	    case (cpu.rMXDST)
+	      2'o2: begin
+		 if (dwb_stb_o) $writeh("R",cpu.rRW,"=RAM(h",cpu.regf.xWDAT,")");
+		 if (fsl_stb_o) $writeh("R",cpu.rRW,"=FSL(h",cpu.regf.xWDAT,")");
+	      end
+	      2'o1: $writeh("R",cpu.rRW,"=LNK(h",cpu.regf.xWDAT,")");
+	      2'o0: $writeh("R",cpu.rRW,"=ALU(h",cpu.regf.xWDAT,")");
+	    endcase // case (cpu.rMXDST)
+	 end
+	 
+	 // STORE
+	 if (dwb_stb_o & dwb_wre_o) begin
+	    $writeh("RAM(", dwb_adr ,")=", dwb_dat_o);
+	    case (dwb_sel_o)
+	      4'hF: $write(":L");
+	      4'h3,4'hC: $write(":W");
+	      4'h1,4'h2,4'h4,4'h8: $write(":B");
+	    endcase // case (dwb_sel_o)
+	    
+	 end
+	 
+      end // if (cpu.gena)
+      
+   end // always @ (posedge cpu.gclk)
+   `endif //  `ifdef AEMB_SIM_KERNEL
+   
+   // synopsys translate_on
+   
+endmodule // aeMB_sim
+
+/* 
+ $Log: aeMB_sim.v,v $
+ Revision 1.2  2008/06/06 09:36:02  sybreon
+ single thread design
+
+ Revision 1.1  2007/12/23 20:40:45  sybreon
+ Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
+ 
+ */
\ No newline at end of file
diff --git a/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v
new file mode 100644
index 000000000..5de2ea619
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_xecu.v
@@ -0,0 +1,412 @@
+/* $Id: aeMB_xecu.v,v 1.12 2008/05/11 13:48:46 sybreon Exp $
+**
+** AEMB MAIN EXECUTION ALU
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+module aeMB_xecu (/*AUTOARG*/
+   // Outputs
+   dwb_adr_o, dwb_sel_o, fsl_adr_o, fsl_tag_o, rRESULT, rDWBSEL,
+   rMSR_IE, rMSR_BIP,
+   // Inputs
+   rREGA, rREGB, rMXSRC, rMXTGT, rRA, rRB, rMXALU, rBRA, rDLY, rALT,
+   rSTALL, rSIMM, rIMM, rOPC, rRD, rDWBDI, rPC, gclk, grst, gena
+   );
+   parameter DW=32;
+
+   parameter MUL=0;
+   parameter BSF=0;   
+   
+   // DATA WISHBONE
+   output [DW-1:2] dwb_adr_o;
+   output [3:0]    dwb_sel_o;
+
+   // FSL WISHBONE
+   output [6:2]   fsl_adr_o;
+   output [1:0]   fsl_tag_o;   
+   
+   // INTERNAL
+   output [31:0]   rRESULT;
+   output [3:0]    rDWBSEL;   
+   output 	   rMSR_IE;
+   output 	   rMSR_BIP;
+   input [31:0]    rREGA, rREGB;
+   input [1:0] 	   rMXSRC, rMXTGT;
+   input [4:0] 	   rRA, rRB;
+   input [2:0] 	   rMXALU;
+   input 	   rBRA, rDLY;
+   input [10:0]    rALT;   
+
+   input 	   rSTALL;   
+   input [31:0]    rSIMM;
+   input [15:0]    rIMM;
+   input [5:0] 	   rOPC;
+   input [4:0] 	   rRD;   
+   input [31:0]    rDWBDI;
+   input [31:2]    rPC;   
+   
+   // SYSTEM
+   input 	   gclk, grst, gena;
+
+   reg 		   rMSR_C, xMSR_C;
+   reg 		   rMSR_IE, xMSR_IE;
+   reg 		   rMSR_BE, xMSR_BE;
+   reg 		   rMSR_BIP, xMSR_BIP;
+   
+   wire 	   fSKIP = rBRA & !rDLY;
+
+   // --- OPERAND SELECT
+
+   reg [31:0] 	   rOPA, rOPB;
+   always @(/*AUTOSENSE*/rDWBDI or rMXSRC or rPC or rREGA or rRESULT)
+     case (rMXSRC)
+       2'o0: rOPA <= rREGA;
+       2'o1: rOPA <= rRESULT;
+       2'o2: rOPA <= rDWBDI;
+       2'o3: rOPA <= {rPC, 2'o0};       
+     endcase // case (rMXSRC)
+   
+   always @(/*AUTOSENSE*/rDWBDI or rMXTGT or rREGB or rRESULT or rSIMM)
+     case (rMXTGT)
+       2'o0: rOPB <= rREGB;
+       2'o1: rOPB <= rRESULT;
+       2'o2: rOPB <= rDWBDI;
+       2'o3: rOPB <= rSIMM;       
+     endcase // case (rMXTGT)
+
+   // --- ADD/SUB SELECTOR ----
+
+   reg 		    rRES_ADDC;
+   reg [31:0] 	    rRES_ADD;
+   
+   wire [31:0] 		wADD;
+   wire 		wADC;
+
+   wire 		fCCC = !rOPC[5] & rOPC[1]; // & !rOPC[4]
+   wire 		fSUB = !rOPC[5] & rOPC[0]; // & !rOPC[4]
+   wire 		fCMP = !rOPC[3] & rIMM[1]; // unsigned only
+   wire 		wCMP = (fCMP) ? !wADC : wADD[31]; // cmpu adjust
+   
+   wire [31:0] 		wOPA = (fSUB) ? ~rOPA : rOPA;
+   wire 		wOPC = (fCCC) ? rMSR_C : fSUB;
+   
+   assign 		{wADC, wADD} = (rOPB + wOPA) + wOPC; // add carry
+   
+   always @(/*AUTOSENSE*/wADC or wADD or wCMP) begin
+      {rRES_ADDC, rRES_ADD} <= #1 {wADC, wCMP, wADD[30:0]}; // add with carry
+   end
+   
+   // --- LOGIC SELECTOR --------------------------------------
+
+   reg [31:0] 	    rRES_LOG;
+   always @(/*AUTOSENSE*/rOPA or rOPB or rOPC)
+     case (rOPC[1:0])
+       2'o0: rRES_LOG <= #1 rOPA | rOPB;
+       2'o1: rRES_LOG <= #1 rOPA & rOPB;
+       2'o2: rRES_LOG <= #1 rOPA ^ rOPB;
+       2'o3: rRES_LOG <= #1 rOPA & ~rOPB;       
+     endcase // case (rOPC[1:0])
+
+   // --- SHIFTER SELECTOR ------------------------------------
+   
+   reg [31:0] 	    rRES_SFT;
+   reg 		    rRES_SFTC;
+   
+   always @(/*AUTOSENSE*/rIMM or rMSR_C or rOPA)
+     case (rIMM[6:5])
+       2'o0: {rRES_SFT, rRES_SFTC} <= #1 {rOPA[31],rOPA[31:0]};
+       2'o1: {rRES_SFT, rRES_SFTC} <= #1 {rMSR_C,rOPA[31:0]};
+       2'o2: {rRES_SFT, rRES_SFTC} <= #1 {1'b0,rOPA[31:0]};
+       2'o3: {rRES_SFT, rRES_SFTC} <= #1 (rIMM[0]) ? { {(16){rOPA[15]}}, rOPA[15:0], rMSR_C} :
+				      { {(24){rOPA[7]}}, rOPA[7:0], rMSR_C};
+     endcase // case (rIMM[6:5])
+
+   // --- MOVE SELECTOR ---------------------------------------
+   
+   wire [31:0] 	    wMSR = {rMSR_C, 3'o0, 
+			    20'h0ED32, 
+			    4'h0, rMSR_BIP, rMSR_C, rMSR_IE, rMSR_BE};      
+   wire 	    fMFSR = (rOPC == 6'o45) & !rIMM[14] & rIMM[0];
+   wire 	    fMFPC = (rOPC == 6'o45) & !rIMM[14] & !rIMM[0];
+   reg [31:0] 	    rRES_MOV;
+   always @(/*AUTOSENSE*/fMFPC or fMFSR or rOPA or rOPB or rPC or rRA
+	    or wMSR)
+     rRES_MOV <= (fMFSR) ? wMSR :
+		 (fMFPC) ? rPC :
+		 (rRA[3]) ? rOPB : 
+		 rOPA;   
+   
+   // --- MULTIPLIER ------------------------------------------
+   // TODO: 2 stage multiplier
+   
+   reg [31:0] 	    rRES_MUL, rRES_MUL0, xRES_MUL;
+   always @(/*AUTOSENSE*/rOPA or rOPB) begin
+      xRES_MUL <= (rOPA * rOPB);
+   end
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rRES_MUL <= 32'h0;
+	// End of automatics
+     end else if (rSTALL) begin
+	rRES_MUL <= #1 xRES_MUL;	
+     end
+
+   
+   // --- BARREL SHIFTER --------------------------------------
+
+   reg [31:0] 	 rRES_BSF;
+   reg [31:0] 	 xBSRL, xBSRA, xBSLL;
+   
+   // Infer a logical left barrel shifter.   
+   always @(/*AUTOSENSE*/rOPA or rOPB)
+     xBSLL <= rOPA << rOPB[4:0];
+   
+   // Infer a logical right barrel shifter.
+   always @(/*AUTOSENSE*/rOPA or rOPB)
+     xBSRL <= rOPA >> rOPB[4:0];
+
+   // Infer a arithmetic right barrel shifter.
+   always @(/*AUTOSENSE*/rOPA or rOPB)
+     case (rOPB[4:0])
+       5'd00: xBSRA <= rOPA;
+       5'd01: xBSRA <= {{(1){rOPA[31]}}, rOPA[31:1]};
+       5'd02: xBSRA <= {{(2){rOPA[31]}}, rOPA[31:2]};
+       5'd03: xBSRA <= {{(3){rOPA[31]}}, rOPA[31:3]};
+       5'd04: xBSRA <= {{(4){rOPA[31]}}, rOPA[31:4]};
+       5'd05: xBSRA <= {{(5){rOPA[31]}}, rOPA[31:5]};
+       5'd06: xBSRA <= {{(6){rOPA[31]}}, rOPA[31:6]};
+       5'd07: xBSRA <= {{(7){rOPA[31]}}, rOPA[31:7]};
+       5'd08: xBSRA <= {{(8){rOPA[31]}}, rOPA[31:8]};
+       5'd09: xBSRA <= {{(9){rOPA[31]}}, rOPA[31:9]};
+       5'd10: xBSRA <= {{(10){rOPA[31]}}, rOPA[31:10]};
+       5'd11: xBSRA <= {{(11){rOPA[31]}}, rOPA[31:11]};
+       5'd12: xBSRA <= {{(12){rOPA[31]}}, rOPA[31:12]};
+       5'd13: xBSRA <= {{(13){rOPA[31]}}, rOPA[31:13]};
+       5'd14: xBSRA <= {{(14){rOPA[31]}}, rOPA[31:14]};
+       5'd15: xBSRA <= {{(15){rOPA[31]}}, rOPA[31:15]};
+       5'd16: xBSRA <= {{(16){rOPA[31]}}, rOPA[31:16]};
+       5'd17: xBSRA <= {{(17){rOPA[31]}}, rOPA[31:17]};
+       5'd18: xBSRA <= {{(18){rOPA[31]}}, rOPA[31:18]};
+       5'd19: xBSRA <= {{(19){rOPA[31]}}, rOPA[31:19]};
+       5'd20: xBSRA <= {{(20){rOPA[31]}}, rOPA[31:20]};
+       5'd21: xBSRA <= {{(21){rOPA[31]}}, rOPA[31:21]};
+       5'd22: xBSRA <= {{(22){rOPA[31]}}, rOPA[31:22]};
+       5'd23: xBSRA <= {{(23){rOPA[31]}}, rOPA[31:23]};
+       5'd24: xBSRA <= {{(24){rOPA[31]}}, rOPA[31:24]};
+       5'd25: xBSRA <= {{(25){rOPA[31]}}, rOPA[31:25]};
+       5'd26: xBSRA <= {{(26){rOPA[31]}}, rOPA[31:26]};
+       5'd27: xBSRA <= {{(27){rOPA[31]}}, rOPA[31:27]};
+       5'd28: xBSRA <= {{(28){rOPA[31]}}, rOPA[31:28]};
+       5'd29: xBSRA <= {{(29){rOPA[31]}}, rOPA[31:29]};
+       5'd30: xBSRA <= {{(30){rOPA[31]}}, rOPA[31:30]};
+       5'd31: xBSRA <= {{(31){rOPA[31]}}, rOPA[31]};
+     endcase // case (rOPB[4:0])
+
+   reg [31:0] 	 rBSRL, rBSRA, rBSLL;
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rBSLL <= 32'h0;
+	rBSRA <= 32'h0;
+	rBSRL <= 32'h0;
+	// End of automatics
+     end else if (rSTALL) begin
+	rBSRL <= #1 xBSRL;
+	rBSRA <= #1 xBSRA;
+	rBSLL <= #1 xBSLL;	
+     end
+   
+   always @(/*AUTOSENSE*/rALT or rBSLL or rBSRA or rBSRL)
+     case (rALT[10:9])
+       2'd0: rRES_BSF <= rBSRL;
+       2'd1: rRES_BSF <= rBSRA;       
+       2'd2: rRES_BSF <= rBSLL;
+       default: rRES_BSF <= 32'hX;       
+     endcase // case (rALT[10:9])
+   
+   
+   // --- MSR REGISTER -----------------
+   
+   // C
+   wire 	   fMTS = (rOPC == 6'o45) & rIMM[14] & !fSKIP;
+   wire 	   fADDC = ({rOPC[5:4], rOPC[2]} == 3'o0);
+   
+   always @(/*AUTOSENSE*/fADDC or fMTS or fSKIP or rMSR_C or rMXALU
+	    or rOPA or rRES_ADDC or rRES_SFTC)
+     //if (fSKIP | |rXCE) begin
+     if (fSKIP) begin
+	xMSR_C <= rMSR_C;
+     end else
+       case (rMXALU)
+	 3'o0: xMSR_C <= (fADDC) ? rRES_ADDC : rMSR_C;	 
+	 3'o1: xMSR_C <= rMSR_C; // LOGIC       
+	 3'o2: xMSR_C <= rRES_SFTC; // SHIFT
+	 3'o3: xMSR_C <= (fMTS) ? rOPA[2] : rMSR_C;
+	 3'o4: xMSR_C <= rMSR_C;	 
+	 3'o5: xMSR_C <= rMSR_C;	 
+	 default: xMSR_C <= 1'hX;       
+       endcase // case (rMXALU)
+
+   // IE/BIP/BE
+   wire 	    fRTID = (rOPC == 6'o55) & rRD[0] & !fSKIP;   
+   wire 	    fRTBD = (rOPC == 6'o55) & rRD[1] & !fSKIP;
+   wire 	    fBRK = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hC);
+   wire 	    fINT = ((rOPC == 6'o56) | (rOPC == 6'o66)) & (rRA == 5'hE);
+   
+   always @(/*AUTOSENSE*/fINT or fMTS or fRTID or rMSR_IE or rOPA)
+     xMSR_IE <= (fINT) ? 1'b0 :
+		(fRTID) ? 1'b1 : 
+		(fMTS) ? rOPA[1] :
+		rMSR_IE;      
+   
+   always @(/*AUTOSENSE*/fBRK or fMTS or fRTBD or rMSR_BIP or rOPA)
+     xMSR_BIP <= (fBRK) ? 1'b1 :
+		 (fRTBD) ? 1'b0 : 
+		 (fMTS) ? rOPA[3] :
+		 rMSR_BIP;      
+   
+   always @(/*AUTOSENSE*/fMTS or rMSR_BE or rOPA)
+     xMSR_BE <= (fMTS) ? rOPA[0] : rMSR_BE;      
+
+   // --- RESULT SELECTOR -------------------------------------------
+   // Selects results from functional units. 
+   reg [31:0] 	   rRESULT, xRESULT;
+
+   // RESULT
+   always @(/*AUTOSENSE*/fSKIP or rMXALU or rRES_ADD or rRES_BSF
+	    or rRES_LOG or rRES_MOV or rRES_MUL or rRES_SFT)
+     if (fSKIP) 
+       /*AUTORESET*/
+       // Beginning of autoreset for uninitialized flops
+       xRESULT <= 32'h0;
+       // End of automatics
+     else
+       case (rMXALU)
+	 3'o0: xRESULT <= rRES_ADD;
+	 3'o1: xRESULT <= rRES_LOG;
+	 3'o2: xRESULT <= rRES_SFT;
+	 3'o3: xRESULT <= rRES_MOV;
+	 3'o4: xRESULT <= (MUL) ? rRES_MUL : 32'hX;	 
+	 3'o5: xRESULT <= (BSF) ? rRES_BSF : 32'hX;	 
+	 default: xRESULT <= 32'hX;       
+       endcase // case (rMXALU)
+
+   // --- DATA WISHBONE -----
+   
+   reg [3:0] 	    rDWBSEL, xDWBSEL;
+   assign 	    dwb_adr_o = rRESULT[DW-1:2];
+   assign 	    dwb_sel_o = rDWBSEL;
+
+   always @(/*AUTOSENSE*/rOPC or wADD)
+     case (rOPC[1:0])
+       2'o0: case (wADD[1:0]) // 8'bit
+	       2'o0: xDWBSEL <= 4'h8;	       
+	       2'o1: xDWBSEL <= 4'h4;	       
+	       2'o2: xDWBSEL <= 4'h2;	       
+	       2'o3: xDWBSEL <= 4'h1;	       
+	     endcase // case (wADD[1:0])
+       2'o1: xDWBSEL <= (wADD[1]) ? 4'h3 : 4'hC; // 16'bit
+       2'o2: xDWBSEL <= 4'hF; // 32'bit
+       2'o3: xDWBSEL <= 4'h0; // FSL
+     endcase // case (rOPC[1:0])
+
+   // --- FSL WISHBONE --------------------
+
+   reg [14:2] 	    rFSLADR, xFSLADR;   
+   
+   assign 	    {fsl_adr_o, fsl_tag_o} = rFSLADR[8:2];
+
+   always @(/*AUTOSENSE*/rALT or rRB) begin
+      xFSLADR <= {rALT, rRB[3:2]};      
+   end
+   
+   // --- SYNC ---
+
+   always @(posedge gclk)
+     if (grst) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	rDWBSEL <= 4'h0;
+	rFSLADR <= 13'h0;
+	rMSR_BE <= 1'h0;
+	rMSR_BIP <= 1'h0;
+	rMSR_C <= 1'h0;
+	rMSR_IE <= 1'h0;
+	rRESULT <= 32'h0;
+	// End of automatics
+     end else if (gena) begin // if (grst)
+	rRESULT <= #1 xRESULT;
+	rDWBSEL <= #1 xDWBSEL;
+	rMSR_C <= #1 xMSR_C;
+	rMSR_IE <= #1 xMSR_IE;	
+	rMSR_BE <= #1 xMSR_BE;	
+	rMSR_BIP <= #1 xMSR_BIP;
+	rFSLADR <= #1 xFSLADR;
+     end
+   
+endmodule // aeMB_xecu
+
+/*
+ $Log: aeMB_xecu.v,v $
+ Revision 1.12  2008/05/11 13:48:46  sybreon
+ Backported Adder from AEMB2_EDK62.
+ Fixes 64-bit math problem reported by M. Ettus.
+
+ Revision 1.11  2008/01/19 15:57:36  sybreon
+ Fix MTS during interrupt vectoring bug (reported by M. Ettus).
+
+ Revision 1.10  2007/12/25 22:15:09  sybreon
+ Stalls pipeline on MUL/BSF instructions results in minor speed improvements.
+
+ Revision 1.9  2007/11/30 16:42:51  sybreon
+ Minor code cleanup.
+
+ Revision 1.8  2007/11/16 21:52:03  sybreon
+ Added fsl_tag_o to FSL bus (tag either address or data).
+
+ Revision 1.7  2007/11/14 22:14:34  sybreon
+ Changed interrupt handling system (reported by M. Ettus).
+
+ Revision 1.6  2007/11/10 16:39:38  sybreon
+ Upgraded license to LGPLv3.
+ Significant performance optimisations.
+
+ Revision 1.5  2007/11/09 20:51:52  sybreon
+ Added GET/PUT support through a FSL bus.
+
+ Revision 1.4  2007/11/08 14:17:47  sybreon
+ Parameterised optional components.
+
+ Revision 1.3  2007/11/03 08:34:55  sybreon
+ Minor code cleanup.
+
+ Revision 1.2  2007/11/02 19:20:58  sybreon
+ Added better (beta) interrupt support.
+ Changed MSR_IE to disabled at reset as per MB docs.
+
+ Revision 1.1  2007/11/02 03:25:41  sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+
+*/
\ No newline at end of file
diff --git a/fpga/usrp2/opencores/aemb/sim/.gitignore b/fpga/usrp2/opencores/aemb/sim/.gitignore
new file mode 100644
index 000000000..4ef5da542
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/.gitignore
@@ -0,0 +1,4 @@
+/*.bin
+/*.dump
+/*.vcd
+/*.rom
diff --git a/fpga/usrp2/opencores/aemb/sim/CODE_DEBUG.sav b/fpga/usrp2/opencores/aemb/sim/CODE_DEBUG.sav
new file mode 100644
index 000000000..f777173c4
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/CODE_DEBUG.sav
@@ -0,0 +1,16 @@
+[size] 1400 971
+[pos] -1 -1
+*-5.188574 2727 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@28
+testbench.dut.dwb_we_o
+@22
+testbench.dut.dwb_sel_o[3:0]
+testbench.dut.dwb_adr_o[15:0]
+@28
+testbench.dut.sys_clk_i
+@22
+testbench.dut.dwb_dat_o[31:0]
+@821
+testbench.dut.dwb_dat_i[31:0]
+@22
+testbench.dut.dwb_dat_i[31:0]
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Entries b/fpga/usrp2/opencores/aemb/sim/CVS/Entries
new file mode 100644
index 000000000..bf457ae67
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/CVS/Entries
@@ -0,0 +1,3 @@
+D/verilog////
+/cversim/1.5/Tue Jan 15 18:38:57 2008//
+/iversim/1.5/Tue Jan 15 18:38:57 2008//
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Repository b/fpga/usrp2/opencores/aemb/sim/CVS/Repository
new file mode 100644
index 000000000..c6bd1aa80
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/CVS/Repository
@@ -0,0 +1 @@
+aemb/sim
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Root b/fpga/usrp2/opencores/aemb/sim/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/sim/CVS/Template b/fpga/usrp2/opencores/aemb/sim/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/sim/cversim b/fpga/usrp2/opencores/aemb/sim/cversim
new file mode 100755
index 000000000..0dbb7aea1
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/cversim
@@ -0,0 +1,22 @@
+#!/bin/sh
+# $Id: cversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
+# $Log: cversim,v $
+# Revision 1.5  2007/12/11 00:44:30  sybreon
+# Modified for AEMB2
+#
+# Revision 1.4  2007/11/30 17:08:30  sybreon
+# Moved simulation kernel into code.
+#
+# Revision 1.3  2007/11/05 10:59:31  sybreon
+# Added random seed for simulation.
+#
+# Revision 1.2  2007/04/12 20:21:33  sybreon
+# Moved testbench into /sim/verilog.
+# Simulation cleanups.
+#
+# Revision 1.1  2007/03/09 17:41:55  sybreon
+# initial import
+#
+RANDOM=$(date +%s)
+echo "parameter randseed = $RANDOM;" > random.v
+cver -q -w +define+AEMBX_SIMULATION_KERNEL $@ ../rtl/verilog/*.v
diff --git a/fpga/usrp2/opencores/aemb/sim/iversim b/fpga/usrp2/opencores/aemb/sim/iversim
new file mode 100755
index 000000000..9d2384b5a
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/iversim
@@ -0,0 +1,21 @@
+#!/bin/sh
+# $Id: iversim,v 1.5 2007/12/11 00:44:30 sybreon Exp $
+# $Log: iversim,v $
+# Revision 1.5  2007/12/11 00:44:30  sybreon
+# Modified for AEMB2
+#
+# Revision 1.4  2007/11/30 17:08:30  sybreon
+# Moved simulation kernel into code.
+#
+# Revision 1.3  2007/11/09 20:50:51  sybreon
+# Added log output to iverilog.log
+#
+# Revision 1.2  2007/11/05 10:59:31  sybreon
+# Added random seed for simulation.
+#
+# Revision 1.1  2007/03/09 17:41:55  sybreon
+# initial import
+#
+RANDOM=$(date +%s)
+echo "parameter randseed = $RANDOM;" > random.v
+iverilog $@ -DAEMBX_SIMULATION_KERNEL ../rtl/verilog/*.v && vvp -l iverilog.log a.out && rm a.out
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Entries b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Entries
new file mode 100644
index 000000000..34e896e80
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Entries
@@ -0,0 +1,3 @@
+/aemb2.v/1.3/Tue Jan 15 18:38:57 2008//
+/edk32.v/1.12/Tue Jan 15 18:38:57 2008//
+D
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Repository b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Repository
new file mode 100644
index 000000000..ff3eabf2d
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Repository
@@ -0,0 +1 @@
+aemb/sim/verilog
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Root b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Template b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v b/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v
new file mode 100644
index 000000000..bda1704e3
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/verilog/aemb2.v
@@ -0,0 +1,242 @@
+/* $Id: aemb2.v,v 1.3 2007/12/28 21:44:50 sybreon Exp $
+**
+** AEMB2 TEST BENCH
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
+*/
+
+module aemb2 ();
+   parameter IWB=16;
+   parameter DWB=16;
+
+   parameter TXE = 0; ///< thread execution enable
+   
+   parameter MUL = 1; ///< enable hardware multiplier
+   parameter BSF = 1; ///< enable barrel shifter
+   parameter FSL = 1; ///< enable FSL bus
+   parameter DIV = 0; ///< enable hardware divider   
+   
+`include "random.v"
+   
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [6:2]		cwb_adr_o;		// From dut of aeMB2_sim.v
+   wire [31:0]		cwb_dat_o;		// From dut of aeMB2_sim.v
+   wire [3:0]		cwb_sel_o;		// From dut of aeMB2_sim.v
+   wire			cwb_stb_o;		// From dut of aeMB2_sim.v
+   wire [1:0]		cwb_tga_o;		// From dut of aeMB2_sim.v
+   wire			cwb_wre_o;		// From dut of aeMB2_sim.v
+   wire [DWB-1:2]	dwb_adr_o;		// From dut of aeMB2_sim.v
+   wire			dwb_cyc_o;		// From dut of aeMB2_sim.v
+   wire [31:0]		dwb_dat_o;		// From dut of aeMB2_sim.v
+   wire [3:0]		dwb_sel_o;		// From dut of aeMB2_sim.v
+   wire			dwb_stb_o;		// From dut of aeMB2_sim.v
+   wire			dwb_tga_o;		// From dut of aeMB2_sim.v
+   wire			dwb_wre_o;		// From dut of aeMB2_sim.v
+   wire [IWB-1:2]	iwb_adr_o;		// From dut of aeMB2_sim.v
+   wire			iwb_stb_o;		// From dut of aeMB2_sim.v
+   wire			iwb_tga_o;		// From dut of aeMB2_sim.v
+   wire			iwb_wre_o;		// From dut of aeMB2_sim.v
+   // End of automatics
+   /*AUTOREGINPUT*/
+   // Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
+   reg			cwb_ack_i;		// To dut of aeMB2_sim.v
+   reg			dwb_ack_i;		// To dut of aeMB2_sim.v
+   reg			iwb_ack_i;		// To dut of aeMB2_sim.v
+   reg			sys_clk_i;		// To dut of aeMB2_sim.v
+   reg			sys_int_i;		// To dut of aeMB2_sim.v
+   reg			sys_rst_i;		// To dut of aeMB2_sim.v
+   // End of automatics
+  
+   // INITIAL SETUP //////////////////////////////////////////////////////
+   
+   //reg 			sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+   reg 	     svc;
+   integer   inttime;
+   integer   seed;   
+   integer   theend;
+   
+   always #5 sys_clk_i = ~sys_clk_i;   
+
+   initial begin
+      //$dumpfile("dump.vcd");
+      //$dumpvars(1,dut, dut.bpcu);
+   end
+   
+   initial begin
+      seed = randseed;
+      theend = 0;      
+      svc = 0;      
+      sys_clk_i = $random(seed);
+      sys_rst_i = 1;
+      sys_int_i = 0;
+      #50 sys_rst_i = 0;
+      #3500000 $finish;      
+   end
+   
+   // FAKE MEMORY ////////////////////////////////////////////////////////
+
+   reg [31:0]  rom [0:65535];
+   reg [31:0]  ram[0:65535];
+   reg [31:0]  dwblat;
+   reg [15:2]  dadr, iadr;
+
+   wire [31:0] dwb_dat_t = ram[dwb_adr_o];   
+   wire [31:0] iwb_dat_i = rom[iadr]; 
+   wire [31:0] dwb_dat_i = ram[dadr];     
+   wire [31:0] cwb_dat_i = cwb_adr_o;   
+
+`ifdef POSEDGE  
+`else // !`ifdef POSEDGE
+   
+   always @(negedge sys_clk_i) 
+     if (sys_rst_i) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	cwb_ack_i <= 1'h0;
+	dwb_ack_i <= 1'h0;
+	iwb_ack_i <= 1'h0;
+	// End of automatics
+     end else begin
+	iwb_ack_i <= #1 iwb_stb_o;      
+	dwb_ack_i <= #1 dwb_stb_o;
+	cwb_ack_i <= #1 cwb_stb_o;
+     end // else: !if(sys_rst_i)
+   
+   always @(negedge sys_clk_i) begin
+      iadr <= #1 iwb_adr_o;      
+      dadr <= #1 dwb_adr_o;
+      
+      if (dwb_wre_o & dwb_stb_o) begin
+	 case (dwb_sel_o)
+	   4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
+	   4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
+	   4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
+	   4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
+	   4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
+	   4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
+	   4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
+	 endcase // case (dwb_sel_o)
+      end // if (dwb_we_o & dwb_stb_o)
+   end // always @ (negedge sys_clk_i)
+   
+`endif // !`ifdef POSEDGE
+   
+
+   integer i;   
+   initial begin
+      for (i=0;i<65535;i=i+1) begin
+	 ram[i] <= $random;
+      end
+      #1 $readmemh("dump.vmem",rom);
+      #1 $readmemh("dump.vmem",ram);
+   end
+
+   // DISPLAY OUTPUTS ///////////////////////////////////////////////////
+
+   integer rnd;
+   
+   always @(posedge sys_clk_i) begin
+	      
+      // Interrupt Monitors
+      if (!dut.sim.rMSR_IE) begin
+	 rnd = $random % 30;	 
+	 inttime = $stime + 1000 + (rnd*rnd * 10);
+      end
+      if ($stime > inttime) begin
+	 sys_int_i = 1;
+	 svc = 0;	 
+      end
+      if (($stime > inttime + 500) && !svc) begin
+	 $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);	 
+	 $finish;	 
+      end
+      if (dwb_wre_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;
+      /*
+      if (dut.regf.fRDWE && (dut.rRD == 5'h0e) && !svc && dut.gena) begin 
+	 svc = 1;
+	 //$display("\nLATENCY: ", ($stime - inttime)/10);	 
+      end
+       */
+      
+      // Pass/Fail Monitors
+      if (dwb_wre_o & (dwb_dat_o == "FAIL")) begin
+	 $display("\n\tFAIL");	 
+	 $finish;
+      end
+      
+      if (iwb_dat_i == 32'hb8000000) begin
+	 theend = theend + 1;	 
+      end
+
+      if (theend == 5) begin
+	 $display("\n\t*** PASSED ALL TESTS ***");
+	 $finish;	 
+      end
+      
+   end // always @ (posedge sys_clk_i)
+   
+   // INTERNAL WIRING ////////////////////////////////////////////////////
+   
+   aeMB2_sim
+     #(/*AUTOINSTPARAM*/
+       // Parameters
+       .IWB				(IWB),
+       .DWB				(DWB),
+       .TXE				(TXE),
+       .MUL				(MUL),
+       .BSF				(BSF),
+       .FSL				(FSL),
+       .DIV				(DIV))
+   dut (/*AUTOINST*/
+	// Outputs
+	.cwb_adr_o			(cwb_adr_o[6:2]),
+	.cwb_dat_o			(cwb_dat_o[31:0]),
+	.cwb_sel_o			(cwb_sel_o[3:0]),
+	.cwb_stb_o			(cwb_stb_o),
+	.cwb_tga_o			(cwb_tga_o[1:0]),
+	.cwb_wre_o			(cwb_wre_o),
+	.dwb_adr_o			(dwb_adr_o[DWB-1:2]),
+	.dwb_cyc_o			(dwb_cyc_o),
+	.dwb_dat_o			(dwb_dat_o[31:0]),
+	.dwb_sel_o			(dwb_sel_o[3:0]),
+	.dwb_stb_o			(dwb_stb_o),
+	.dwb_tga_o			(dwb_tga_o),
+	.dwb_wre_o			(dwb_wre_o),
+	.iwb_adr_o			(iwb_adr_o[IWB-1:2]),
+	.iwb_stb_o			(iwb_stb_o),
+	.iwb_tga_o			(iwb_tga_o),
+	.iwb_wre_o			(iwb_wre_o),
+	// Inputs
+	.cwb_ack_i			(cwb_ack_i),
+	.cwb_dat_i			(cwb_dat_i[31:0]),
+	.dwb_ack_i			(dwb_ack_i),
+	.dwb_dat_i			(dwb_dat_i[31:0]),
+	.iwb_ack_i			(iwb_ack_i),
+	.iwb_dat_i			(iwb_dat_i[31:0]),
+	.sys_clk_i			(sys_clk_i),
+	.sys_int_i			(sys_int_i),
+	.sys_rst_i			(sys_rst_i));
+
+endmodule // edk32
+
+/* $Log $ */
+
+// Local Variables:
+// verilog-library-directories:("." "../../rtl/verilog/")
+// verilog-library-files:("")
+// End:
diff --git a/fpga/usrp2/opencores/aemb/sim/verilog/edk32.v b/fpga/usrp2/opencores/aemb/sim/verilog/edk32.v
new file mode 100644
index 000000000..68465e9e0
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sim/verilog/edk32.v
@@ -0,0 +1,288 @@
+/* $Id: edk32.v,v 1.12 2007/12/23 20:40:51 sybreon Exp $
+**
+** AEMB EDK 3.2 Compatible Core TEST
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+`define AEMB_SIMULATION_KERNEL   
+
+module edk32 ();
+
+`include "random.v"
+  
+   // INITIAL SETUP //////////////////////////////////////////////////////
+   
+   reg 	     sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+   reg 	     svc;
+   integer   inttime;
+   integer   seed;   
+   integer   theend;
+   
+   always #5 sys_clk_i = ~sys_clk_i;   
+
+   initial begin
+      //$dumpfile("dump.vcd");
+      //$dumpvars(1,dut);
+   end
+   
+   initial begin
+      seed = randseed;
+      theend = 0;      
+      svc = 0;      
+      sys_clk_i = $random(seed);
+      sys_rst_i = 1;
+      sys_int_i = 0;
+      sys_exc_i = 0;      
+      #50 sys_rst_i = 0;
+   end
+
+   initial fork
+      //inttime $display("FSADFASDFSDAF");      
+      //#10000 sys_int_i = 1;
+      //#1100 sys_int_i = 0;
+      //#100000 $displayh("\nTest Completed."); 
+      //#4000 $finish;
+   join   
+
+   
+   // FAKE MEMORY ////////////////////////////////////////////////////////
+
+   wire        fsl_stb_o;
+   wire        fsl_wre_o;
+   wire [31:0] fsl_dat_o;
+   wire [31:0] fsl_dat_i;   
+   wire [6:2]  fsl_adr_o;
+   
+   wire [15:2] iwb_adr_o;
+   wire        iwb_stb_o;
+   wire        dwb_stb_o;
+   reg [31:0]  rom [0:65535];
+   wire [31:0] iwb_dat_i;
+   reg 	       iwb_ack_i, dwb_ack_i, fsl_ack_i;
+
+   reg [31:0]  ram[0:65535];
+   wire [31:0] dwb_dat_i;
+   reg [31:0]  dwblat;
+   wire        dwb_we_o;
+   reg [15:2]  dadr,iadr;
+   wire [3:0]  dwb_sel_o; 
+   wire [31:0] dwb_dat_o;
+   wire [15:2] dwb_adr_o;
+   wire [31:0] dwb_dat_t;
+
+   initial begin
+      dwb_ack_i = 0;
+      iwb_ack_i = 0;
+      fsl_ack_i = 0;      
+   end
+   
+   assign      dwb_dat_t = ram[dwb_adr_o];   
+   assign      iwb_dat_i = ram[iadr]; 
+   assign      dwb_dat_i = ram[dadr];     
+   assign      fsl_dat_i = fsl_adr_o;   
+
+`ifdef POSEDGE
+   
+   always @(posedge sys_clk_i) 
+     if (sys_rst_i) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	dwb_ack_i <= 1'h0;
+	fsl_ack_i <= 1'h0;
+	iwb_ack_i <= 1'h0;
+	// End of automatics
+     end else begin
+	iwb_ack_i <= #1 iwb_stb_o ^ iwb_ack_i;      
+	dwb_ack_i <= #1 dwb_stb_o ^ dwb_ack_i;
+	fsl_ack_i <= #1 fsl_stb_o ^ fsl_ack_i;
+     end // else: !if(sys_rst_i)
+   
+   always @(posedge sys_clk_i) begin
+      iadr <= #1 iwb_adr_o;      
+      dadr <= #1 dwb_adr_o;
+      
+      if (dwb_we_o & dwb_stb_o) begin
+	 case (dwb_sel_o)
+	   4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
+	   4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
+	   4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
+	   4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
+	   4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
+	   4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
+	   4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
+	 endcase // case (dwb_sel_o)
+      end // if (dwb_we_o & dwb_stb_o)
+   end // always @ (posedge sys_clk_i)
+
+`else // !`ifdef POSEDGE
+   
+   always @(negedge sys_clk_i) 
+     if (sys_rst_i) begin
+	/*AUTORESET*/
+	// Beginning of autoreset for uninitialized flops
+	dwb_ack_i <= 1'h0;
+	fsl_ack_i <= 1'h0;
+	iwb_ack_i <= 1'h0;
+	// End of automatics
+     end else begin
+	iwb_ack_i <= #1 iwb_stb_o;      
+	dwb_ack_i <= #1 dwb_stb_o;
+	fsl_ack_i <= #1 fsl_stb_o;
+     end // else: !if(sys_rst_i)
+   
+   always @(negedge sys_clk_i) begin
+      iadr <= #1 iwb_adr_o;      
+      dadr <= #1 dwb_adr_o;
+      
+      if (dwb_we_o & dwb_stb_o) begin
+	 case (dwb_sel_o)
+	   4'h1: ram[dwb_adr_o] <= {dwb_dat_t[31:8], dwb_dat_o[7:0]};
+	   4'h2: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:8], dwb_dat_t[7:0]};
+	   4'h4: ram[dwb_adr_o] <= {dwb_dat_t[31:24], dwb_dat_o[23:16], dwb_dat_t[15:0]};
+	   4'h8: ram[dwb_adr_o] <= {dwb_dat_o[31:24], dwb_dat_t[23:0]};
+	   4'h3: ram[dwb_adr_o] <= {dwb_dat_t[31:16], dwb_dat_o[15:0]};
+	   4'hC: ram[dwb_adr_o] <= {dwb_dat_o[31:16], dwb_dat_t[15:0]};
+	   4'hF: ram[dwb_adr_o] <= {dwb_dat_o};
+	 endcase // case (dwb_sel_o)
+      end // if (dwb_we_o & dwb_stb_o)
+   end // always @ (negedge sys_clk_i)
+   
+`endif // !`ifdef POSEDGE
+   
+
+   integer i;   
+   initial begin
+      for (i=0;i<65535;i=i+1) begin
+	 ram[i] <= $random;
+      end
+      #1 $readmemh("dump.vmem",ram);
+   end
+
+   // DISPLAY OUTPUTS ///////////////////////////////////////////////////
+
+   integer rnd;
+   
+   always @(posedge sys_clk_i) begin
+
+      // Interrupt Monitors
+      if (!dut.cpu.rMSR_IE) begin
+	 rnd = $random % 30;	 
+	 inttime = $stime + 1000 + (rnd*rnd * 10);
+      end
+      if ($stime > inttime) begin
+	 sys_int_i = 1;
+	 svc = 0;	 
+      end
+      if (($stime > inttime + 500) && !svc) begin
+	 $display("\n\t*** INTERRUPT TIMEOUT ***", inttime);	 
+	 $finish;	 
+      end
+      if (dwb_we_o & (dwb_dat_o == "RTNI")) sys_int_i = 0;	 
+      if (dut.cpu.regf.fRDWE && (dut.cpu.rRD == 5'h0e) && !svc && dut.cpu.gena) begin 
+	 svc = 1;
+	 //$display("\nLATENCY: ", ($stime - inttime)/10);	 
+      end
+      
+      // Pass/Fail Monitors
+      if (dwb_we_o & (dwb_dat_o == "FAIL")) begin
+	 $display("\n\tFAIL");	 
+	 $finish;
+      end
+      
+      if (iwb_dat_i == 32'hb8000000) begin
+	 theend = theend + 1;	 
+      end
+
+      if (theend == 5) begin
+	 $display("\n\t*** PASSED ALL TESTS ***");
+	 $finish;	 
+      end
+   end // always @ (posedge sys_clk_i)
+   
+   // INTERNAL WIRING ////////////////////////////////////////////////////
+   
+   aeMB_sim #(16,16)
+     dut (
+	  .sys_int_i(sys_int_i),
+	  .dwb_ack_i(dwb_ack_i),
+	  .dwb_stb_o(dwb_stb_o),
+	  .dwb_adr_o(dwb_adr_o),
+	  .dwb_dat_o(dwb_dat_o),
+	  .dwb_dat_i(dwb_dat_i),
+	  .dwb_wre_o(dwb_we_o),
+	  .dwb_sel_o(dwb_sel_o),
+
+	  .fsl_ack_i(fsl_ack_i),
+	  .fsl_stb_o(fsl_stb_o),
+	  .fsl_adr_o(fsl_adr_o),
+	  .fsl_dat_o(fsl_dat_o),
+	  .fsl_dat_i(fsl_dat_i),
+	  .fsl_wre_o(fsl_we_o),
+
+	  .iwb_adr_o(iwb_adr_o),
+	  .iwb_dat_i(iwb_dat_i),
+	  .iwb_stb_o(iwb_stb_o),
+	  .iwb_ack_i(iwb_ack_i),
+	  .sys_clk_i(sys_clk_i),
+	  .sys_rst_i(sys_rst_i)
+	  );
+
+endmodule // edk32
+
+/*
+ $Log: edk32.v,v $
+ Revision 1.12  2007/12/23 20:40:51  sybreon
+ Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.
+
+ Revision 1.11  2007/12/11 00:44:31  sybreon
+ Modified for AEMB2
+
+ Revision 1.10  2007/11/30 17:08:30  sybreon
+ Moved simulation kernel into code.
+
+ Revision 1.9  2007/11/20 18:36:00  sybreon
+ Removed unnecessary byte acrobatics with VMEM data.
+
+ Revision 1.8  2007/11/18 19:41:45  sybreon
+ Minor simulation fixes.
+
+ Revision 1.7  2007/11/14 22:11:41  sybreon
+ Added posedge/negedge bus interface.
+ Modified interrupt test system.
+
+ Revision 1.6  2007/11/13 23:37:28  sybreon
+ Updated simulation to also check BRI 0x00 instruction.
+
+ Revision 1.5  2007/11/09 20:51:53  sybreon
+ Added GET/PUT support through a FSL bus.
+
+ Revision 1.4  2007/11/08 14:18:00  sybreon
+ Parameterised optional components.
+
+ Revision 1.3  2007/11/05 10:59:31  sybreon
+ Added random seed for simulation.
+
+ Revision 1.2  2007/11/02 19:16:10  sybreon
+ Added interrupt simulation.
+ Changed "human readable" simulation output.
+
+ Revision 1.1  2007/11/02 03:25:45  sybreon
+ New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+ Fixed various minor data hazard bugs.
+ Code compatible with -O0/1/2/3/s generated code.
+ */
\ No newline at end of file
diff --git a/fpga/usrp2/opencores/aemb/sw/CVS/Entries b/fpga/usrp2/opencores/aemb/sw/CVS/Entries
new file mode 100644
index 000000000..45725bed9
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/CVS/Entries
@@ -0,0 +1,2 @@
+D/c////
+/gccrom/1.13/Sun Jan 20 19:47:57 2008//
diff --git a/fpga/usrp2/opencores/aemb/sw/CVS/Repository b/fpga/usrp2/opencores/aemb/sw/CVS/Repository
new file mode 100644
index 000000000..6de31b8b0
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/CVS/Repository
@@ -0,0 +1 @@
+aemb/sw
diff --git a/fpga/usrp2/opencores/aemb/sw/CVS/Root b/fpga/usrp2/opencores/aemb/sw/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/sw/CVS/Template b/fpga/usrp2/opencores/aemb/sw/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/sw/c/CVS/Entries b/fpga/usrp2/opencores/aemb/sw/c/CVS/Entries
new file mode 100644
index 000000000..4867b6318
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/c/CVS/Entries
@@ -0,0 +1,3 @@
+/aeMB_testbench.c/1.14/Tue Jan 15 18:38:57 2008//
+/libaemb.h/1.3/Tue Jan 15 18:38:57 2008//
+D
diff --git a/fpga/usrp2/opencores/aemb/sw/c/CVS/Repository b/fpga/usrp2/opencores/aemb/sw/c/CVS/Repository
new file mode 100644
index 000000000..86c411d03
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/c/CVS/Repository
@@ -0,0 +1 @@
+aemb/sw/c
diff --git a/fpga/usrp2/opencores/aemb/sw/c/CVS/Root b/fpga/usrp2/opencores/aemb/sw/c/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/c/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/aemb/sw/c/CVS/Template b/fpga/usrp2/opencores/aemb/sw/c/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/c/CVS/Template
diff --git a/fpga/usrp2/opencores/aemb/sw/c/aeMB_testbench.c b/fpga/usrp2/opencores/aemb/sw/c/aeMB_testbench.c
new file mode 100644
index 000000000..c3402e0ef
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/c/aeMB_testbench.c
@@ -0,0 +1,385 @@
+/* $Id: aeMB_testbench.c,v 1.14 2007/12/28 21:44:04 sybreon Exp $
+** 
+** AEMB Function Verification C Testbench
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU General Public License as published by
+** the Free Software Foundation, either version 3 of the License, or
+** (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+** License for more details.
+**
+** You should have received a copy of the GNU General Public License
+** along with AEMB.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <malloc.h>
+#include <errno.h>
+#include <reent.h>
+
+#include "libaemb.h"
+
+/**
+   INTERRUPT TEST
+
+   This tests for the following:
+   - Pointer addressing
+   - Interrupt handling
+ */
+
+void __attribute__ ((interrupt_handler)) int_handler();
+volatile int service = 0xDEADDEAD;
+
+void int_service() 
+{
+  int* pio = (int*)0xFFFFFFFC;
+  *pio = 0x52544E49; // "INTR"
+  service = 0;
+}
+
+void int_handler()
+{
+  int_service();
+}
+
+/**
+   INTERRUPT TEST ROUTINE
+*/
+int int_test ()
+{
+  // Delay loop until hardware interrupt triggers
+  volatile int i;
+  for (i=0; i < 999; i++) {
+    if (service == 0) return 0;
+  };
+
+  return -1;
+}
+
+/**
+   FIBONACCI TEST
+   http://en.literateprograms.org/Fibonacci_numbers_(C)
+
+   This tests for the following:
+   - Recursion & Iteration
+   - 32/16/8-bit data handling
+*/
+
+unsigned int fib_slow(unsigned int n)
+{
+  return n < 2 ? n : fib_slow(n-1) + fib_slow(n-2);
+}
+
+unsigned int fib_fast(unsigned int n)
+{
+  unsigned int a[3];
+  unsigned int *p=a;
+  unsigned int i;
+  
+  for(i=0; i<=n; ++i) {
+    if(i<2) *p=i;
+    else {
+      if(p==a) *p=*(a+1)+*(a+2);
+      else if(p==a+1) *p=*a+*(a+2);
+      else *p=*a+*(a+1);
+    }
+    if(++p>a+2) p=a;
+  }
+  
+  return p==a?*(p+2):*(p-1);
+}
+
+int fib_test(int max) {
+  unsigned int n;
+  unsigned int fast, slow;  
+  // 32-bit LUT
+  unsigned int fib_lut32[] = {
+    0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233
+  };  
+  // 16-bit LUT
+  unsigned short fib_lut16[] = {
+    0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233
+  };    
+  // 8-bit LUT
+  unsigned char fib_lut8[] = {
+    0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233
+  };  
+  
+  for (n=0;n<max;n++) {
+    slow = fib_slow(n);    
+    fast = fib_fast(n);
+    if ((slow != fast) || 
+	(fast != fib_lut32[n]) || 
+	(fast != fib_lut16[n]) || 
+	(fast != fib_lut8[n])) {
+      return -1;      
+    }
+  }      
+  return 0;  
+}
+
+/**
+   EUCLIDEAN TEST
+   http://en.literateprograms.org/Euclidean_algorithm_(C)
+   
+   This tests for the following:
+   - Modulo arithmetic
+   - Goto
+*/
+
+int euclid_gcd(int a, int b) {
+  if (b > a) goto b_larger;
+  while (1) {
+    a = a % b;
+    if (a == 0) return b;
+  b_larger:
+    b = b % a;
+    if (b == 0) return a;
+  }
+}
+
+int euclid_test(int max) 
+{
+  int n;
+  int euclid;
+  // Random Numbers
+  int euclid_a[] = {
+    1804289383, 1681692777, 1957747793, 719885386, 596516649,
+    1025202362, 783368690, 2044897763, 1365180540, 304089172,
+    35005211, 294702567, 336465782, 278722862
+  };  
+  int euclid_b[] = {
+    846930886, 1714636915, 424238335, 1649760492, 1189641421,
+    1350490027, 1102520059, 1967513926, 1540383426, 1303455736,
+    521595368, 1726956429, 861021530, 233665123
+  };
+  
+  // GCD 
+  int euclid_lut[] = {
+    1, 1, 1, 2, 1, 1, 1, 1, 6, 4, 1, 3, 2, 1
+  };
+    
+  for (n=0;n<max;n++) {
+    euclid = euclid_gcd(euclid_a[n],euclid_b[n]);
+    if (euclid != euclid_lut[n]) {
+      return -1;
+    }
+  }
+  return 0;
+}
+
+/**
+   NEWTON-RHAPSON
+   http://en.literateprograms.org/Newton-Raphson's_method_for_root_finding_(C)
+
+   This tests for the following:
+   - Multiplication & Division
+   - Floating point arithmetic
+   - Integer to Float conversion
+*/
+
+float newton_sqrt(float n)
+{
+  float x = 0.0;
+  float xn = 0.0;  
+  int iters = 0;  
+  int i;
+  for (i = 0; i <= (int)n; ++i)
+    {
+      float val = i*i-n;
+      if (val == 0.0)
+	return i;
+      if (val > 0.0)
+	{
+	  xn = (i+(i-1))/2.0;
+	  break;
+	}
+    }  
+  while (!(iters++ >= 100
+	   || x == xn))
+    {
+      x = xn;
+      xn = x - (x * x - n) / (2 * x);
+    }
+  return xn;
+}
+
+int newton_test (int max) {
+  int n;
+  float newt;
+  // 32-bit LUT
+  float newt_lut[] = {
+    0.000000000000000000000000,
+    1.000000000000000000000000,
+    1.414213538169860839843750,
+    1.732050776481628417968750,
+    2.000000000000000000000000,
+    2.236068010330200195312500,
+    2.449489831924438476562500,
+    2.645751237869262695312500,
+    2.828427076339721679687500,
+    3.000000000000000000000000,
+    3.162277698516845703125000,
+    3.316624879837036132812500,
+    3.464101552963256835937500,
+    3.605551242828369140625000,
+    3.741657495498657226562500
+  };
+
+  for (n=0;n<max;n++) {
+    newt = newton_sqrt(n);
+    if (newt != newt_lut[n]) {
+      return -1;
+    }
+  } 
+  return 0;
+}
+
+
+/**
+   FSL TEST ROUTINE
+*/
+
+int fsl_test ()
+{
+  // TEST FSL1 ONLY
+  int FSL = 0xCAFEF00D;
+
+  asm ("PUT %0, RFSL1" :: "r"(FSL));
+  asm ("GET %0, RFSL1" : "=r"(FSL));
+  
+  if (FSL != 0x01) return -1;
+  
+  asm ("PUT %0, RFSL31" :: "r"(FSL));
+  asm ("GET %0, RFSL31" : "=r"(FSL));
+  
+  if (FSL != 0x1F) return -1;
+  
+  return 0;  
+}
+
+// static int errnum;
+/*
+int *__errno ()
+{
+  return &_REENT->_errno;
+  // return &errnum;
+}
+*/
+
+int malloc_test()
+{
+  void *alloc;
+
+  alloc = (void *)malloc(256); // allocate 32 bytes
+
+  if (alloc == NULL)
+    return -1;
+  else
+    return (int) alloc;
+}
+
+/**
+   MAIN TEST PROGRAMME
+
+   This is the main test procedure. It will output signals onto the
+   MPI port that is checked by the testbench.
+ */
+
+int main () 
+{
+  // Message Passing Port
+  int* mpi = (int*)0xFFFFFFFF;
+  
+  // Number of each test to run
+  int max = 10;
+
+  // lock T0 if it's multi-threaded
+  /*
+  if ((aemb_isthreaded() == 0) && (aemb_isthread1() != 0)) {
+    while (1) {
+      asm volatile ("nop;");
+    }
+  }
+  */
+
+  // Enable Global Interrupts
+  aemb_enable_interrupt();
+
+  // INT TEST
+  //if (int_test() == -1) { *mpi = 0x4641494C; }
+
+  // TEST MALLOC
+  if (malloc_test() == -1) { *mpi = 0x4641494C; }
+
+  // FSL TEST
+  //if (fsl_test() == -1) { *mpi = 0x4641494C; }
+
+  // Fibonacci Test
+  if (fib_test(max) == -1) { *mpi = 0x4641494C; }
+
+  // Euclid Test
+  if (euclid_test(max) == -1) { *mpi = 0x4641494C; }
+
+  // Newton-Rhapson Test
+  if (newton_test(max) == -1) { *mpi = 0x4641494C; }
+  
+  // Disable Global Interrupts
+  aemb_disable_interrupt();
+
+  // ALL PASSED
+  return 0;
+}
+
+/*
+  HISTORY
+  $Log: aeMB_testbench.c,v $
+  Revision 1.14  2007/12/28 21:44:04  sybreon
+  Added malloc() test
+
+  Revision 1.13  2007/12/11 00:44:31  sybreon
+  Modified for AEMB2
+  
+  Revision 1.12  2007/11/18 19:41:45  sybreon
+  Minor simulation fixes.
+  
+  Revision 1.11  2007/11/14 23:41:06  sybreon
+  Fixed minor interrupt test typo.
+  
+  Revision 1.10  2007/11/14 22:12:02  sybreon
+  Added interrupt test routine.
+  
+  Revision 1.9  2007/11/09 20:51:53  sybreon
+  Added GET/PUT support through a FSL bus.
+  
+  Revision 1.8  2007/11/03 08:40:18  sybreon
+  Minor code cleanup.
+  
+  Revision 1.7  2007/11/02 18:32:19  sybreon
+  Enable MSR_IE with software.
+  
+  Revision 1.6  2007/04/30 15:57:10  sybreon
+  Removed byte acrobatics.
+  
+  Revision 1.5  2007/04/27 15:17:59  sybreon
+  Added code documentation.
+  Added new tests that test floating point, modulo arithmetic and multiplication/division.
+  
+  Revision 1.4  2007/04/25 22:15:05  sybreon
+  Added support for 8-bit and 16-bit data types.
+  
+  Revision 1.3  2007/04/04 14:09:04  sybreon
+  Added initial interrupt/exception support.
+  
+  Revision 1.2  2007/04/04 06:07:45  sybreon
+  Fixed C code bug which passes the test
+  
+  Revision 1.1  2007/03/09 17:41:57  sybreon
+  initial import  
+*/
diff --git a/fpga/usrp2/opencores/aemb/sw/c/endian-test.c b/fpga/usrp2/opencores/aemb/sw/c/endian-test.c
new file mode 100644
index 000000000..b585f7a30
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/c/endian-test.c
@@ -0,0 +1,86 @@
+
+#include "memory_map.h"
+
+int main() {
+  char *p = (char *)0x4000;
+  short *q = (short *)0x5000;
+  int *r= (int *)0x6000;
+
+  int *output = (int *)0x7000;
+
+  char s;
+  short t;
+  int u;
+
+  // Write
+  // Bytes
+  *p = (char)1;
+  p++;
+  *p = (char)2;
+  p++;
+  *p = (char)3;
+  p++; 
+  *p = (char)4;
+  p++;
+  *p = (char)5;
+
+  // Words
+  *q = (short) 0x1112;
+  q++;
+  *q = (short) 0x1314;
+  q++;
+  *q = (short) 0x1516;
+
+  // Double Words
+  *r = 0x21222324;
+  r++;
+  *r = 0x25262728;
+  r++;
+  *r = 0x292a2b2c;
+
+
+  // Read
+  p = (char *)0x6000;
+  s = *p;
+  if(s == 0x21)
+    *output = 0x53534150;  // PASS
+  else
+    *output = 0x4C494146;  // FAIL
+
+  p = (char *)0x6001;
+  s = *p;
+  if(s == 0x22)
+    *output = 0x53534150;  // PASS
+  else
+    *output = 0x4C494146;  // FAIL
+
+  p = (char *)0x6002;
+  s = *p;
+  if(s == 0x23)
+    *output = 0x53534150;  // PASS
+  else
+    *output = 0x4C494146;  // FAIL
+
+
+  p = (char *)0x6003;
+  s = *p;
+  if(s == 0x24)
+    *output = 0x53534150;  // PASS
+  else
+    *output = 0x4C494146;  // FAIL
+
+  q = (short *)0x4000;
+  t = *q;
+  if(t == 0x0102)
+    *output = 0x53534150;  // PASS
+  else
+    *output = 0x4C494146;  // FAIL
+
+  r = (int *)0x4000;
+  u = *r;
+  if(u == 0x01020304)
+    *output = 0x53534150;  // PASS
+  else
+    *output = 0x4C494146;  // FAIL
+
+}
diff --git a/fpga/usrp2/opencores/aemb/sw/c/libaemb.h b/fpga/usrp2/opencores/aemb/sw/c/libaemb.h
new file mode 100644
index 000000000..329a327a1
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/c/libaemb.h
@@ -0,0 +1,218 @@
+/* $Id: libaemb.h,v 1.3 2007/12/16 03:26:37 sybreon Exp $
+**
+** AEMB2 CUSTOM LIBRARY
+** 
+** Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <shawn.tan@aeste.net>
+**  
+** This file is part of AEMB.
+**
+** AEMB is free software: you can redistribute it and/or modify it
+** under the terms of the GNU Lesser General Public License as
+** published by the Free Software Foundation, either version 3 of the
+** License, or (at your option) any later version.
+**
+** AEMB is distributed in the hope that it will be useful, but WITHOUT
+** ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+** or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Lesser General
+** Public License for more details.
+**
+** You should have received a copy of the GNU Lesser General Public
+** License along with AEMB. If not, see <http:**www.gnu.org/licenses/>.
+*/
+
+#ifndef LIBAEMB_H
+#define LIBAEMB_H
+
+#define AEMB_TXE 0x0100
+#define AEMB_TXP 0x0400
+#define AEMB_TX0 0x0300
+#define AEMB_TX1 0x0700
+#define AEMB_MSK 0x0F00
+
+#define AEMB_BIP 0x0008
+#define AEMB_CCC 0x0004
+#define AEMB_ITE 0x0002
+#define AEMB_BLE 0x0001
+
+
+// Linker symbols
+extern void* _STACK_SIZE;
+extern void* _stack_end;
+
+
+void aemb_hook_init () asm ("_program_init");
+void aemb_hook_clean () asm ("_program_clean");
+
+inline void aemb_enable_interrupt ();
+inline void aemb_disable_interrupt ();
+inline int aemb_isthread1();
+inline int aemb_isthread0();
+inline int aemb_isthreaded();
+
+/*!
+* Assembly macro to enable MSR_IE
+*/
+void aemb_enable_interrupt ()
+{
+  int msr, tmp;
+  asm volatile ("mfs %0, rmsr;"
+		"ori %1, %0, 0x02;"
+		"mts rmsr, %1;"
+		: "=r"(msr)
+		: "r" (tmp)
+		);
+}
+
+/*!
+* Assembly macro to disable MSR_IE
+*/
+void aemb_disable_interrupt ()
+{
+  int msr, tmp;
+  asm volatile ("mfs %0, rmsr;"
+		"andi %1, %0, 0xFD;"
+		"mts rmsr, %1;"
+		: "=r"(msr)
+		: "r" (tmp)
+		);
+}
+
+/*!
+* Bootstrap Hook Override
+*/
+
+void aemb_hook_init ()
+{
+  int msr, tmp;
+  int stk_end, stk_siz;
+
+  /*
+  // Check to see if hardware threads are enabled
+  if (((msr & AEMB_TXE) != AEMB_TXE) ||
+  // Check to see if second thread is started
+      ((msr & AEMB_TX1) == AEMB_TX1)) return;
+  */
+  //return;
+  asm volatile ("mfs %0, rmsr;"
+		// Check for BIP
+		"andi %1, %0, %5;"
+		"xori %1, %1, %5;"
+		"beqi %1, 44;"
+
+		// Check for TXE
+		"andi %1, %0, %2;"
+		"xori %1, %1, %2;"
+		"bnei %1, 36;"	
+
+		// Check for TX1
+		"andi %1, %0, %3;"
+		"xori %1, %1, %3;"
+		"beqi %1, 20;"
+		
+		// reallocate stack pointer for T0
+		"ori %1, r0, %4;"
+		"sra %1, %1;"
+		"rsubk r1, %1, r1;"
+
+		// reboot the machine
+		//"brki r0, _crtinit;"
+		"brid 0;"
+		"nop;"
+
+		// clear BIP
+		"andni %1, %0, %5;"
+		"mts rmsr, %1;"
+		
+		:"=r"(msr), "=r"(tmp)
+		:"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE), "i"(AEMB_BIP)
+		);
+
+}
+
+/*!
+ Undo the changes made by programme init
+*/
+
+void aemb_hook_clean ()
+{
+  int msr, tmp;
+  int stk_end, stk_siz;
+
+  /*
+  // Check to see if hardware threads are enabled
+  if (((msr & AEMB_TXE) != AEMB_TXE) ||
+  // Check to see if second thread is started
+      ((msr & AEMB_TX1) == AEMB_TX1)) return;
+  */
+  return;
+  asm volatile ("mfs %0, rmsr;"
+		"andi %1, %0, %2;"
+		"xori %1, %1, %2;"
+		"bnei %1, 28;"		
+		"andi %1, %0, %3;"
+		"xori %1, %1, %3;"
+		"beqi %1, 16;"
+		
+		// reallocate stack pointer for T0
+		"ori %1, r0, %4;"
+		"sra %1, %1;"
+		"addk r1, %1, r1;"
+
+		:"=r"(msr), "=r"(tmp)
+		:"i"(AEMB_TXE), "i"(AEMB_TX1), "i"(&_STACK_SIZE)
+		);
+
+  
+}
+
+/* Checks if it's T1, and returns 0 if true */
+
+int aemb_isthread1 ()
+{
+  int msr, tmp, res;
+  asm volatile ("mfs %0, rmsr;"
+		"andi %1, %0, %3;"
+		"xori %1, %1, %3;"	       
+		:"=r"(msr), "=r"(tmp)
+		:"i"(AEMB_TXE), "i"(AEMB_TXP)
+		);
+  return tmp;  
+}
+
+/* Checks if it's T0, and returns 0 if true */
+
+int aemb_isthread0 ()
+{
+  int msr, tmp, res;
+  asm volatile ("mfs %0, rmsr;"
+		"andi %1, %0, %3;"
+		"xori %1, %1, %2;"	       
+		:"=r"(msr), "=r"(tmp)
+		:"i"(AEMB_TXP), "i"(AEMB_MSK)
+		);
+  return tmp;  
+}
+
+/* Checks if TXE is available, and returns 0 if true */
+
+int aemb_isthreaded ()
+{
+  int msr, tmp, res;
+  asm volatile ("mfs %0, rmsr;"
+		"andi %1, %0, %2;"
+		"xori %1, %1, %2;"	       
+		:"=r"(msr), "=r"(tmp)
+		:"i"(AEMB_TXE), "i"(AEMB_MSK)
+		);
+  return tmp;  
+}
+
+#endif
+
+/* $Log: libaemb.h,v $
+/* Revision 1.3  2007/12/16 03:26:37  sybreon
+/* Made T0 loop.
+/*
+/* Revision 1.1  2007/12/11 00:44:04  sybreon
+/* initial import
+/* */
diff --git a/fpga/usrp2/opencores/aemb/sw/gccrom b/fpga/usrp2/opencores/aemb/sw/gccrom
new file mode 100755
index 000000000..f6e581f1f
--- /dev/null
+++ b/fpga/usrp2/opencores/aemb/sw/gccrom
@@ -0,0 +1,62 @@
+#!/bin/sh
+# $Id: gccrom,v 1.13 2008/01/19 16:42:54 sybreon Exp $
+
+# Compile using C++ pre-processor
+mb-g++ -g -Wl,-defsym -Wl,_HEAP_SIZE=0x800 -mxl-soft-div -msoft-float -mxl-barrel-shift -mno-xl-soft-mul -mno-clearbss $@ -o rom.elf -lc_m_bs -lm_m_bs && \
+
+# Create a text listing of the compiled code
+mb-objdump -DSC rom.elf > rom.dump && \
+
+# Convert the ELF file to an SREC file
+mb-objcopy -O srec rom.elf rom.srec && \
+
+# Generate a Verilog VMEM file from the SREC file
+srec_cat rom.srec -o ../sim/dump.vmem -vmem 32 && \
+
+# Cleanup code
+rm rom.srec && \
+
+# Say Cheeze!
+echo "ROM generated"
+
+# $Log: gccrom,v $
+# Revision 1.13  2008/01/19 16:42:54  sybreon
+# Uses multiplier + barrel shifter as default.
+#
+# Revision 1.12  2007/12/11 00:44:32  sybreon
+# Modified for AEMB2
+#
+# Revision 1.11  2007/11/30 17:09:27  sybreon
+# Minor code cleanup.
+#
+# Revision 1.10  2007/11/20 18:35:34  sybreon
+# Generate VMEM instead of HEX dumps of programme.
+#
+# Revision 1.9  2007/11/18 19:41:46  sybreon
+# Minor simulation fixes.
+#
+# Revision 1.8  2007/11/09 20:52:37  sybreon
+# Added some compilation optimisations.
+#
+# Revision 1.7  2007/11/04 05:16:25  sybreon
+# Added -msoft-float and -mxl-soft-div compiler flags.
+#
+# Revision 1.6  2007/11/02 03:25:46  sybreon
+# New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
+# Fixed various minor data hazard bugs.
+# Code compatible with -O0/1/2/3/s generated code.
+#
+# Revision 1.5  2007/10/22 19:14:38  sybreon
+# Recommended to compile code with -O2/3/s
+#
+# Revision 1.4  2007/04/30 15:57:31  sybreon
+# Modified compilation sequence.
+#
+# Revision 1.3  2007/04/25 22:15:06  sybreon
+# Added support for 8-bit and 16-bit data types.
+#
+# Revision 1.2  2007/04/04 06:14:39  sybreon
+# Minor changes
+#
+# Revision 1.1  2007/03/09 17:41:56  sybreon
+# initial import
diff --git a/fpga/usrp2/opencores/i2c/CVS/Entries b/fpga/usrp2/opencores/i2c/CVS/Entries
new file mode 100644
index 000000000..d6947544a
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/CVS/Entries
@@ -0,0 +1,8 @@
+D/bench////
+D/doc////
+D/documentation////
+D/rtl////
+D/sim////
+D/software////
+D/verilog////
+D/vhdl////
diff --git a/fpga/usrp2/opencores/i2c/CVS/Repository b/fpga/usrp2/opencores/i2c/CVS/Repository
new file mode 100644
index 000000000..1a9fe8960
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/CVS/Repository
@@ -0,0 +1 @@
+i2c
diff --git a/fpga/usrp2/opencores/i2c/CVS/Root b/fpga/usrp2/opencores/i2c/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/CVS/Template b/fpga/usrp2/opencores/i2c/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/bench/CVS/Entries b/fpga/usrp2/opencores/i2c/bench/CVS/Entries
new file mode 100644
index 000000000..428c5622d
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/CVS/Entries
@@ -0,0 +1 @@
+D/verilog////
diff --git a/fpga/usrp2/opencores/i2c/bench/CVS/Repository b/fpga/usrp2/opencores/i2c/bench/CVS/Repository
new file mode 100644
index 000000000..5597c8aac
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/CVS/Repository
@@ -0,0 +1 @@
+i2c/bench
diff --git a/fpga/usrp2/opencores/i2c/bench/CVS/Root b/fpga/usrp2/opencores/i2c/bench/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/bench/CVS/Template b/fpga/usrp2/opencores/i2c/bench/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Entries b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Entries
new file mode 100644
index 000000000..2dd779100
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Entries
@@ -0,0 +1,5 @@
+/i2c_slave_model.v/1.7/Mon Sep  4 09:08:51 2006//
+/spi_slave_model.v/1.1/Sat Feb 28 15:32:54 2004//
+/tst_bench_top.v/1.8/Mon Sep  4 09:08:51 2006//
+/wb_master_model.v/1.4/Sat Feb 28 15:40:42 2004//
+D
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Repository b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Repository
new file mode 100644
index 000000000..b37c379e9
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Repository
@@ -0,0 +1 @@
+i2c/bench/verilog
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Root b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Template b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v b/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v
new file mode 100644
index 000000000..0c8ecae0d
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/i2c_slave_model.v
@@ -0,0 +1,360 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant synthesizable I2C Slave model    ////
+////                                                             ////
+////                                                             ////
+////  Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
+////           John Sheahan (jrsheahan@optushome.com.au)         ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001,2002 Richard Herveille                   ////
+////                         richard@asics.ws                    ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_slave_model.v,v 1.7 2006/09/04 09:08:51 rherveille Exp $
+//
+//  $Date: 2006/09/04 09:08:51 $
+//  $Revision: 1.7 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_slave_model.v,v $
+//               Revision 1.7  2006/09/04 09:08:51  rherveille
+//               fixed (n)ack generation
+//
+//               Revision 1.6  2005/02/28 11:33:48  rherveille
+//               Fixed Tsu:sta timing check.
+//               Added Thd:sta timing check.
+//
+//               Revision 1.5  2003/12/05 11:05:19  rherveille
+//               Fixed slave address MSB='1' bug
+//
+//               Revision 1.4  2003/09/11 08:25:37  rherveille
+//               Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'.
+//
+//               Revision 1.3  2002/10/30 18:11:06  rherveille
+//               Added timing tests to i2c_model.
+//               Updated testbench.
+//
+//               Revision 1.2  2002/03/17 10:26:38  rherveille
+//               Fixed some race conditions in the i2c-slave model.
+//               Added debug information.
+//               Added headers.
+//
+
+`include "timescale.v"
+
+module i2c_slave_model (scl, sda);
+
+	//
+	// parameters
+	//
+	parameter I2C_ADR = 7'b001_0000;
+
+	//
+	// input && outpus
+	//
+	input scl;
+	inout sda;
+
+	//
+	// Variable declaration
+	//
+	wire debug = 1'b1;
+
+	reg [7:0] mem [3:0]; // initiate memory
+	reg [7:0] mem_adr;   // memory address
+	reg [7:0] mem_do;    // memory data output
+
+	reg sta, d_sta;
+	reg sto, d_sto;
+
+	reg [7:0] sr;        // 8bit shift register
+	reg       rw;        // read/write direction
+
+	wire      my_adr;    // my address called ??
+	wire      i2c_reset; // i2c-statemachine reset
+	reg [2:0] bit_cnt;   // 3bit downcounter
+	wire      acc_done;  // 8bits transfered
+	reg       ld;        // load downcounter
+
+	reg       sda_o;     // sda-drive level
+	wire      sda_dly;   // delayed version of sda
+
+	// statemachine declaration
+	parameter idle        = 3'b000;
+	parameter slave_ack   = 3'b001;
+	parameter get_mem_adr = 3'b010;
+	parameter gma_ack     = 3'b011;
+	parameter data        = 3'b100;
+	parameter data_ack    = 3'b101;
+
+	reg [2:0] state; // synopsys enum_state
+
+	//
+	// module body
+	//
+
+	initial
+	begin
+	   sda_o = 1'b1;
+	   state = idle;
+	end
+
+	// generate shift register
+	always @(posedge scl)
+	  sr <= #1 {sr[6:0],sda};
+
+	//detect my_address
+	assign my_adr = (sr[7:1] == I2C_ADR);
+	// FIXME: This should not be a generic assign, but rather
+	// qualified on address transfer phase and probably reset by stop
+
+	//generate bit-counter
+	always @(posedge scl)
+	  if(ld)
+	    bit_cnt <= #1 3'b111;
+	  else
+	    bit_cnt <= #1 bit_cnt - 3'h1;
+
+	//generate access done signal
+	assign acc_done = !(|bit_cnt);
+
+	// generate delayed version of sda
+	// this model assumes a hold time for sda after the falling edge of scl.
+	// According to the Phillips i2c spec, there s/b a 0 ns hold time for sda
+	// with regards to scl. If the data changes coincident with the clock, the
+	// acknowledge is missed
+	// Fix by Michael Sosnoski
+	assign #1 sda_dly = sda;
+
+
+	//detect start condition
+	always @(negedge sda)
+	  if(scl)
+	    begin
+	        sta   <= #1 1'b1;
+		d_sta <= #1 1'b0;
+		sto   <= #1 1'b0;
+
+	        if(debug)
+	          $display("DEBUG i2c_slave; start condition detected at %t", $time);
+	    end
+	  else
+	    sta <= #1 1'b0;
+
+	always @(posedge scl)
+	  d_sta <= #1 sta;
+
+	// detect stop condition
+	always @(posedge sda)
+	  if(scl)
+	    begin
+	       sta <= #1 1'b0;
+	       sto <= #1 1'b1;
+
+	       if(debug)
+	         $display("DEBUG i2c_slave; stop condition detected at %t", $time);
+	    end
+	  else
+	    sto <= #1 1'b0;
+
+	//generate i2c_reset signal
+	assign i2c_reset = sta || sto;
+
+	// generate statemachine
+	always @(negedge scl or posedge sto)
+	  if (sto || (sta && !d_sta) )
+	    begin
+	        state <= #1 idle; // reset statemachine
+
+	        sda_o <= #1 1'b1;
+	        ld    <= #1 1'b1;
+	    end
+	  else
+	    begin
+	        // initial settings
+	        sda_o <= #1 1'b1;
+	        ld    <= #1 1'b0;
+
+	        case(state) // synopsys full_case parallel_case
+	            idle: // idle state
+	              if (acc_done && my_adr)
+	                begin
+	                    state <= #1 slave_ack;
+	                    rw <= #1 sr[0];
+	                    sda_o <= #1 1'b0; // generate i2c_ack
+
+	                    #2;
+	                    if(debug && rw)
+	                      $display("DEBUG i2c_slave; command byte received (read) at %t", $time);
+	                    if(debug && !rw)
+	                      $display("DEBUG i2c_slave; command byte received (write) at %t", $time);
+
+	                    if(rw)
+	                      begin
+	                          mem_do <= #1 mem[mem_adr];
+
+	                          if(debug)
+	                            begin
+	                                #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr);
+	                                #2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]);
+	                            end
+	                      end
+	                end
+
+	            slave_ack:
+	              begin
+	                  if(rw)
+	                    begin
+	                        state <= #1 data;
+	                        sda_o <= #1 mem_do[7];
+	                    end
+	                  else
+	                    state <= #1 get_mem_adr;
+
+	                  ld    <= #1 1'b1;
+	              end
+
+	            get_mem_adr: // wait for memory address
+	              if(acc_done)
+	                begin
+	                    state <= #1 gma_ack;
+	                    mem_adr <= #1 sr; // store memory address
+	                    sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address
+
+	                    if(debug)
+	                      #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o);
+	                end
+
+	            gma_ack:
+	              begin
+	                  state <= #1 data;
+	                  ld    <= #1 1'b1;
+	              end
+
+	            data: // receive or drive data
+	              begin
+	                  if(rw)
+	                    sda_o <= #1 mem_do[7];
+
+	                  if(acc_done)
+	                    begin
+	                        state <= #1 data_ack;
+	                        mem_adr <= #2 mem_adr + 8'h1;
+	                        sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read
+
+	                        if(rw)
+	                          begin
+	                              #3 mem_do <= mem[mem_adr];
+
+	                              if(debug)
+	                                #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr);
+	                          end
+
+	                        if(!rw)
+	                          begin
+	                              mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory
+
+	                              if(debug)
+	                                #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr);
+	                          end
+	                    end
+	              end
+
+	            data_ack:
+	              begin
+	                  ld <= #1 1'b1;
+
+	                  if(rw)
+	                    if(sr[0]) // read operation && master send NACK
+	                      begin
+	                          state <= #1 idle;
+	                          sda_o <= #1 1'b1;
+	                      end
+	                    else
+	                      begin
+	                          state <= #1 data;
+	                          sda_o <= #1 mem_do[7];
+	                      end
+	                  else
+	                    begin
+	                        state <= #1 data;
+	                        sda_o <= #1 1'b1;
+	                    end
+	              end
+
+	        endcase
+	    end
+
+	// read data from memory
+	always @(posedge scl)
+	  if(!acc_done && rw)
+	    mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation
+
+	// generate tri-states
+	assign sda = sda_o ? 1'bz : 1'b0;
+
+
+	//
+	// Timing checks
+	//
+
+	wire tst_sto = sto;
+	wire tst_sta = sta;
+
+	specify
+	  specparam normal_scl_low  = 4700,
+	            normal_scl_high = 4000,
+	            normal_tsu_sta  = 4700,
+	            normal_thd_sta  = 4000,
+	            normal_tsu_sto  = 4000,
+	            normal_tbuf     = 4700,
+
+	            fast_scl_low  = 1300,
+	            fast_scl_high =  600,
+	            fast_tsu_sta  = 1300,
+	            fast_thd_sta  =  600,
+	            fast_tsu_sto  =  600,
+	            fast_tbuf     = 1300;
+
+	  $width(negedge scl, normal_scl_low);  // scl low time
+	  $width(posedge scl, normal_scl_high); // scl high time
+
+	  $setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start
+	  $setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start
+	  $setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop
+
+	  $setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time
+	endspecify
+
+endmodule
+
+
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v b/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v
new file mode 100644
index 000000000..7d2f436f9
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/spi_slave_model.v
@@ -0,0 +1,128 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  SPI Slave Model                                            ////
+////                                                             ////
+////                                                             ////
+////  Authors: Richard Herveille (richard@asics.ws) www.asics.ws ////
+////                                                             ////
+////  http://www.opencores.org/projects/simple_spi/              ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2004 Richard Herveille                        ////
+////                         richard@asics.ws                    ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: spi_slave_model.v,v 1.1 2004/02/28 15:32:54 rherveille Exp $
+//
+//  $Date: 2004/02/28 15:32:54 $
+//  $Revision: 1.1 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: spi_slave_model.v,v $
+//               Revision 1.1  2004/02/28 15:32:54  rherveille
+//               Added testbench
+//
+//
+//
+
+
+// Requires: Verilog2001
+
+`include "timescale.v"
+
+module spi_slave_model (
+	input  wire csn;
+	input  wire sck
+	input  wire di;
+	output wire do
+);
+
+	//
+	// Variable declaration
+	//
+	wire debug = 1'b1;
+
+	wire cpol = 1'b0;
+	wire cpha  = 1'b0;
+
+	reg [7:0] mem [7:0]; // initiate memory
+	reg [2:0] mem_adr;   // memory address
+	reg [7:0] mem_do;    // memory data output
+
+	reg [7:0] sri, sro;  // 8bit shift register
+
+	reg [2:0] bit_cnt;
+	reg       ld;
+
+	wire clk;
+
+	//
+	// module body
+	//
+
+	assign clk = cpol ^ cpha ^ sck;
+
+	// generate shift registers
+	always @(posedge clk)
+	  sri <= #1 {sri[6:0],di};
+
+	always @(posedge clk)
+	  if (&bit_cnt)
+	    sro <= #1 mem[mem_adr];
+	  else
+	    sro <= #1 {sro[6:0],1'bx};
+
+	assign do = sro[7];
+
+	//generate bit-counter
+	always @(posedge clk, posedge csn)
+	  if(csn)
+	    bit_cnt <= #1 3'b111;
+	  else
+	    bit_cnt <= #1 bit_cnt - 3'h1;
+
+	//generate access done signal
+        always @(posedge clk)
+	  ld <= #1 ~(|bit_cnt);
+
+	always @(negedge clk)
+          if (ld) begin
+	    mem[mem_adr] <= #1 sri;
+	    mem_adr      <= #1 mem_adr + 1'b1;
+	  end
+
+	initial
+	begin
+	  bit_cnt=3'b111;
+	  mem_adr = 0;
+	  sro = mem[mem_adr];
+	end
+endmodule
+
+
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v b/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v
new file mode 100644
index 000000000..66284e4d4
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v
@@ -0,0 +1,467 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master controller Testbench  ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: tst_bench_top.v,v 1.8 2006/09/04 09:08:51 rherveille Exp $
+//
+//  $Date: 2006/09/04 09:08:51 $
+//  $Revision: 1.8 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: tst_bench_top.v,v $
+//               Revision 1.8  2006/09/04 09:08:51  rherveille
+//               fixed (n)ack generation
+//
+//               Revision 1.7  2005/02/27 09:24:18  rherveille
+//               Fixed scl, sda delay.
+//
+//               Revision 1.6  2004/02/28 15:40:42  rherveille
+//               *** empty log message ***
+//
+//               Revision 1.4  2003/12/05 11:04:38  rherveille
+//               Added slave address configurability
+//
+//               Revision 1.3  2002/10/30 18:11:06  rherveille
+//               Added timing tests to i2c_model.
+//               Updated testbench.
+//
+//               Revision 1.2  2002/03/17 10:26:38  rherveille
+//               Fixed some race conditions in the i2c-slave model.
+//               Added debug information.
+//               Added headers.
+//
+
+`include "timescale.v"
+
+module tst_bench_top();
+
+	//
+	// wires && regs
+	//
+	reg  clk;
+	reg  rstn;
+
+	wire [31:0] adr;
+	wire [ 7:0] dat_i, dat_o, dat0_i, dat1_i;
+	wire we;
+	wire stb;
+	wire cyc;
+	wire ack;
+	wire inta;
+
+	reg [7:0] q, qq;
+
+	wire scl, scl0_o, scl0_oen, scl1_o, scl1_oen;
+	wire sda, sda0_o, sda0_oen, sda1_o, sda1_oen;
+
+	parameter PRER_LO = 3'b000;
+	parameter PRER_HI = 3'b001;
+	parameter CTR     = 3'b010;
+	parameter RXR     = 3'b011;
+	parameter TXR     = 3'b011;
+	parameter CR      = 3'b100;
+	parameter SR      = 3'b100;
+
+	parameter TXR_R   = 3'b101; // undocumented / reserved output
+	parameter CR_R    = 3'b110; // undocumented / reserved output
+
+	parameter RD      = 1'b1;
+	parameter WR      = 1'b0;
+	parameter SADR    = 7'b0010_000;
+
+	//
+	// Module body
+	//
+
+	// generate clock
+	always #5 clk = ~clk;
+
+	// hookup wishbone master model
+	wb_master_model #(8, 32) u0 (
+		.clk(clk),
+		.rst(rstn),
+		.adr(adr),
+		.din(dat_i),
+		.dout(dat_o),
+		.cyc(cyc),
+		.stb(stb),
+		.we(we),
+		.sel(),
+		.ack(ack),
+		.err(1'b0),
+		.rty(1'b0)
+	);
+
+	wire stb0 = stb & ~adr[3];
+	wire stb1 = stb &  adr[3];
+
+	assign dat_i = ({{8'd8}{stb0}} & dat0_i) | ({{8'd8}{stb1}} & dat1_i);
+
+	// hookup wishbone_i2c_master core
+	i2c_master_top i2c_top (
+
+		// wishbone interface
+		.wb_clk_i(clk),
+		.wb_rst_i(1'b0),
+		.arst_i(rstn),
+		.wb_adr_i(adr[2:0]),
+		.wb_dat_i(dat_o),
+		.wb_dat_o(dat0_i),
+		.wb_we_i(we),
+		.wb_stb_i(stb0),
+		.wb_cyc_i(cyc),
+		.wb_ack_o(ack),
+		.wb_inta_o(inta),
+
+		// i2c signals
+		.scl_pad_i(scl),
+		.scl_pad_o(scl0_o),
+		.scl_padoen_o(scl0_oen),
+		.sda_pad_i(sda),
+		.sda_pad_o(sda0_o),
+		.sda_padoen_o(sda0_oen)
+	),
+	i2c_top2 (
+
+		// wishbone interface
+		.wb_clk_i(clk),
+		.wb_rst_i(1'b0),
+		.arst_i(rstn),
+		.wb_adr_i(adr[2:0]),
+		.wb_dat_i(dat_o),
+		.wb_dat_o(dat1_i),
+		.wb_we_i(we),
+		.wb_stb_i(stb1),
+		.wb_cyc_i(cyc),
+		.wb_ack_o(ack),
+		.wb_inta_o(inta),
+
+		// i2c signals
+		.scl_pad_i(scl),
+		.scl_pad_o(scl1_o),
+		.scl_padoen_o(scl1_oen),
+		.sda_pad_i(sda),
+		.sda_pad_o(sda1_o),
+		.sda_padoen_o(sda1_oen)
+	);
+
+
+	// hookup i2c slave model
+	i2c_slave_model #(SADR) i2c_slave (
+		.scl(scl),
+		.sda(sda)
+	);
+
+        // create i2c lines
+	delay m0_scl (scl0_oen ? 1'bz : scl0_o, scl),
+	      m1_scl (scl1_oen ? 1'bz : scl1_o, scl),
+	      m0_sda (sda0_oen ? 1'bz : sda0_o, sda),
+	      m1_sda (sda1_oen ? 1'bz : sda1_o, sda);
+
+	pullup p1(scl); // pullup scl line
+	pullup p2(sda); // pullup sda line
+
+	initial
+	  begin
+	      `ifdef WAVES
+	         $shm_open("waves");
+	         $shm_probe("AS",tst_bench_top,"AS");
+	         $display("INFO: Signal dump enabled ...\n\n");
+	      `endif
+
+//	      force i2c_slave.debug = 1'b1; // enable i2c_slave debug information
+	      force i2c_slave.debug = 1'b0; // disable i2c_slave debug information
+
+	      $display("\nstatus: %t Testbench started\n\n", $time);
+
+//	      $dumpfile("bench.vcd");
+//	      $dumpvars(1, tst_bench_top);
+//	      $dumpvars(1, tst_bench_top.i2c_slave);
+
+	      // initially values
+	      clk = 0;
+
+	      // reset system
+	      rstn = 1'b1; // negate reset
+	      #2;
+	      rstn = 1'b0; // assert reset
+	      repeat(1) @(posedge clk);
+	      rstn = 1'b1; // negate reset
+
+	      $display("status: %t done reset", $time);
+
+	      @(posedge clk);
+
+	      //
+	      // program core
+	      //
+
+	      // program internal registers
+	      u0.wb_write(1, PRER_LO, 8'hfa); // load prescaler lo-byte
+	      u0.wb_write(1, PRER_LO, 8'hc8); // load prescaler lo-byte
+	      u0.wb_write(1, PRER_HI, 8'h00); // load prescaler hi-byte
+	      $display("status: %t programmed registers", $time);
+
+	      u0.wb_cmp(0, PRER_LO, 8'hc8); // verify prescaler lo-byte
+	      u0.wb_cmp(0, PRER_HI, 8'h00); // verify prescaler hi-byte
+	      $display("status: %t verified registers", $time);
+
+	      u0.wb_write(1, CTR,     8'h80); // enable core
+	      $display("status: %t core enabled", $time);
+
+	      //
+	      // access slave (write)
+	      //
+
+	      // drive slave address
+	      u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
+	      u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
+	      $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(0, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // send memory address
+	      u0.wb_write(1, TXR,     8'h01); // present slave's memory address
+	      u0.wb_write(0, CR,      8'h10); // set command (write)
+	      $display("status: %t write slave memory address 01", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(0, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // send memory contents
+	      u0.wb_write(1, TXR,     8'ha5); // present data
+	      u0.wb_write(0, CR,      8'h10); // set command (write)
+	      $display("status: %t write data a5", $time);
+
+while (scl) #1;
+force scl= 1'b0;
+#100000;
+release scl;
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // send memory contents for next memory address (auto_inc)
+	      u0.wb_write(1, TXR,     8'h5a); // present data
+	      u0.wb_write(0, CR,      8'h50); // set command (stop, write)
+	      $display("status: %t write next data 5a, generate 'stop'", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      //
+	      // delay
+	      //
+//	      #100000; // wait for 100us.
+//	      $display("status: %t wait 100us", $time);
+
+	      //
+	      // access slave (read)
+	      //
+
+	      // drive slave address
+	      u0.wb_write(1, TXR,{SADR,WR} ); // present slave address, set write-bit
+	      u0.wb_write(0, CR,     8'h90 ); // set command (start, write)
+	      $display("status: %t generate 'start', write cmd %0h (slave address+write)", $time, {SADR,WR} );
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // send memory address
+	      u0.wb_write(1, TXR,     8'h01); // present slave's memory address
+	      u0.wb_write(0, CR,      8'h10); // set command (write)
+	      $display("status: %t write slave address 01", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // drive slave address
+	      u0.wb_write(1, TXR, {SADR,RD} ); // present slave's address, set read-bit
+	      u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
+	      $display("status: %t generate 'repeated start', write cmd %0h (slave address+read)", $time, {SADR,RD} );
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // read data from slave
+	      u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
+	      $display("status: %t read + ack", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // check data just received
+	      u0.wb_read(1, RXR, qq);
+	      if(qq !== 8'ha5)
+	        $display("\nERROR: Expected a5, received %x at time %t", qq, $time);
+	      else
+	        $display("status: %t received %x", $time, qq);
+
+	      // read data from slave
+	      u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
+	      $display("status: %t read + ack", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // check data just received
+	      u0.wb_read(1, RXR, qq);
+	      if(qq !== 8'h5a)
+	        $display("\nERROR: Expected 5a, received %x at time %t", qq, $time);
+	      else
+	        $display("status: %t received %x", $time, qq);
+
+	      // read data from slave
+	      u0.wb_write(1, CR,      8'h20); // set command (read, ack_read)
+	      $display("status: %t read + ack", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // check data just received
+	      u0.wb_read(1, RXR, qq);
+	      $display("status: %t received %x from 3rd read address", $time, qq);
+
+	      // read data from slave
+	      u0.wb_write(1, CR,      8'h28); // set command (read, nack_read)
+	      $display("status: %t read + nack", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // check data just received
+	      u0.wb_read(1, RXR, qq);
+	      $display("status: %t received %x from 4th read address", $time, qq);
+
+	      //
+	      // check invalid slave memory address
+	      //
+
+	      // drive slave address
+	      u0.wb_write(1, TXR, {SADR,WR} ); // present slave address, set write-bit
+	      u0.wb_write(0, CR,      8'h90 ); // set command (start, write)
+	      $display("status: %t generate 'start', write cmd %0h (slave address+write). Check invalid address", $time, {SADR,WR} );
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // send memory address
+	      u0.wb_write(1, TXR,     8'h10); // present slave's memory address
+	      u0.wb_write(0, CR,      8'h10); // set command (write)
+	      $display("status: %t write slave memory address 10", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	           u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      // slave should have send NACK
+	      $display("status: %t Check for nack", $time);
+	      if(!q[7])
+	        $display("\nERROR: Expected NACK, received ACK\n");
+
+	      // read data from slave
+	      u0.wb_write(1, CR,      8'h40); // set command (stop)
+	      $display("status: %t generate 'stop'", $time);
+
+	      // check tip bit
+	      u0.wb_read(1, SR, q);
+	      while(q[1])
+	      u0.wb_read(1, SR, q); // poll it until it is zero
+	      $display("status: %t tip==0", $time);
+
+	      #250000; // wait 250us
+	      $display("\n\nstatus: %t Testbench done", $time);
+	      $finish;
+	  end
+
+endmodule
+
+module delay (in, out);
+  input  in;
+  output out;
+
+  assign out = in;
+
+  specify
+    (in => out) = (600,600);
+  endspecify
+endmodule
+
+
diff --git a/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v b/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v
new file mode 100644
index 000000000..14ed6cbf5
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v
@@ -0,0 +1,205 @@
+///////////////////////////////////////////////////////////////////////
+////                                                               ////
+////  WISHBONE rev.B2 Wishbone Master model                        ////
+////                                                               ////
+////                                                               ////
+////  Author: Richard Herveille                                    ////
+////          richard@asics.ws                                     ////
+////          www.asics.ws                                         ////
+////                                                               ////
+////  Downloaded from: http://www.opencores.org/projects/mem_ctrl  ////
+////                                                               ////
+///////////////////////////////////////////////////////////////////////
+////                                                               ////
+//// Copyright (C) 2001 Richard Herveille                          ////
+////                    richard@asics.ws                           ////
+////                                                               ////
+//// This source file may be used and distributed without          ////
+//// restriction provided that this copyright statement is not     ////
+//// removed from the file and that any derivative work contains   ////
+//// the original copyright notice and the associated disclaimer.  ////
+////                                                               ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY       ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED     ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS     ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR        ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,           ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES      ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE     ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR          ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF    ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT    ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT    ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
+//// POSSIBILITY OF SUCH DAMAGE.                                   ////
+////                                                               ////
+///////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: wb_master_model.v,v 1.4 2004/02/28 15:40:42 rherveille Exp $
+//
+//  $Date: 2004/02/28 15:40:42 $
+//  $Revision: 1.4 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//
+`include "timescale.v"
+
+module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
+
+parameter dwidth = 32;
+parameter awidth = 32;
+
+input                  clk, rst;
+output [awidth   -1:0]	adr;
+input  [dwidth   -1:0]	din;
+output [dwidth   -1:0]	dout;
+output                 cyc, stb;
+output       	        	we;
+output [dwidth/8 -1:0] sel;
+input		                ack, err, rty;
+
+////////////////////////////////////////////////////////////////////
+//
+// Local Wires
+//
+
+reg	[awidth   -1:0]	adr;
+reg	[dwidth   -1:0]	dout;
+reg		               cyc, stb;
+reg		               we;
+reg [dwidth/8 -1:0] sel;
+
+reg [dwidth   -1:0] q;
+
+////////////////////////////////////////////////////////////////////
+//
+// Memory Logic
+//
+
+initial
+	begin
+		//adr = 32'hxxxx_xxxx;
+		//adr = 0;
+		adr  = {awidth{1'bx}};
+		dout = {dwidth{1'bx}};
+		cyc  = 1'b0;
+		stb  = 1'bx;
+		we   = 1'hx;
+		sel  = {dwidth/8{1'bx}};
+		#1;
+		$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
+	end
+
+////////////////////////////////////////////////////////////////////
+//
+// Wishbone write cycle
+//
+
+task wb_write;
+	input   delay;
+	integer delay;
+
+	input	[awidth -1:0]	a;
+	input	[dwidth -1:0]	d;
+
+	begin
+
+		// wait initial delay
+		repeat(delay) @(posedge clk);
+
+		// assert wishbone signal
+		#1;
+		adr  = a;
+		dout = d;
+		cyc  = 1'b1;
+		stb  = 1'b1;
+		we   = 1'b1;
+		sel  = {dwidth/8{1'b1}};
+		@(posedge clk);
+
+		// wait for acknowledge from slave
+		while(~ack)	@(posedge clk);
+
+		// negate wishbone signals
+		#1;
+		cyc  = 1'b0;
+		stb  = 1'bx;
+		adr  = {awidth{1'bx}};
+		dout = {dwidth{1'bx}};
+		we   = 1'hx;
+		sel  = {dwidth/8{1'bx}};
+
+	end
+endtask
+
+////////////////////////////////////////////////////////////////////
+//
+// Wishbone read cycle
+//
+
+task wb_read;
+	input   delay;
+	integer delay;
+
+	input	 [awidth -1:0]	a;
+	output	[dwidth -1:0]	d;
+
+	begin
+
+		// wait initial delay
+		repeat(delay) @(posedge clk);
+
+		// assert wishbone signals
+		#1;
+		adr  = a;
+		dout = {dwidth{1'bx}};
+		cyc  = 1'b1;
+		stb  = 1'b1;
+		we   = 1'b0;
+		sel  = {dwidth/8{1'b1}};
+		@(posedge clk);
+
+		// wait for acknowledge from slave
+		while(~ack)	@(posedge clk);
+
+		// negate wishbone signals
+		#1;
+		cyc  = 1'b0;
+		stb  = 1'bx;
+		adr  = {awidth{1'bx}};
+		dout = {dwidth{1'bx}};
+		we   = 1'hx;
+		sel  = {dwidth/8{1'bx}};
+		d    = din;
+
+	end
+endtask
+
+////////////////////////////////////////////////////////////////////
+//
+// Wishbone compare cycle (read data from location and compare with expected data)
+//
+
+task wb_cmp;
+	input   delay;
+	integer delay;
+
+	input [awidth -1:0]	a;
+	input	[dwidth -1:0]	d_exp;
+
+	begin
+		wb_read (delay, a, q);
+
+		if (d_exp !== q)
+			$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
+	end
+endtask
+
+endmodule
+
+
diff --git a/fpga/usrp2/opencores/i2c/doc/CVS/Entries b/fpga/usrp2/opencores/i2c/doc/CVS/Entries
new file mode 100644
index 000000000..ec323c90b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/CVS/Entries
@@ -0,0 +1,2 @@
+/i2c_specs.pdf/1.3/Thu Jul  3 15:20:47 2003/-kb/
+D/src////
diff --git a/fpga/usrp2/opencores/i2c/doc/CVS/Repository b/fpga/usrp2/opencores/i2c/doc/CVS/Repository
new file mode 100644
index 000000000..2ee10951a
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/CVS/Repository
@@ -0,0 +1 @@
+i2c/doc
diff --git a/fpga/usrp2/opencores/i2c/doc/CVS/Root b/fpga/usrp2/opencores/i2c/doc/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/doc/CVS/Template b/fpga/usrp2/opencores/i2c/doc/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/doc/i2c_specs.pdf b/fpga/usrp2/opencores/i2c/doc/i2c_specs.pdf
new file mode 100644
index 000000000..72021df11
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/i2c_specs.pdf
diff --git a/fpga/usrp2/opencores/i2c/doc/src/CVS/Entries b/fpga/usrp2/opencores/i2c/doc/src/CVS/Entries
new file mode 100644
index 000000000..5eeda5738
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/src/CVS/Entries
@@ -0,0 +1,2 @@
+/I2C_specs.doc/1.7/Thu Jul  3 15:21:23 2003/-kb/
+D
diff --git a/fpga/usrp2/opencores/i2c/doc/src/CVS/Repository b/fpga/usrp2/opencores/i2c/doc/src/CVS/Repository
new file mode 100644
index 000000000..74dd64858
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/src/CVS/Repository
@@ -0,0 +1 @@
+i2c/doc/src
diff --git a/fpga/usrp2/opencores/i2c/doc/src/CVS/Root b/fpga/usrp2/opencores/i2c/doc/src/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/src/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/doc/src/CVS/Template b/fpga/usrp2/opencores/i2c/doc/src/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/src/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/doc/src/I2C_specs.doc b/fpga/usrp2/opencores/i2c/doc/src/I2C_specs.doc
new file mode 100644
index 000000000..31ab2684f
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/doc/src/I2C_specs.doc
diff --git a/fpga/usrp2/opencores/i2c/documentation/CVS/Entries b/fpga/usrp2/opencores/i2c/documentation/CVS/Entries
new file mode 100644
index 000000000..178481050
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/documentation/CVS/Entries
@@ -0,0 +1 @@
+D
diff --git a/fpga/usrp2/opencores/i2c/documentation/CVS/Repository b/fpga/usrp2/opencores/i2c/documentation/CVS/Repository
new file mode 100644
index 000000000..1ccd8f6ce
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/documentation/CVS/Repository
@@ -0,0 +1 @@
+i2c/documentation
diff --git a/fpga/usrp2/opencores/i2c/documentation/CVS/Root b/fpga/usrp2/opencores/i2c/documentation/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/documentation/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/documentation/CVS/Template b/fpga/usrp2/opencores/i2c/documentation/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/documentation/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/rtl/CVS/Entries b/fpga/usrp2/opencores/i2c/rtl/CVS/Entries
new file mode 100644
index 000000000..354f0dfb5
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/CVS/Entries
@@ -0,0 +1,2 @@
+D/verilog////
+D/vhdl////
diff --git a/fpga/usrp2/opencores/i2c/rtl/CVS/Repository b/fpga/usrp2/opencores/i2c/rtl/CVS/Repository
new file mode 100644
index 000000000..cfb83efd3
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/CVS/Repository
@@ -0,0 +1 @@
+i2c/rtl
diff --git a/fpga/usrp2/opencores/i2c/rtl/CVS/Root b/fpga/usrp2/opencores/i2c/rtl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/rtl/CVS/Template b/fpga/usrp2/opencores/i2c/rtl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Entries b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Entries
new file mode 100644
index 000000000..441bd81af
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Entries
@@ -0,0 +1,6 @@
+/i2c_master_bit_ctrl.v/1.12/Mon Sep  4 09:08:13 2006//
+/i2c_master_byte_ctrl.v/1.7/Wed Feb 18 11:40:46 2004//
+/i2c_master_defines.v/1.3/Mon Nov  5 11:59:25 2001//
+/i2c_master_top.v/1.11/Sun Feb 27 09:26:24 2005//
+/timescale.v/1.1/Mon Sep 24 12:21:50 2001//
+D
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Repository b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Repository
new file mode 100644
index 000000000..49cc6cce0
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Repository
@@ -0,0 +1 @@
+i2c/rtl/verilog
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Root b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Template b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v
new file mode 100644
index 000000000..edab94f61
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v
@@ -0,0 +1,538 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master bit-controller        ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_bit_ctrl.v,v 1.12 2006/09/04 09:08:13 rherveille Exp $
+//
+//  $Date: 2006/09/04 09:08:13 $
+//  $Revision: 1.12 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_bit_ctrl.v,v $
+//               Revision 1.12  2006/09/04 09:08:13  rherveille
+//               fixed short scl high pulse after clock stretch
+//               fixed slave model not returning correct '(n)ack' signal
+//
+//               Revision 1.11  2004/05/07 11:02:26  rherveille
+//               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
+//
+//               Revision 1.10  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.9  2003/03/10 14:26:37  rherveille
+//               Fixed cmd_ack generation item (no bug).
+//
+//               Revision 1.8  2003/02/05 00:06:10  rherveille
+//               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
+//
+//               Revision 1.7  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.6  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.5  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.4  2002/10/30 18:10:07  rherveille
+//               Fixed some reported minor start/stop generation timing issuess.
+//
+//               Revision 1.3  2002/06/15 07:37:03  rherveille
+//               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
+//
+//               Revision 1.2  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+//
+/////////////////////////////////////
+// Bit controller section
+/////////////////////////////////////
+//
+// Translate simple commands into SCL/SDA transitions
+// Each command has 5 states, A/B/C/D/idle
+//
+// start:	SCL	~~~~~~~~~~\____
+//	SDA	~~~~~~~~\______
+//		 x | A | B | C | D | i
+//
+// repstart	SCL	____/~~~~\___
+//	SDA	__/~~~\______
+//		 x | A | B | C | D | i
+//
+// stop	SCL	____/~~~~~~~~
+//	SDA	==\____/~~~~~
+//		 x | A | B | C | D | i
+//
+//- write	SCL	____/~~~~\____
+//	SDA	==X=========X=
+//		 x | A | B | C | D | i
+//
+//- read	SCL	____/~~~~\____
+//	SDA	XXXX=====XXXX
+//		 x | A | B | C | D | i
+//
+
+// Timing:     Normal mode      Fast mode
+///////////////////////////////////////////////////////////////////////
+// Fscl        100KHz           400KHz
+// Th_scl      4.0us            0.6us   High period of SCL
+// Tl_scl      4.7us            1.3us   Low period of SCL
+// Tsu:sta     4.7us            0.6us   setup time for a repeated start condition
+// Tsu:sto     4.0us            0.6us   setup time for a stop conditon
+// Tbuf        4.7us            1.3us   Bus free time between a stop and start condition
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_bit_ctrl(
+	clk, rst, nReset, 
+	clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
+	scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
+	);
+
+	//
+	// inputs & outputs
+	//
+	input clk;
+	input rst;
+	input nReset;
+	input ena;            // core enable signal
+
+	input [15:0] clk_cnt; // clock prescale value
+
+	input  [3:0] cmd;
+	output       cmd_ack; // command complete acknowledge
+	reg cmd_ack;
+	output       busy;    // i2c bus busy
+	reg busy;
+	output       al;      // i2c bus arbitration lost
+	reg al;
+
+	input  din;
+	output dout;
+	reg dout;
+
+	// I2C lines
+	input  scl_i;         // i2c clock line input
+	output scl_o;         // i2c clock line output
+	output scl_oen;       // i2c clock line output enable (active low)
+	reg scl_oen;
+	input  sda_i;         // i2c data line input
+	output sda_o;         // i2c data line output
+	output sda_oen;       // i2c data line output enable (active low)
+	reg sda_oen;
+
+
+	//
+	// variable declarations
+	//
+
+	reg sSCL, sSDA;             // synchronized SCL and SDA inputs
+	reg dscl_oen;               // delayed scl_oen
+	reg sda_chk;                // check SDA output (Multi-master arbitration)
+	reg clk_en;                 // clock generation signals
+	wire slave_wait;
+//	reg [15:0] cnt = clk_cnt;   // clock divider counter (simulation)
+	reg [15:0] cnt;             // clock divider counter (synthesis)
+
+	// state machine variable
+	reg [16:0] c_state; // synopsys enum_state
+
+	//
+	// module body
+	//
+
+	// whenever the slave is not ready it can delay the cycle by pulling SCL low
+	// delay scl_oen
+	always @(posedge clk)
+	  dscl_oen <= #1 scl_oen;
+
+	assign slave_wait = dscl_oen && !sSCL;
+
+
+	// generate clk enable signal
+	always @(posedge clk or negedge nReset)
+	  if(~nReset)
+	    begin
+	        cnt    <= #1 16'h0;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if (rst)
+	    begin
+	        cnt    <= #1 16'h0;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if ( ~|cnt || !ena)
+	    begin
+	        cnt    <= #1 clk_cnt;
+	        clk_en <= #1 1'b1;
+	    end
+	  else if (slave_wait)
+	    begin
+	        cnt    <= #1 cnt;
+	        clk_en <= #1 1'b0;    
+	    end
+	  else
+	    begin
+	        cnt    <= #1 cnt - 16'h1;
+	        clk_en <= #1 1'b0;
+	    end
+
+
+	// generate bus status controller
+	reg dSCL, dSDA;
+	reg sta_condition;
+	reg sto_condition;
+
+	// synchronize SCL and SDA inputs
+	// reduce metastability risc
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    begin
+	        sSCL <= #1 1'b1;
+	        sSDA <= #1 1'b1;
+
+	        dSCL <= #1 1'b1;
+	        dSDA <= #1 1'b1;
+	    end
+	  else if (rst)
+	    begin
+	        sSCL <= #1 1'b1;
+	        sSDA <= #1 1'b1;
+
+	        dSCL <= #1 1'b1;
+	        dSDA <= #1 1'b1;
+	    end
+	  else
+	    begin
+	        sSCL <= #1 scl_i;
+	        sSDA <= #1 sda_i;
+
+	        dSCL <= #1 sSCL;
+	        dSDA <= #1 sSDA;
+	    end
+
+	// detect start condition => detect falling edge on SDA while SCL is high
+	// detect stop condition => detect rising edge on SDA while SCL is high
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    begin
+	        sta_condition <= #1 1'b0;
+	        sto_condition <= #1 1'b0;
+	    end
+	  else if (rst)
+	    begin
+	        sta_condition <= #1 1'b0;
+	        sto_condition <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        sta_condition <= #1 ~sSDA &  dSDA & sSCL;
+	        sto_condition <= #1  sSDA & ~dSDA & sSCL;
+	    end
+
+	// generate i2c bus busy signal
+	always @(posedge clk or negedge nReset)
+	  if(!nReset)
+	    busy <= #1 1'b0;
+	  else if (rst)
+	    busy <= #1 1'b0;
+	  else
+	    busy <= #1 (sta_condition | busy) & ~sto_condition;
+
+	// generate arbitration lost signal
+	// aribitration lost when:
+	// 1) master drives SDA high, but the i2c bus is low
+	// 2) stop detected while not requested
+	reg cmd_stop;
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    cmd_stop <= #1 1'b0;
+	  else if (rst)
+	    cmd_stop <= #1 1'b0;
+	  else if (clk_en)
+	    cmd_stop <= #1 cmd == `I2C_CMD_STOP;
+
+	always @(posedge clk or negedge nReset)
+	  if (~nReset)
+	    al <= #1 1'b0;
+	  else if (rst)
+	    al <= #1 1'b0;
+	  else
+	    al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
+
+
+	// generate dout signal (store SDA on rising edge of SCL)
+	always @(posedge clk)
+	  if(sSCL & ~dSCL)
+	    dout <= #1 sSDA;
+
+	// generate statemachine
+
+	// nxt_state decoder
+	parameter [16:0] idle    = 17'b0_0000_0000_0000_0000;
+	parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
+	parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
+	parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
+	parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
+	parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
+	parameter [16:0] stop_a  = 17'b0_0000_0000_0010_0000;
+	parameter [16:0] stop_b  = 17'b0_0000_0000_0100_0000;
+	parameter [16:0] stop_c  = 17'b0_0000_0000_1000_0000;
+	parameter [16:0] stop_d  = 17'b0_0000_0001_0000_0000;
+	parameter [16:0] rd_a    = 17'b0_0000_0010_0000_0000;
+	parameter [16:0] rd_b    = 17'b0_0000_0100_0000_0000;
+	parameter [16:0] rd_c    = 17'b0_0000_1000_0000_0000;
+	parameter [16:0] rd_d    = 17'b0_0001_0000_0000_0000;
+	parameter [16:0] wr_a    = 17'b0_0010_0000_0000_0000;
+	parameter [16:0] wr_b    = 17'b0_0100_0000_0000_0000;
+	parameter [16:0] wr_c    = 17'b0_1000_0000_0000_0000;
+	parameter [16:0] wr_d    = 17'b1_0000_0000_0000_0000;
+
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    begin
+	        c_state <= #1 idle;
+	        cmd_ack <= #1 1'b0;
+	        scl_oen <= #1 1'b1;
+	        sda_oen <= #1 1'b1;
+	        sda_chk <= #1 1'b0;
+	    end
+	  else if (rst | al)
+	    begin
+	        c_state <= #1 idle;
+	        cmd_ack <= #1 1'b0;
+	        scl_oen <= #1 1'b1;
+	        sda_oen <= #1 1'b1;
+	        sda_chk <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
+
+	        if (clk_en)
+	          case (c_state) // synopsys full_case parallel_case
+	            // idle state
+	            idle:
+	            begin
+	                case (cmd) // synopsys full_case parallel_case
+	                  `I2C_CMD_START:
+	                     c_state <= #1 start_a;
+
+	                  `I2C_CMD_STOP:
+	                     c_state <= #1 stop_a;
+
+	                  `I2C_CMD_WRITE:
+	                     c_state <= #1 wr_a;
+
+	                  `I2C_CMD_READ:
+	                     c_state <= #1 rd_a;
+
+	                  default:
+	                    c_state <= #1 idle;
+	                endcase
+
+	                scl_oen <= #1 scl_oen; // keep SCL in same state
+	                sda_oen <= #1 sda_oen; // keep SDA in same state
+	                sda_chk <= #1 1'b0;    // don't check SDA output
+	            end
+
+	            // start
+	            start_a:
+	            begin
+	                c_state <= #1 start_b;
+	                scl_oen <= #1 scl_oen; // keep SCL in same state
+	                sda_oen <= #1 1'b1;    // set SDA high
+	                sda_chk <= #1 1'b0;    // don't check SDA output
+	            end
+
+	            start_b:
+	            begin
+	                c_state <= #1 start_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b1; // keep SDA high
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_c:
+	            begin
+	                c_state <= #1 start_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // set SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_d:
+	            begin
+	                c_state <= #1 start_e;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            start_e:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // stop
+	            stop_a:
+	            begin
+	                c_state <= #1 stop_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 1'b0; // set SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_b:
+	            begin
+	                c_state <= #1 stop_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_c:
+	            begin
+	                c_state <= #1 stop_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b0; // keep SDA low
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            stop_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b1; // set SDA high
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // read
+	            rd_a:
+	            begin
+	                c_state <= #1 rd_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 1'b1; // tri-state SDA
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_b:
+	            begin
+	                c_state <= #1 rd_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_c:
+	            begin
+	                c_state <= #1 rd_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            rd_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 1'b1; // keep SDA tri-stated
+	                sda_chk <= #1 1'b0; // don't check SDA output
+	            end
+
+	            // write
+	            wr_a:
+	            begin
+	                c_state <= #1 wr_b;
+	                scl_oen <= #1 1'b0; // keep SCL low
+	                sda_oen <= #1 din;  // set SDA
+	                sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+	            end
+
+	            wr_b:
+	            begin
+	                c_state <= #1 wr_c;
+	                scl_oen <= #1 1'b1; // set SCL high
+	                sda_oen <= #1 din;  // keep SDA
+	                sda_chk <= #1 1'b1; // check SDA output
+	            end
+
+	            wr_c:
+	            begin
+	                c_state <= #1 wr_d;
+	                scl_oen <= #1 1'b1; // keep SCL high
+	                sda_oen <= #1 din;
+	                sda_chk <= #1 1'b1; // check SDA output
+	            end
+
+	            wr_d:
+	            begin
+	                c_state <= #1 idle;
+	                cmd_ack <= #1 1'b1;
+	                scl_oen <= #1 1'b0; // set SCL low
+	                sda_oen <= #1 din;
+	                sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
+	            end
+
+	          endcase
+	    end
+
+
+	// assign scl and sda output (always gnd)
+	assign scl_o = 1'b0;
+	assign sda_o = 1'b0;
+
+endmodule
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v
new file mode 100644
index 000000000..d091d1e36
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v
@@ -0,0 +1,344 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master byte-controller       ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_byte_ctrl.v,v 1.7 2004/02/18 11:40:46 rherveille Exp $
+//
+//  $Date: 2004/02/18 11:40:46 $
+//  $Revision: 1.7 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_byte_ctrl.v,v $
+//               Revision 1.7  2004/02/18 11:40:46  rherveille
+//               Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
+//
+//               Revision 1.6  2003/08/09 07:01:33  rherveille
+//               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+//               Fixed a potential bug in the byte controller's host-acknowledge generation.
+//
+//               Revision 1.5  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.4  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.3  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_byte_ctrl (
+	clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
+	cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
+
+	//
+	// inputs & outputs
+	//
+	input clk;     // master clock
+	input rst;     // synchronous active high reset
+	input nReset;  // asynchronous active low reset
+	input ena;     // core enable signal
+
+	input [15:0] clk_cnt; // 4x SCL
+
+	// control inputs
+	input       start;
+	input       stop;
+	input       read;
+	input       write;
+	input       ack_in;
+	input [7:0] din;
+
+	// status outputs
+	output       cmd_ack;
+	reg cmd_ack;
+	output       ack_out;
+	reg ack_out;
+	output       i2c_busy;
+	output       i2c_al;
+	output [7:0] dout;
+
+	// I2C signals
+	input  scl_i;
+	output scl_o;
+	output scl_oen;
+	input  sda_i;
+	output sda_o;
+	output sda_oen;
+
+
+	//
+	// Variable declarations
+	//
+
+	// statemachine
+	parameter [4:0] ST_IDLE  = 5'b0_0000;
+	parameter [4:0] ST_START = 5'b0_0001;
+	parameter [4:0] ST_READ  = 5'b0_0010;
+	parameter [4:0] ST_WRITE = 5'b0_0100;
+	parameter [4:0] ST_ACK   = 5'b0_1000;
+	parameter [4:0] ST_STOP  = 5'b1_0000;
+
+	// signals for bit_controller
+	reg  [3:0] core_cmd;
+	reg        core_txd;
+	wire       core_ack, core_rxd;
+
+	// signals for shift register
+	reg [7:0] sr; //8bit shift register
+	reg       shift, ld;
+
+	// signals for state machine
+	wire       go;
+	reg  [2:0] dcnt;
+	wire       cnt_done;
+
+	//
+	// Module body
+	//
+
+	// hookup bit_controller
+	i2c_master_bit_ctrl bit_controller (
+		.clk     ( clk      ),
+		.rst     ( rst      ),
+		.nReset  ( nReset   ),
+		.ena     ( ena      ),
+		.clk_cnt ( clk_cnt  ),
+		.cmd     ( core_cmd ),
+		.cmd_ack ( core_ack ),
+		.busy    ( i2c_busy ),
+		.al      ( i2c_al   ),
+		.din     ( core_txd ),
+		.dout    ( core_rxd ),
+		.scl_i   ( scl_i    ),
+		.scl_o   ( scl_o    ),
+		.scl_oen ( scl_oen  ),
+		.sda_i   ( sda_i    ),
+		.sda_o   ( sda_o    ),
+		.sda_oen ( sda_oen  )
+	);
+
+	// generate go-signal
+	assign go = (read | write | stop) & ~cmd_ack;
+
+	// assign dout output to shift-register
+	assign dout = sr;
+
+	// generate shift register
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    sr <= #1 8'h0;
+	  else if (rst)
+	    sr <= #1 8'h0;
+	  else if (ld)
+	    sr <= #1 din;
+	  else if (shift)
+	    sr <= #1 {sr[6:0], core_rxd};
+
+	// generate counter
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    dcnt <= #1 3'h0;
+	  else if (rst)
+	    dcnt <= #1 3'h0;
+	  else if (ld)
+	    dcnt <= #1 3'h7;
+	  else if (shift)
+	    dcnt <= #1 dcnt - 3'h1;
+
+	assign cnt_done = ~(|dcnt);
+
+	//
+	// state machine
+	//
+	reg [4:0] c_state; // synopsis enum_state
+
+	always @(posedge clk or negedge nReset)
+	  if (!nReset)
+	    begin
+	        core_cmd <= #1 `I2C_CMD_NOP;
+	        core_txd <= #1 1'b0;
+	        shift    <= #1 1'b0;
+	        ld       <= #1 1'b0;
+	        cmd_ack  <= #1 1'b0;
+	        c_state  <= #1 ST_IDLE;
+	        ack_out  <= #1 1'b0;
+	    end
+	  else if (rst | i2c_al)
+	   begin
+	       core_cmd <= #1 `I2C_CMD_NOP;
+	       core_txd <= #1 1'b0;
+	       shift    <= #1 1'b0;
+	       ld       <= #1 1'b0;
+	       cmd_ack  <= #1 1'b0;
+	       c_state  <= #1 ST_IDLE;
+	       ack_out  <= #1 1'b0;
+	   end
+	else
+	  begin
+	      // initially reset all signals
+	      core_txd <= #1 sr[7];
+	      shift    <= #1 1'b0;
+	      ld       <= #1 1'b0;
+	      cmd_ack  <= #1 1'b0;
+
+	      case (c_state) // synopsys full_case parallel_case
+	        ST_IDLE:
+	          if (go)
+	            begin
+	                if (start)
+	                  begin
+	                      c_state  <= #1 ST_START;
+	                      core_cmd <= #1 `I2C_CMD_START;
+	                  end
+	                else if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else if (write)
+	                  begin
+	                      c_state  <= #1 ST_WRITE;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+	                else // stop
+	                  begin
+	                      c_state  <= #1 ST_STOP;
+	                      core_cmd <= #1 `I2C_CMD_STOP;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+
+	        ST_START:
+	          if (core_ack)
+	            begin
+	                if (read)
+	                  begin
+	                      c_state  <= #1 ST_READ;
+	                      core_cmd <= #1 `I2C_CMD_READ;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_WRITE;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+
+	                ld <= #1 1'b1;
+	            end
+
+	        ST_WRITE:
+	          if (core_ack)
+	            if (cnt_done)
+	              begin
+	                  c_state  <= #1 ST_ACK;
+	                  core_cmd <= #1 `I2C_CMD_READ;
+	              end
+	            else
+	              begin
+	                  c_state  <= #1 ST_WRITE;       // stay in same state
+	                  core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
+	                  shift    <= #1 1'b1;
+	              end
+
+	        ST_READ:
+	          if (core_ack)
+	            begin
+	                if (cnt_done)
+	                  begin
+	                      c_state  <= #1 ST_ACK;
+	                      core_cmd <= #1 `I2C_CMD_WRITE;
+	                  end
+	                else
+	                  begin
+	                      c_state  <= #1 ST_READ;       // stay in same state
+	                      core_cmd <= #1 `I2C_CMD_READ; // read next bit
+	                  end
+
+	                shift    <= #1 1'b1;
+	                core_txd <= #1 ack_in;
+	            end
+
+	        ST_ACK:
+	          if (core_ack)
+	            begin
+	               if (stop)
+	                 begin
+	                     c_state  <= #1 ST_STOP;
+	                     core_cmd <= #1 `I2C_CMD_STOP;
+	                 end
+	               else
+	                 begin
+	                     c_state  <= #1 ST_IDLE;
+	                     core_cmd <= #1 `I2C_CMD_NOP;
+
+	                     // generate command acknowledge signal
+	                     cmd_ack  <= #1 1'b1;
+	                 end
+
+	                 // assign ack_out output to bit_controller_rxd (contains last received bit)
+	                 ack_out <= #1 core_rxd;
+
+	                 core_txd <= #1 1'b1;
+	             end
+	           else
+	             core_txd <= #1 ack_in;
+
+	        ST_STOP:
+	          if (core_ack)
+	            begin
+	                c_state  <= #1 ST_IDLE;
+	                core_cmd <= #1 `I2C_CMD_NOP;
+
+	                // generate command acknowledge signal
+	                cmd_ack  <= #1 1'b1;
+	            end
+
+	      endcase
+	  end
+endmodule
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v
new file mode 100644
index 000000000..ee3b694fa
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_defines.v
@@ -0,0 +1,64 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE rev.B2 compliant I2C Master controller defines    ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_defines.v,v 1.3 2001/11/05 11:59:25 rherveille Exp $
+//
+//  $Date: 2001/11/05 11:59:25 $
+//  $Revision: 1.3 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_defines.v,v $
+//               Revision 1.3  2001/11/05 11:59:25  rherveille
+//               Fixed wb_ack_o generation bug.
+//               Fixed bug in the byte_controller statemachine.
+//               Added headers.
+//
+
+
+// I2C registers wishbone addresses
+
+// bitcontroller states
+`define I2C_CMD_NOP   4'b0000
+`define I2C_CMD_START 4'b0001
+`define I2C_CMD_STOP  4'b0010
+`define I2C_CMD_WRITE 4'b0100
+`define I2C_CMD_READ  4'b1000
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v
new file mode 100644
index 000000000..30689bd70
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/i2c_master_top.v
@@ -0,0 +1,301 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  WISHBONE revB.2 compliant I2C Master controller Top-level  ////
+////                                                             ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+////  Downloaded from: http://www.opencores.org/projects/i2c/    ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: i2c_master_top.v,v 1.11 2005/02/27 09:26:24 rherveille Exp $
+//
+//  $Date: 2005/02/27 09:26:24 $
+//  $Revision: 1.11 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: i2c_master_top.v,v $
+//               Revision 1.11  2005/02/27 09:26:24  rherveille
+//               Fixed register overwrite issue.
+//               Removed full_case pragma, replaced it by a default statement.
+//
+//               Revision 1.10  2003/09/01 10:34:38  rherveille
+//               Fix a blocking vs. non-blocking error in the wb_dat output mux.
+//
+//               Revision 1.9  2003/01/09 16:44:45  rherveille
+//               Fixed a bug in the Command Register declaration.
+//
+//               Revision 1.8  2002/12/26 16:05:12  rherveille
+//               Small code simplifications
+//
+//               Revision 1.7  2002/12/26 15:02:32  rherveille
+//               Core is now a Multimaster I2C controller
+//
+//               Revision 1.6  2002/11/30 22:24:40  rherveille
+//               Cleaned up code
+//
+//               Revision 1.5  2001/11/10 10:52:55  rherveille
+//               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
+//
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+`include "i2c_master_defines.v"
+
+module i2c_master_top(
+	wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
+	wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
+	scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
+
+	// parameters
+	parameter ARST_LVL = 1'b0; // asynchronous reset level
+
+	//
+	// inputs & outputs
+	//
+
+	// wishbone signals
+	input        wb_clk_i;     // master clock input
+	input        wb_rst_i;     // synchronous active high reset
+	input        arst_i;       // asynchronous reset
+	input  [2:0] wb_adr_i;     // lower address bits
+	input  [7:0] wb_dat_i;     // databus input
+	output [7:0] wb_dat_o;     // databus output
+	input        wb_we_i;      // write enable input
+	input        wb_stb_i;     // stobe/core select signal
+	input        wb_cyc_i;     // valid bus cycle input
+	output       wb_ack_o;     // bus cycle acknowledge output
+	output       wb_inta_o;    // interrupt request signal output
+
+	reg [7:0] wb_dat_o;
+	reg wb_ack_o;
+	reg wb_inta_o;
+
+	// I2C signals
+	// i2c clock line
+	input  scl_pad_i;       // SCL-line input
+	output scl_pad_o;       // SCL-line output (always 1'b0)
+	output scl_padoen_o;    // SCL-line output enable (active low)
+
+	// i2c data line
+	input  sda_pad_i;       // SDA-line input
+	output sda_pad_o;       // SDA-line output (always 1'b0)
+	output sda_padoen_o;    // SDA-line output enable (active low)
+
+
+	//
+	// variable declarations
+	//
+
+	// registers
+	reg  [15:0] prer; // clock prescale register
+	reg  [ 7:0] ctr;  // control register
+	reg  [ 7:0] txr;  // transmit register
+	wire [ 7:0] rxr;  // receive register
+	reg  [ 7:0] cr;   // command register
+	wire [ 7:0] sr;   // status register
+
+	// done signal: command completed, clear command register
+	wire done;
+
+	// core enable signal
+	wire core_en;
+	wire ien;
+
+	// status register signals
+	wire irxack;
+	reg  rxack;       // received aknowledge from slave
+	reg  tip;         // transfer in progress
+	reg  irq_flag;    // interrupt pending flag
+	wire i2c_busy;    // bus busy (start signal detected)
+	wire i2c_al;      // i2c bus arbitration lost
+	reg  al;          // status register arbitration lost bit
+
+	//
+	// module body
+	//
+
+	// generate internal reset
+	wire rst_i = arst_i ^ ARST_LVL;
+
+	// generate wishbone signals
+	wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
+
+	// generate acknowledge output signal
+	always @(posedge wb_clk_i)
+	  wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
+
+	// assign DAT_O
+	always @(posedge wb_clk_i)
+	begin
+	  case (wb_adr_i) // synopsis parallel_case
+	    3'b000: wb_dat_o <= #1 prer[ 7:0];
+	    3'b001: wb_dat_o <= #1 prer[15:8];
+	    3'b010: wb_dat_o <= #1 ctr;
+	    3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
+	    3'b100: wb_dat_o <= #1 sr;  // write is command register (cr)
+	    3'b101: wb_dat_o <= #1 txr;
+	    3'b110: wb_dat_o <= #1 cr;
+	    3'b111: wb_dat_o <= #1 0;   // reserved
+	  endcase
+	end
+
+	// generate registers
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    begin
+	        prer <= #1 16'hffff;
+	        ctr  <= #1  8'h0;
+	        txr  <= #1  8'h0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        prer <= #1 16'hffff;
+	        ctr  <= #1  8'h0;
+	        txr  <= #1  8'h0;
+	    end
+	  else
+	    if (wb_wacc)
+	      case (wb_adr_i) // synopsis parallel_case
+	         3'b000 : prer [ 7:0] <= #1 wb_dat_i;
+	         3'b001 : prer [15:8] <= #1 wb_dat_i;
+	         3'b010 : ctr         <= #1 wb_dat_i;
+	         3'b011 : txr         <= #1 wb_dat_i;
+	         default: ;
+	      endcase
+
+	// generate command register (special case)
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (~rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_rst_i)
+	    cr <= #1 8'h0;
+	  else if (wb_wacc)
+	    begin
+	        if (core_en & (wb_adr_i == 3'b100) )
+	          cr <= #1 wb_dat_i;
+	    end
+	  else
+	    begin
+	        if (done | i2c_al)
+	          cr[7:4] <= #1 4'h0;           // clear command bits when done
+	                                        // or when aribitration lost
+	        cr[2:1] <= #1 2'b0;             // reserved bits
+	        cr[0]   <= #1 2'b0;             // clear IRQ_ACK bit
+	    end
+
+
+	// decode command register
+	wire sta  = cr[7];
+	wire sto  = cr[6];
+	wire rd   = cr[5];
+	wire wr   = cr[4];
+	wire ack  = cr[3];
+	wire iack = cr[0];
+
+	// decode control register
+	assign core_en = ctr[7];
+	assign ien = ctr[6];
+
+	// hookup byte controller block
+	i2c_master_byte_ctrl byte_controller (
+		.clk      ( wb_clk_i     ),
+		.rst      ( wb_rst_i     ),
+		.nReset   ( rst_i        ),
+		.ena      ( core_en      ),
+		.clk_cnt  ( prer         ),
+		.start    ( sta          ),
+		.stop     ( sto          ),
+		.read     ( rd           ),
+		.write    ( wr           ),
+		.ack_in   ( ack          ),
+		.din      ( txr          ),
+		.cmd_ack  ( done         ),
+		.ack_out  ( irxack       ),
+		.dout     ( rxr          ),
+		.i2c_busy ( i2c_busy     ),
+		.i2c_al   ( i2c_al       ),
+		.scl_i    ( scl_pad_i    ),
+		.scl_o    ( scl_pad_o    ),
+		.scl_oen  ( scl_padoen_o ),
+		.sda_i    ( sda_pad_i    ),
+		.sda_o    ( sda_pad_o    ),
+		.sda_oen  ( sda_padoen_o )
+	);
+
+	// status register block + interrupt request signal
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else if (wb_rst_i)
+	    begin
+	        al       <= #1 1'b0;
+	        rxack    <= #1 1'b0;
+	        tip      <= #1 1'b0;
+	        irq_flag <= #1 1'b0;
+	    end
+	  else
+	    begin
+	        al       <= #1 i2c_al | (al & ~sta);
+	        rxack    <= #1 irxack;
+	        tip      <= #1 (rd | wr);
+	        irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
+	    end
+
+	// generate interrupt request signals
+	always @(posedge wb_clk_i or negedge rst_i)
+	  if (!rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else if (wb_rst_i)
+	    wb_inta_o <= #1 1'b0;
+	  else
+	    wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
+
+	// assign status register bits
+	assign sr[7]   = rxack;
+	assign sr[6]   = i2c_busy;
+	assign sr[5]   = al;
+	assign sr[4:2] = 3'h0; // reserved
+	assign sr[1]   = tip;
+	assign sr[0]   = irq_flag;
+
+endmodule
diff --git a/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v b/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v
new file mode 100644
index 000000000..60d4ecbd1
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/verilog/timescale.v
@@ -0,0 +1,2 @@
+`timescale 1ns / 10ps
+
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Entries b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Entries
new file mode 100644
index 000000000..2a33278f7
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Entries
@@ -0,0 +1,7 @@
+/I2C.VHD/1.1/Mon Sep 24 12:21:51 2001//
+/i2c_master_bit_ctrl.vhd/1.14/Wed Oct 11 12:10:13 2006//
+/i2c_master_byte_ctrl.vhd/1.5/Wed Feb 18 11:41:48 2004//
+/i2c_master_top.vhd/1.7/Sun Mar 14 10:17:03 2004//
+/readme/1.2/Sat Nov 30 22:25:47 2002//
+/tst_ds1621.vhd/1.1/Mon Sep 24 12:21:51 2001//
+D
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Repository b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Repository
new file mode 100644
index 000000000..c210ff4e3
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Repository
@@ -0,0 +1 @@
+i2c/rtl/vhdl
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Root b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Template b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD b/fpga/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD
new file mode 100644
index 000000000..64d1eb656
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/I2C.VHD
@@ -0,0 +1,620 @@
+--
+-- Simple I2C controller
+--
+-- 1) No multimaster
+-- 2) No slave mode
+-- 3) No fifo's
+--
+-- notes:
+-- Every command is acknowledged. Do not set a new command before previous is acknowledged.
+-- Dout is available 1 clock cycle later as cmd_ack
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+package I2C is
+	component simple_i2c is
+	port (
+		clk : in std_logic;
+		ena : in std_logic;
+		nReset : in std_logic;
+
+		clk_cnt : in unsigned(7 downto 0);	-- 4x SCL 
+
+		-- input signals
+		start,
+		stop,
+		read,
+		write,
+		ack_in : std_logic;
+		Din : in std_logic_vector(7 downto 0);
+
+		-- output signals
+		cmd_ack : out std_logic;
+		ack_out : out std_logic;
+		Dout : out std_logic_vector(7 downto 0);
+
+		-- i2c signals
+		SCL : inout std_logic;
+		SDA : inout std_logic
+	);
+	end component simple_i2c;
+end package I2C;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity simple_i2c is
+	port (
+		clk : in std_logic;
+		ena : in std_logic;
+		nReset : in std_logic;
+
+		clk_cnt : in unsigned(7 downto 0);	-- 4x SCL 
+
+		-- input signals
+		start,
+		stop,
+		read,
+		write,
+		ack_in : std_logic;
+		Din : in std_logic_vector(7 downto 0);
+
+		-- output signals
+		cmd_ack : out std_logic;
+		ack_out : out std_logic;
+		Dout : out std_logic_vector(7 downto 0);
+
+		-- i2c signals
+		SCL : inout std_logic;
+		SDA : inout std_logic
+	);
+end entity simple_i2c;
+
+architecture structural of simple_i2c is
+	component i2c_core is
+	port (
+		clk : in std_logic;
+		nReset : in std_logic;
+
+		clk_cnt : in unsigned(7 downto 0);
+
+		cmd : in std_logic_vector(2 downto 0);
+		cmd_ack : out std_logic;
+		busy : out std_logic;
+
+		Din : in std_logic;
+		Dout : out std_logic;
+
+		SCL : inout std_logic;
+		SDA : inout std_logic
+	);
+	end component i2c_core;
+
+	-- commands for i2c_core
+	constant CMD_NOP	: std_logic_vector(2 downto 0) := "000";
+	constant CMD_START	: std_logic_vector(2 downto 0) := "010";
+	constant CMD_STOP	: std_logic_vector(2 downto 0) := "011";
+	constant CMD_READ	: std_logic_vector(2 downto 0) := "100";
+	constant CMD_WRITE	: std_logic_vector(2 downto 0) := "101";
+
+	-- signals for i2c_core
+	signal core_cmd : std_logic_vector(2 downto 0);
+	signal core_ack, core_busy, core_txd, core_rxd : std_logic;
+
+	-- signals for shift register
+	signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
+	signal shift, ld : std_logic;
+
+	-- signals for state machine
+	signal go, host_ack : std_logic;
+begin
+	-- hookup i2c core
+	u1: i2c_core port map (clk, nReset, clk_cnt, core_cmd, core_ack, core_busy, core_txd, core_rxd, SCL, SDA);
+
+	-- generate host-command-acknowledge
+	cmd_ack <= host_ack;
+	
+	-- generate go-signal
+	go <= (read or write) and not host_ack;
+
+	-- assign Dout output to shift-register
+	Dout <= sr;
+
+	-- assign ack_out output to core_rxd (contains last received bit)
+	ack_out <= core_rxd;
+
+	-- generate shift register
+	shift_register: process(clk)
+	begin
+		if (clk'event and clk = '1') then
+			if (ld = '1') then
+				sr <= din;
+			elsif (shift = '1') then
+				sr <= (sr(6 downto 0) & core_rxd);
+			end if;
+		end if;
+	end process shift_register;
+
+	--
+	-- state machine
+	--
+	statemachine : block
+		type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
+		signal state : states;
+		signal dcnt : unsigned(2 downto 0);
+	begin
+		--
+		-- command interpreter, translate complex commands into simpler I2C commands
+		--
+		nxt_state_decoder: process(clk, nReset, state)
+			variable nxt_state : states;
+			variable idcnt : unsigned(2 downto 0);
+			variable ihost_ack : std_logic;
+			variable icore_cmd : std_logic_vector(2 downto 0);
+			variable icore_txd : std_logic;
+			variable ishift, iload : std_logic;
+		begin
+			-- 8 databits (1byte) of data to shift-in/out
+			idcnt := dcnt;
+
+			-- no acknowledge (until command complete)
+			ihost_ack := '0';
+
+			icore_txd := core_txd;
+
+			-- keep current command to i2c_core
+			icore_cmd := core_cmd;
+
+			-- no shifting or loading of shift-register
+			ishift := '0';
+			iload := '0';
+
+			-- keep current state;
+			nxt_state := state;
+			case state is
+				when st_idle =>
+					if (go = '1') then
+						if (start = '1') then
+							nxt_state := st_start;	
+							icore_cmd := CMD_START;
+						elsif (read = '1') then
+							nxt_state := st_read;
+							icore_cmd := CMD_READ;
+							idcnt := "111";
+						else
+							nxt_state := st_write;
+							icore_cmd := CMD_WRITE;
+							idcnt := "111";
+							iload := '1';
+						end if;
+					end if;
+
+				when st_start =>
+					if (core_ack = '1') then
+						if (read = '1') then
+							nxt_state := st_read;
+							icore_cmd := CMD_READ;
+							idcnt := "111";
+						else
+							nxt_state := st_write;
+							icore_cmd := CMD_WRITE;
+							idcnt := "111";
+							iload := '1';
+						end if;
+					end if;
+
+				when st_write =>
+					if (core_ack = '1') then
+						idcnt := dcnt -1;	-- count down Data_counter
+						icore_txd := sr(7);
+						if (dcnt = 0) then
+							nxt_state := st_ack;
+							icore_cmd := CMD_READ;
+						else
+							ishift := '1';
+--							icore_txd := sr(7);
+						end if;
+					end if;			
+
+				when st_read =>
+					if (core_ack = '1') then
+						idcnt := dcnt -1;	-- count down Data_counter
+						ishift := '1';
+						if (dcnt = 0) then
+							nxt_state := st_ack;
+							icore_cmd := CMD_WRITE;
+							icore_txd := ack_in;
+						end if;
+					end if;			
+
+				when st_ack =>
+					if (core_ack = '1') then
+						-- generate command acknowledge signal
+						ihost_ack := '1';
+
+						-- Perform an additional shift, needed for 'read' (store last received bit in shift register)
+						ishift := '1';
+
+						-- check for stop; Should a STOP command be generated ?
+						if (stop = '1') then
+							nxt_state := st_stop;
+							icore_cmd := CMD_STOP;
+						else
+							nxt_state := st_idle;
+							icore_cmd := CMD_NOP;
+						end if;
+					end if;
+
+				when st_stop =>
+					if (core_ack = '1') then
+						nxt_state := st_idle;
+						icore_cmd := CMD_NOP;
+					end if;
+
+				when others => -- illegal states
+					nxt_state := st_idle;
+					icore_cmd := CMD_NOP;
+			end case;
+
+			-- generate registers
+			if (nReset = '0') then
+				core_cmd <= CMD_NOP;
+				core_txd <= '0';
+				
+				shift <= '0';
+				ld <= '0';
+
+				dcnt <= "111";
+				host_ack <= '0';
+
+				state <= st_idle;
+			elsif (clk'event and clk = '1') then
+				if (ena = '1') then
+					state <= nxt_state;
+
+					dcnt <= idcnt;
+					shift <= ishift;
+					ld <= iload;
+
+					core_cmd <= icore_cmd;
+					core_txd <= icore_txd;
+
+					host_ack <= ihost_ack;
+				end if;
+			end if;
+		end process nxt_state_decoder;
+
+	end block statemachine;
+
+end architecture structural;
+
+
+--
+--
+-- I2C Core
+--
+-- Translate simple commands into SCL/SDA transitions
+-- Each command has 5 states, A/B/C/D/idle
+--
+-- start:	SCL	~~~~~~~~~~\____
+--	SDA	~~~~~~~~\______
+--		 x | A | B | C | D | i
+--
+-- repstart	SCL	____/~~~~\___
+--	SDA	__/~~~\______
+--		 x | A | B | C | D | i
+--
+-- stop	SCL	____/~~~~~~~~
+--	SDA	==\____/~~~~~
+--		 x | A | B | C | D | i
+--
+--- write	SCL	____/~~~~\____
+--	SDA	==X=========X=
+--		 x | A | B | C | D | i
+--
+--- read	SCL	____/~~~~\____
+--	SDA	XXXX=====XXXX
+--		 x | A | B | C | D | i
+--
+
+-- Timing:		Normal mode	Fast mode
+-----------------------------------------------------------------
+-- Fscl		100KHz		400KHz
+-- Th_scl		4.0us		0.6us	High period of SCL
+-- Tl_scl		4.7us		1.3us	Low period of SCL
+-- Tsu:sta		4.7us		0.6us	setup time for a repeated start condition
+-- Tsu:sto		4.0us		0.6us	setup time for a stop conditon
+-- Tbuf		4.7us		1.3us	Bus free time between a stop and start condition
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity i2c_core is
+	port (
+		clk : in std_logic;
+		nReset : in std_logic;
+
+		clk_cnt : in unsigned(7 downto 0);
+
+		cmd : in std_logic_vector(2 downto 0);
+		cmd_ack : out std_logic;
+		busy : out std_logic;
+
+		Din : in std_logic;
+		Dout : out std_logic;
+
+		SCL : inout std_logic;
+		SDA : inout std_logic
+	);
+end entity i2c_core;
+
+architecture structural of i2c_core is
+	constant CMD_NOP	: std_logic_vector(2 downto 0) := "000";
+	constant CMD_START	: std_logic_vector(2 downto 0) := "010";
+	constant CMD_STOP	: std_logic_vector(2 downto 0) := "011";
+	constant CMD_READ	: std_logic_vector(2 downto 0) := "100";
+	constant CMD_WRITE	: std_logic_vector(2 downto 0) := "101";
+
+	type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
+	signal state : cmds;
+	signal SDAo, SCLo : std_logic;
+	signal txd : std_logic;
+	signal clk_en, slave_wait :std_logic;
+	signal cnt : unsigned(7 downto 0) := clk_cnt;
+begin
+	-- whenever the slave is not ready it can delay the cycle by pulling SCL low
+	slave_wait <= '1' when ((SCLo = '1') and (SCL = '0')) else '0';
+
+	-- generate clk enable signal
+	gen_clken: process(clk, nReset)
+	begin
+		if (nReset = '0') then
+			cnt <= (others => '0');
+			clk_en <= '1'; --'0';
+		elsif (clk'event and clk = '1') then
+			if (cnt = 0) then
+				clk_en <= '1';
+				cnt <= clk_cnt;
+			else
+				if (slave_wait = '0') then
+					cnt <= cnt -1;
+				end if;
+				clk_en <= '0';
+			end if;
+		end if;
+	end process gen_clken;
+
+	-- generate statemachine
+	nxt_state_decoder : process (clk, nReset, state, cmd, SDA)
+		variable nxt_state : cmds;
+		variable icmd_ack, ibusy, store_sda : std_logic;
+		variable itxd : std_logic;
+	begin
+
+		nxt_state := state;
+
+		icmd_ack := '0'; -- default no acknowledge
+		ibusy := '1'; -- default busy
+
+		store_sda := '0';
+
+		itxd := txd;
+
+		case (state) is
+			-- idle
+			when idle =>
+				case cmd is
+					when CMD_START =>
+						nxt_state := start_a;
+						icmd_ack := '1'; -- command completed
+
+					when CMD_STOP =>
+						nxt_state := stop_a;
+						icmd_ack := '1'; -- command completed
+
+					when CMD_WRITE =>
+						nxt_state := wr_a;
+						icmd_ack := '1'; -- command completed
+						itxd := Din;
+
+					when CMD_READ =>
+						nxt_state := rd_a;
+						icmd_ack := '1'; -- command completed
+
+					when others =>
+						nxt_state := idle;
+-- don't acknowledge NOP command						icmd_ack := '1'; -- command completed
+						ibusy := '0';
+				end case;
+
+			-- start
+			when start_a =>
+				nxt_state := start_b;
+
+			when start_b =>
+				nxt_state := start_c;
+
+			when start_c =>
+				nxt_state := start_d;
+
+			when start_d =>
+				nxt_state := idle;
+				ibusy := '0'; -- not busy when idle
+
+
+			-- stop
+			when stop_a =>
+				nxt_state := stop_b;
+
+			when stop_b =>
+				nxt_state := stop_c;
+
+			when stop_c =>
+--				nxt_state := stop_d;
+
+--			when stop_d =>
+				nxt_state := idle;
+				ibusy := '0'; -- not busy when idle
+
+			-- read
+			when rd_a =>
+				nxt_state := rd_b;
+
+			when rd_b =>
+				nxt_state := rd_c;
+
+			when rd_c =>
+				nxt_state := rd_d;
+				store_sda := '1';
+
+			when rd_d =>
+				nxt_state := idle;
+				ibusy := '0'; -- not busy when idle
+
+			-- write
+			when wr_a =>
+				nxt_state := wr_b;
+
+			when wr_b =>
+				nxt_state := wr_c;
+
+			when wr_c =>
+				nxt_state := wr_d;
+
+			when wr_d =>
+				nxt_state := idle;
+				ibusy := '0'; -- not busy when idle
+
+		end case;
+
+		-- generate regs
+		if (nReset = '0') then
+			state <= idle;
+			cmd_ack <= '0';
+			busy <= '0';
+			txd <= '0';
+			Dout <= '0';
+		elsif (clk'event and clk = '1') then
+			if (clk_en = '1') then
+				state <= nxt_state;
+				busy <= ibusy;
+
+				txd <= itxd;
+				if (store_sda = '1') then
+					Dout <= SDA;
+				end if;
+			end if;
+
+			cmd_ack <= icmd_ack and clk_en;
+		end if;
+	end process nxt_state_decoder;
+
+	--
+	-- convert states to SCL and SDA signals
+	--
+	output_decoder: process (clk, nReset, state)
+		variable iscl, isda : std_logic;
+	begin
+		case (state) is
+			when idle =>
+				iscl := SCLo; -- keep SCL in same state
+				isda := SDA; -- keep SDA in same state
+
+			-- start
+			when start_a =>
+				iscl := SCLo; -- keep SCL in same state (for repeated start)
+				isda := '1'; -- set SDA high
+
+			when start_b =>
+				iscl := '1';	-- set SCL high
+				isda := '1'; -- keep SDA high
+
+			when start_c =>
+				iscl := '1';	-- keep SCL high
+				isda := '0'; -- sel SDA low
+
+			when start_d =>
+				iscl := '0'; -- set SCL low
+				isda := '0'; -- keep SDA low
+
+			-- stop
+			when stop_a =>
+				iscl := '0'; -- keep SCL disabled
+				isda := '0'; -- set SDA low
+
+			when stop_b =>
+				iscl := '1'; -- set SCL high
+				isda := '0'; -- keep SDA low
+
+			when stop_c =>
+				iscl := '1'; -- keep SCL high
+				isda := '1'; -- set SDA high
+
+			-- write
+			when wr_a =>
+				iscl := '0';	-- keep SCL low
+--				isda := txd; -- set SDA
+				isda := Din;
+
+			when wr_b =>
+				iscl := '1';	-- set SCL high
+--				isda := txd; -- set SDA
+				isda := Din;
+
+			when wr_c =>
+				iscl := '1';	-- keep SCL high
+--				isda := txd; -- set SDA
+				isda := Din;
+
+			when wr_d =>
+				iscl := '0'; -- set SCL low
+--				isda := txd; -- set SDA
+				isda := Din;
+
+			-- read
+			when rd_a =>
+				iscl := '0'; -- keep SCL low
+				isda := '1'; -- tri-state SDA
+
+			when rd_b =>
+				iscl := '1'; -- set SCL high
+				isda := '1'; -- tri-state SDA
+
+			when rd_c =>
+				iscl := '1'; -- keep SCL high
+				isda := '1'; -- tri-state SDA
+
+			when rd_d =>
+				iscl := '0'; -- set SCL low
+				isda := '1'; -- tri-state SDA
+		end case;
+
+		-- generate registers
+		if (nReset = '0') then
+			SCLo <= '1';
+			SDAo <= '1';
+		elsif (clk'event and clk = '1') then
+			if (clk_en = '1') then
+				SCLo <= iscl;
+				SDAo <= isda;
+			end if;
+		end if;
+	end process output_decoder;
+
+	SCL <= '0' when (SCLo = '0') else 'Z'; -- since SCL is externally pulled-up convert a '1' to a 'Z'(tri-state)
+	SDA <= '0' when (SDAo = '0') else 'Z'; -- since SDA is externally pulled-up convert a '1' to a 'Z'(tri-state)
+--	SCL <= SCLo;
+--	SDA <= SDAo;
+
+end architecture structural;
+
+
+
+
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
new file mode 100644
index 000000000..1b8eb96d2
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_bit_ctrl.vhd
@@ -0,0 +1,495 @@
+---------------------------------------------------------------------
+----                                                             ----
+----  WISHBONE revB2 I2C Master Core; bit-controller             ----
+----                                                             ----
+----                                                             ----
+----  Author: Richard Herveille                                  ----
+----          richard@asics.ws                                   ----
+----          www.asics.ws                                       ----
+----                                                             ----
+----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
+----                                                             ----
+---------------------------------------------------------------------
+----                                                             ----
+---- Copyright (C) 2000 Richard Herveille                        ----
+----                    richard@asics.ws                         ----
+----                                                             ----
+---- This source file may be used and distributed without        ----
+---- restriction provided that this copyright statement is not   ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer.----
+----                                                             ----
+----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
+---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
+---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
+---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
+---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
+---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
+---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
+---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
+---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
+---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
+---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
+---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
+---- POSSIBILITY OF SUCH DAMAGE.                                 ----
+----                                                             ----
+---------------------------------------------------------------------
+
+--  CVS Log
+--
+--  $Id: i2c_master_bit_ctrl.vhd,v 1.14 2006/10/11 12:10:13 rherveille Exp $
+--
+--  $Date: 2006/10/11 12:10:13 $
+--  $Revision: 1.14 $
+--  $Author: rherveille $
+--  $Locker:  $
+--  $State: Exp $
+--
+-- Change History:
+--               $Log: i2c_master_bit_ctrl.vhd,v $
+--               Revision 1.14  2006/10/11 12:10:13  rherveille
+--               Added missing semicolons ';' on endif
+--
+--               Revision 1.13  2006/10/06 10:48:24  rherveille
+--               fixed short scl high pulse after clock stretch
+--
+--               Revision 1.12  2004/05/07 11:53:31  rherveille
+--               Fixed previous fix :) Made a variable vs signal mistake.
+--
+--               Revision 1.11  2004/05/07 11:04:00  rherveille
+--               Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.
+--
+--               Revision 1.10  2004/02/27 07:49:43  rherveille
+--               Fixed a bug in the arbitration-lost signal generation. VHDL version only.
+--
+--               Revision 1.9  2003/08/12 14:48:37  rherveille
+--               Forgot an 'end if' :-/
+--
+--               Revision 1.8  2003/08/09 07:01:13  rherveille
+--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+--               Fixed a potential bug in the byte controller's host-acknowledge generation.
+--
+--               Revision 1.7  2003/02/05 00:06:02  rherveille
+--               Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.
+--
+--               Revision 1.6  2003/02/01 02:03:06  rherveille
+--               Fixed a few 'arbitration lost' bugs. VHDL version only.
+--
+--               Revision 1.5  2002/12/26 16:05:47  rherveille
+--               Core is now a Multimaster I2C controller.
+--
+--               Revision 1.4  2002/11/30 22:24:37  rherveille
+--               Cleaned up code
+--
+--               Revision 1.3  2002/10/30 18:09:53  rherveille
+--               Fixed some reported minor start/stop generation timing issuess.
+--
+--               Revision 1.2  2002/06/15 07:37:04  rherveille
+--               Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.
+--
+--               Revision 1.1  2001/11/05 12:02:33  rherveille
+--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
+--               Code updated, is now up-to-date to doc. rev.0.4.
+--               Added headers.
+--
+
+
+--
+-------------------------------------
+-- Bit controller section
+------------------------------------
+--
+-- Translate simple commands into SCL/SDA transitions
+-- Each command has 5 states, A/B/C/D/idle
+--
+-- start:    SCL  ~~~~~~~~~~~~~~\____
+--	     SDA  XX/~~~~~~~\______
+--	          x | A | B | C | D | i
+--
+-- repstart  SCL  ______/~~~~~~~\___
+--	     SDA  __/~~~~~~~\______
+--	          x | A | B | C | D | i
+--
+-- stop      SCL  _______/~~~~~~~~~~~
+--	     SDA  ==\___________/~~~~~
+--	          x | A | B | C | D | i
+--
+--- write    SCL  ______/~~~~~~~\____
+--	     SDA  XXX===============XX
+--	          x | A | B | C | D | i
+--
+--- read     SCL  ______/~~~~~~~\____
+--	     SDA  XXXXXXX=XXXXXXXXXXX
+--	          x | A | B | C | D | i
+--
+
+-- Timing:      Normal mode     Fast mode
+-----------------------------------------------------------------
+-- Fscl         100KHz          400KHz
+-- Th_scl       4.0us           0.6us   High period of SCL
+-- Tl_scl       4.7us           1.3us   Low period of SCL
+-- Tsu:sta      4.7us           0.6us   setup time for a repeated start condition
+-- Tsu:sto      4.0us           0.6us   setup time for a stop conditon
+-- Tbuf         4.7us           1.3us   Bus free time between a stop and start condition
+--
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity i2c_master_bit_ctrl is
+	port (
+		clk    : in std_logic;
+		rst    : in std_logic;
+		nReset : in std_logic;
+		ena    : in std_logic;				-- core enable signal
+
+		clk_cnt : in unsigned(15 downto 0);		-- clock prescale value
+
+		cmd     : in std_logic_vector(3 downto 0);
+		cmd_ack : out std_logic; -- command completed
+		busy    : out std_logic; -- i2c bus busy
+		al      : out std_logic; -- arbitration lost
+
+		din  : in std_logic;
+		dout : out std_logic;
+
+		-- i2c lines
+		scl_i   : in std_logic;  -- i2c clock line input
+		scl_o   : out std_logic; -- i2c clock line output
+		scl_oen : out std_logic; -- i2c clock line output enable, active low
+		sda_i   : in std_logic;  -- i2c data line input
+		sda_o   : out std_logic; -- i2c data line output
+		sda_oen : out std_logic  -- i2c data line output enable, active low
+	);
+end entity i2c_master_bit_ctrl;
+
+architecture structural of i2c_master_bit_ctrl is
+	constant I2C_CMD_NOP    : std_logic_vector(3 downto 0) := "0000";
+	constant I2C_CMD_START  : std_logic_vector(3 downto 0) := "0001";
+	constant I2C_CMD_STOP   : std_logic_vector(3 downto 0) := "0010";
+	constant I2C_CMD_READ   : std_logic_vector(3 downto 0) := "0100";
+	constant I2C_CMD_WRITE  : std_logic_vector(3 downto 0) := "1000";
+
+	type states is (idle, start_a, start_b, start_c, start_d, start_e,
+	                stop_a, stop_b, stop_c, stop_d, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
+	signal c_state : states;
+
+	signal iscl_oen, isda_oen : std_logic;          -- internal I2C lines
+	signal sda_chk            : std_logic;          -- check SDA status (multi-master arbitration)
+	signal dscl_oen           : std_logic;          -- delayed scl_oen signals
+	signal sSCL, sSDA         : std_logic;          -- synchronized SCL and SDA inputs
+	signal clk_en, slave_wait : std_logic;          -- clock generation signals
+	signal ial                : std_logic;          -- internal arbitration lost signal
+--	signal cnt : unsigned(15 downto 0) := clk_cnt;  -- clock divider counter (simulation)
+	signal cnt : unsigned(15 downto 0);             -- clock divider counter (synthesis)
+
+begin
+	-- whenever the slave is not ready it can delay the cycle by pulling SCL low
+	-- delay scl_oen
+	process (clk)
+	begin
+	    if (clk'event and clk = '1') then
+	      dscl_oen <= iscl_oen;
+	    end if;
+	end process;
+	slave_wait <= dscl_oen and not sSCL;
+
+	-- generate clk enable signal
+	gen_clken: process(clk, nReset)
+	begin
+	    if (nReset = '0') then
+	      cnt    <= (others => '0');
+	      clk_en <= '1';
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1') then
+	        cnt    <= (others => '0');
+	        clk_en <= '1';
+	      elsif ( (cnt = 0) or (ena = '0') ) then
+	        cnt    <= clk_cnt;
+	        clk_en <= '1';
+	      elsif (slave_wait = '1') then
+	        cnt    <= cnt;
+	        clk_en <= '0';
+	      else
+	        cnt    <= cnt -1;
+	        clk_en <= '0';
+	      end if;
+	    end if;
+	end process gen_clken;
+
+
+	-- generate bus status controller
+	bus_status_ctrl: block
+	  signal dSCL, dSDA          : std_logic;  -- delayes sSCL and sSDA
+	  signal sta_condition       : std_logic;  -- start detected
+	  signal sto_condition       : std_logic;  -- stop detected
+	  signal cmd_stop            : std_logic;  -- STOP command
+	  signal ibusy               : std_logic;  -- internal busy signal
+	begin
+	    -- synchronize SCL and SDA inputs
+	    synch_scl_sda: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          sSCL <= '1';
+	          sSDA <= '1';
+
+	          dSCL <= '1';
+	          dSDA <= '1';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1') then
+	            sSCL <= '1';
+	            sSDA <= '1';
+
+	            dSCL <= '1';
+	            dSDA <= '1';
+	          else
+	            sSCL <= scl_i;
+	            sSDA <= sda_i;
+
+	            dSCL <= sSCL;
+	            dSDA <= sSDA;
+	          end if;
+	        end if;
+	    end process synch_SCL_SDA;
+
+	    -- detect start condition => detect falling edge on SDA while SCL is high
+	    -- detect stop condition  => detect rising edge on SDA while SCL is high
+	    detect_sta_sto: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          sta_condition <= '0';
+	          sto_condition <= '0';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1') then
+	            sta_condition <= '0';
+	            sto_condition <= '0';
+	          else
+	            sta_condition <= (not sSDA and dSDA) and sSCL;
+	            sto_condition <= (sSDA and not dSDA) and sSCL;
+	          end if;
+	        end if;
+	    end process detect_sta_sto;
+
+	    -- generate i2c-bus busy signal
+	    gen_busy: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          ibusy <= '0';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1') then
+	            ibusy <= '0';
+	          else
+	            ibusy <= (sta_condition or ibusy) and not sto_condition;
+	          end if;
+	        end if;
+	    end process gen_busy;
+	    busy <= ibusy;
+
+
+	    -- generate arbitration lost signal
+	    -- aribitration lost when:
+	    -- 1) master drives SDA high, but the i2c bus is low
+	    -- 2) stop detected while not requested (detect during 'idle' state)
+	    gen_al: process(clk, nReset)
+	    begin
+	      if (nReset = '0') then
+	        cmd_stop  <= '0';
+	        ial       <= '0';
+	      elsif (clk'event and clk = '1') then
+	        if (rst = '1') then
+	          cmd_stop  <= '0';
+	          ial       <= '0';
+	        else
+	          if (clk_en = '1') then
+	            if (cmd = I2C_CMD_STOP) then
+	              cmd_stop <= '1';
+	            else
+	              cmd_stop <= '0';
+	            end if;
+	          end if;
+
+	          if (c_state = idle) then
+	            ial <= (sda_chk and not sSDA and isda_oen);
+	          else
+	            ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
+	          end if;
+
+	        end if;
+	      end if;
+	    end process gen_al;
+	    al <= ial;
+
+	    -- generate dout signal, store dout on rising edge of SCL
+	    gen_dout: process(clk)
+	    begin
+	      if (clk'event and clk = '1') then
+	        if (sSCL = '1' and dSCL = '0') then
+	          dout <= sSDA;
+	        end if;
+	      end if;
+	    end process gen_dout;
+	end block bus_status_ctrl;
+
+
+	-- generate statemachine
+	nxt_state_decoder : process (clk, nReset, c_state, cmd)
+	begin
+	    if (nReset = '0') then
+	      c_state  <= idle;
+	      cmd_ack  <= '0';
+	      iscl_oen <= '1';
+	      isda_oen <= '1';
+	      sda_chk  <= '0';
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1' or ial = '1') then
+	        c_state  <= idle;
+	        cmd_ack  <= '0';
+	        iscl_oen <= '1';
+	        isda_oen <= '1';
+	        sda_chk  <= '0';
+	      else
+	        cmd_ack <= '0'; -- default no acknowledge
+
+	        if (clk_en = '1') then
+	          case (c_state) is
+	             -- idle
+	             when idle =>
+	                case cmd is
+	                  when I2C_CMD_START => c_state <= start_a;
+	                  when I2C_CMD_STOP  => c_state <= stop_a;
+	                  when I2C_CMD_WRITE => c_state <= wr_a;
+	                  when I2C_CMD_READ  => c_state <= rd_a;
+	                  when others        => c_state <= idle; -- NOP command
+	                end case;
+
+	                iscl_oen <= iscl_oen; -- keep SCL in same state
+	                isda_oen <= isda_oen; -- keep SDA in same state
+	                sda_chk  <= '0';      -- don't check SDA
+
+	             -- start
+	             when start_a =>
+	                c_state  <= start_b;
+	                iscl_oen <= iscl_oen; -- keep SCL in same state (for repeated start)
+	                isda_oen <= '1';      -- set SDA high
+	                sda_chk  <= '0';      -- don't check SDA
+
+	             when start_b =>
+	                c_state  <= start_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= '1'; -- keep SDA high
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when start_c =>
+	                c_state  <= start_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '0'; -- set SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when start_d =>
+	                c_state  <= start_e;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when start_e =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '0'; -- set SCL low
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             -- stop
+	             when stop_a =>
+	                c_state  <= stop_b;
+	                iscl_oen <= '0'; -- keep SCL low
+	                isda_oen <= '0'; -- set SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when stop_b =>
+	                c_state  <= stop_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when stop_c =>
+	                c_state  <= stop_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '0'; -- keep SDA low
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when stop_d =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '1'; -- set SDA high
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             -- read
+	             when rd_a =>
+	                c_state  <= rd_b;
+	                iscl_oen <= '0'; -- keep SCL low
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when rd_b =>
+	                c_state  <= rd_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when rd_c =>
+	                c_state  <= rd_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             when rd_d =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '0'; -- set SCL low
+	                isda_oen <= '1'; -- tri-state SDA
+	                sda_chk  <= '0'; -- don't check SDA
+
+	             -- write
+	             when wr_a =>
+	                c_state  <= wr_b;
+	                iscl_oen <= '0'; -- keep SCL low
+	                isda_oen <= din; -- set SDA
+	                sda_chk  <= '0'; -- don't check SDA (SCL low)
+
+	             when wr_b =>
+	                c_state  <= wr_c;
+	                iscl_oen <= '1'; -- set SCL high
+	                isda_oen <= din; -- keep SDA
+	                sda_chk  <= '1'; -- check SDA
+
+	             when wr_c =>
+	                c_state  <= wr_d;
+	                iscl_oen <= '1'; -- keep SCL high
+	                isda_oen <= din; -- keep SDA
+	                sda_chk  <= '1'; -- check SDA
+
+	             when wr_d =>
+	                c_state  <= idle;
+	                cmd_ack  <= '1'; -- command completed
+	                iscl_oen <= '0'; -- set SCL low
+	                isda_oen <= din; -- keep SDA
+	                sda_chk  <= '0'; -- don't check SDA (SCL low)
+
+	             when others =>
+
+	          end case;
+	        end if;
+	      end if;
+	    end if;
+	end process nxt_state_decoder;
+
+
+	-- assign outputs
+	scl_o   <= '0';
+	scl_oen <= iscl_oen;
+	sda_o   <= '0';
+	sda_oen <= isda_oen;
+end architecture structural;
+
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
new file mode 100644
index 000000000..bdb2a881e
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_byte_ctrl.vhd
@@ -0,0 +1,370 @@
+---------------------------------------------------------------------
+----                                                             ----
+----  WISHBONE revB2 compl. I2C Master Core; byte-controller     ----
+----                                                             ----
+----                                                             ----
+----  Author: Richard Herveille                                  ----
+----          richard@asics.ws                                   ----
+----          www.asics.ws                                       ----
+----                                                             ----
+----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
+----                                                             ----
+---------------------------------------------------------------------
+----                                                             ----
+---- Copyright (C) 2000 Richard Herveille                        ----
+----                    richard@asics.ws                         ----
+----                                                             ----
+---- This source file may be used and distributed without        ----
+---- restriction provided that this copyright statement is not   ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer.----
+----                                                             ----
+----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
+---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
+---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
+---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
+---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
+---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
+---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
+---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
+---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
+---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
+---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
+---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
+---- POSSIBILITY OF SUCH DAMAGE.                                 ----
+----                                                             ----
+---------------------------------------------------------------------
+
+--  CVS Log
+--
+--  $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
+--
+--  $Date: 2004/02/18 11:41:48 $
+--  $Revision: 1.5 $
+--  $Author: rherveille $
+--  $Locker:  $
+--  $State: Exp $
+--
+-- Change History:
+--               $Log: i2c_master_byte_ctrl.vhd,v $
+--               Revision 1.5  2004/02/18 11:41:48  rherveille
+--               Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
+--
+--               Revision 1.4  2003/08/09 07:01:13  rherveille
+--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+--               Fixed a potential bug in the byte controller's host-acknowledge generation.
+--
+--               Revision 1.3  2002/12/26 16:05:47  rherveille
+--               Core is now a Multimaster I2C controller.
+--
+--               Revision 1.2  2002/11/30 22:24:37  rherveille
+--               Cleaned up code
+--
+--               Revision 1.1  2001/11/05 12:02:33  rherveille
+--               Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
+--               Code updated, is now up-to-date to doc. rev.0.4.
+--               Added headers.
+--
+
+
+
+
+--
+------------------------------------------
+-- Byte controller section
+------------------------------------------
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity i2c_master_byte_ctrl is
+	port (
+		clk    : in std_logic;
+		rst    : in std_logic; -- synchronous active high reset (WISHBONE compatible)
+		nReset : in std_logic;	-- asynchornous active low reset (FPGA compatible)
+		ena    : in std_logic; -- core enable signal
+
+		clk_cnt : in unsigned(15 downto 0);	-- 4x SCL
+
+		-- input signals
+		start,
+		stop,
+		read,
+		write,
+		ack_in : std_logic;
+		din    : in std_logic_vector(7 downto 0);
+
+		-- output signals
+		cmd_ack  : out std_logic; -- command done
+		ack_out  : out std_logic;
+		i2c_busy : out std_logic; -- arbitration lost
+		i2c_al   : out std_logic; -- i2c bus busy
+		dout     : out std_logic_vector(7 downto 0);
+
+		-- i2c lines
+		scl_i   : in std_logic;  -- i2c clock line input
+		scl_o   : out std_logic; -- i2c clock line output
+		scl_oen : out std_logic; -- i2c clock line output enable, active low
+		sda_i   : in std_logic;  -- i2c data line input
+		sda_o   : out std_logic; -- i2c data line output
+		sda_oen : out std_logic  -- i2c data line output enable, active low
+	);
+end entity i2c_master_byte_ctrl;
+
+architecture structural of i2c_master_byte_ctrl is
+	component i2c_master_bit_ctrl is
+	port (
+		clk    : in std_logic;
+		rst    : in std_logic;
+		nReset : in std_logic;
+		ena    : in std_logic;				-- core enable signal
+
+		clk_cnt : in unsigned(15 downto 0);		-- clock prescale value
+
+		cmd     : in std_logic_vector(3 downto 0);
+		cmd_ack : out std_logic; -- command done
+		busy    : out std_logic; -- i2c bus busy
+		al      : out std_logic; -- arbitration lost
+
+		din  : in std_logic;
+		dout : out std_logic;
+
+		-- i2c lines
+		scl_i   : in std_logic;  -- i2c clock line input
+		scl_o   : out std_logic; -- i2c clock line output
+		scl_oen : out std_logic; -- i2c clock line output enable, active low
+		sda_i   : in std_logic;  -- i2c data line input
+		sda_o   : out std_logic; -- i2c data line output
+		sda_oen : out std_logic  -- i2c data line output enable, active low
+	);
+	end component i2c_master_bit_ctrl;
+
+	-- commands for bit_controller block
+	constant I2C_CMD_NOP  	: std_logic_vector(3 downto 0) := "0000";
+	constant I2C_CMD_START	: std_logic_vector(3 downto 0) := "0001";
+	constant I2C_CMD_STOP	 : std_logic_vector(3 downto 0) := "0010";
+	constant I2C_CMD_READ	 : std_logic_vector(3 downto 0) := "0100";
+	constant I2C_CMD_WRITE	: std_logic_vector(3 downto 0) := "1000";
+
+	-- signals for bit_controller
+	signal core_cmd : std_logic_vector(3 downto 0);
+	signal core_ack, core_txd, core_rxd : std_logic;
+	signal al : std_logic;
+
+	-- signals for shift register
+	signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
+	signal shift, ld : std_logic;
+
+	-- signals for state machine
+	signal go, host_ack : std_logic;
+	signal dcnt : unsigned(2 downto 0); -- data counter
+	signal cnt_done : std_logic;
+
+begin
+	-- hookup bit_controller
+	bit_ctrl: i2c_master_bit_ctrl port map(
+		clk     => clk,
+		rst     => rst,
+		nReset  => nReset,
+		ena     => ena,
+		clk_cnt => clk_cnt,
+		cmd     => core_cmd,
+		cmd_ack => core_ack,
+		busy    => i2c_busy,
+		al      => al,
+		din     => core_txd,
+		dout    => core_rxd,
+		scl_i   => scl_i,
+		scl_o   => scl_o,
+		scl_oen => scl_oen,
+		sda_i   => sda_i,
+		sda_o   => sda_o,
+		sda_oen => sda_oen
+	);
+	i2c_al <= al;
+
+	-- generate host-command-acknowledge
+	cmd_ack <= host_ack;
+
+	-- generate go-signal
+	go <= (read or write or stop) and not host_ack;
+
+	-- assign Dout output to shift-register
+	dout <= sr;
+
+	-- generate shift register
+	shift_register: process(clk, nReset)
+	begin
+	    if (nReset = '0') then
+	      sr <= (others => '0');
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1') then
+	        sr <= (others => '0');
+	      elsif (ld = '1') then
+	        sr <= din;
+	      elsif (shift = '1') then
+	        sr <= (sr(6 downto 0) & core_rxd);
+	      end if;
+	    end if;
+	end process shift_register;
+
+	-- generate data-counter
+	data_cnt: process(clk, nReset)
+	begin
+	    if (nReset = '0') then
+	      dcnt <= (others => '0');
+	    elsif (clk'event and clk = '1') then
+	      if (rst = '1') then
+	        dcnt <= (others => '0');
+	      elsif (ld = '1') then
+	        dcnt <= (others => '1');  -- load counter with 7
+	      elsif (shift = '1') then
+	        dcnt <= dcnt -1;
+	      end if;
+	    end if;
+	end process data_cnt;
+
+	cnt_done <= '1' when (dcnt = 0) else '0';
+
+	--
+	-- state machine
+	--
+	statemachine : block
+	    type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
+	    signal c_state : states;
+	begin
+	    --
+	    -- command interpreter, translate complex commands into simpler I2C commands
+	    --
+	    nxt_state_decoder: process(clk, nReset)
+	    begin
+	        if (nReset = '0') then
+	          core_cmd <= I2C_CMD_NOP;
+	          core_txd <= '0';
+	          shift    <= '0';
+	          ld       <= '0';
+	          host_ack <= '0';
+	          c_state  <= st_idle;
+	          ack_out  <= '0';
+	        elsif (clk'event and clk = '1') then
+	          if (rst = '1' or al = '1') then
+	            core_cmd <= I2C_CMD_NOP;
+	            core_txd <= '0';
+	            shift    <= '0';
+	            ld       <= '0';
+	            host_ack <= '0';
+	            c_state  <= st_idle;
+	            ack_out  <= '0';
+	          else
+	            -- initialy reset all signal
+	            core_txd <= sr(7);
+	            shift    <= '0';
+	            ld       <= '0';
+	            host_ack <= '0';
+
+	            case c_state is
+	              when st_idle =>
+	                 if (go = '1') then
+	                   if (start = '1') then
+	                     c_state  <= st_start;
+	                     core_cmd <= I2C_CMD_START;
+	                   elsif (read = '1') then
+	                     c_state  <= st_read;
+	                     core_cmd <= I2C_CMD_READ;
+	                   elsif (write = '1') then
+	                     c_state  <= st_write;
+	                     core_cmd <= I2C_CMD_WRITE;
+	                   else -- stop
+	                     c_state  <= st_stop;
+	                     core_cmd <= I2C_CMD_STOP;
+	                   end if;
+
+	                   ld <= '1';
+	                 end if;
+
+	              when st_start =>
+	                 if (core_ack = '1') then
+	                   if (read = '1') then
+	                     c_state  <= st_read;
+	                     core_cmd <= I2C_CMD_READ;
+	                   else
+	                     c_state  <= st_write;
+	                     core_cmd <= I2C_CMD_WRITE;
+	                   end if;
+
+	                   ld <= '1';
+	                 end if;
+
+	              when st_write =>
+	                 if (core_ack = '1') then
+	                   if (cnt_done = '1') then
+	                     c_state  <= st_ack;
+	                     core_cmd <= I2C_CMD_READ;
+	                   else
+	                     c_state  <= st_write;       -- stay in same state
+	                     core_cmd <= I2C_CMD_WRITE;  -- write next bit
+	                     shift    <= '1';
+	                   end if;
+	                 end if;
+
+	              when st_read =>
+	                 if (core_ack = '1') then
+	                   if (cnt_done = '1') then
+	                     c_state  <= st_ack;
+	                     core_cmd <= I2C_CMD_WRITE;
+	                   else
+	                     c_state  <= st_read;      -- stay in same state
+	                     core_cmd <= I2C_CMD_READ; -- read next bit
+	                   end if;
+
+	                   shift    <= '1';
+	                   core_txd <= ack_in;
+	                 end if;
+
+	              when st_ack =>
+	                 if (core_ack = '1') then
+	                   -- check for stop; Should a STOP command be generated ?
+	                   if (stop = '1') then
+	                     c_state  <= st_stop;
+	                     core_cmd <= I2C_CMD_STOP;
+	                   else
+	                     c_state  <= st_idle;
+	                     core_cmd <= I2C_CMD_NOP;
+
+	                     -- generate command acknowledge signal
+	                     host_ack <= '1';
+	                   end if;
+
+	                   -- assign ack_out output to core_rxd (contains last received bit)
+	                   ack_out  <= core_rxd;
+
+	                   core_txd <= '1';
+	                 else
+	                   core_txd <= ack_in;
+	                 end if;
+
+	              when st_stop =>
+	                 if (core_ack = '1') then
+	                   c_state  <= st_idle;
+	                   core_cmd <= I2C_CMD_NOP;
+
+	                   -- generate command acknowledge signal
+	                   host_ack <= '1';
+	                 end if;
+
+	              when others => -- illegal states
+	                 c_state  <= st_idle;
+	                 core_cmd <= I2C_CMD_NOP;
+	                 report ("Byte controller entered illegal state.");
+
+	            end case;
+
+	          end if;
+	        end if;
+	    end process nxt_state_decoder;
+
+	end block statemachine;
+
+end architecture structural;
+
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd
new file mode 100644
index 000000000..a2557120f
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/i2c_master_top.vhd
@@ -0,0 +1,359 @@
+---------------------------------------------------------------------
+----                                                             ----
+----  WISHBONE revB2 compl. I2C Master Core; top level           ----
+----                                                             ----
+----                                                             ----
+----  Author: Richard Herveille                                  ----
+----          richard@asics.ws                                   ----
+----          www.asics.ws                                       ----
+----                                                             ----
+----  Downloaded from: http://www.opencores.org/projects/i2c/    ----
+----                                                             ----
+---------------------------------------------------------------------
+----                                                             ----
+---- Copyright (C) 2000 Richard Herveille                        ----
+----                    richard@asics.ws                         ----
+----                                                             ----
+---- This source file may be used and distributed without        ----
+---- restriction provided that this copyright statement is not   ----
+---- removed from the file and that any derivative work contains ----
+---- the original copyright notice and the associated disclaimer.----
+----                                                             ----
+----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
+---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
+---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
+---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
+---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
+---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
+---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
+---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
+---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
+---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
+---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
+---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
+---- POSSIBILITY OF SUCH DAMAGE.                                 ----
+----                                                             ----
+---------------------------------------------------------------------
+
+--  CVS Log
+--
+--  $Id: i2c_master_top.vhd,v 1.7 2004/03/14 10:17:03 rherveille Exp $
+--
+--  $Date: 2004/03/14 10:17:03 $
+--  $Revision: 1.7 $
+--  $Author: rherveille $
+--  $Locker:  $
+--  $State: Exp $
+--
+-- Change History:
+--               $Log: i2c_master_top.vhd,v $
+--               Revision 1.7  2004/03/14 10:17:03  rherveille
+--               Fixed simulation issue when writing to CR register
+--
+--               Revision 1.6  2003/08/09 07:01:13  rherveille
+--               Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
+--               Fixed a potential bug in the byte controller's host-acknowledge generation.
+--
+--               Revision 1.5  2003/02/01 02:03:06  rherveille
+--               Fixed a few 'arbitration lost' bugs. VHDL version only.
+--
+--               Revision 1.4  2002/12/26 16:05:47  rherveille
+--               Core is now a Multimaster I2C controller.
+--
+--               Revision 1.3  2002/11/30 22:24:37  rherveille
+--               Cleaned up code
+--
+--               Revision 1.2  2001/11/10 10:52:44  rherveille
+--               Changed PRER reset value from 0x0000 to 0xffff, conform specs.
+--
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity i2c_master_top is
+	generic(
+		ARST_LVL : std_logic := '0'                   -- asynchronous reset level
+	);
+	port (
+		-- wishbone signals
+		wb_clk_i  : in  std_logic;                    -- master clock input
+		wb_rst_i  : in  std_logic := '0';             -- synchronous active high reset
+		arst_i    : in  std_logic := not ARST_LVL;    -- asynchronous reset
+		wb_adr_i  : in  unsigned(2 downto 0);         -- lower address bits
+		wb_dat_i  : in  std_logic_vector(7 downto 0); -- Databus input
+		wb_dat_o  : out std_logic_vector(7 downto 0); -- Databus output
+		wb_we_i   : in  std_logic;	              -- Write enable input
+		wb_stb_i  : in  std_logic;                    -- Strobe signals / core select signal
+		wb_cyc_i  : in  std_logic;	              -- Valid bus cycle input
+		wb_ack_o  : out std_logic;                    -- Bus cycle acknowledge output
+		wb_inta_o : out std_logic;                    -- interrupt request output signal
+
+		-- i2c lines
+		scl_pad_i     : in  std_logic;                -- i2c clock line input
+		scl_pad_o     : out std_logic;                -- i2c clock line output
+		scl_padoen_o  : out std_logic;                -- i2c clock line output enable, active low
+		sda_pad_i     : in  std_logic;                -- i2c data line input
+		sda_pad_o     : out std_logic;                -- i2c data line output
+		sda_padoen_o  : out std_logic                 -- i2c data line output enable, active low
+	);
+end entity i2c_master_top;
+
+architecture structural of i2c_master_top is
+	component i2c_master_byte_ctrl is
+	port (
+		clk    : in std_logic;
+		rst    : in std_logic; -- synchronous active high reset (WISHBONE compatible)
+		nReset : in std_logic;	-- asynchornous active low reset (FPGA compatible)
+		ena    : in std_logic; -- core enable signal
+
+		clk_cnt : in unsigned(15 downto 0);	-- 4x SCL
+
+		-- input signals
+		start,
+		stop,
+		read,
+		write,
+		ack_in : std_logic;
+		din    : in std_logic_vector(7 downto 0);
+
+		-- output signals
+		cmd_ack  : out std_logic;
+		ack_out  : out std_logic;
+		i2c_busy : out std_logic;
+		i2c_al   : out std_logic;
+		dout     : out std_logic_vector(7 downto 0);
+
+		-- i2c lines
+		scl_i   : in std_logic;  -- i2c clock line input
+		scl_o   : out std_logic; -- i2c clock line output
+		scl_oen : out std_logic; -- i2c clock line output enable, active low
+		sda_i   : in std_logic;  -- i2c data line input
+		sda_o   : out std_logic; -- i2c data line output
+		sda_oen : out std_logic  -- i2c data line output enable, active low
+	);
+	end component i2c_master_byte_ctrl;
+
+	-- registers
+	signal prer : unsigned(15 downto 0);             -- clock prescale register
+	signal ctr  : std_logic_vector(7 downto 0);      -- control register
+	signal txr  : std_logic_vector(7 downto 0);      -- transmit register
+	signal rxr  : std_logic_vector(7 downto 0);      -- receive register
+	signal cr   : std_logic_vector(7 downto 0);      -- command register
+	signal sr   : std_logic_vector(7 downto 0);      -- status register
+
+	-- internal reset signal
+	signal rst_i : std_logic;
+
+	-- wishbone write access
+	signal wb_wacc : std_logic;
+
+	-- internal acknowledge signal
+	signal iack_o : std_logic;
+
+	-- done signal: command completed, clear command register
+	signal done : std_logic;
+
+	-- command register signals
+	signal sta, sto, rd, wr, ack, iack : std_logic;
+
+	signal core_en : std_logic;                      -- core enable signal
+	signal ien     : std_logic;                      -- interrupt enable signal
+
+	-- status register signals
+	signal irxack, rxack : std_logic;                -- received aknowledge from slave
+	signal tip           : std_logic;                -- transfer in progress
+	signal irq_flag      : std_logic;                -- interrupt pending flag
+	signal i2c_busy      : std_logic;                -- i2c bus busy (start signal detected)
+	signal i2c_al, al    : std_logic;                -- arbitration lost
+
+begin
+	-- generate internal reset signal
+	rst_i <= arst_i xor ARST_LVL;
+
+	-- generate acknowledge output signal
+	gen_ack_o : process(wb_clk_i)
+	begin
+	    if (wb_clk_i'event and wb_clk_i = '1') then
+	      iack_o <= wb_cyc_i and wb_stb_i and not iack_o;         -- because timing is always honored
+	    end if;
+	end process gen_ack_o;
+	wb_ack_o <= iack_o;
+	
+	
+	-- generate wishbone write access signal
+	wb_wacc <= wb_cyc_i and wb_stb_i and wb_we_i;
+
+	-- assign wb_dat_o
+	assign_dato : process(wb_clk_i)
+	begin
+	    if (wb_clk_i'event and wb_clk_i = '1') then
+	      case wb_adr_i is
+	        when "000"  => wb_dat_o <= std_logic_vector(prer( 7 downto 0));
+	        when "001"  => wb_dat_o <= std_logic_vector(prer(15 downto 8));
+	        when "010"  => wb_dat_o <= ctr;
+	        when "011"  => wb_dat_o <= rxr; -- write is transmit register TxR
+	        when "100"  => wb_dat_o <= sr;  -- write is command register CR
+
+	        -- Debugging registers:
+	        -- These registers are not documented.
+	        -- Functionality could change in future releases
+	        when "101"  => wb_dat_o <= txr;
+	        when "110"  => wb_dat_o <= cr;
+	        when "111"  => wb_dat_o <= (others => '0');
+	        when others => wb_dat_o <= (others => 'X');	-- for simulation only
+	      end case;
+	    end if;
+	end process assign_dato;
+
+
+	-- generate registers (CR, SR see below)
+	gen_regs: process(rst_i, wb_clk_i)
+	begin
+	    if (rst_i = '0') then
+	      prer <= (others => '1');
+	      ctr  <= (others => '0');
+	      txr  <= (others => '0');
+	    elsif (wb_clk_i'event and wb_clk_i = '1') then
+	      if (wb_rst_i = '1') then
+	        prer <= (others => '1');
+	        ctr  <= (others => '0');
+	        txr  <= (others => '0');
+	      elsif (wb_wacc = '1') then
+	        case wb_adr_i is
+	           when "000" => prer( 7 downto 0) <= unsigned(wb_dat_i);
+	           when "001" => prer(15 downto 8) <= unsigned(wb_dat_i);
+	           when "010" => ctr               <= wb_dat_i;
+	           when "011" => txr               <= wb_dat_i;
+	           when "100" => null; --write to CR, avoid executing the others clause
+
+	           -- illegal cases, for simulation only
+	           when others =>
+	              report ("Illegal write address, setting all registers to unknown.");
+	              prer <= (others => 'X');
+	              ctr  <= (others => 'X');
+	              txr  <= (others => 'X');
+	        end case;
+	      end if;
+	    end if;
+	end process gen_regs;
+
+
+	-- generate command register
+	gen_cr: process(rst_i, wb_clk_i)
+	begin
+	    if (rst_i = '0') then
+	        cr <= (others => '0');
+	    elsif (wb_clk_i'event and wb_clk_i = '1') then
+	        if (wb_rst_i = '1') then
+	            cr <= (others => '0');
+	        elsif (wb_wacc = '1') then
+	            if ( (core_en = '1') and (wb_adr_i = 4) ) then
+	                -- only take new commands when i2c core enabled
+	                -- pending commands are finished
+	                cr <= wb_dat_i;
+	            end if;
+	        else
+	            if (done = '1' or i2c_al = '1') then
+	                cr(7 downto 4) <= (others => '0'); -- clear command bits when command done or arbitration lost
+	            end if;
+
+	            cr(2 downto 1) <= (others => '0');   -- reserved bits, always '0'
+	            cr(0) <= '0';                        -- clear IRQ_ACK bit
+	        end if;
+	    end if;
+	end process gen_cr;
+
+	-- decode command register
+	sta  <= cr(7);
+	sto  <= cr(6);
+	rd   <= cr(5);
+	wr   <= cr(4);
+	ack  <= cr(3);
+	iack <= cr(0);
+
+	-- decode control register
+	core_en <= ctr(7);
+	ien     <= ctr(6);
+
+	-- hookup byte controller block
+	byte_ctrl: i2c_master_byte_ctrl port map (
+		clk      => wb_clk_i,
+		rst      => wb_rst_i,
+		nReset   => rst_i,
+		ena      => core_en,
+		clk_cnt  => prer,
+		start    => sta,
+		stop     => sto,
+		read     => rd,
+		write    => wr,
+		ack_in   => ack,
+		i2c_busy => i2c_busy,
+		i2c_al   => i2c_al,
+		din      => txr,
+		cmd_ack  => done,
+		ack_out  => irxack,
+		dout     => rxr,
+		scl_i    => scl_pad_i,
+		scl_o    => scl_pad_o,
+		scl_oen  => scl_padoen_o,
+		sda_i    => sda_pad_i,
+		sda_o    => sda_pad_o,
+		sda_oen  => sda_padoen_o
+	);
+
+
+	-- status register block + interrupt request signal
+	st_irq_block : block
+	begin
+	    -- generate status register bits
+	    gen_sr_bits: process (wb_clk_i, rst_i)
+	    begin
+	        if (rst_i = '0') then
+	          al       <= '0';
+	          rxack    <= '0';
+	          tip      <= '0';
+	          irq_flag <= '0';
+	        elsif (wb_clk_i'event and wb_clk_i = '1') then
+	          if (wb_rst_i = '1') then
+	            al       <= '0';
+	            rxack    <= '0';
+	            tip      <= '0';
+	            irq_flag <= '0';
+	          else
+	            al       <= i2c_al or (al and not sta);
+	            rxack    <= irxack;
+	            tip      <= (rd or wr);
+
+	            -- interrupt request flag is always generated
+	            irq_flag <= (done or i2c_al or irq_flag) and not iack;
+	          end if;
+	        end if;
+	    end process gen_sr_bits;
+
+	    -- generate interrupt request signals
+	    gen_irq: process (wb_clk_i, rst_i)
+	    begin
+	        if (rst_i = '0') then
+	          wb_inta_o <= '0';
+	        elsif (wb_clk_i'event and wb_clk_i = '1') then
+	          if (wb_rst_i = '1') then
+	            wb_inta_o <= '0';
+	          else
+	            -- interrupt signal is only generated when IEN (interrupt enable bit) is set
+	            wb_inta_o <= irq_flag and ien;
+	          end if;
+	        end if;
+	    end process gen_irq;
+
+	    -- assign status register bits
+	    sr(7)          <= rxack;
+	    sr(6)          <= i2c_busy;
+	    sr(5)          <= al;
+	    sr(4 downto 2) <= (others => '0'); -- reserved
+	    sr(1)          <= tip;
+	    sr(0)          <= irq_flag;
+	end block;
+
+end architecture structural;
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/readme b/fpga/usrp2/opencores/i2c/rtl/vhdl/readme
new file mode 100644
index 000000000..0d049f736
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/readme
@@ -0,0 +1,25 @@
+
+
+-- This code is provided for free and may be used and   --
+-- distributed without restriction provided that the    --
+-- copyright statement is not removed from the file and --
+-- that any derivative work contains the original       --
+-- copyright notice and the associated disclaimer.      --
+
+--   Comments and suggestions are always welcome        --
+
+The i2c_master core consists of three files:
+
+- i2c_master_top        -- top level
+- i2c_master_byte_ctrl  -- byte controller
+- i2c_master_bit_ctrl   -- bit controller
+
+VHDL needs to be compiled in order. The files are listed 
+above in descending order.
+
+I2C.VHD and tst_ds1621.vhd are not supported anymore.
+They remain mostly for historical purposes, altough they
+might prove usefull.
+
+Richard Herveille
+rherveille@opencores.org
diff --git a/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd b/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd
new file mode 100644
index 000000000..ccf50460c
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd
@@ -0,0 +1,283 @@
+--
+--
+-- State machine for reading data from Dallas 1621
+--
+-- Testsystem for i2c controller
+--
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+use work.i2c.all;
+
+entity DS1621_interface is
+	port (
+		clk : in std_logic;
+		nReset : in std_logic;
+
+		Dout : out std_logic_vector(7 downto 0);	-- data read from ds1621
+
+		error : out std_logic; -- no correct ack received
+
+		SCL : inout std_logic;
+		SDA : inout std_logic
+	);
+end entity DS1621_interface;
+
+architecture structural of DS1621_interface is
+	constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1001000";
+	constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8);
+
+	signal cmd_ack : std_logic;
+	signal D : std_logic_vector(7 downto 0);
+	signal lack, store_dout : std_logic;
+
+	signal start, read, write, ack, stop : std_logic;
+	signal i2c_dout : std_logic_vector(7 downto 0);
+
+begin
+	-- hookup I2C controller
+	u1: simple_i2c port map (clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset,
+			read => read, write => write, start => start, stop => stop, ack_in => ack, cmd_ack => cmd_ack, 
+			Din => D, Dout => i2c_dout, ack_out => lack, SCL => SCL, SDA => SDA);
+
+	init_statemachine : block
+		type states is (i1, i2, i3, i4, i5, t1, t2, t3, t4, t5);
+		signal state : states;
+	begin
+		nxt_state_decoder: process(clk, nReset, state)
+			variable nxt_state : states;
+			variable iD : std_logic_vector(7 downto 0);
+			variable ierr : std_logic;
+			variable istart, iread, iwrite, iack, istop : std_logic;
+			variable istore_dout : std_logic;
+		begin
+			nxt_state := state;
+			ierr := '0';
+			istore_dout := '0';
+
+			istart := start;
+			iread := read;
+			iwrite := write;
+			iack := ack;
+			istop := stop;
+			iD := D;
+
+			case (state) is
+				-- init DS1621
+				-- 1) send start condition
+				-- 2) send slave address + write
+				-- 3) check ack
+				-- 4) send "access config" command (0xAC)
+				-- 5) check ack
+				-- 6) send config register data (0x00)
+				-- 7) check ack
+				-- 8) send stop condition
+				-- 9) send start condition
+				-- 10) send slave address + write
+				-- 11) check ack
+				-- 12) send "start conversion" command (0xEE)
+				-- 13) check ack
+				-- 14) send stop condition
+
+				when i1 =>	-- send start condition, sent slave address + write
+					nxt_state := i2;
+					istart := '1';
+					iread := '0';
+					iwrite := '1';
+					iack := '0';
+					istop := '0';
+					iD := (slave_addr & '0'); -- write to slave (R/W = '0')
+
+				when i2 =>	-- send "access config" command
+					if (cmd_ack = '1') then
+						nxt_state := i3;
+						-- check aknowledge bit
+						if (lack = '1') then
+							ierr := '1'; -- no acknowledge received from last command, expected ACK
+						end if;
+
+						istart := '0';
+						iread := '0';
+						iwrite := '1';
+						iack := '0';
+						istop := '0';
+						iD := x"AC";
+					end if;
+
+				when i3 =>	-- send config register data, sent stop condition
+					if (cmd_ack = '1') then
+						nxt_state := i4;
+						-- check aknowledge bit
+						if (lack = '1') then
+							ierr := '1'; -- no acknowledge received from last command, expected ACK
+						end if;
+
+						istart := '0';
+						iread := '0';
+						iwrite := '1';
+						iack := '0';
+						istop := '1';
+						iD := x"00";
+					end if;
+
+				when i4 =>	-- send start condition, sent slave address + write
+					if (cmd_ack = '1') then
+						nxt_state := i5;
+	
+						istart := '1';
+						iread := '0';
+						iwrite := '1';
+						iack := '0';
+						istop := '0';
+						iD := (slave_addr & '0'); -- write to slave (R/W = '0')
+					end if;
+
+				when i5 =>	-- send "start conversion" command + stop condition
+					if (cmd_ack = '1') then
+						nxt_state := t1;
+						-- check aknowledge bit
+						if (lack = '1') then
+							ierr := '1'; -- no acknowledge received from last command, expected ACK
+						end if;
+
+						istart := '0';
+						iread := '0';
+						iwrite := '1';
+						iack := '0';
+						istop := '1';
+						iD := x"EE";
+					end if;
+				-- read temperature
+				-- 1) sent start condition
+				-- 2) sent slave address + write
+				-- 3) check ack
+				-- 4) sent "read temperature" command (0xAA)
+				-- 5) check ack
+				-- 6) sent start condition
+				-- 7) sent slave address + read
+				-- 8) check ack
+				-- 9) read msb
+				-- 10) send ack
+				-- 11) read lsb
+				-- 12) send nack
+				-- 13) send stop condition
+
+				when t1 =>	-- send start condition, sent slave address + write
+					if (cmd_ack = '1') then
+						nxt_state := t2;
+						-- check aknowledge bit
+						if (lack = '1') then
+							ierr := '1'; -- no acknowledge received from last command, expected ACK
+						end if;
+
+						istart := '1';
+						iread := '0';
+						iwrite := '1';
+						iack := '0';
+						istop := '0';
+						iD := (slave_addr & '0'); -- write to slave (R/W = '0')
+					end if;
+
+				when t2 =>	-- send read temperature command
+					if (cmd_ack = '1') then
+						nxt_state := t3;
+						-- check aknowledge bit
+						if (lack = '1') then
+							ierr := '1'; -- no acknowledge received from last command, expected ACK
+						end if;
+
+						istart := '0';
+						iread := '0';
+						iwrite := '1';
+						iack := '0';
+						istop := '0';
+						iD := x"AA";
+					end if;
+
+				when t3 =>	-- send (repeated) start condition, send slave address + read
+					if (cmd_ack = '1') then
+						nxt_state := t4;
+						-- check aknowledge bit
+						if (lack = '1') then
+							ierr := '1'; -- no acknowledge received, expected ACK
+						end if;
+
+						istart := '1';
+						iread := '0';
+						iwrite := '1';
+						iack := '0';
+						istop := '0';
+						iD := (slave_addr & '1'); -- read from slave (R/W = '1')
+					end if;
+
+				when t4 =>	-- read MSB (hi-byte), send acknowledge
+					if (cmd_ack = '1') then
+						nxt_state := t5;
+						-- check aknowledge bit
+						if (lack = '1') then
+							ierr := '1'; -- no acknowledge received from last command, expected ACK
+						end if;
+
+						istart := '0';
+						iread := '1';
+						iwrite := '0';
+						iack := '0'; --ACK
+						istop := '0';
+					end if;
+
+				when t5 =>	-- read LSB (lo-byte), send acknowledge, sent stop
+					if (cmd_ack = '1') then
+						nxt_state := t1;
+
+						istart := '0';
+						iread := '1';
+						iwrite := '0';
+						iack := '1'; --NACK
+						istop := '1';
+
+						istore_dout := '1';
+					end if;
+			end case;
+
+			-- genregs
+			if (nReset = '0') then
+				state <= i1;
+				error <= '0';
+				store_dout <= '0';
+
+				start <= '0';
+				read <= '0';
+				write <= '0';
+				ack <= '0';
+				stop <= '0';
+				D <= (others => '0');
+			elsif (clk'event and clk = '1') then
+				state <= nxt_state;
+				error <= ierr;
+				store_dout <= istore_dout;
+
+				start <= istart;
+				read <= iread;
+				write <= iwrite;
+				ack <= iack;
+				stop <= istop;
+				D <= iD;
+			end if;
+		end process nxt_state_decoder;
+	end block init_statemachine;
+
+	-- store temp
+	gen_dout : process(clk)
+	begin
+		if (clk'event and clk = '1') then
+			if (store_dout = '1') then
+				Dout <= i2c_dout;
+			end if;
+		end if;
+	end process gen_dout;
+
+end architecture structural;
+
+
diff --git a/fpga/usrp2/opencores/i2c/sim/CVS/Entries b/fpga/usrp2/opencores/i2c/sim/CVS/Entries
new file mode 100644
index 000000000..d08a896a5
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/CVS/Entries
@@ -0,0 +1 @@
+D/i2c_verilog////
diff --git a/fpga/usrp2/opencores/i2c/sim/CVS/Repository b/fpga/usrp2/opencores/i2c/sim/CVS/Repository
new file mode 100644
index 000000000..500d85906
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/CVS/Repository
@@ -0,0 +1 @@
+i2c/sim
diff --git a/fpga/usrp2/opencores/i2c/sim/CVS/Root b/fpga/usrp2/opencores/i2c/sim/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/sim/CVS/Template b/fpga/usrp2/opencores/i2c/sim/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Entries b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Entries
new file mode 100644
index 000000000..8ab9f73a7
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Entries
@@ -0,0 +1 @@
+D/run////
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository
new file mode 100644
index 000000000..b97ee33c8
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Repository
@@ -0,0 +1 @@
+i2c/sim/i2c_verilog
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Template b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
new file mode 100644
index 000000000..ddea0baae
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
@@ -0,0 +1,6 @@
+/bench.vcd/1.1/Sat Jun 15 07:37:05 2002//
+/ncverilog.key/1.1/Sat Jun 15 07:37:11 2002//
+/ncverilog.log/1.1/Sat Jun 15 07:37:11 2002//
+/run/1.2/Fri Apr  6 09:02:38 2007//
+D/INCA_libs////
+D/waves////
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository
new file mode 100644
index 000000000..bdd990e7c
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Repository
@@ -0,0 +1 @@
+i2c/sim/i2c_verilog/run
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Template b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
new file mode 100644
index 000000000..178481050
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Entries
@@ -0,0 +1 @@
+D
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
new file mode 100644
index 000000000..6b760e397
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Repository
@@ -0,0 +1 @@
+i2c/sim/i2c_verilog/run/INCA_libs
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/INCA_libs/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd
new file mode 100644
index 000000000..9a364415f
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/bench.vcd
@@ -0,0 +1,1496812 @@
+$date
+    Jun 15, 2002  13:36:37
+$end
+$version
+    ncsim: v03.40.(b001)
+$end
+$timescale
+    10 ps
+$end
+
+$scope module tst_bench_top $end
+$var reg       1 !    clk  $end
+$var reg       1 "    rstn  $end
+$var wire      1 #    adr [31] $end
+$var wire      1 $    adr [30] $end
+$var wire      1 %    adr [29] $end
+$var wire      1 &    adr [28] $end
+$var wire      1 '    adr [27] $end
+$var wire      1 (    adr [26] $end
+$var wire      1 )    adr [25] $end
+$var wire      1 *    adr [24] $end
+$var wire      1 +    adr [23] $end
+$var wire      1 ,    adr [22] $end
+$var wire      1 -    adr [21] $end
+$var wire      1 .    adr [20] $end
+$var wire      1 /    adr [19] $end
+$var wire      1 0    adr [18] $end
+$var wire      1 1    adr [17] $end
+$var wire      1 2    adr [16] $end
+$var wire      1 3    adr [15] $end
+$var wire      1 4    adr [14] $end
+$var wire      1 5    adr [13] $end
+$var wire      1 6    adr [12] $end
+$var wire      1 7    adr [11] $end
+$var wire      1 8    adr [10] $end
+$var wire      1 9    adr [9] $end
+$var wire      1 :    adr [8] $end
+$var wire      1 ;    adr [7] $end
+$var wire      1 <    adr [6] $end
+$var wire      1 =    adr [5] $end
+$var wire      1 >    adr [4] $end
+$var wire      1 ?    adr [3] $end
+$var wire      1 @    adr [2] $end
+$var wire      1 A    adr [1] $end
+$var wire      1 B    adr [0] $end
+$var wire      8 C    dat_i [7:0] $end
+$var wire      8 D    dat_o [7:0] $end
+$var wire      1 E    we  $end
+$var wire      1 F    stb  $end
+$var wire      1 G    cyc  $end
+$var wire      1 H    ack  $end
+$var wire      1 I    inta  $end
+$var reg       8 J    q [7:0] $end
+$var reg       8 K    qq [7:0] $end
+$var wire      1 L    scl  $end
+$var wire      1 M    scl_o  $end
+$var wire      1 N    scl_oen  $end
+$var wire      1 O    sda  $end
+$var wire      1 P    sda_o  $end
+$var wire      1 Q    sda_oen  $end
+$var parameter  3 R    PRER_LO  $end
+$var parameter  3 S    PRER_HI  $end
+$var parameter  3 T    CTR  $end
+$var parameter  3 U    RXR  $end
+$var parameter  3 V    TXR  $end
+$var parameter  3 W    CR  $end
+$var parameter  3 X    SR  $end
+$var parameter  3 Y    TXR_R  $end
+$var parameter  3 Z    CR_R  $end
+
+$scope module i2c_slave $end
+$var parameter  7 [    I2C_ADR  $end
+$var wire      1 L    scl  $end
+$var wire      1 O    sda  $end
+$var wire      1 \    debug  $end
+$var reg       8 ]    mem_adr [7:0] $end
+$var reg       8 ^    mem_do [7:0] $end
+$var reg       1 _    sta  $end
+$var reg       1 `    d_sta  $end
+$var reg       1 a    sto  $end
+$var reg       1 b    d_sto  $end
+$var reg       8 c    sr [7:0] $end
+$var reg       1 d    rw  $end
+$var wire      1 e    my_adr  $end
+$var wire      1 f    i2c_reset  $end
+$var reg       3 g    bit_cnt [2:0] $end
+$var wire      1 h    acc_done  $end
+$var reg       1 i    ld  $end
+$var reg       1 j    sda_o  $end
+$var parameter  3 k    idle  $end
+$var parameter  3 l    slave_ack  $end
+$var parameter  3 m    get_mem_adr  $end
+$var parameter  3 n    gma_ack  $end
+$var parameter  3 o    data  $end
+$var parameter  3 p    data_ack  $end
+$var reg       3 q    state [2:0] $end
+$upscope $end
+
+$upscope $end
+
+$enddefinitions $end
+$dumpvars
+b101 p
+b100 o
+b11 n
+b10 m
+b1 l
+b0 k
+b1010000 [
+b110 Z
+b101 Y
+b100 X
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+$end
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+#20000
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+b110010 D
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+0,
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diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key
new file mode 100644
index 000000000..a3abe5090
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/ncverilog.key
@@ -0,0 +1 @@
+exit
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/run b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/run
new file mode 100755
index 000000000..41bcaab30
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/run
@@ -0,0 +1,25 @@
+#!/bin/csh
+
+set i2c      = ../../..
+set bench    = $i2c/bench
+set wave_dir = $i2c/sim/rtl_sim/i2c_verilog/waves
+
+ncverilog							\
+								\
+	+access+rwc						\
+	+define+WAVES						\
+								\
+	+incdir+$bench/verilog					\
+	+incdir+$i2c/rtl/verilog				\
+								\
+	$i2c/rtl/verilog/i2c_master_bit_ctrl.v			\
+	$i2c/rtl/verilog/i2c_master_byte_ctrl.v			\
+	$i2c/rtl/verilog/i2c_master_top.v			\
+								\
+	$bench/verilog/i2c_slave_model.v			\
+	$bench/verilog/wb_master_model.v			\
+	$bench/verilog/tst_bench_top.v
+
+
+
+
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries
new file mode 100644
index 000000000..178481050
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Entries
@@ -0,0 +1 @@
+D
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository
new file mode 100644
index 000000000..94d106eb0
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Repository
@@ -0,0 +1 @@
+i2c/sim/i2c_verilog/run/waves
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/sim/i2c_verilog/run/waves/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/software/CVS/Entries b/fpga/usrp2/opencores/i2c/software/CVS/Entries
new file mode 100644
index 000000000..934613477
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/CVS/Entries
@@ -0,0 +1,2 @@
+D/drivers////
+D/include////
diff --git a/fpga/usrp2/opencores/i2c/software/CVS/Repository b/fpga/usrp2/opencores/i2c/software/CVS/Repository
new file mode 100644
index 000000000..1b4c9f0bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/CVS/Repository
@@ -0,0 +1 @@
+i2c/software
diff --git a/fpga/usrp2/opencores/i2c/software/CVS/Root b/fpga/usrp2/opencores/i2c/software/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/software/CVS/Template b/fpga/usrp2/opencores/i2c/software/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/software/drivers/CVS/Entries b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Entries
new file mode 100644
index 000000000..178481050
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Entries
@@ -0,0 +1 @@
+D
diff --git a/fpga/usrp2/opencores/i2c/software/drivers/CVS/Repository b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Repository
new file mode 100644
index 000000000..260d7873c
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Repository
@@ -0,0 +1 @@
+i2c/software/drivers
diff --git a/fpga/usrp2/opencores/i2c/software/drivers/CVS/Root b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/software/drivers/CVS/Template b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/drivers/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/software/include/CVS/Entries b/fpga/usrp2/opencores/i2c/software/include/CVS/Entries
new file mode 100644
index 000000000..ef11b0c73
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/include/CVS/Entries
@@ -0,0 +1,2 @@
+/oc_i2c_master.h/1.1/Thu Nov 22 10:02:19 2001//
+D
diff --git a/fpga/usrp2/opencores/i2c/software/include/CVS/Repository b/fpga/usrp2/opencores/i2c/software/include/CVS/Repository
new file mode 100644
index 000000000..2ea08eeec
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/include/CVS/Repository
@@ -0,0 +1 @@
+i2c/software/include
diff --git a/fpga/usrp2/opencores/i2c/software/include/CVS/Root b/fpga/usrp2/opencores/i2c/software/include/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/include/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/software/include/CVS/Template b/fpga/usrp2/opencores/i2c/software/include/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/include/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h b/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h
new file mode 100644
index 000000000..7f7cfc417
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/software/include/oc_i2c_master.h
@@ -0,0 +1,102 @@
+/*
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  Include file for OpenCores I2C Master core                 ////
+////                                                             ////
+////  File    : oc_i2c_master.h                                  ////
+////  Function: c-include file                                   ////
+////                                                             ////
+////  Authors: Richard Herveille (richard@asics.ws)              ////
+////           Filip Miletic                                     ////
+////                                                             ////
+////           www.opencores.org                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2001 Richard Herveille                        ////
+////                    Filip Miletic                            ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+*/
+
+/*
+ * Definitions for the Opencores i2c master core
+ */
+
+/* --- Definitions for i2c master's registers --- */
+	
+/* ----- Read-write access                                            */
+
+#define OC_I2C_PRER_LO 0x00     /* Low byte clock prescaler register  */	
+#define OC_I2C_PRER_HI 0x01     /* High byte clock prescaler register */	
+#define OC_I2C_CTR     0x02     /* Control register                   */	
+										
+/* ----- Write-only registers                                         */
+										
+#define OC_I2C_TXR     0x03     /* Transmit byte register             */	
+#define OC_I2C_CR      0x04     /* Command register                   */	
+	
+/* ----- Read-only registers                                          */
+										
+#define OC_I2C_RXR     0x03     /* Receive byte register              */
+#define OC_I2C_SR      0x04     /* Status register                    */
+	
+/* ----- Bits definition                                              */
+	
+/* ----- Control register                                             */
+	
+#define OC_I2C_EN (1<<7)        /* Core enable bit:                   */
+                                /*      1 - core is enabled           */
+                                /*      0 - core is disabled          */
+#define OC_I2C_IEN (1<<6)       /* Interrupt enable bit               */
+                                /*      1 - Interrupt enabled         */
+                                /*      0 - Interrupt disabled        */
+                                /* Other bits in CR are reserved      */
+
+/* ----- Command register bits                                        */
+ 
+#define OC_I2C_STA (1<<7)       /* Generate (repeated) start condition*/
+#define OC_I2C_STO (1<<6)       /* Generate stop condition            */
+#define OC_I2C_RD  (1<<5)       /* Read from slave                    */
+#define OC_I2C_WR  (1<<4)       /* Write to slave                     */
+#define OC_I2C_ACK (1<<3)       /* Acknowledge from slave             */
+                                /*      1 - ACK                       */
+                                /*      0 - NACK                      */
+#define OC_I2C_IACK (1<<0)      /* Interrupt acknowledge              */
+
+/* ----- Status register bits                                         */
+
+#define OC_I2C_RXACK (1<<7)     /* ACK received from slave            */
+                                /*      1 - ACK                       */
+                                /*      0 - NACK                      */
+#define OC_I2C_BUSY  (1<<6)     /* Busy bit                           */
+#define OC_I2C_TIP   (1<<1)     /* Transfer in progress               */
+#define OC_I2C_IF    (1<<0)     /* Interrupt flag                     */
+
+/* bit testing and setting macros                                     */
+
+#define OC_ISSET(reg,bitmask)       ((reg)&(bitmask))
+#define OC_ISCLEAR(reg,bitmask)     (!(OC_ISSET(reg,bitmask)))
+#define OC_BITSET(reg,bitmask)      ((reg)|(bitmask))
+#define OC_BITCLEAR(reg,bitmask)    ((reg)|(~(bitmask)))
+#define OC_BITTOGGLE(reg,bitmask)   ((reg)^(bitmask))
+#define OC_REGMOVE(reg,value)       ((reg)=(value))
\ No newline at end of file
diff --git a/fpga/usrp2/opencores/i2c/verilog/CVS/Entries b/fpga/usrp2/opencores/i2c/verilog/CVS/Entries
new file mode 100644
index 000000000..178481050
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/verilog/CVS/Entries
@@ -0,0 +1 @@
+D
diff --git a/fpga/usrp2/opencores/i2c/verilog/CVS/Repository b/fpga/usrp2/opencores/i2c/verilog/CVS/Repository
new file mode 100644
index 000000000..acc23265f
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/verilog/CVS/Repository
@@ -0,0 +1 @@
+i2c/verilog
diff --git a/fpga/usrp2/opencores/i2c/verilog/CVS/Root b/fpga/usrp2/opencores/i2c/verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/verilog/CVS/Template b/fpga/usrp2/opencores/i2c/verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/i2c/vhdl/CVS/Entries b/fpga/usrp2/opencores/i2c/vhdl/CVS/Entries
new file mode 100644
index 000000000..178481050
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/vhdl/CVS/Entries
@@ -0,0 +1 @@
+D
diff --git a/fpga/usrp2/opencores/i2c/vhdl/CVS/Repository b/fpga/usrp2/opencores/i2c/vhdl/CVS/Repository
new file mode 100644
index 000000000..8ee00a788
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/vhdl/CVS/Repository
@@ -0,0 +1 @@
+i2c/vhdl
diff --git a/fpga/usrp2/opencores/i2c/vhdl/CVS/Root b/fpga/usrp2/opencores/i2c/vhdl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/vhdl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/i2c/vhdl/CVS/Template b/fpga/usrp2/opencores/i2c/vhdl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/i2c/vhdl/CVS/Template
diff --git a/fpga/usrp2/opencores/simple_gpio/CVS/Entries b/fpga/usrp2/opencores/simple_gpio/CVS/Entries
new file mode 100644
index 000000000..df1462bb9
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/CVS/Entries
@@ -0,0 +1 @@
+D/rtl////
diff --git a/fpga/usrp2/opencores/simple_gpio/CVS/Repository b/fpga/usrp2/opencores/simple_gpio/CVS/Repository
new file mode 100644
index 000000000..b869a0de8
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/CVS/Repository
@@ -0,0 +1 @@
+simple_gpio
diff --git a/fpga/usrp2/opencores/simple_gpio/CVS/Root b/fpga/usrp2/opencores/simple_gpio/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/simple_gpio/CVS/Template b/fpga/usrp2/opencores/simple_gpio/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/CVS/Template
diff --git a/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Entries b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Entries
new file mode 100644
index 000000000..8c6258130
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Entries
@@ -0,0 +1,2 @@
+/simple_gpio.v/1.2/Sun Dec 22 16:10:17 2002//
+D
diff --git a/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Repository b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Repository
new file mode 100644
index 000000000..955303d8a
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Repository
@@ -0,0 +1 @@
+simple_gpio/rtl
diff --git a/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Root b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Template b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/rtl/CVS/Template
diff --git a/fpga/usrp2/opencores/simple_gpio/rtl/simple_gpio.v b/fpga/usrp2/opencores/simple_gpio/rtl/simple_gpio.v
new file mode 100644
index 000000000..0b78f9921
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_gpio/rtl/simple_gpio.v
@@ -0,0 +1,193 @@
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores Simple General Purpose IO core                   ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+
+//  CVS Log
+//
+//  $Id: simple_gpio.v,v 1.2 2002/12/22 16:10:17 rherveille Exp $
+//
+//  $Date: 2002/12/22 16:10:17 $
+//  $Revision: 1.2 $
+//  $Author: rherveille $
+//  $Locker:  $
+//  $State: Exp $
+//
+// Change History:
+//               $Log: simple_gpio.v,v $
+//               Revision 1.2  2002/12/22 16:10:17  rherveille
+//               Fixed some typos in the documentation section.
+//
+//
+
+
+
+//
+// Very basic 8bit GPIO core
+//
+//
+// Registers:
+//
+// 0x00: Control Register   <io[7:0]>
+//       bits 7:0 R/W Input/Output    '1' = output mode
+//                                    '0' = input mode
+// 0x01: Line Register
+//       bits 7:0 R   Status                Current GPIO pin level
+//                W   Output                GPIO pin output level
+//
+//
+// HOWTO:
+//
+// Use a pin as an input:
+// Program the corresponding bit in the control register to 'input mode' ('0').
+// The pin's state (input level) can be checked by reading the Line Register.
+// Writing to the GPIO pin's Line Register bit while in input mode has no effect.
+//
+// Use a pin as an output:
+// Program the corresponding bit in the control register to 'output mode' ('1').
+// Program the GPIO pin's output level by writing to the corresponding bit in
+// the Line Register.
+// Reading the GPIO pin's Line Register bit while in output mode returns the
+// current output level.
+//
+// Addapt the core for fewer GPIOs:
+// If less than 8 GPIOs are required, than the 'io' parameter can be set to
+// the amount of required interrupts. GPIOs are mapped starting at the LSBs.
+// So only the 'io' LSBs per register are valid.
+// All other bits (i.e. the 8-'io' MSBs) are set to zero '0'.
+// Codesize is approximately linear to the amount of interrupts. I.e. using
+// 4 instead of 8 GPIO sources reduces the size by approx. half.
+//
+
+
+// synopsys translate_off
+`include "timescale.v"
+// synopsys translate_on
+
+module simple_gpio(
+  clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o,
+  gpio
+);
+
+  //
+  // Inputs & outputs
+  //
+  parameter io = 8;            // number of GPIOs
+
+  // 8bit WISHBONE bus slave interface
+  input         clk_i;         // clock
+  input         rst_i;         // reset (asynchronous active low)
+  input         cyc_i;         // cycle
+  input         stb_i;         // strobe
+  input         adr_i;         // address adr_i[1]
+  input         we_i;          // write enable
+  input  [ 7:0] dat_i;         // data output
+  output [ 7:0] dat_o;         // data input
+  output        ack_o;         // normal bus termination
+
+  // GPIO pins
+  inout  [io:1] gpio;
+
+  //
+  // Module body
+  //
+  reg [io:1] ctrl, line;                  // ControlRegister, LineRegister
+  reg [io:1] lgpio, llgpio;               // LatchedGPIO pins
+
+  //
+  // perform parameter checks
+  //
+  // synopsys translate_off
+  initial
+  begin
+      if(io > 8)
+        $display("simple_gpio: max. 8 GPIOs supported.");
+  end
+  // synopsys translate_on
+
+  //
+  // WISHBONE interface
+
+  wire wb_acc = cyc_i & stb_i;            // WISHBONE access
+  wire wb_wr  = wb_acc & we_i;            // WISHBONE write access
+
+  always @(posedge clk_i or negedge rst_i)
+    if (~rst_i)
+      begin
+          ctrl <= #1 {io{1'b0}};
+          line <= #1 {io{1'b0}};
+      end
+    else if (wb_wr)
+       if ( adr_i )
+         line <= #1 dat_i[io-1:0];
+       else
+         ctrl <= #1 dat_i[io-1:0];
+
+
+  reg [7:0] dat_o;
+  always @(posedge clk_i)
+    if ( adr_i )
+      dat_o <= #1 { {(8-io){1'b0}}, llgpio};
+    else
+      dat_o <= #1 { {(8-io){1'b0}}, ctrl};
+
+  reg ack_o;
+  always @(posedge clk_i or negedge rst_i)
+    if (~rst_i)
+      ack_o <= #1 1'b0;
+    else
+      ack_o <= #1 wb_acc & !ack_o;
+
+
+  //
+  // GPIO section
+
+  // latch GPIO input pins
+  always @(posedge clk_i)
+    lgpio <= #1 gpio;
+
+  // latch again (reduce meta-stability risc)
+  always @(posedge clk_i)
+    llgpio <= #1 lgpio;
+
+  // assign GPIO outputs
+  integer n;
+  reg [io:1] igpio; // temporary internal signal
+
+  always @(ctrl or line)
+    for(n=1;n<=io;n=n+1)
+      igpio[n] <= ctrl[n] ? line[n] : 1'bz;
+
+  assign gpio = igpio;
+
+endmodule
+
diff --git a/fpga/usrp2/opencores/simple_pic/CVS/Entries b/fpga/usrp2/opencores/simple_pic/CVS/Entries
new file mode 100644
index 000000000..df1462bb9
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/CVS/Entries
@@ -0,0 +1 @@
+D/rtl////
diff --git a/fpga/usrp2/opencores/simple_pic/CVS/Repository b/fpga/usrp2/opencores/simple_pic/CVS/Repository
new file mode 100644
index 000000000..73de5bf2b
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/CVS/Repository
@@ -0,0 +1 @@
+simple_pic
diff --git a/fpga/usrp2/opencores/simple_pic/CVS/Root b/fpga/usrp2/opencores/simple_pic/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/simple_pic/CVS/Template b/fpga/usrp2/opencores/simple_pic/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/CVS/Template
diff --git a/fpga/usrp2/opencores/simple_pic/rtl/CVS/Entries b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Entries
new file mode 100644
index 000000000..e5e641097
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Entries
@@ -0,0 +1,2 @@
+/simple_pic.v/1.3/Tue Dec 24 10:26:51 2002//
+D
diff --git a/fpga/usrp2/opencores/simple_pic/rtl/CVS/Repository b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Repository
new file mode 100644
index 000000000..2639a29e2
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Repository
@@ -0,0 +1 @@
+simple_pic/rtl
diff --git a/fpga/usrp2/opencores/simple_pic/rtl/CVS/Root b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/simple_pic/rtl/CVS/Template b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/rtl/CVS/Template
diff --git a/fpga/usrp2/opencores/simple_pic/rtl/simple_pic.v b/fpga/usrp2/opencores/simple_pic/rtl/simple_pic.v
new file mode 100644
index 000000000..28184cbe2
--- /dev/null
+++ b/fpga/usrp2/opencores/simple_pic/rtl/simple_pic.v
@@ -0,0 +1,228 @@
+
+// Modified by M. Ettus, 2008 for 32 bit width
+
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+////  OpenCores         Simple Programmable Interrupt Controller ////
+////                                                             ////
+////  Author: Richard Herveille                                  ////
+////          richard@asics.ws                                   ////
+////          www.asics.ws                                       ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+////                                                             ////
+//// Copyright (C) 2002 Richard Herveille                        ////
+////                    richard@asics.ws                         ////
+////                                                             ////
+//// This source file may be used and distributed without        ////
+//// restriction provided that this copyright statement is not   ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+////                                                             ////
+////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
+//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
+//// POSSIBILITY OF SUCH DAMAGE.                                 ////
+////                                                             ////
+/////////////////////////////////////////////////////////////////////
+//
+// This is a simple Programmable Interrupt Controller.
+// The number of interrupts is depending on the databus size.
+// There's one interrupt input per databit (i.e. 16 interrupts for a 16
+// bit databus).
+// All attached devices share the same CPU priority level.
+//
+//
+//
+// Registers:
+//
+// 0x00: EdgeEnable Register
+//       bits 7:0 R/W  Edge Enable '1' = edge triggered interrupt source
+//                                 '0' = level triggered interrupt source
+// 0x01: PolarityRegister
+//       bits 7:0 R/W Polarity     '1' = high level / rising edge
+//                                 '0' = low level / falling edge
+// 0x02: MaskRegister
+//       bits 7:0 R/W Mask         '1' = interrupt masked (disabled)
+//                                 '0' = interrupt not masked (enabled)
+// 0x03: PendingRegister
+//       bits 7:0 R/W Pending      '1' = interrupt pending
+//                                 '0' = no interrupt pending
+//
+// A CPU interrupt is generated when an interrupt is pending and its
+// MASK bit is cleared.
+//
+//
+//
+// HOWTO:
+//
+// Clearing pending interrupts:
+// Writing a '1' to a bit in the interrupt pending register clears the
+// interrupt. Make sure to clear the interrupt at the source before
+// writing to the interrupt pending register. Otherwise the interrupt
+// will be set again.
+//
+// Priority based interrupts:
+// Upon reception of an interrupt, check the interrupt register and
+// determine the highest priority interrupt. Mask all interrupts from the
+// current level to the lowest level. This negates the interrupt line, and
+// makes sure only interrupts with a higher level are triggered. After
+// completion of the interrupt service routine, clear the interrupt source,
+// the interrupt bit in the pending register, and restore the MASK register
+// to it's previous state.
+//
+// Addapt the core for fewer interrupt sources:
+// If less than 8 interrupt sources are required, than the 'is' parameter
+// can be set to the amount of required interrupts. Interrupts are mapped
+// starting at the LSBs. So only the 'is' LSBs per register are valid. All
+// other bits (i.e. the 8-'is' MSBs) are set to zero '0'.
+// Codesize is approximately linear to the amount of interrupts. I.e. using
+// 4 instead of 8 interrupt sources reduces the size by approx. half.
+//
+
+
+module simple_pic(
+  clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o,
+  irq
+);
+   parameter is = 8;            // Number of interrupt sources
+   parameter dwidth = 32;
+  //
+  // Inputs & outputs
+  //
+
+  // 8bit WISHBONE bus slave interface
+  input         clk_i;         // clock
+  input         rst_i;         // reset (asynchronous active low)
+  input         cyc_i;         // cycle
+  input         stb_i;         // strobe  (cycle and strobe are the same signal)
+  input  [ 2:1] adr_i;         // address
+  input         we_i;          // write enable
+  input  [ dwidth-1:0] dat_i;         // data output
+  output [ dwidth-1:0] dat_o;         // data input
+  output        ack_o;         // normal bus termination
+
+  output        int_o;         // interrupt output
+
+  //
+  // Interrupt sources
+  //
+  input  [is:1] irq;           // interrupt request inputs
+
+
+  //
+  //  Module body
+  //
+  reg  [is:1] pol, edgen, pending, mask;   // register bank
+  reg  [is:1] lirq, dirq;                  // latched irqs, delayed latched irqs
+
+
+  //
+  // perform parameter checks
+  //
+  // synopsys translate_off
+  initial
+  begin
+      if(is > dwidth)
+        $display("simple_pic: max number of interrupts = data bus width.");
+  end
+  // synopsys translate_on
+
+  //
+  // latch interrupt inputs
+  always @(posedge clk_i)
+    lirq <= #1 irq;
+
+  //
+  // generate delayed latched irqs
+  always @(posedge clk_i)
+    dirq <= #1 lirq;
+
+
+  //
+  // generate actual triggers
+  function trigger;
+    input edgen, pol, lirq, dirq;
+
+    reg   edge_irq, level_irq;
+  begin
+      edge_irq  = pol ? (lirq & ~dirq) : (dirq & ~lirq);
+      level_irq = pol ? lirq : ~lirq;
+
+      trigger = edgen ? edge_irq : level_irq;
+  end
+  endfunction
+
+  reg  [is:1] irq_event;
+  integer n;
+  always @(posedge clk_i)
+    for(n=1; n<=is; n=n+1)
+      irq_event[n] <= #1 trigger(edgen[n], pol[n], lirq[n], dirq[n]);
+
+  //
+  // generate wishbone register bank writes
+  wire wb_acc = cyc_i & stb_i;                   // WISHBONE access
+  wire wb_wr  = wb_acc & we_i;                   // WISHBONE write access
+
+  always @(posedge clk_i)
+    if (rst_i)
+      begin
+          pol   <= #1 {is{1'b0}};              // clear polarity register
+          edgen <= #1 {is{1'b0}};              // clear edge enable register
+          mask  <= #1 {is{1'b1}};              // mask all interrupts
+      end
+    else if(wb_wr)                               // wishbone write cycle??
+      case (adr_i) // synopsys full_case parallel_case
+        2'b00: edgen <= #1 dat_i[is-1:0];        // EDGE-ENABLE register
+        2'b01: pol   <= #1 dat_i[is-1:0];        // POLARITY register
+        2'b10: mask  <= #1 dat_i[is-1:0];        // MASK register
+        2'b11: ;                                 // PENDING register is a special case (see below)
+      endcase
+
+
+    // pending register is a special case
+    always @(posedge clk_i)
+      if (rst_i)
+          pending <= #1 {is{1'b0}};            // clear all pending interrupts
+      else if ( wb_wr & (&adr_i) )
+          pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event;
+      else
+          pending <= #1 pending | irq_event;
+
+    //
+    // generate dat_o
+    reg [dwidth-1:0] dat_o;
+    always @(posedge clk_i)
+      case (adr_i) // synopsys full_case parallel_case
+        2'b00: dat_o <= #1 { {(dwidth-is){1'b0}}, edgen};
+        2'b01: dat_o <= #1 { {(dwidth-is){1'b0}}, pol};
+        2'b10: dat_o <= #1 { {(dwidth-is){1'b0}}, mask};
+        2'b11: dat_o <= #1 { {(dwidth-is){1'b0}}, pending};
+      endcase
+
+   //
+   // generate ack_o
+   reg ack_o;
+   always @(posedge clk_i)
+     ack_o <= #1 wb_acc & !ack_o;
+
+  //
+  // generate CPU interrupt signal
+  reg int_o;
+  always @(posedge clk_i)
+    if(rst_i)
+      int_o <= #1 0;
+    else
+      int_o <= #1 |(pending & ~mask);
+
+endmodule
+
diff --git a/fpga/usrp2/opencores/spi/CVS/Entries b/fpga/usrp2/opencores/spi/CVS/Entries
new file mode 100644
index 000000000..62011c465
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/CVS/Entries
@@ -0,0 +1,4 @@
+D/bench////
+D/doc////
+D/rtl////
+D/sim////
diff --git a/fpga/usrp2/opencores/spi/CVS/Repository b/fpga/usrp2/opencores/spi/CVS/Repository
new file mode 100644
index 000000000..c928c4b77
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/CVS/Repository
@@ -0,0 +1 @@
+spi
diff --git a/fpga/usrp2/opencores/spi/CVS/Root b/fpga/usrp2/opencores/spi/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/CVS/Template b/fpga/usrp2/opencores/spi/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/bench/CVS/Entries b/fpga/usrp2/opencores/spi/bench/CVS/Entries
new file mode 100644
index 000000000..428c5622d
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/CVS/Entries
@@ -0,0 +1 @@
+D/verilog////
diff --git a/fpga/usrp2/opencores/spi/bench/CVS/Repository b/fpga/usrp2/opencores/spi/bench/CVS/Repository
new file mode 100644
index 000000000..f45728d0f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/CVS/Repository
@@ -0,0 +1 @@
+spi/bench
diff --git a/fpga/usrp2/opencores/spi/bench/CVS/Root b/fpga/usrp2/opencores/spi/bench/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/bench/CVS/Template b/fpga/usrp2/opencores/spi/bench/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/bench/verilog/CVS/Entries b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Entries
new file mode 100644
index 000000000..68404f871
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Entries
@@ -0,0 +1,4 @@
+/spi_slave_model.v/1.2/Wed Mar 26 16:00:03 2003//
+/tb_spi_top.v/1.6/Mon Mar 15 17:46:04 2004//
+/wb_master_model.v/1.1.1.1/Wed Jun 12 15:45:23 2002//
+D
diff --git a/fpga/usrp2/opencores/spi/bench/verilog/CVS/Repository b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Repository
new file mode 100644
index 000000000..78a3c4a9f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Repository
@@ -0,0 +1 @@
+spi/bench/verilog
diff --git a/fpga/usrp2/opencores/spi/bench/verilog/CVS/Root b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/bench/verilog/CVS/Template b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v b/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v
new file mode 100644
index 000000000..dfdaed929
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/verilog/spi_slave_model.v
@@ -0,0 +1,73 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_slave_model.v                                           ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module spi_slave_model (rst, ss, sclk, mosi, miso);
+
+  input         rst;            // reset
+  input         ss;             // slave select
+  input         sclk;           // serial clock
+  input         mosi;           // master out slave in
+  output        miso;           // master in slave out
+
+  reg           miso;
+
+  reg           rx_negedge;     // slave receiving on negedge
+  reg           tx_negedge;     // slave transmiting on negedge
+  reg    [31:0] data;           // data register
+
+  parameter     Tp = 1;
+
+  always @(posedge(sclk && !rx_negedge) or negedge(sclk && rx_negedge) or rst)
+  begin
+    if (rst)
+      data <= #Tp 32'b0;
+    else if (!ss)
+      data <= #Tp {data[30:0], mosi};
+  end
+
+  always @(posedge(sclk && !tx_negedge) or negedge(sclk && tx_negedge))
+  begin
+    miso <= #Tp data[31];
+  end
+
+endmodule
+      
diff --git a/fpga/usrp2/opencores/spi/bench/verilog/tb_spi_top.v b/fpga/usrp2/opencores/spi/bench/verilog/tb_spi_top.v
new file mode 100644
index 000000000..529c0aca1
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/verilog/tb_spi_top.v
@@ -0,0 +1,339 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  tb_spi_top.v                                                ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  Based on:                                                   ////
+////      - i2c/bench/verilog/tst_bench_top.v                     ////
+////        Copyright (C) 2001 Richard Herveille                  ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module tb_spi_top();
+
+  reg         clk;
+  reg         rst;
+  wire [31:0] adr;
+  wire [31:0] dat_i, dat_o;
+  wire        we;
+  wire  [3:0] sel;
+  wire        stb;
+  wire        cyc;
+  wire        ack;
+  wire        err;
+  wire        int;
+
+  wire  [7:0] ss;
+  wire        sclk;
+  wire        mosi;
+  wire        miso;
+
+  reg  [31:0] q;
+  reg  [31:0] q1;
+  reg  [31:0] q2;
+  reg  [31:0] q3;
+  reg  [31:0] result;
+
+  parameter SPI_RX_0   = 5'h0;
+  parameter SPI_RX_1   = 5'h4;
+  parameter SPI_RX_2   = 5'h8;
+  parameter SPI_RX_3   = 5'hc;
+  parameter SPI_TX_0   = 5'h0;
+  parameter SPI_TX_1   = 5'h4;
+  parameter SPI_TX_2   = 5'h8;
+  parameter SPI_TX_3   = 5'hc;
+  parameter SPI_CTRL   = 5'h10;
+  parameter SPI_DIVIDE = 5'h14;
+  parameter SPI_SS     = 5'h18;
+
+  // Generate clock
+  always #5 clk = ~clk;
+
+  // Wishbone master model
+  wb_master_model #(32, 32) i_wb_master (
+    .clk(clk), .rst(rst),
+    .adr(adr), .din(dat_i), .dout(dat_o),
+    .cyc(cyc), .stb(stb), .we(we), .sel(sel), .ack(ack), .err(err), .rty(1'b0)
+  );
+
+  // SPI master core
+  spi_top i_spi_top (
+    .wb_clk_i(clk), .wb_rst_i(rst), 
+    .wb_adr_i(adr[4:0]), .wb_dat_i(dat_o), .wb_dat_o(dat_i), 
+    .wb_sel_i(sel), .wb_we_i(we), .wb_stb_i(stb), 
+    .wb_cyc_i(cyc), .wb_ack_o(ack), .wb_err_o(err), .wb_int_o(int),
+    .ss_pad_o(ss), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) 
+  );
+
+  // SPI slave model
+  spi_slave_model i_spi_slave (
+    .rst(rst), .ss(ss[0]), .sclk(sclk), .mosi(mosi), .miso(miso)
+  );
+
+  initial
+    begin
+      $display("\nstatus: %t Testbench started\n\n", $time);
+
+      $dumpfile("bench.vcd");
+      $dumpvars(1, tb_spi_top);
+      $dumpvars(1, tb_spi_top.i_spi_slave);
+
+      // Initial values
+      clk = 0;
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b0;
+
+      result = 32'h0;
+
+      // Reset system
+      rst = 1'b0; // negate reset
+      #2;
+      rst = 1'b1; // assert reset
+      repeat(20) @(posedge clk);
+      rst = 1'b0; // negate reset
+
+      $display("status: %t done reset", $time);
+      
+      @(posedge clk);
+
+      // Program core
+      i_wb_master.wb_write(0, SPI_DIVIDE, 32'h00); // set devider register
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h5a);   // set tx register to 0x5a
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h208);   // set 8 bit transfer
+      i_wb_master.wb_write(0, SPI_SS, 32'h01);     // set ss 0
+
+      $display("status: %t programmed registers", $time);
+
+      i_wb_master.wb_cmp(0, SPI_DIVIDE, 32'h00);   // verify devider register
+      i_wb_master.wb_cmp(0, SPI_TX_0, 32'h5a);     // verify tx register
+      i_wb_master.wb_cmp(0, SPI_CTRL, 32'h208);     // verify tx register
+      i_wb_master.wb_cmp(0, SPI_SS, 32'h01);       // verify ss register
+
+      $display("status: %t verified registers", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_spi_slave.data[31:0] = 32'ha5967e5a;
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h308);   // set 8 bit transfer, start transfer
+
+      $display("status: %t generate transfer:  8 bit, msb first, tx posedge, rx negedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      if (i_spi_slave.data[7:0] == 8'h5a && q == 32'h000000a5)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'ha5);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h408);   // set 8 bit transfer, tx negedge
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h508);   // set 8 bit transfer, tx negedge, start transfer
+
+      $display("status: %t generate transfer:  8 bit, msb first, tx negedge, rx posedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      if (i_spi_slave.data[7:0] == 8'ha5 && q == 32'h00000096)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h5aa5);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'hc10);   // set 16 bit transfer, tx negedge, lsb
+      i_wb_master.wb_write(0, SPI_CTRL, 32'hd10);   // set 16 bit transfer, tx negedge, start transfer
+
+      $display("status: %t generate transfer: 16 bit, lsb first, tx negedge, rx posedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      if (i_spi_slave.data[15:0] == 16'ha55a && q == 32'h00005a7e)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h76543210);
+      i_wb_master.wb_write(0, SPI_TX_1, 32'hfedcba98);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1a40);   // set 64 bit transfer, rx negedge, lsb
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1b40);   // set 64 bit transfer, rx negedge, start transfer
+
+      $display("status: %t generate transfer: 64 bit, lsb first, tx posedge, rx negedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+      i_wb_master.wb_read(1, SPI_RX_1, q1);
+      result = result + q1;
+
+      if (i_spi_slave.data == 32'h195d3b7f && q == 32'h5aa5a55a && q1 == 32'h76543210)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'hccddeeff);
+      i_wb_master.wb_write(0, SPI_TX_1, 32'h8899aabb);
+      i_wb_master.wb_write(0, SPI_TX_2, 32'h44556677);
+      i_wb_master.wb_write(0, SPI_TX_3, 32'h00112233);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h400);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h500);
+
+      $display("status: %t generate transfer: 128 bit, msb first, tx posedge, rx negedge", $time);
+
+      // Check bsy bit
+      i_wb_master.wb_read(0, SPI_CTRL, q);
+      while (q[8])
+        i_wb_master.wb_read(1, SPI_CTRL, q);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+      i_wb_master.wb_read(1, SPI_RX_1, q1);
+      result = result + q1;
+      i_wb_master.wb_read(1, SPI_RX_2, q2);
+      result = result + q2;
+      i_wb_master.wb_read(1, SPI_RX_3, q3);
+      result = result + q3;
+
+      if (i_spi_slave.data == 32'hccddeeff && q == 32'h8899aabb && q1 == 32'h44556677 && q2 == 32'h00112233 && q3 == 32'h195d3b7f)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b0;
+      i_spi_slave.tx_negedge = 1'b1;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'haa55a5a5);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1420);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h1520);
+
+      $display("status: %t generate transfer: 32 bit, msb first, tx negedge, rx posedge, ie", $time);
+
+      // Check interrupt signal
+      while (!int)
+        @(posedge clk);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+    
+      @(posedge clk);
+      if (!int && i_spi_slave.data == 32'haa55a5a5 && q == 32'hccddeeff)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h01248421);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3220);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3320);
+
+      $display("status: %t generate transfer: 32 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
+
+      while (!int)
+        @(posedge clk);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      @(posedge clk);
+      if (!int && i_spi_slave.data == 32'h01248421 && q == 32'haa55a5a5)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      i_spi_slave.rx_negedge = 1'b1;
+      i_spi_slave.tx_negedge = 1'b0;
+      i_wb_master.wb_write(0, SPI_TX_0, 32'h1);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3201);
+      i_wb_master.wb_write(0, SPI_CTRL, 32'h3301);
+
+      $display("status: %t generate transfer: 1 bit, msb first, tx posedge, rx negedge, ie, ass", $time);
+
+      while (!int)
+        @(posedge clk);
+
+      i_wb_master.wb_read(1, SPI_RX_0, q);
+      result = result + q;
+
+      @(posedge clk);
+      if (!int && i_spi_slave.data == 32'h02490843 && q == 32'h0)
+        $display("status: %t transfer completed: ok", $time);
+      else
+        $display("status: %t transfer completed: nok", $time);
+
+      $display("\n\nstatus: %t Testbench done", $time);
+
+      #25000; // wait 25us
+
+      $display("report (%h)", (result ^ 32'h2e8b36ab) + 32'hdeaddead);
+      $display("exit (%h)", result ^ 32'h2e8b36ab);
+
+      $stop;
+    end
+
+endmodule
+
+
diff --git a/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v b/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v
new file mode 100644
index 000000000..3f8b7ee6a
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/bench/verilog/wb_master_model.v
@@ -0,0 +1,176 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  wb_master_model.v                                           ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  Based on:                                                   ////
+////      - i2c/bench/verilog/wb_master_model.v                   ////
+////        Copyright (C) 2001 Richard Herveille                  ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "timescale.v"
+
+module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
+
+  parameter dwidth = 32;
+  parameter awidth = 32;
+  
+  input                  clk, rst;
+  output [awidth   -1:0] adr;
+  input  [dwidth   -1:0] din;
+  output [dwidth   -1:0] dout;
+  output                 cyc, stb;
+  output                 we;
+  output [dwidth/8 -1:0] sel;
+  input                  ack, err, rty;
+  
+  // Internal signals
+  reg    [awidth   -1:0] adr;
+  reg    [dwidth   -1:0] dout;
+  reg                    cyc, stb;
+  reg                    we;
+  reg    [dwidth/8 -1:0] sel;
+         
+  reg    [dwidth   -1:0] q;
+  
+  // Memory Logic
+  initial
+    begin
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      #1;
+    end
+  
+  // Wishbone write cycle
+  task wb_write;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signal
+      #1;
+      adr  = a;
+      dout = d;
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b1;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+  
+    end
+  endtask
+  
+  // Wishbone read cycle
+  task wb_read;
+    input   delay;
+    integer delay;
+  
+    input  [awidth -1:0]  a;
+    output  [dwidth -1:0] d;
+  
+    begin
+  
+      // wait initial delay
+      repeat(delay) @(posedge clk);
+  
+      // assert wishbone signals
+      #1;
+      adr  = a;
+      dout = {dwidth{1'bx}};
+      cyc  = 1'b1;
+      stb  = 1'b1;
+      we   = 1'b0;
+      sel  = {dwidth/8{1'b1}};
+      @(posedge clk);
+  
+      // wait for acknowledge from slave
+      while(~ack) @(posedge clk);
+  
+      // negate wishbone signals
+      #1;
+      cyc  = 1'b0;
+      stb  = 1'bx;
+      adr  = {awidth{1'bx}};
+      dout = {dwidth{1'bx}};
+      we   = 1'hx;
+      sel  = {dwidth/8{1'bx}};
+      d    = din;
+  
+    end
+  endtask
+  
+  // Wishbone compare cycle (read data from location and compare with expected data)
+  task wb_cmp;
+    input   delay;
+    integer delay;
+  
+    input [awidth -1:0] a;
+    input [dwidth -1:0] d_exp;
+  
+    begin
+      wb_read (delay, a, q);
+
+    if (d_exp !== q)
+      $display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
+    end
+  endtask
+  
+endmodule
+ 
diff --git a/fpga/usrp2/opencores/spi/doc/CVS/Entries b/fpga/usrp2/opencores/spi/doc/CVS/Entries
new file mode 100644
index 000000000..ff33fa590
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/CVS/Entries
@@ -0,0 +1,2 @@
+/spi.pdf/1.5/Mon Mar 15 17:46:05 2004/-kb/
+D/src////
diff --git a/fpga/usrp2/opencores/spi/doc/CVS/Repository b/fpga/usrp2/opencores/spi/doc/CVS/Repository
new file mode 100644
index 000000000..772adcef5
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/CVS/Repository
@@ -0,0 +1 @@
+spi/doc
diff --git a/fpga/usrp2/opencores/spi/doc/CVS/Root b/fpga/usrp2/opencores/spi/doc/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/doc/CVS/Template b/fpga/usrp2/opencores/spi/doc/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/doc/spi.pdf b/fpga/usrp2/opencores/spi/doc/spi.pdf
new file mode 100644
index 000000000..d88ee2807
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/spi.pdf
diff --git a/fpga/usrp2/opencores/spi/doc/src/CVS/Entries b/fpga/usrp2/opencores/spi/doc/src/CVS/Entries
new file mode 100644
index 000000000..adcbf083d
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/src/CVS/Entries
@@ -0,0 +1,2 @@
+/spi.doc/1.7/Mon Mar 15 17:46:06 2004/-kb/
+D
diff --git a/fpga/usrp2/opencores/spi/doc/src/CVS/Repository b/fpga/usrp2/opencores/spi/doc/src/CVS/Repository
new file mode 100644
index 000000000..09b1f4a98
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/src/CVS/Repository
@@ -0,0 +1 @@
+spi/doc/src
diff --git a/fpga/usrp2/opencores/spi/doc/src/CVS/Root b/fpga/usrp2/opencores/spi/doc/src/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/src/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/doc/src/CVS/Template b/fpga/usrp2/opencores/spi/doc/src/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/src/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/doc/src/spi.doc b/fpga/usrp2/opencores/spi/doc/src/spi.doc
new file mode 100755
index 000000000..b04700177
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/doc/src/spi.doc
diff --git a/fpga/usrp2/opencores/spi/rtl/CVS/Entries b/fpga/usrp2/opencores/spi/rtl/CVS/Entries
new file mode 100644
index 000000000..428c5622d
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/CVS/Entries
@@ -0,0 +1 @@
+D/verilog////
diff --git a/fpga/usrp2/opencores/spi/rtl/CVS/Repository b/fpga/usrp2/opencores/spi/rtl/CVS/Repository
new file mode 100644
index 000000000..5fd79b19b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/CVS/Repository
@@ -0,0 +1 @@
+spi/rtl
diff --git a/fpga/usrp2/opencores/spi/rtl/CVS/Root b/fpga/usrp2/opencores/spi/rtl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/rtl/CVS/Template b/fpga/usrp2/opencores/spi/rtl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Entries b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Entries
new file mode 100644
index 000000000..d125a1657
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Entries
@@ -0,0 +1,6 @@
+/spi_clgen.v/1.3/Thu Jul  3 17:32:15 2003//
+/spi_defines.v/1.8/Mon Mar 15 17:46:08 2004//
+/spi_shift.v/1.7/Tue Jul  8 15:36:37 2003//
+/spi_top.v/1.8/Tue Jul  8 15:36:37 2003//
+/timescale.v/1.1.1.1/Wed Jun 12 15:45:23 2002//
+D
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Repository b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Repository
new file mode 100644
index 000000000..361b93bf8
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Repository
@@ -0,0 +1 @@
+spi/rtl/verilog
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Root b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Template b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
new file mode 100644
index 000000000..7bc4f6e5e
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_clgen.v
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_clgen.v                                                 ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "spi_defines.v"
+`include "timescale.v"
+
+module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge); 
+
+  parameter Tp = 1;
+  
+  input                            clk_in;   // input clock (system clock)
+  input                            rst;      // reset
+  input                            enable;   // clock enable
+  input                            go;       // start transfer
+  input                            last_clk; // last clock
+  input     [`SPI_DIVIDER_LEN-1:0] divider;  // clock divider (output clock is divided by this value)
+  output                           clk_out;  // output clock
+  output                           pos_edge; // pulse marking positive edge of clk_out
+  output                           neg_edge; // pulse marking negative edge of clk_out
+                            
+  reg                              clk_out;
+  reg                              pos_edge;
+  reg                              neg_edge;
+                            
+  reg       [`SPI_DIVIDER_LEN-1:0] cnt;      // clock counter 
+  wire                             cnt_zero; // conter is equal to zero
+  wire                             cnt_one;  // conter is equal to one
+  
+  
+  assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
+  assign cnt_one  = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+  
+  // Counter counts half period
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
+    else
+      begin
+        if(!enable || cnt_zero)
+          cnt <= #Tp divider;
+        else
+          cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
+      end
+  end
+  
+  // clk_out is asserted every other half period
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      clk_out <= #Tp 1'b0;
+    else
+      clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
+  end
+   
+  // Pos and neg edge signals
+  always @(posedge clk_in or posedge rst)
+  begin
+    if(rst)
+      begin
+        pos_edge  <= #Tp 1'b0;
+        neg_edge  <= #Tp 1'b0;
+      end
+    else
+      begin
+        pos_edge  <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
+        neg_edge  <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
+      end
+  end
+endmodule
+ 
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
new file mode 100644
index 000000000..a6925918e
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -0,0 +1,159 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_define.v                                                ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+//
+// Number of bits used for devider register. If used in system with
+// low frequency of system clock this can be reduced.
+// Use SPI_DIVIDER_LEN for fine tuning theexact number.
+//
+//`define SPI_DIVIDER_LEN_8
+`define SPI_DIVIDER_LEN_16
+//`define SPI_DIVIDER_LEN_24
+//`define SPI_DIVIDER_LEN_32
+
+`ifdef SPI_DIVIDER_LEN_8
+  `define SPI_DIVIDER_LEN       8    // Can be set from 1 to 8
+`endif                                                          
+`ifdef SPI_DIVIDER_LEN_16                                       
+  `define SPI_DIVIDER_LEN       16   // Can be set from 9 to 16
+`endif                                                          
+`ifdef SPI_DIVIDER_LEN_24                                       
+  `define SPI_DIVIDER_LEN       24   // Can be set from 17 to 24
+`endif                                                          
+`ifdef SPI_DIVIDER_LEN_32                                       
+  `define SPI_DIVIDER_LEN       32   // Can be set from 25 to 32 
+`endif
+
+//
+// Maximum nuber of bits that can be send/received at once. 
+// Use SPI_MAX_CHAR for fine tuning the exact number, when using
+// SPI_MAX_CHAR_32, SPI_MAX_CHAR_24, SPI_MAX_CHAR_16, SPI_MAX_CHAR_8.
+//
+`define SPI_MAX_CHAR_128
+//`define SPI_MAX_CHAR_64
+//`define SPI_MAX_CHAR_32
+//`define SPI_MAX_CHAR_24
+//`define SPI_MAX_CHAR_16
+//`define SPI_MAX_CHAR_8
+
+`ifdef SPI_MAX_CHAR_128
+  `define SPI_MAX_CHAR          128  // Can only be set to 128 
+  `define SPI_CHAR_LEN_BITS     7
+`endif
+`ifdef SPI_MAX_CHAR_64
+  `define SPI_MAX_CHAR          64   // Can only be set to 64 
+  `define SPI_CHAR_LEN_BITS     6
+`endif
+`ifdef SPI_MAX_CHAR_32
+  `define SPI_MAX_CHAR          32   // Can be set from 25 to 32 
+  `define SPI_CHAR_LEN_BITS     5
+`endif
+`ifdef SPI_MAX_CHAR_24
+  `define SPI_MAX_CHAR          24   // Can be set from 17 to 24 
+  `define SPI_CHAR_LEN_BITS     5
+`endif
+`ifdef SPI_MAX_CHAR_16
+  `define SPI_MAX_CHAR          16   // Can be set from 9 to 16 
+  `define SPI_CHAR_LEN_BITS     4
+`endif
+`ifdef SPI_MAX_CHAR_8
+  `define SPI_MAX_CHAR          8    // Can be set from 1 to 8 
+  `define SPI_CHAR_LEN_BITS     3
+`endif
+
+//
+// Number of device select signals. Use SPI_SS_NB for fine tuning the 
+// exact number.
+//
+`define SPI_SS_NB_8
+//`define SPI_SS_NB_16
+//`define SPI_SS_NB_24
+//`define SPI_SS_NB_32
+
+`ifdef SPI_SS_NB_8
+  `define SPI_SS_NB             8    // Can be set from 1 to 8
+`endif
+`ifdef SPI_SS_NB_16
+  `define SPI_SS_NB             16   // Can be set from 9 to 16
+`endif
+`ifdef SPI_SS_NB_24
+  `define SPI_SS_NB             24   // Can be set from 17 to 24
+`endif
+`ifdef SPI_SS_NB_32
+  `define SPI_SS_NB             32   // Can be set from 25 to 32
+`endif
+
+//
+// Bits of WISHBONE address used for partial decoding of SPI registers.
+//
+`define SPI_OFS_BITS	          4:2
+
+//
+// Register offset
+//
+`define SPI_RX_0                0
+`define SPI_RX_1                1
+`define SPI_RX_2                2
+`define SPI_RX_3                3
+`define SPI_TX_0                0
+`define SPI_TX_1                1
+`define SPI_TX_2                2
+`define SPI_TX_3                3
+`define SPI_CTRL                4
+`define SPI_DEVIDE              5
+`define SPI_SS                  6
+
+//
+// Number of bits in ctrl register
+//
+`define SPI_CTRL_BIT_NB         14
+
+//
+// Control register bit position
+//
+`define SPI_CTRL_ASS            13
+`define SPI_CTRL_IE             12
+`define SPI_CTRL_LSB            11
+`define SPI_CTRL_TX_NEGEDGE     10
+`define SPI_CTRL_RX_NEGEDGE     9
+`define SPI_CTRL_GO             8
+`define SPI_CTRL_RES_1          7
+`define SPI_CTRL_CHAR_LEN       6:0
+
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
new file mode 100644
index 000000000..b17ac8b1f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_shift.v
@@ -0,0 +1,238 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_shift.v                                                 ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+`include "spi_defines.v"
+`include "timescale.v"
+
+module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
+                  pos_edge, neg_edge, rx_negedge, tx_negedge,
+                  tip, last, 
+                  p_in, p_out, s_clk, s_in, s_out);
+
+  parameter Tp = 1;
+  
+  input                          clk;          // system clock
+  input                          rst;          // reset
+  input                    [3:0] latch;        // latch signal for storing the data in shift register
+  input                    [3:0] byte_sel;     // byte select signals for storing the data in shift register
+  input [`SPI_CHAR_LEN_BITS-1:0] len;          // data len in bits (minus one)
+  input                          lsb;          // lbs first on the line
+  input                          go;           // start stansfer
+  input                          pos_edge;     // recognize posedge of sclk
+  input                          neg_edge;     // recognize negedge of sclk
+  input                          rx_negedge;   // s_in is sampled on negative edge 
+  input                          tx_negedge;   // s_out is driven on negative edge
+  output                         tip;          // transfer in progress
+  output                         last;         // last bit
+  input                   [31:0] p_in;         // parallel in
+  output     [`SPI_MAX_CHAR-1:0] p_out;        // parallel out
+  input                          s_clk;        // serial clock
+  input                          s_in;         // serial in
+  output                         s_out;        // serial out
+                                               
+  reg                            s_out;        
+  reg                            tip;
+                              
+  reg     [`SPI_CHAR_LEN_BITS:0] cnt;          // data bit count
+  reg        [`SPI_MAX_CHAR-1:0] data;         // shift register
+  wire    [`SPI_CHAR_LEN_BITS:0] tx_bit_pos;   // next bit position
+  wire    [`SPI_CHAR_LEN_BITS:0] rx_bit_pos;   // next bit position
+  wire                           rx_clk;       // rx clock enable
+  wire                           tx_clk;       // tx clock enable
+  
+  assign p_out = data;
+  
+  assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
+  assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) : 
+                            (rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
+  
+  assign last = !(|cnt);
+  
+  assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
+  assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
+  
+  // Character bit counter
+  always @(posedge clk or posedge rst)
+  begin
+    if(rst)
+      cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
+    else
+      begin
+        if(tip)
+          cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
+        else
+          cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
+      end
+  end
+  
+  // Transfer in progress
+  always @(posedge clk or posedge rst)
+  begin
+    if(rst)
+      tip <= #Tp 1'b0;
+  else if(go && ~tip)
+    tip <= #Tp 1'b1;
+  else if(tip && last && pos_edge)
+    tip <= #Tp 1'b0;
+  end
+  
+  // Sending bits to the line
+  always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      s_out   <= #Tp 1'b0;
+    else
+      s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
+  end
+  
+  // Receiving bits from the line
+  always @(posedge clk or posedge rst)
+  begin
+    if (rst)
+      data   <= #Tp {`SPI_MAX_CHAR{1'b0}};
+`ifdef SPI_MAX_CHAR_128
+    else if (latch[0] && !tip)
+      begin
+        if (byte_sel[3])
+          data[31:24] <= #Tp p_in[31:24];
+        if (byte_sel[2])
+          data[23:16] <= #Tp p_in[23:16];
+        if (byte_sel[1])
+          data[15:8] <= #Tp p_in[15:8];
+        if (byte_sel[0])
+          data[7:0] <= #Tp p_in[7:0];
+      end
+    else if (latch[1] && !tip)
+      begin
+        if (byte_sel[3])
+          data[63:56] <= #Tp p_in[31:24];
+        if (byte_sel[2])
+          data[55:48] <= #Tp p_in[23:16];
+        if (byte_sel[1])
+          data[47:40] <= #Tp p_in[15:8];
+        if (byte_sel[0])
+          data[39:32] <= #Tp p_in[7:0];
+      end
+    else if (latch[2] && !tip)
+      begin
+        if (byte_sel[3])
+          data[95:88] <= #Tp p_in[31:24];
+        if (byte_sel[2])
+          data[87:80] <= #Tp p_in[23:16];
+        if (byte_sel[1])
+          data[79:72] <= #Tp p_in[15:8];
+        if (byte_sel[0])
+          data[71:64] <= #Tp p_in[7:0];
+      end
+    else if (latch[3] && !tip)
+      begin
+        if (byte_sel[3])
+          data[127:120] <= #Tp p_in[31:24];
+        if (byte_sel[2])
+          data[119:112] <= #Tp p_in[23:16];
+        if (byte_sel[1])
+          data[111:104] <= #Tp p_in[15:8];
+        if (byte_sel[0])
+          data[103:96] <= #Tp p_in[7:0];
+      end
+`else
+`ifdef SPI_MAX_CHAR_64
+    else if (latch[0] && !tip)
+      begin
+        if (byte_sel[3])
+          data[31:24] <= #Tp p_in[31:24];
+        if (byte_sel[2])
+          data[23:16] <= #Tp p_in[23:16];
+        if (byte_sel[1])
+          data[15:8] <= #Tp p_in[15:8];
+        if (byte_sel[0])
+          data[7:0] <= #Tp p_in[7:0];
+      end
+    else if (latch[1] && !tip)
+      begin
+        if (byte_sel[3])
+          data[63:56] <= #Tp p_in[31:24];
+        if (byte_sel[2])
+          data[55:48] <= #Tp p_in[23:16];
+        if (byte_sel[1])
+          data[47:40] <= #Tp p_in[15:8];
+        if (byte_sel[0])
+          data[39:32] <= #Tp p_in[7:0];
+      end
+`else
+    else if (latch[0] && !tip)
+      begin
+      `ifdef SPI_MAX_CHAR_8
+        if (byte_sel[0])
+          data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
+      `endif
+      `ifdef SPI_MAX_CHAR_16
+        if (byte_sel[0])
+          data[7:0] <= #Tp p_in[7:0];
+        if (byte_sel[1])
+          data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
+      `endif
+      `ifdef SPI_MAX_CHAR_24
+        if (byte_sel[0])
+          data[7:0] <= #Tp p_in[7:0];
+        if (byte_sel[1])
+          data[15:8] <= #Tp p_in[15:8];
+        if (byte_sel[2])
+          data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
+      `endif
+      `ifdef SPI_MAX_CHAR_32
+        if (byte_sel[0])
+          data[7:0] <= #Tp p_in[7:0];
+        if (byte_sel[1])
+          data[15:8] <= #Tp p_in[15:8];
+        if (byte_sel[2])
+          data[23:16] <= #Tp p_in[23:16];
+        if (byte_sel[3])
+          data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
+      `endif
+      end
+`endif
+`endif
+    else
+      data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
+  end
+  
+endmodule
+
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
new file mode 100644
index 000000000..09b2e50e1
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/spi_top.v
@@ -0,0 +1,287 @@
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+////  spi_top.v                                                   ////
+////                                                              ////
+////  This file is part of the SPI IP core project                ////
+////  http://www.opencores.org/projects/spi/                      ////
+////                                                              ////
+////  Author(s):                                                  ////
+////      - Simon Srot (simons@opencores.org)                     ////
+////                                                              ////
+////  All additional information is avaliable in the Readme.txt   ////
+////  file.                                                       ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+////                                                              ////
+//// Copyright (C) 2002 Authors                                   ////
+////                                                              ////
+//// This source file may be used and distributed without         ////
+//// restriction provided that this copyright statement is not    ////
+//// removed from the file and that any derivative work contains  ////
+//// the original copyright notice and the associated disclaimer. ////
+////                                                              ////
+//// This source file is free software; you can redistribute it   ////
+//// and/or modify it under the terms of the GNU Lesser General   ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any   ////
+//// later version.                                               ////
+////                                                              ////
+//// This source is distributed in the hope that it will be       ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
+//// PURPOSE.  See the GNU Lesser General Public License for more ////
+//// details.                                                     ////
+////                                                              ////
+//// You should have received a copy of the GNU Lesser General    ////
+//// Public License along with this source; if not, download it   ////
+//// from http://www.opencores.org/lgpl.shtml                     ////
+////                                                              ////
+//////////////////////////////////////////////////////////////////////
+
+
+`include "spi_defines.v"
+`include "timescale.v"
+
+module spi_top
+(
+  // Wishbone signals
+  wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
+  wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o,
+
+  // SPI signals
+  ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
+);
+
+  parameter Tp = 1;
+
+  // Wishbone signals
+  input                            wb_clk_i;         // master clock input
+  input                            wb_rst_i;         // synchronous active high reset
+  input                      [4:0] wb_adr_i;         // lower address bits
+  input                   [32-1:0] wb_dat_i;         // databus input
+  output                  [32-1:0] wb_dat_o;         // databus output
+  input                      [3:0] wb_sel_i;         // byte select inputs
+  input                            wb_we_i;          // write enable input
+  input                            wb_stb_i;         // stobe/core select signal
+  input                            wb_cyc_i;         // valid bus cycle input
+  output                           wb_ack_o;         // bus cycle acknowledge output
+  output                           wb_err_o;         // termination w/ error
+  output                           wb_int_o;         // interrupt request signal output
+                                                     
+  // SPI signals                                     
+  output          [`SPI_SS_NB-1:0] ss_pad_o;         // slave select
+  output                           sclk_pad_o;       // serial clock
+  output                           mosi_pad_o;       // master out slave in
+  input                            miso_pad_i;       // master in slave out
+                                                     
+  reg                     [32-1:0] wb_dat_o;
+  reg                              wb_ack_o;
+  reg                              wb_int_o;
+                                               
+  // Internal signals
+  reg       [`SPI_DIVIDER_LEN-1:0] divider;          // Divider register
+  reg       [`SPI_CTRL_BIT_NB-1:0] ctrl;             // Control and status register
+  reg             [`SPI_SS_NB-1:0] ss;               // Slave select register
+  reg                     [32-1:0] wb_dat;           // wb data out
+  wire         [`SPI_MAX_CHAR-1:0] rx;               // Rx register
+  wire                             rx_negedge;       // miso is sampled on negative edge
+  wire                             tx_negedge;       // mosi is driven on negative edge
+  wire    [`SPI_CHAR_LEN_BITS-1:0] char_len;         // char len
+  wire                             go;               // go
+  wire                             lsb;              // lsb first on line
+  wire                             ie;               // interrupt enable
+  wire                             ass;              // automatic slave select
+  wire                             spi_divider_sel;  // divider register select
+  wire                             spi_ctrl_sel;     // ctrl register select
+  wire                       [3:0] spi_tx_sel;       // tx_l register select
+  wire                             spi_ss_sel;       // ss register select
+  wire                             tip;              // transfer in progress
+  wire                             pos_edge;         // recognize posedge of sclk
+  wire                             neg_edge;         // recognize negedge of sclk
+  wire                             last_bit;         // marks last character bit
+  
+  // Address decoder
+  assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE);
+  assign spi_ctrl_sel    = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
+  assign spi_tx_sel[0]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
+  assign spi_tx_sel[1]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1);
+  assign spi_tx_sel[2]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2);
+  assign spi_tx_sel[3]   = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3);
+  assign spi_ss_sel      = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
+  
+  // Read from registers
+  always @(wb_adr_i or rx or ctrl or divider or ss)
+  begin
+    case (wb_adr_i[`SPI_OFS_BITS])
+`ifdef SPI_MAX_CHAR_128
+      `SPI_RX_0:    wb_dat = rx[31:0];
+      `SPI_RX_1:    wb_dat = rx[63:32];
+      `SPI_RX_2:    wb_dat = rx[95:64];
+      `SPI_RX_3:    wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]};
+`else
+`ifdef SPI_MAX_CHAR_64
+      `SPI_RX_0:    wb_dat = rx[31:0];
+      `SPI_RX_1:    wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]};
+      `SPI_RX_2:    wb_dat = 32'b0;
+      `SPI_RX_3:    wb_dat = 32'b0;
+`else
+      `SPI_RX_0:    wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]};
+      `SPI_RX_1:    wb_dat = 32'b0;
+      `SPI_RX_2:    wb_dat = 32'b0;
+      `SPI_RX_3:    wb_dat = 32'b0;
+`endif
+`endif
+      `SPI_CTRL:    wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
+      `SPI_DEVIDE:  wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
+      `SPI_SS:      wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
+      default:      wb_dat = 32'bx;
+    endcase
+  end
+  
+  // Wb data out
+  always @(posedge wb_clk_i or posedge wb_rst_i)
+  begin
+    if (wb_rst_i)
+      wb_dat_o <= #Tp 32'b0;
+    else
+      wb_dat_o <= #Tp wb_dat;
+  end
+  
+  // Wb acknowledge
+  always @(posedge wb_clk_i or posedge wb_rst_i)
+  begin
+    if (wb_rst_i)
+      wb_ack_o <= #Tp 1'b0;
+    else
+      wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
+  end
+  
+  // Wb error
+  assign wb_err_o = 1'b0;
+  
+  // Interrupt
+  always @(posedge wb_clk_i or posedge wb_rst_i)
+  begin
+    if (wb_rst_i)
+      wb_int_o <= #Tp 1'b0;
+    else if (ie && tip && last_bit && pos_edge)
+      wb_int_o <= #Tp 1'b1;
+    else if (wb_ack_o)
+      wb_int_o <= #Tp 1'b0;
+  end
+  
+  // Divider register
+  always @(posedge wb_clk_i or posedge wb_rst_i)
+  begin
+    if (wb_rst_i)
+        divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
+    else if (spi_divider_sel && wb_we_i && !tip)
+      begin
+      `ifdef SPI_DIVIDER_LEN_8
+        if (wb_sel_i[0])
+          divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
+      `endif
+      `ifdef SPI_DIVIDER_LEN_16
+        if (wb_sel_i[0])
+          divider[7:0] <= #Tp wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
+      `endif
+      `ifdef SPI_DIVIDER_LEN_24
+        if (wb_sel_i[0])
+          divider[7:0] <= #Tp wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          divider[15:8] <= #Tp wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
+      `endif
+      `ifdef SPI_DIVIDER_LEN_32
+        if (wb_sel_i[0])
+          divider[7:0] <= #Tp wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          divider[15:8] <= #Tp wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          divider[23:16] <= #Tp wb_dat_i[23:16];
+        if (wb_sel_i[3])
+          divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
+      `endif
+      end
+  end
+  
+  // Ctrl register
+  always @(posedge wb_clk_i or posedge wb_rst_i)
+  begin
+    if (wb_rst_i)
+      ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
+    else if(spi_ctrl_sel && wb_we_i && !tip)
+      begin
+        if (wb_sel_i[0])
+          ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
+        if (wb_sel_i[1])
+          ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
+      end
+    else if(tip && last_bit && pos_edge)
+      ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
+  end
+  
+  assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
+  assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
+  assign go         = ctrl[`SPI_CTRL_GO];
+  assign char_len   = ctrl[`SPI_CTRL_CHAR_LEN];
+  assign lsb        = ctrl[`SPI_CTRL_LSB];
+  assign ie         = ctrl[`SPI_CTRL_IE];
+  assign ass        = ctrl[`SPI_CTRL_ASS];
+  
+  // Slave select register
+  always @(posedge wb_clk_i or posedge wb_rst_i)
+  begin
+    if (wb_rst_i)
+      ss <= #Tp {`SPI_SS_NB{1'b0}};
+    else if(spi_ss_sel && wb_we_i && !tip)
+      begin
+      `ifdef SPI_SS_NB_8
+        if (wb_sel_i[0])
+          ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
+      `endif
+      `ifdef SPI_SS_NB_16
+        if (wb_sel_i[0])
+          ss[7:0] <= #Tp wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
+      `endif
+      `ifdef SPI_SS_NB_24
+        if (wb_sel_i[0])
+          ss[7:0] <= #Tp wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          ss[15:8] <= #Tp wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
+      `endif
+      `ifdef SPI_SS_NB_32
+        if (wb_sel_i[0])
+          ss[7:0] <= #Tp wb_dat_i[7:0];
+        if (wb_sel_i[1])
+          ss[15:8] <= #Tp wb_dat_i[15:8];
+        if (wb_sel_i[2])
+          ss[23:16] <= #Tp wb_dat_i[23:16];
+        if (wb_sel_i[3])
+          ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
+      `endif
+      end
+  end
+  
+  assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
+  
+  spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
+                   .divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge), 
+                   .neg_edge(neg_edge));
+  
+  spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
+                   .latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb), 
+                   .go(go), .pos_edge(pos_edge), .neg_edge(neg_edge), 
+                   .rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
+                   .tip(tip), .last(last_bit), 
+                   .p_in(wb_dat_i), .p_out(rx), 
+                   .s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
+endmodule
+  
diff --git a/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v b/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v
new file mode 100644
index 000000000..60d4ecbd1
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/rtl/verilog/timescale.v
@@ -0,0 +1,2 @@
+`timescale 1ns / 10ps
+
diff --git a/fpga/usrp2/opencores/spi/sim/CVS/Entries b/fpga/usrp2/opencores/spi/sim/CVS/Entries
new file mode 100644
index 000000000..545533337
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/CVS/Entries
@@ -0,0 +1,2 @@
+D/rtl_sim////
+D/run////
diff --git a/fpga/usrp2/opencores/spi/sim/CVS/Repository b/fpga/usrp2/opencores/spi/sim/CVS/Repository
new file mode 100644
index 000000000..9ec769309
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/CVS/Repository
@@ -0,0 +1 @@
+spi/sim
diff --git a/fpga/usrp2/opencores/spi/sim/CVS/Root b/fpga/usrp2/opencores/spi/sim/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/sim/CVS/Template b/fpga/usrp2/opencores/spi/sim/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries
new file mode 100644
index 000000000..8ab9f73a7
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Entries
@@ -0,0 +1 @@
+D/run////
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository
new file mode 100644
index 000000000..c8c6a94c6
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Repository
@@ -0,0 +1 @@
+spi/sim/rtl_sim
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Root b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Template b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries
new file mode 100644
index 000000000..8947f64a0
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Entries
@@ -0,0 +1,4 @@
+/rtl.fl/1.1/Mon Mar 15 17:46:08 2004//
+/run_sim/1.1/Mon Mar 15 17:46:08 2004//
+/sim.fl/1.1/Mon Mar 15 17:46:08 2004//
+D
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository
new file mode 100644
index 000000000..5200bb196
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Repository
@@ -0,0 +1 @@
+spi/sim/rtl_sim/run
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/CVS/Template
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl
new file mode 100644
index 000000000..d84a0840d
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/rtl.fl
@@ -0,0 +1,3 @@
+spi_top.v
+spi_clgen.v
+spi_shift.v
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/run_sim b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/run_sim
new file mode 100755
index 000000000..1b13a35b9
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/run_sim
@@ -0,0 +1,108 @@
+#!/bin/csh -f
+
+set current_par = 0
+set output_waveform = 0
+while ( $current_par < $# )
+    @ current_par = $current_par + 1
+    case wave:
+        @ output_waveform = 1
+        breaksw
+    default:
+        echo 'Unknown option "'$argv[$current_par]'"!'
+        exit
+        breaksw
+    endsw
+end
+
+echo "TEST: spi"
+
+#echo "-CDSLIB ./cds.lib"               > ncvlog.args
+#echo "-HDLVAR ./hdl.var"              >> ncvlog.args
+echo "-MESSAGES"                       > ncvlog.args
+echo "-INCDIR ../../../bench/verilog" >> ncvlog.args
+echo "-INCDIR ../../../rtl/verilog"   >> ncvlog.args
+echo "-NOCOPYRIGHT"                   >> ncvlog.args
+echo "-UPDATE"                        >> ncvlog.args
+echo "-LOGFILE ncvlog.log"            >> ncvlog.args
+
+foreach filename ( `cat ./rtl.fl` )
+    echo "../../../rtl/verilog/"$filename >> ncvlog.args
+end
+
+foreach filename ( `cat ./sim.fl` )
+    echo "../../../bench/verilog/"$filename >> ncvlog.args
+end
+
+ncvlog -f ncvlog.args
+if ($status != 0) then
+  echo "STATUS: failed"
+  exit
+endif
+
+
+echo "-MESSAGES"                             > ncelab.args
+echo "-NOCOPYRIGHT"                         >> ncelab.args
+#echo "-CDSLIB ./cds.lib"                    >> ncelab.args
+#echo "-HDLVAR ./hdl.var"                    >> ncelab.args
+echo "-LOGFILE ncelab.log"                  >> ncelab.args
+echo "-SNAPSHOT worklib.tb_spi_top:v"       >> ncelab.args
+echo "-NOTIMINGCHECKS"                      >> ncelab.args
+echo "-ACCESS +RWC"                         >> ncelab.args
+echo "tb_spi_top"                           >> ncelab.args
+
+ncelab -f ncelab.args
+if ($status != 0) then
+  echo "STATUS: failed"
+  exit
+endif
+
+
+echo "-MESSAGES"                   > ncsim.args
+echo "-NOCOPYRIGHT"               >> ncsim.args
+#echo "-CDSLIB ./cds.lib"          >> ncsim.args
+#echo "-HDLVAR ./hdl.var"          >> ncsim.args
+echo "-INPUT ncsim.tcl"           >> ncsim.args
+echo "-LOGFILE ncsim.log"         >> ncsim.args
+echo "worklib.tb_spi_top:v"       >> ncsim.args
+
+if ( $output_waveform ) then
+    echo "database -open waves -shm -into ../out/wav"                         > ./ncsim.tcl
+    echo "probe -create -database waves -shm tb_spi_top -all -depth all"      >> ./ncsim.tcl
+    echo "stop -create -time 25000000 -relative"                              >> ./ncsim.tcl
+    echo "run"                                                                >> ./ncsim.tcl
+else
+    echo "stop -create -time 25000000 -relative"                              >> ./ncsim.tcl
+    echo "run"  > ./ncsim.tcl
+endif
+
+echo "exit" >> ncsim.tcl
+
+ncsim -LICQUEUE -f ./ncsim.args
+
+set exit_line_nb = `sed -n '/exit/=' < ./ncsim.log`
+
+set dead_line_nb = 0
+
+if ( $exit_line_nb ) then
+
+  @ dead_line_nb = $exit_line_nb - 1
+  set exit_line=`sed -n $exit_line_nb's/exit/&/gp' < ./ncsim.log`
+  set dead_line=`sed -n $dead_line_nb's/report/&/gp' < ./ncsim.log`
+
+  if ( "$dead_line" == "report (deaddead)" ) then
+    if ( "$exit_line" == "exit (00000000)"   ) then
+      echo "STATUS: passed"  #|tee -a ./run_sim.log 2>&1
+    else
+      echo "STATUS: failed"  #|tee -a ./run_sim.log 2>&1
+    endif
+  else
+    echo "STATUS: failed"
+  endif
+
+endif
+
+exit
+
+
+
+
diff --git a/fpga/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl
new file mode 100644
index 000000000..283aad1f8
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/rtl_sim/run/sim.fl
@@ -0,0 +1,3 @@
+tb_spi_top.v
+wb_master_model.v
+spi_slave_model.v
diff --git a/fpga/usrp2/opencores/spi/sim/run/CVS/Entries b/fpga/usrp2/opencores/spi/sim/run/CVS/Entries
new file mode 100644
index 000000000..178481050
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/run/CVS/Entries
@@ -0,0 +1 @@
+D
diff --git a/fpga/usrp2/opencores/spi/sim/run/CVS/Repository b/fpga/usrp2/opencores/spi/sim/run/CVS/Repository
new file mode 100644
index 000000000..e8646e70d
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/run/CVS/Repository
@@ -0,0 +1 @@
+spi/sim/run
diff --git a/fpga/usrp2/opencores/spi/sim/run/CVS/Root b/fpga/usrp2/opencores/spi/sim/run/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/run/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi/sim/run/CVS/Template b/fpga/usrp2/opencores/spi/sim/run/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi/sim/run/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/COMPILE_LIST b/fpga/usrp2/opencores/spi_boot/COMPILE_LIST
new file mode 100644
index 000000000..fc8f7d418
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/COMPILE_LIST
@@ -0,0 +1,33 @@
+
+Compile list for the spi_boot core
+==================================
+Version: $Date: 2005/04/14 21:26:22 $
+
+bench/vhdl/tb.vhd
+rtl/vhdl/spi_boot_pack-p.vhd
+bench/vhdl/tb_pack-p.vhd
+bench/vhdl/tb_elem.vhd
+rtl/vhdl/chip-e.vhd
+rtl/vhdl/chip-full-a.vhd
+rtl/vhdl/spi_boot.vhd
+rtl/vhdl/spi_counter.vhd
+rtl/vhdl/spi_counter-c.vhd
+rtl/vhdl/spi_boot-c.vhd
+rtl/vhdl/chip-full-c.vhd
+bench/vhdl/card.vhd
+bench/vhdl/card-c.vhd
+bench/vhdl/tb_elem-full-c.vhd
+rtl/vhdl/chip-mmc-a.vhd
+rtl/vhdl/chip-mmc-c.vhd
+bench/vhdl/tb_elem-mmc-c.vhd
+rtl/vhdl/chip-sd-a.vhd
+rtl/vhdl/chip-sd-c.vhd
+bench/vhdl/tb_elem-sd-c.vhd
+rtl/vhdl/chip-minimal-a.vhd
+rtl/vhdl/chip-minimal-c.vhd
+bench/vhdl/tb_elem-minimal-c.vhd
+bench/vhdl/tb-c.vhd
+bench/vhdl/tb_rl.vhd
+rtl/vhdl/sample/ram_loader.vhd
+rtl/vhdl/sample/ram_loader-c.vhd
+bench/vhdl/tb_rl-c.vhd
diff --git a/fpga/usrp2/opencores/spi_boot/COPYING b/fpga/usrp2/opencores/spi_boot/COPYING
new file mode 100644
index 000000000..60549be51
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/COPYING
@@ -0,0 +1,340 @@
+		    GNU GENERAL PUBLIC LICENSE
+		       Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+                       59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+			    Preamble
+
+  The licenses for most software are designed to take away your
+freedom to share and change it.  By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users.  This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it.  (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.)  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+  To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have.  You must make sure that they, too, receive or can get the
+source code.  And you must show them these terms so they know their
+rights.
+
+  We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+  Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software.  If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+  Finally, any free program is threatened constantly by software
+patents.  We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary.  To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+  The precise terms and conditions for copying, distribution and
+modification follow.
+
+		    GNU GENERAL PUBLIC LICENSE
+   TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+  0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License.  The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language.  (Hereinafter, translation is included without limitation in
+the term "modification".)  Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope.  The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+  1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+  2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+    a) You must cause the modified files to carry prominent notices
+    stating that you changed the files and the date of any change.
+
+    b) You must cause any work that you distribute or publish, that in
+    whole or in part contains or is derived from the Program or any
+    part thereof, to be licensed as a whole at no charge to all third
+    parties under the terms of this License.
+
+    c) If the modified program normally reads commands interactively
+    when run, you must cause it, when started running for such
+    interactive use in the most ordinary way, to print or display an
+    announcement including an appropriate copyright notice and a
+    notice that there is no warranty (or else, saying that you provide
+    a warranty) and that users may redistribute the program under
+    these conditions, and telling the user how to view a copy of this
+    License.  (Exception: if the Program itself is interactive but
+    does not normally print such an announcement, your work based on
+    the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole.  If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works.  But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+  3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+    a) Accompany it with the complete corresponding machine-readable
+    source code, which must be distributed under the terms of Sections
+    1 and 2 above on a medium customarily used for software interchange; or,
+
+    b) Accompany it with a written offer, valid for at least three
+    years, to give any third party, for a charge no more than your
+    cost of physically performing source distribution, a complete
+    machine-readable copy of the corresponding source code, to be
+    distributed under the terms of Sections 1 and 2 above on a medium
+    customarily used for software interchange; or,
+
+    c) Accompany it with the information you received as to the offer
+    to distribute corresponding source code.  (This alternative is
+    allowed only for noncommercial distribution and only if you
+    received the program in object code or executable form with such
+    an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it.  For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable.  However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+  4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License.  Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+  5. You are not required to accept this License, since you have not
+signed it.  However, nothing else grants you permission to modify or
+distribute the Program or its derivative works.  These actions are
+prohibited by law if you do not accept this License.  Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+  6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions.  You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+  7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License.  If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all.  For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices.  Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+  8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded.  In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+  9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time.  Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number.  If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation.  If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+  10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission.  For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this.  Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+			    NO WARRANTY
+
+  11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW.  EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.  THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.  SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+  12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+		     END OF TERMS AND CONDITIONS
+
+	    How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) 19yy  <name of author>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+    Gnomovision version 69, Copyright (C) 19yy name of author
+    Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary.  Here is a sample; alter the names:
+
+  Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+  `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+  <signature of Ty Coon>, 1 April 1989
+  Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs.  If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library.  If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/fpga/usrp2/opencores/spi_boot/CVS/Entries b/fpga/usrp2/opencores/spi_boot/CVS/Entries
new file mode 100644
index 000000000..d339433f3
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/CVS/Entries
@@ -0,0 +1,9 @@
+/COMPILE_LIST/1.2/Thu Apr 14 21:26:22 2005//
+/COPYING/1.1/Tue Feb  8 20:14:49 2005//
+/KNOWN_BUGS/1.1/Sun Feb 13 18:28:35 2005//
+/README/1.12/Thu Apr 14 21:32:58 2005//
+D/bench////
+D/doc////
+D/rtl////
+D/sim////
+D/sw////
diff --git a/fpga/usrp2/opencores/spi_boot/CVS/Repository b/fpga/usrp2/opencores/spi_boot/CVS/Repository
new file mode 100644
index 000000000..6aa579d49
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/CVS/Repository
@@ -0,0 +1 @@
+spi_boot
diff --git a/fpga/usrp2/opencores/spi_boot/CVS/Root b/fpga/usrp2/opencores/spi_boot/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/CVS/Template b/fpga/usrp2/opencores/spi_boot/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS b/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS
new file mode 100644
index 000000000..298e4ba2e
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/KNOWN_BUGS
@@ -0,0 +1,4 @@
+
+Known bugs of the spi_boot core
+===============================
+Version: $Date: 2005/02/13 18:28:35 $
diff --git a/fpga/usrp2/opencores/spi_boot/README b/fpga/usrp2/opencores/spi_boot/README
new file mode 100644
index 000000000..926b35bff
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/README
@@ -0,0 +1,170 @@
+
+README for the spi_boot core
+============================
+Version: $Date: 2005/04/14 21:32:58 $
+
+
+Description
+-----------
+
+The SD/MMC Bootloader is a CPLD design that manages configuration and
+bootstrapping of FPGAs. It is able to retrieve the required data from
+SecureDigital (SD) cards or MultiMediaCards (MMC) and manages the FPGA
+configuration process. SD cards as well as MMCs are operated in SPI mode which
+is part of both standards thus eliminating the need for dedicated
+implementations. The SD/MMC Bootloader fits both. Beyond configuration, this
+core supports a bootstrapping strategy where multiple images are stored on one
+single memory card.
+For example consider a system completely based on SRAM. The bootloader
+provides the initial configuration data from the first image to the FPGA. This
+image contains a design which pulls the next image from the memory card and
+transfers this data to SRAM. In the third step the final FPGA design is loaded
+from the third image.
+These images are clustered in sets which can be selected by external switches
+for example. Several configuration sets can be stored on one memory card
+allowing you to provide a number of applications which are downloaded quickly
+to the FPGA.
+The schematic (rev. B) shows how the core can be used with an FPGA board. I
+use it to configure/boot the Xilinx Spartan IIe on BurchED's B5-X300
+board. SV2 fits the "SERIAL MODE" connector on this board but you will have to
+add a separate wire from R6 to attach INIT. Please check the proper use of the
+pull-up resistors for your specific board.
+
+
+Features
+--------
+
+* Configuration mode: configures SRAM based FPGAs via slave serial mode
+  (Xilinx and Altera)
+* Data mode: provides stored data over a simple synchronous serial interface
+* Broad compatability using SPI mode
+    + SecureDigital cards using dedicated initialization command
+    + MultiMediaCards (see below)
+* Operation triggerd by power-up or card insertion
+* Multiple configuration sets stored on on single memory card
+
+
+Compatability
+-------------
+
+These cards have been tested with the SD/MMC Bootloader:
+
+  * Hama 64 MB SD
+  * SanDisk 128 MB SD
+  * SanDisk 64 MB MMC
+  * Panasonic 32 MB SD 
+
+Some MMC might fail with this core as not all cards support CMD18
+(READ_MULTIPLE_BLOCK). Please consult the data sheet of your specific
+model. In case your MMC does not implement CMD18 you might want to have a look
+at the FPGA MMC-Card Config project.
+
+
+Tools
+-----
+
+Downloading the configuration data to the card is a straight forward
+process. The images have to be written starting at dedicated locations. For
+the provided toplevel designs, these locations are multiples of 256 K. I.e. 0,
+0x40000, 0x80000 and so forth.
+
+dd (part of the GNU coreutils) serves this purpose:
+$ dd if=ram_loader.bin of=/dev/sdX bs=512
+$ dd if=pongrom_6.bin of=/dev/sdX bs=512 seek=512
+$ dd if=pacman.bin of=/dev/sdX bs=512 seek=1024
+
+The name of the device node depends on how the card reader is attached to the
+kernel. For Linux systems this is most often something like /dev/sdX with X
+ranging from a-z. Please note that it is essential to use the device without
+any trailing numbers as they refer to partitions leading to wrong offsets for
+data written to the card.
+All this works perfectly for my Spartan IIe device as this FPGA expects the
+configuration data as it is delivered from the card: Consecutive bytes each
+with its most significant bit first. Altera devices like the FLEX family are
+different here. They expect the bytes with least significant bit
+first. Therefore, the configuration data has to be swapped bitwise before it
+is written to the card.
+
+
+Verification
+------------
+
+The spi_boot core comes with a simple testbench that simulates an SD/MMC
+card. All four implementations of the core are verified there in parallel
+while transferring the data for several sets.
+You should normally not need to run the testbench. But in case you modified
+the VHDL code the testbench gives some hints if the design has been broken.
+
+
+Directory Structure
+-------------------
+
+The core's directory structure follows the proposal of OpenCores.org.
+
+spi_boot
+ |
+ \--+-- doc                 : Documentation
+    |    |
+    |    \-- src            : Source files of documentation
+    |
+    +-- rtl
+    |    |
+    |    \-- vhdl           : VHDL code containing the RTL description
+    |                         of the core.
+    |
+    +-- bench
+    |    |
+    |    \-- vhdl           : VHDL testbench code.
+    |
+    \-- sim
+         |
+         \-- rtl_sim        : Directory for running simulations.
+
+
+RAM Loader
+----------
+
+Directory rtl/vhdl/ram_loader contains the sample design which loads the next
+image from the card and stores its contents to external asynchronous
+RAM. After reading 64 KB it triggers a new configuration process for the final
+FPGA design.
+Refer to the code for the mechanisms involved.
+
+
+Compiling the VHDL Code
+-----------------------
+
+VHDL compilation and simulation tasks take place inside in sim/rtl_sim
+directory. The project setup supports only the GHDL simulator (see
+http://ghdl.free.fr).
+
+To compile the code simply type at the shell
+
+$ make
+
+This should result in a file called tb_behav_c0 which can be executed as any
+other executable.
+
+The basic simple sequence list can be found in COMPILE_LIST. This can be
+useful to quickly set up the analyze stage of any compiler or
+synthesizer. Especially when synthesizing the code, you want to skip the VHDL
+configurations in *-c.vhd and everything below the bench/ directory.
+
+
+References
+----------
+
+  * SanDisk SD Card Product Manual
+    http://www.sandisk.com/pdf/oem/ProdManualSDCardv1.9.pdf
+
+  * SanDisk MMC Product Manual
+    http://www.sandisk.com/pdf/oem/manual-rs-mmcv1.0.pdf
+
+  * Toshiba SD Card Specification
+    http://i.cmpnet.com/chipcenter/memory/images/prod055.pdf
+
+  * BurchED
+    http://burched.biz/
+
+  * FPGA MMC-Card Config project
+    http://www.opencores.org/projects.cgi/web/mmcfpgaconfig/overview
diff --git a/fpga/usrp2/opencores/spi_boot/bench/CVS/Entries b/fpga/usrp2/opencores/spi_boot/bench/CVS/Entries
new file mode 100644
index 000000000..a4756ee6f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/CVS/Entries
@@ -0,0 +1 @@
+D/vhdl////
diff --git a/fpga/usrp2/opencores/spi_boot/bench/CVS/Repository b/fpga/usrp2/opencores/spi_boot/bench/CVS/Repository
new file mode 100644
index 000000000..ac45542a6
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/bench
diff --git a/fpga/usrp2/opencores/spi_boot/bench/CVS/Root b/fpga/usrp2/opencores/spi_boot/bench/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/bench/CVS/Template b/fpga/usrp2/opencores/spi_boot/bench/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries
new file mode 100644
index 000000000..8649c9f90
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Entries
@@ -0,0 +1,13 @@
+/card-c.vhd/1.1/Tue Feb  8 21:09:18 2005//
+/card.vhd/1.2/Sun Feb 13 17:06:22 2005//
+/tb-c.vhd/1.1/Tue Feb  8 21:09:20 2005//
+/tb.vhd/1.1/Tue Feb  8 21:09:20 2005//
+/tb_elem-full-c.vhd/1.1/Tue Feb  8 21:09:20 2005//
+/tb_elem-minimal-c.vhd/1.1/Tue Feb  8 21:09:20 2005//
+/tb_elem-mmc-c.vhd/1.1/Tue Feb  8 21:09:20 2005//
+/tb_elem-sd-c.vhd/1.1/Tue Feb  8 21:09:20 2005//
+/tb_elem.vhd/1.7/Thu Apr  7 20:43:36 2005//
+/tb_pack-p.vhd/1.2/Tue Mar  8 22:06:39 2005//
+/tb_rl-c.vhd/1.1/Sun Apr 10 18:07:26 2005//
+/tb_rl.vhd/1.1/Sun Apr 10 18:07:25 2005//
+D
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository
new file mode 100644
index 000000000..ce62c2b8e
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/bench/vhdl
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd
new file mode 100644
index 000000000..797eb1c90
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card-c.vhd
@@ -0,0 +1,14 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: card-c.vhd,v 1.1 2005/02/08 21:09:18 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration card_behav_c0 of card is
+
+  for behav
+  end for;
+
+end card_behav_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd
new file mode 100644
index 000000000..dcd676095
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd
@@ -0,0 +1,446 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Simple SD and MMC model
+--
+-- $Id: card.vhd,v 1.2 2005/02/13 17:06:22 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity card is
+
+  generic (
+    card_type_g  : string := "none";
+    is_sd_card_g : integer := 1
+  );
+
+  port (
+    spi_clk_i  : in  std_logic;
+    spi_cs_n_i : in  std_logic;
+    spi_data_i : in  std_logic;
+    spi_data_o : out std_logic
+  );
+
+end card;
+
+
+library ieee;
+use ieee.numeric_std.all;
+library std;
+use std.textio.all;
+
+use work.tb_pack.all;
+
+architecture behav of card is
+
+  signal power_on_n_s : std_logic;
+  signal soft_res_n_s : std_logic;
+  signal res_n_s      : std_logic;
+
+  signal rx_s : std_logic_vector(47 downto 0);
+
+  signal set_spi_mode_s,
+         spi_mode_q       : boolean;
+  signal set_idle_mode_s,
+         poll_idle_mode_s : boolean;
+  signal idle_mode_q      : natural;
+
+  signal block_len_q,
+         block_len_s     : unsigned(31 downto 0);
+  signal set_block_len_s : boolean;
+
+  signal new_read_addr_s,
+         read_addr_q     : unsigned(31 downto 0);
+  signal set_read_addr_s,
+         inc_read_addr_s : boolean;
+
+  signal cmd_spi_data_s,
+         read_spi_data_s : std_logic;
+  signal start_read_s    : boolean;
+  signal reading_s       : boolean;
+
+  procedure rise_clk is
+  begin
+    wait until spi_clk_i'event and to_X01(spi_clk_i) = '1';
+  end rise_clk;
+
+--  procedure rise_clk(num : natural) is
+--  begin
+--    for i in 1 to num loop
+--      rise_clk;
+--    end loop;
+--  end rise_clk;
+
+  procedure fall_clk is
+  begin
+    wait until spi_clk_i'event and to_X01(spi_clk_i) = '0';
+  end fall_clk;
+
+  procedure fall_clk(num : natural) is
+  begin
+    for i in 1 to num loop
+      fall_clk;
+    end loop;
+  end fall_clk;
+
+begin
+
+  res_n_s <= power_on_n_s and soft_res_n_s;
+
+  -----------------------------------------------------------------------------
+  -- Power on reset
+  -----------------------------------------------------------------------------
+  por: process
+  begin
+    power_on_n_s <= '0';
+    wait for 200 ns;
+    power_on_n_s <= '1';
+    wait;
+  end process por;
+
+
+  -----------------------------------------------------------------------------
+  --
+  ctrl: process
+
+    function check_crc(payload : in std_logic_vector(47 downto 0))
+      return boolean is
+
+    begin
+
+      return calc_crc(payload(47 downto 8)) = payload(7 downto 1);
+    end check_crc;
+
+    variable rx_v        : std_logic_vector(47 downto 0);
+    variable cmd_v       : std_logic_vector( 5 downto 0);
+    variable arg_v       : std_logic_vector(31 downto 0);
+    variable crc_v       : std_logic_vector( 6 downto 0);
+    variable wrong_v     : std_logic;
+    variable read_data_v : boolean;
+
+  begin
+    rx_s <= (others => '0');
+    set_spi_mode_s   <= false;
+    set_idle_mode_s  <= false;
+    poll_idle_mode_s <= false;
+    cmd_spi_data_s   <= '1';
+    soft_res_n_s     <= '1';
+    set_block_len_s  <= false;
+    block_len_s      <= (others => '0');
+    new_read_addr_s  <= (others => '0');
+    set_read_addr_s  <= false;
+    start_read_s     <= false;
+    read_data_v      := false;
+
+    loop
+
+      rise_clk;
+      -- wait for startbit of command
+      while to_X01(spi_data_i) = '1' loop
+        rise_clk;
+      end loop;
+      rx_v(47) := '0';
+
+      -- read remaining 47 bits of command
+      for i in 46 downto 0 loop
+        rise_clk;
+        rx_v(i) := to_X01(spi_data_i);
+      end loop;
+      rx_s <= rx_v;
+
+      -- dissect received data
+      cmd_v := rx_v(45 downto 40);
+      arg_v := rx_v(39 downto  8);
+      crc_v := rx_v( 7 downto  1);
+
+      assert spi_mode_q or check_crc(payload => rx_v)
+        report "CRC mismatch"
+        severity error;
+
+      wrong_v     := '0';
+      case cmd_v is
+        -- CMD0: GO_IDLE_STATE ------------------------------------------------
+        when "000000" =>
+          set_spi_mode_s  <= true;
+          set_idle_mode_s <= true;
+        -- CMD1: SEND_OP_COND -------------------------------------------------
+        when "000001" =>
+          poll_idle_mode_s <= true;
+        -- CMD12: STOP_TRANSMISSION -------------------------------------------
+        when "001100" =>
+          start_read_s <= false;
+          read_data_v  := false;
+        -- CMD16: SET_BLOCKLEN ------------------------------------------------
+        when "010000" =>
+          block_len_s     <= unsigned(arg_v);
+          set_block_len_s <= true;
+        -- CMD18: READ_MULTIPLE_BLOCK -----------------------------------------
+        when "010010" =>
+          new_read_addr_s <= unsigned(arg_v);
+          set_read_addr_s <= true;
+          read_data_v     := true;
+        -- CMD55: APPL_CMD ----------------------------------------------------
+        when "110111" =>
+          -- command only available for SD card
+          if is_sd_card_g /= 1 then
+            wrong_v := '1';
+          end if;
+        -- ACMD41: SEND_OP_COND -----------------------------------------------
+        when "101001" =>
+          -- command only available for SD card
+          if is_sd_card_g /= 1 then
+            wrong_v := '1';
+          else
+            poll_idle_mode_s <= true;
+          end if;
+
+        when others =>
+          wrong_v := '1';
+          null;
+      end case;
+
+
+      -- spend some time before removing control signals
+      fall_clk(2);
+      poll_idle_mode_s <= false;
+      set_idle_mode_s <= false;
+      fall_clk(6);
+      set_spi_mode_s  <= false;
+      set_block_len_s <= false;
+      set_read_addr_s <= false;
+
+      if reading_s then
+        wait until not reading_s;
+      end if;
+
+
+      -- wait for a total two "bytes" before sending out response
+      for i in 1 to 8 loop
+        fall_clk;
+      end loop;
+
+      for i in 7 downto 0 loop
+        fall_clk;
+        case i is
+          when 2 =>
+            cmd_spi_data_s <= wrong_v;
+          when 0 =>
+            if idle_mode_q = 0 then
+              cmd_spi_data_s <= '0';
+            else
+              cmd_spi_data_s <= '1';
+            end if;
+          when others =>
+            cmd_spi_data_s <= '0';
+        end case;
+      end loop;
+      fall_clk;
+      cmd_spi_data_s <= '1';
+
+      -- transmit data if requested
+      start_read_s <= read_data_v;
+
+    end loop;
+  end process ctrl;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  --
+  seq: process (res_n_s,
+                spi_clk_i,
+                set_spi_mode_s,
+                set_idle_mode_s,
+                poll_idle_mode_s,
+                set_block_len_s,
+                block_len_s)
+
+  begin
+    if res_n_s = '0' then
+      spi_mode_q  <= false;
+      idle_mode_q <= 5;
+      block_len_q <= (others => '0');
+      read_addr_q <= (others => '0');
+
+    elsif spi_clk_i'event and spi_clk_i = '1' then
+      if set_spi_mode_s then
+        spi_mode_q  <= true;
+      end if;
+
+      if set_idle_mode_s then
+        idle_mode_q  <= 5;
+      elsif poll_idle_mode_s then
+        if idle_mode_q > 0 then
+          idle_mode_q <= idle_mode_q - 1;
+        end if;
+      end if;
+
+      if set_block_len_s then
+        block_len_q <= block_len_s;
+      end if;
+
+      if set_read_addr_s then
+        read_addr_q <= new_read_addr_s;
+      elsif inc_read_addr_s then
+        read_addr_q <= read_addr_q + 1;
+      end if;
+
+    end if;
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  --
+  read_block: process
+
+    variable t_v : unsigned(7 downto 0);
+
+  begin
+    -- default assignments
+    inc_read_addr_s <= false;
+    reading_s       <= false;
+    read_spi_data_s <= '1';
+
+    loop
+      if not start_read_s then
+        wait until start_read_s;
+      end if;
+
+      reading_s <= true;
+
+      fall_clk(8);                    -- delay for one "byte"
+
+      -- send data token
+      fall_clk(7);                    -- 7 ones in a data token
+      read_spi_data_s <= '0';
+
+      -- send payload
+      payload: for i in 0 to to_integer(block_len_q)-1 loop
+        t_v := read_addr_q(0) & calc_crc(read_addr_q);
+        for bit in 7 downto 0 loop
+          fall_clk;
+          read_spi_data_s <= t_v(bit);
+
+          exit payload when not start_read_s;
+        end loop;
+        inc_read_addr_s <= true;
+        rise_clk;
+        inc_read_addr_s <= false;
+        wait for 10 ns;
+      end loop;
+
+      if start_read_s then
+        -- send crc
+        for i in 0 to 15 loop
+          fall_clk;
+          t_v := to_unsigned(i, 8);
+          read_spi_data_s <= t_v(0);
+        end loop;
+        fall_clk;
+      end if;
+
+      read_spi_data_s <= '1';
+      reading_s <= false;
+      -- loop for one "byte"
+      fall_clk(8);
+
+    end loop;
+  end process read_block;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  --
+  clk_check: process (spi_clk_i)
+
+    variable last_rising_v : time := 0 ns;
+    variable dump_line     : line;
+
+  begin
+    if spi_clk_i'event and spi_clk_i = '1' then
+      if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and
+         idle_mode_q > 0 then
+        if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then
+          write(dump_line, card_type_g);
+          write(dump_line, string'(" @ "));
+          write(dump_line, now);
+          write(dump_line, string'(": Last rising edge of SPI clock "));
+          write(dump_line, now - last_rising_v);
+          write(dump_line, string'(" ago."));
+          writeline(output, dump_line);
+        end if;
+
+        last_rising_v := now;
+      end if;
+    end if;
+  end process clk_check;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  spi_data_o <=   cmd_spi_data_s and read_spi_data_s
+                when spi_cs_n_i = '0' else
+                  'Z';
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: card.vhd,v $
+-- Revision 1.2  2005/02/13 17:06:22  arniml
+-- handle termination properly
+--
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd
new file mode 100644
index 000000000..caa171362
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb-c.vhd
@@ -0,0 +1,31 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_behav_c0 of tb is
+
+  for behav
+
+    for tb_elem_full_b : tb_elem
+      use configuration work.tb_elem_behav_full;
+    end for;
+
+    for tb_elem_mmc_b : tb_elem
+      use configuration work.tb_elem_behav_mmc;
+    end for;
+
+    for tb_elem_sd_b : tb_elem
+      use configuration work.tb_elem_behav_sd;
+    end for;
+
+    for tb_elem_minimal_b : tb_elem
+      use configuration work.tb_elem_behav_minimal;
+    end for;
+
+  end for;
+
+end tb_behav_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd
new file mode 100644
index 000000000..b359fa7c5
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb.vhd
@@ -0,0 +1,201 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Testbench
+--
+-- $Id: tb.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+entity tb is
+
+end tb;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb is
+
+  component tb_elem
+    generic (
+      chip_type_g   : string := "none";
+      has_sd_card_g : integer := 1
+    );
+    port (
+      clk_i   : in  std_logic;
+      reset_i : in  std_logic;
+      eos_o   : out boolean
+    );
+  end component;
+
+  constant period_c      : time := 100 ns;
+  constant reset_level_c : integer := 0;
+
+  signal clk_s   : std_logic;
+  signal reset_s : std_logic;
+
+  signal eos_full_s,
+         eos_mmc_s,
+         eos_sd_s,
+         eos_minimal_s : boolean;
+
+begin
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including full featured chip
+  -----------------------------------------------------------------------------
+  tb_elem_full_b : tb_elem
+    generic map (
+      chip_type_g   => "Full Chip",
+      has_sd_card_g => 1
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_full_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including MMC chip
+  -----------------------------------------------------------------------------
+  tb_elem_mmc_b : tb_elem
+    generic map (
+      chip_type_g   => "MMC Chip",
+      has_sd_card_g => 0
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_mmc_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including SD chip
+  -----------------------------------------------------------------------------
+  tb_elem_sd_b : tb_elem
+    generic map (
+      chip_type_g   => "SD Chip",
+      has_sd_card_g => 1
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_sd_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Testbench element including cip with minimal features
+  -----------------------------------------------------------------------------
+  tb_elem_minimal_b : tb_elem
+    generic map (
+      chip_type_g   => "Minimal Chip",
+      has_sd_card_g => 0
+    )
+    port map (
+      clk_i   => clk_s,
+      reset_i => reset_s,
+      eos_o   => eos_minimal_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- Clock Generator
+  -----------------------------------------------------------------------------
+  clk: process
+  begin
+    clk_s <= '0';
+    wait for period_c / 2;
+    clk_s <= '1';
+    wait for period_c / 2;
+  end process clk;
+
+
+  -----------------------------------------------------------------------------
+  -- Reset Generator
+  -----------------------------------------------------------------------------
+  reset: process
+  begin
+    if reset_level_c = 0 then
+      reset_s <= '0';
+    else
+      reset_s <= '1';
+    end if;
+
+    wait for period_c * 4 + 10 ns;
+
+    reset_s <= not reset_s;
+
+    wait;
+  end process reset;
+
+
+  -----------------------------------------------------------------------------
+  -- End Of Simulation Detection
+  -----------------------------------------------------------------------------
+  eos: process (eos_full_s,
+                eos_mmc_s,
+                eos_sd_s,
+                eos_minimal_s)
+  begin
+
+    if eos_full_s and eos_mmc_s and eos_sd_s and eos_minimal_s then
+      assert false
+        report "End of Simulation."
+        severity failure;
+    end if;
+
+  end process eos;
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb.vhd,v $
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
new file mode 100644
index 000000000..3c0fb902f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-full-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-full-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_full of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_full_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_full;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
new file mode 100644
index 000000000..1c33ac3d0
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-minimal-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-minimal-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_minimal of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_minimal_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_minimal;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
new file mode 100644
index 000000000..b5baf604e
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-mmc-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-mmc-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_mmc of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_mmc_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_mmc;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
new file mode 100644
index 000000000..9cdf3eaa1
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem-sd-c.vhd
@@ -0,0 +1,23 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_elem-sd-c.vhd,v 1.1 2005/02/08 21:09:20 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_elem_behav_sd of tb_elem is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_sd_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+  end for;
+
+end tb_elem_behav_sd;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd
new file mode 100644
index 000000000..689cec037
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd
@@ -0,0 +1,376 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Generic testbench element for a specific feature set
+--
+-- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity tb_elem is
+
+  generic (
+    chip_type_g   : string := "none";
+    has_sd_card_g : integer := 1
+  );
+  port (
+    clk_i   : in  std_logic;
+    reset_i : in  std_logic;
+    eos_o   : out boolean
+  );
+
+end tb_elem;
+
+
+library ieee;
+use ieee.numeric_std.all;
+library std;
+use std.textio.all;
+
+use work.spi_boot_pack.all;
+use work.tb_pack.all;
+
+architecture behav of tb_elem is
+
+  component chip
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_n_i    : in  std_logic_vector(3 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  component card
+    generic (
+      card_type_g  : string := "none";
+      is_sd_card_g : integer := 1
+    );
+    port (
+      spi_clk_i  : in  std_logic;
+      spi_cs_n_i : in  std_logic;
+      spi_data_i : in  std_logic;
+      spi_data_o : out std_logic
+    );
+  end component;
+
+  signal reset_s : std_logic;
+
+  -- SPI interface signals
+  signal spi_clk_s            : std_logic;
+  signal spi_data_to_card_s   : std_logic;
+  signal spi_data_from_card_s : std_logic;
+  signal spi_cs_n_s           : std_logic;
+
+  -- config related signals
+  signal start_s      : std_logic;
+  signal mode_s       : std_logic;
+  signal config_n_s   : std_logic;
+  signal cfg_init_n_s : std_logic;
+  signal cfg_done_s   : std_logic;
+  signal dat_done_s   : std_logic;
+  signal cfg_clk_s    : std_logic;
+  signal cfg_dat_s    : std_logic;
+  signal data_s       : unsigned(7 downto 0);
+
+  signal set_sel_n_s : std_logic_vector(3 downto 0);
+
+  constant verbose_c : boolean := false;
+
+begin
+
+  -- weak pull-ups
+  spi_clk_s          <= 'H';
+  spi_cs_n_s         <= 'H';
+  spi_data_to_card_s <= 'H';
+
+  -----------------------------------------------------------------------------
+  -- DUT
+  -----------------------------------------------------------------------------
+  dut_b : chip
+    port map (
+      clk_i          => clk_i,
+      reset_i        => reset_s,
+      set_sel_n_i    => set_sel_n_s,
+      spi_clk_o      => spi_clk_s,
+      spi_cs_n_o     => spi_cs_n_s,
+      spi_data_in_i  => spi_data_from_card_s,
+      spi_data_out_o => spi_data_to_card_s,
+      start_i        => start_s,
+      mode_i         => mode_s,
+      config_n_o     => config_n_s,
+      detached_o     => open,
+      cfg_init_n_i   => cfg_init_n_s,
+      cfg_done_i     => cfg_done_s,
+      dat_done_i     => dat_done_s,
+      cfg_clk_o      => cfg_clk_s,
+      cfg_dat_o      => cfg_dat_s
+    );
+
+  card_b : card
+    generic map (
+      card_type_g  => chip_type_g,
+      is_sd_card_g => has_sd_card_g
+    )
+    port map (
+      spi_clk_i  => spi_clk_s,
+      spi_cs_n_i => spi_cs_n_s,
+      spi_data_i => spi_data_to_card_s,
+      spi_data_o => spi_data_from_card_s
+    );
+
+
+  -----------------------------------------------------------------------------
+  -- DUT Stimuli
+  --
+  stim: process
+
+    procedure rise_cfg_clk(num : integer) is
+    begin
+      for i in 1 to num loop
+        wait until cfg_clk_s'event and cfg_clk_s = '1';
+      end loop;
+    end rise_cfg_clk;
+
+--     procedure fall_cfg_clk(num : integer) is
+--     begin
+--       for i in 1 to num loop
+--         wait until cfg_clk_s'event and cfg_clk_s = '0';
+--       end loop;
+--     end fall_cfg_clk;
+
+    procedure rise_clk(num : integer) is
+    begin
+      for i in 1 to num loop
+        wait until clk_i'event and clk_i = '1';
+      end loop;
+    end rise_clk;
+
+    procedure read_check_byte(ref : unsigned(7 downto 0)) is
+      variable byte_v : unsigned(7 downto 0);
+      variable dump_line : line;
+    begin
+      for bit in 7 downto 0 loop
+        rise_cfg_clk(1);
+        byte_v(bit) := cfg_dat_s;
+      end loop;
+      data_s <= byte_v;
+
+      if byte_v /= ref then
+        write(dump_line, chip_type_g);
+        write(dump_line, string'(" at "));
+        write(dump_line, now);
+        write(dump_line, string'(": read_check_byte failed "));
+        write(dump_line, to_integer(byte_v));
+        write(dump_line, string'(" "));
+        write(dump_line, to_integer(ref));
+        writeline(output, dump_line);
+      end if;
+    end read_check_byte;
+
+    variable dump_line : line;
+    variable addr_v    : unsigned(31 downto 0);
+    variable temp_v    : unsigned( 7 downto 0);
+    variable set_sel_v : unsigned(3 downto 0);
+
+  begin
+    -- default assignments
+    -- these defaults show the required pull resistors
+    -- except start_i as this must be pulled high for automatic start
+    start_s      <= '0';
+    mode_s       <= '1';
+    cfg_init_n_s <= '1';
+    cfg_done_s   <= '0';
+    dat_done_s   <= '1';
+    data_s       <= (others => '1');
+    addr_v       := (others => '0');
+    eos_o        <= false;
+    set_sel_n_s  <= (others => '1');
+    reset_s      <= '0';
+
+    -- loop through some sets
+    for set in 0 to 3 loop
+      set_sel_v := to_unsigned(set, 4);
+      addr_v(23 downto 20) := set_sel_v;  -- must match num_bits_per_img_g
+                                          -- plus width_img_cnt_g
+      set_sel_n_s <= not std_logic_vector(set_sel_v);
+
+      assert not verbose_c
+        report chip_type_g & ": Processing set " & to_string(set)
+        severity note;
+
+      wait for 100 us;
+      reset_s <= '1';
+
+      assert not verbose_c
+        report chip_type_g & ": Requesting image 0"
+        severity note;
+
+      -- signal start
+      start_s    <= '1';
+      mode_s     <= '1';
+      cfg_done_s <= '0';
+      addr_v(19 downto 0) := (others => '0');
+      wait until config_n_s = '0';
+      -- run through configuration sequence
+      rise_clk(1);
+      cfg_init_n_s <= '0';
+      rise_clk(3);
+      cfg_init_n_s <= '1';
+
+      -- and receive 32 bytes from image 0
+      for i in 1 to 32 loop
+        temp_v := addr_v(0) & calc_crc(addr_v);
+        read_check_byte(temp_v);
+        addr_v := addr_v + 1;
+      end loop;
+      start_s    <= '0';
+      cfg_done_s <= '1';
+
+      rise_clk(10);
+
+      assert not verbose_c
+        report chip_type_g & ": Requesting image 1"
+        severity note;
+
+      -- request next image
+      mode_s  <= '0';
+      start_s <= '1';
+      addr_v(17 downto  0) := (others => '0');
+      addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd
+      dat_done_s <= '0';
+
+      -- receive another 32 bytes from image 1
+      for i in 1 to 32 loop
+        temp_v := addr_v(0) & calc_crc(addr_v);
+        read_check_byte(temp_v);
+        addr_v := addr_v + 1;
+      end loop;
+      start_s    <= '0';
+      dat_done_s <= '1';
+      
+
+      rise_clk(10);
+
+      assert not verbose_c
+        report chip_type_g & ": Requesting image 2"
+        severity note;
+
+      -- request next image
+      mode_s  <= '1';
+      start_s <= '1';
+      addr_v(17 downto  0) := (others => '0');
+      addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd
+
+      wait until config_n_s = '0';
+      -- run through configuration sequence
+      rise_clk(1);
+      cfg_done_s   <= '0';
+      cfg_init_n_s <= '0';
+      rise_clk(3);
+      cfg_init_n_s <= '1';
+
+      -- receive another 32 bytes from image 2
+      for i in 1 to 32 loop
+        temp_v := addr_v(0) & calc_crc(addr_v);
+        read_check_byte(temp_v);
+        addr_v := addr_v + 1;
+      end loop;
+      start_s    <= '0';
+      cfg_done_s <= '1';
+
+      -- give dut a chance to stop current transfer
+      wait until spi_cs_n_s = '1';
+      rise_clk(10);
+
+      reset_s <= '0';
+    end loop;
+
+    eos_o <= true;
+    wait;
+  end process stim;
+  --
+  -----------------------------------------------------------------------------
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb_elem.vhd,v $
+-- Revision 1.7  2005/04/07 20:43:36  arniml
+-- add new port detached_o
+--
+-- Revision 1.6  2005/03/09 19:48:04  arniml
+-- make verbosity level switchable
+--
+-- Revision 1.5  2005/03/08 22:06:21  arniml
+-- added set selection
+--
+-- Revision 1.4  2005/02/17 18:59:23  arniml
+-- clarify wording for images
+--
+-- Revision 1.3  2005/02/16 19:34:56  arniml
+-- add weak pull-ups for SPI lines
+--
+-- Revision 1.2  2005/02/13 17:14:03  arniml
+-- change dat_done handling
+--
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
new file mode 100644
index 000000000..7534aafdc
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd
@@ -0,0 +1,93 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_pack-p.vhd,v 1.2 2005/03/08 22:06:39 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package tb_pack is
+
+  function calc_crc(payload : in std_logic_vector) return std_logic_vector;
+  function calc_crc(payload : in unsigned) return unsigned;
+
+  function to_string(value : in integer) return string;
+
+end tb_pack;
+
+
+package body tb_pack is
+
+  function calc_crc(payload : in std_logic_vector) return std_logic_vector is
+
+    variable crc_v  : std_logic_vector(6 downto 0);
+    variable temp_v : std_logic;
+
+  begin
+
+    crc_v := (others => '0');
+
+    for i in payload'high downto payload'low loop
+      temp_v := payload(i) xor crc_v(6);
+
+      crc_v(6 downto 4) := crc_v(5 downto 3);
+      crc_v(3) := crc_v(2) xor temp_v;
+      crc_v(2 downto 1) := crc_v(1 downto 0);
+      crc_v(0) := temp_v;
+    end loop;
+
+    return crc_v;
+  end calc_crc;
+
+  function calc_crc(payload : in unsigned) return unsigned is
+  begin
+    return unsigned(calc_crc(std_logic_vector(payload)));
+  end calc_crc;
+
+  function to_string(value : in integer) return string is
+    variable str: string (11 downto 1);
+    variable val: integer := value;
+    variable digit: natural;
+    variable index: natural := 0;
+  begin
+    -- Taken from:
+    --  textio package body.  This file is part of GHDL.
+    --  Copyright (C) 2002 Tristan Gingold.
+    --  Note: the absolute value of VAL cannot be directly taken, since
+    --  it may be greather that the maximum value of an INTEGER.
+    loop
+      --  LRM93 7.2.6
+      --  (A rem B) has the sign of A and an absolute value less then
+      --   the absoulte value of B.
+      digit := abs (val rem 10);
+      val := val / 10;
+      index := index + 1;
+      str (index) := character'val(48 + digit);
+      exit when val = 0;
+    end loop;
+    if value < 0 then
+      index := index + 1;
+      str(index) := '-';
+    end if;
+
+    return str;
+  end to_string;
+
+end tb_pack;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb_pack-p.vhd,v $
+-- Revision 1.2  2005/03/08 22:06:39  arniml
+-- added integer->string conversion function
+--
+-- Revision 1.1  2005/02/08 21:09:20  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
new file mode 100644
index 000000000..84273abc5
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl-c.vhd
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: tb_rl-c.vhd,v 1.1 2005/04/10 18:07:26 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration tb_rl_behav_c0 of tb_rl is
+
+  for behav
+
+    for dut_b : chip
+      use configuration work.chip_full_c0;
+    end for;
+
+    for card_b : card
+      use configuration work.card_behav_c0;
+    end for;
+
+    for rl_b : ram_loader
+      use configuration work.ram_loader_rtl_c0;
+    end for;
+
+  end for;
+
+end tb_rl_behav_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd
new file mode 100644
index 000000000..9f28e62b4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_rl.vhd
@@ -0,0 +1,259 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Testbench for ram_loader
+--
+-- $Id: tb_rl.vhd,v 1.1 2005/04/10 18:07:25 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+entity tb_rl is
+
+end tb_rl;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_rl is
+
+  component chip
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_n_i    : in  std_logic_vector(3 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  component card
+    generic (
+      card_type_g  : string := "none";
+      is_sd_card_g : integer := 1
+    );
+    port (
+      spi_clk_i  : in  std_logic;
+      spi_cs_n_i : in  std_logic;
+      spi_data_i : in  std_logic;
+      spi_data_o : out std_logic
+    );
+  end component;
+
+  component ram_loader
+    port (
+      clk_i      : in    std_logic;
+      reset_i    : in    std_logic;
+      lamp_o     : out   std_logic;
+      cfg_clk_i  : in    std_logic;
+      cfg_data_i : in    std_logic;
+      start_o    : out   std_logic;
+      mode_o     : out   std_logic;
+      done_o     : out   std_logic;
+      detached_i : in    std_logic;
+      ram_addr_o : out   std_logic_vector(15 downto 0);
+      ram_data_b : out   std_logic_vector( 7 downto 0);
+      ram_ce_no  : out   std_logic_vector( 3 downto 0);
+      ram_oe_no  : out   std_logic;
+      ram_we_no  : out   std_logic
+    );
+  end component;
+
+  constant period_c      : time := 100 ns;
+  constant rl_period_c   : time :=  20 ns;
+  constant reset_level_c : integer := 0;
+
+  signal clk_s   : std_logic;
+  signal rl_clk_s: std_logic;
+  signal reset_s : std_logic;
+
+  -- SPI interface signals
+  signal spi_clk_s            : std_logic;
+  signal spi_data_to_card_s   : std_logic;
+  signal spi_data_from_card_s : std_logic;
+  signal spi_cs_n_s           : std_logic;
+
+  -- config related signals
+  signal start_s      : std_logic;
+  signal mode_s       : std_logic;
+  signal config_n_s   : std_logic;
+  signal cfg_init_n_s : std_logic;
+  signal cfg_done_s   : std_logic;
+  signal dat_done_s   : std_logic;
+  signal cfg_clk_s    : std_logic;
+  signal cfg_dat_s    : std_logic;
+  signal detached_s   : std_logic;
+
+  signal set_sel_n_s : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_n_s  <= (others => '1');
+  cfg_init_n_s <= '1';
+  cfg_done_s   <= '1';
+
+  -----------------------------------------------------------------------------
+  -- DUT
+  -----------------------------------------------------------------------------
+  dut_b : chip
+    port map (
+      clk_i          => clk_s,
+      reset_i        => reset_s,
+      set_sel_n_i    => set_sel_n_s,
+      spi_clk_o      => spi_clk_s,
+      spi_cs_n_o     => spi_cs_n_s,
+      spi_data_in_i  => spi_data_from_card_s,
+      spi_data_out_o => spi_data_to_card_s,
+      start_i        => start_s,
+      mode_i         => mode_s,
+      config_n_o     => config_n_s,
+      detached_o     => detached_s,
+      cfg_init_n_i   => cfg_init_n_s,
+      cfg_done_i     => cfg_done_s,
+      dat_done_i     => dat_done_s,
+      cfg_clk_o      => cfg_clk_s,
+      cfg_dat_o      => cfg_dat_s
+    );
+
+  card_b : card
+    generic map (
+      card_type_g  => "Full Chip",
+      is_sd_card_g => 1
+    )
+    port map (
+      spi_clk_i  => spi_clk_s,
+      spi_cs_n_i => spi_cs_n_s,
+      spi_data_i => spi_data_to_card_s,
+      spi_data_o => spi_data_from_card_s
+    );
+
+  rl_b : ram_loader
+    port map (
+      clk_i      => rl_clk_s,
+      reset_i    => reset_s,
+      lamp_o     => open,
+      cfg_clk_i  => cfg_clk_s,
+      cfg_data_i => cfg_dat_s,
+      start_o    => start_s,
+      mode_o     => mode_s,
+      done_o     => dat_done_s,
+      detached_i => detached_s,
+      ram_addr_o => open,
+      ram_data_b => open,
+      ram_ce_no  => open,
+      ram_oe_no  => open,
+      ram_we_no  => open
+    );
+
+  -----------------------------------------------------------------------------
+  -- Clock Generator
+  -----------------------------------------------------------------------------
+  clk: process
+  begin
+    clk_s <= '0';
+    wait for period_c / 2;
+    clk_s <= '1';
+    wait for period_c / 2;
+  end process clk;
+
+  rl_clk: process
+  begin
+    rl_clk_s <= '0';
+    wait for rl_period_c / 2;
+    rl_clk_s <= '1';
+    wait for rl_period_c / 2;
+  end process rl_clk;
+
+
+  -----------------------------------------------------------------------------
+  -- Reset Generator
+  -----------------------------------------------------------------------------
+  reset: process
+  begin
+    if reset_level_c = 0 then
+      reset_s <= '0';
+    else
+      reset_s <= '1';
+    end if;
+
+    wait for period_c * 4 + 10 ns;
+
+    reset_s <= not reset_s;
+
+    wait;
+  end process reset;
+
+
+  -----------------------------------------------------------------------------
+  -- End of Simulation
+  -----------------------------------------------------------------------------
+  eos: process
+  begin
+    wait for 4 ms;
+    assert false
+      report "No checks have been performed. Investigate waveforms."
+      severity note;
+    assert false
+      report "End of simulation."
+      severity failure;
+  end process eos;
+
+end behav;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: tb_rl.vhd,v $
+-- Revision 1.1  2005/04/10 18:07:25  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/doc/CVS/Entries b/fpga/usrp2/opencores/spi_boot/doc/CVS/Entries
new file mode 100644
index 000000000..630615f41
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/CVS/Entries
@@ -0,0 +1,3 @@
+/spi_boot.pdf/1.6/Thu Mar 16 17:09:56 2006/-kb/
+/spi_boot_schematic.pdf/1.3/Thu Apr 14 21:20:35 2005/-kb/
+D/src////
diff --git a/fpga/usrp2/opencores/spi_boot/doc/CVS/Repository b/fpga/usrp2/opencores/spi_boot/doc/CVS/Repository
new file mode 100644
index 000000000..07fb78846
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/doc
diff --git a/fpga/usrp2/opencores/spi_boot/doc/CVS/Root b/fpga/usrp2/opencores/spi_boot/doc/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/doc/CVS/Template b/fpga/usrp2/opencores/spi_boot/doc/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf
new file mode 100644
index 000000000..a889c3f22
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/spi_boot.pdf
diff --git a/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf b/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
new file mode 100644
index 000000000..92755d5f3
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/spi_boot_schematic.pdf
diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Entries b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Entries
new file mode 100644
index 000000000..b2d32af23
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Entries
@@ -0,0 +1,10 @@
+/architecture.eps/1.4/Thu Apr 14 21:18:11 2005/-kb/
+/architecture.fig/1.4/Thu Apr 14 21:18:11 2005/-kb/
+/initialization.eps/1.2/Thu Mar 16 15:41:16 2006/-kb/
+/initialization.fig/1.2/Thu Mar 16 15:41:16 2006/-kb/
+/memory_organization.eps/1.2/Thu Mar 16 16:50:57 2006/-kb/
+/memory_organization.fig/1.2/Thu Mar 16 16:50:57 2006/-kb/
+/spi_boot.sxw/1.6/Thu Mar 16 17:09:31 2006/-kb/
+/transfer.eps/1.1/Sun Feb 27 19:24:30 2005/-kb/
+/transfer.fig/1.1/Sun Feb 27 19:24:35 2005/-kb/
+D
diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Repository b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Repository
new file mode 100644
index 000000000..5f8aafef8
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/doc/src
diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Root b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Template b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/CVS/Template
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new file mode 100644
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diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/initialization.fig b/fpga/usrp2/opencores/spi_boot/doc/src/initialization.fig
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+$F2psEnd
+rs
diff --git a/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig b/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig
new file mode 100644
index 000000000..3d1724050
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/doc/src/transfer.fig
@@ -0,0 +1,119 @@
+#FIG 3.2
+Landscape
+Center
+Metric
+A4      
+65.00
+Single
+-2
+1200 2
+6 2700 4725 4860 5445
+6 2970 4860 4590 5265
+4 1 0 50 0 16 10 0.0000 4 120 435 3780 5017 CMD18\001
+4 1 0 50 0 16 10 0.0000 4 120 1560 3780 5242 READ_MULTIPLE_BLOCKS\001
+-6
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 2745 4770 4815 4770 4815 5400 2745 5400 2745 4770
+-6
+6 3015 2745 4545 3465
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+	 3060 2790 4500 2790 4500 3420 3060 3420 3060 2790
+4 1 0 50 0 16 10 0.0000 4 120 705 3780 3150 Wait for start\001
+-6
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+	 3780 3780 4500 4050 3780 4410 3060 4050 3780 3780
+4 1 0 50 0 16 10 0.0000 4 135 615 3780 4132 mode = 1?\001
+-6
+6 3015 5715 4545 6435
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 3060 5760 4500 5760 4500 6390 3060 6390 3060 5760
+4 1 0 50 0 16 10 0.0000 4 120 645 3780 6120 Read block\001
+-6
+6 3015 6705 4545 7425
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+	 3780 6750 4500 7020 3780 7380 3060 7020 3780 6750
+4 1 0 50 0 16 10 0.0000 4 120 675 3780 7102 ???_done?\001
+-6
+6 2835 7695 4725 8415
+6 3105 7830 4455 8235
+4 1 0 50 0 16 10 0.0000 4 120 435 3780 7987 CMD12\001
+4 1 0 50 0 16 10 0.0000 4 120 1290 3780 8212 STOP_TRANSMISSION\001
+-6
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 2880 7740 4680 7740 4680 8370 2880 8370 2880 7740
+-6
+6 5895 4725 7425 5445
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+	 5940 4770 7380 4770 7380 5400 5940 5400 5940 4770
+4 1 0 50 0 16 10 0.0000 4 135 960 6660 5130 Activate config_n\001
+-6
+6 5895 5715 7425 6435
+2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 6660 5760 7380 6030 6660 6390 5940 6030 6660 5760
+4 1 0 50 0 16 10 0.0000 4 135 855 6660 6112 cfg_init_n low?\001
+-6
+6 5895 6705 7425 7425
+2 2 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 5940 6750 7380 6750 7380 7380 5940 7380 5940 6750
+4 1 0 50 0 16 10 0.0000 4 135 1125 6660 7110 Deactivate config_n\001
+-6
+6 5895 7695 7425 8415
+2 3 0 2 0 7 50 0 -1 0.000 0 0 -1 0 0 5
+	 6660 7740 7380 8010 6660 8370 5940 8010 6660 7740
+4 1 0 50 0 16 10 0.0000 4 135 915 6660 8092 cfg_init_n high?\001
+-6
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 3420 3780 3780
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 4410 3780 4770
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 5400 3780 5760
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 3780 6390 3780 6750
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+	1 1 1.00 45.00 90.00
+	 3780 7380 3780 7740
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4
+	1 1 1.00 45.00 90.00
+	 4545 7020 5130 7020 5130 5535 3780 5535
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 6
+	1 1 1.00 45.00 90.00
+	 3780 8370 3780 8640 2520 8640 2520 2520 3780 2520 3780 2790
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
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+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 3
+	1 1 1.00 45.00 90.00
+	 4500 4050 6660 4050 6660 4770
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4
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+	 7380 6030 7920 6030 7920 4050 6660 4050
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 4
+	1 1 1.00 45.00 90.00
+	 7380 8010 7920 8010 7920 6525 6660 6525
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 5
+	1 1 1.00 45.00 90.00
+	 6660 8370 6660 8640 5310 8640 5310 4545 3780 4545
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
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+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
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+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+	1 1 1.00 45.00 90.00
+	 6660 7380 6660 7740
+4 0 0 50 0 16 10 0.0000 4 105 210 3870 7560 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 4590 6930 No\001
+4 0 0 50 0 16 10 0.0000 4 105 240 4770 3600 start\001
+4 2 0 50 0 16 10 0.0000 4 105 165 3690 4590 No\001
+4 0 0 50 0 16 10 0.0000 4 105 210 4590 3960 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 7470 5940 No\001
+4 2 0 50 0 16 10 0.0000 4 105 210 6570 6570 Yes\001
+4 0 0 50 0 16 10 0.0000 4 105 165 7470 7920 No\001
+4 0 0 50 0 16 10 0.0000 4 105 210 6750 8550 Yes\001
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/CVS/Entries b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Entries
new file mode 100644
index 000000000..a4756ee6f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Entries
@@ -0,0 +1 @@
+D/vhdl////
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/CVS/Repository b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Repository
new file mode 100644
index 000000000..dcb0a69bc
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/rtl
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/CVS/Root b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/CVS/Template b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries
new file mode 100644
index 000000000..880f353ca
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Entries
@@ -0,0 +1,15 @@
+/chip-e.vhd/1.3/Thu Apr  7 20:44:23 2005//
+/chip-full-a.vhd/1.6/Thu Apr  7 20:44:23 2005//
+/chip-full-c.vhd/1.1/Tue Feb  8 20:41:31 2005//
+/chip-minimal-a.vhd/1.6/Thu Apr  7 20:44:23 2005//
+/chip-minimal-c.vhd/1.1/Tue Feb  8 20:41:32 2005//
+/chip-mmc-a.vhd/1.6/Thu Apr  7 20:44:23 2005//
+/chip-mmc-c.vhd/1.1/Tue Feb  8 20:41:32 2005//
+/chip-sd-a.vhd/1.6/Thu Apr  7 20:44:23 2005//
+/chip-sd-c.vhd/1.1/Tue Feb  8 20:41:33 2005//
+/spi_boot-c.vhd/1.2/Fri Feb 18 06:42:11 2005//
+/spi_boot.vhd/1.9/Sun Feb 25 18:24:12 2007//
+/spi_boot_pack-p.vhd/1.1/Tue Feb  8 20:41:33 2005//
+/spi_counter-c.vhd/1.1/Tue Feb  8 20:41:33 2005//
+/spi_counter.vhd/1.2/Sun Feb 25 18:24:12 2007//
+D/sample////
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository
new file mode 100644
index 000000000..a09f391ea
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/rtl/vhdl
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd
new file mode 100644
index 000000000..0bdd05aff
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-e.vhd
@@ -0,0 +1,91 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel
+--
+-- $Id: chip-e.vhd,v 1.3 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity chip is
+
+  port (
+    -- System Interface -------------------------------------------------------
+    clk_i          : in  std_logic;
+    reset_i        : in  std_logic;
+    set_sel_n_i    : in  std_logic_vector(3 downto 0);
+    -- SD Card Interface ------------------------------------------------------
+    spi_clk_o      : out std_logic;
+    spi_cs_n_o     : out std_logic;
+    spi_data_in_i  : in  std_logic;
+    spi_data_out_o : out std_logic;
+    -- FPGA Configuration Interface -------------------------------------------
+    start_i        : in  std_logic;
+    mode_i         : in  std_logic;
+    config_n_o     : out std_logic;
+    detached_o     : out std_logic;
+    cfg_init_n_i   : in  std_logic;
+    cfg_done_i     : in  std_logic;
+    dat_done_i     : in  std_logic;
+    cfg_clk_o      : out std_logic;
+    cfg_dat_o      : out std_logic
+  );
+
+end chip;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-e.vhd,v $
+-- Revision 1.3  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.2  2005/03/08 22:07:11  arniml
+-- added set selection
+--
+-- Revision 1.1  2005/02/08 20:41:30  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
new file mode 100644
index 000000000..e43ecb3c4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with full feature set
+--
+-- $Id: chip-full-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture full of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 12,       -- 512 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 1,        -- use SD specific initialization
+      mmc_compat_clk_div_g => 13,       -- MMC compat 400 kHz > 10 MHz / (13*2)
+      width_mmc_clk_div_g  => 4         -- need 5 bits for MMC compat divider
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i          => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end full;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-full-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:11  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:37  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:31  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
new file mode 100644
index 000000000..da88552c4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-full-c.vhd,v 1.1 2005/02/08 20:41:31 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_full_c0 of chip is
+
+  for full
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_full_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
new file mode 100644
index 000000000..090d0b79c
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with minimal feature set
+--
+-- $Id: chip-minimal-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture minimal of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 6,        -- 8 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 0,        -- no SD specific initialization
+      mmc_compat_clk_div_g => 0,        -- no MMC compatibility
+      width_mmc_clk_div_g  => 0         -- no MMC compatibility
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i            => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end minimal;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-minimal-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:12  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:39  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:31  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
new file mode 100644
index 000000000..5547747b2
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-minimal-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_minimal_c0 of chip is
+
+  for minimal
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_minimal_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
new file mode 100644
index 000000000..cef42d268
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with MMC feature set
+--
+-- $Id: chip-mmc-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture mmc of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 12,       -- 512 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 0,        -- no SD specific initialization
+      mmc_compat_clk_div_g => 13,       -- MMC compat 400 kHz > 10 MHz / (13*2)
+      width_mmc_clk_div_g  => 4         -- need 5 bits for MMC compat divider
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i            => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end mmc;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-mmc-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:13  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:39  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:32  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
new file mode 100644
index 000000000..6131013e4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-mmc-c.vhd,v 1.1 2005/02/08 20:41:32 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_mmc_c0 of chip is
+
+  for mmc
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_mmc_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
new file mode 100644
index 000000000..c955a5f3a
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-a.vhd
@@ -0,0 +1,164 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Chip toplevel design with SD feature set
+--
+-- $Id: chip-sd-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+architecture sd of chip is
+
+  component spi_boot
+    generic (
+      width_set_sel_g      : integer := 4;
+      width_bit_cnt_g      : integer := 6;
+      width_img_cnt_g      : integer := 2;
+      num_bits_per_img_g   : integer := 18;
+      sd_init_g            : integer := 0;
+      mmc_compat_clk_div_g : integer := 0;
+      width_mmc_clk_div_g  : integer := 0;
+      reset_level_g        : integer := 0
+    );
+    port (
+      clk_i          : in  std_logic;
+      reset_i        : in  std_logic;
+      set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+      spi_clk_o      : out std_logic;
+      spi_cs_n_o     : out std_logic;
+      spi_data_in_i  : in  std_logic;
+      spi_data_out_o : out std_logic;
+      spi_en_outs_o  : out std_logic;
+      start_i        : in  std_logic;
+      mode_i         : in  std_logic;
+      config_n_o     : out std_logic;
+      detached_o     : out std_logic;
+      cfg_init_n_i   : in  std_logic;
+      cfg_done_i     : in  std_logic;
+      dat_done_i     : in  std_logic;
+      cfg_clk_o      : out std_logic;
+      cfg_dat_o      : out std_logic
+    );
+  end component;
+
+  signal spi_clk_s      : std_logic;
+  signal spi_cs_n_s     : std_logic;
+  signal spi_data_out_s : std_logic;
+  signal spi_en_outs_s  : std_logic;
+
+  signal set_sel_s      : std_logic_vector(3 downto 0);
+
+begin
+
+  set_sel_s <= not set_sel_n_i;
+
+  spi_boot_b : spi_boot
+    generic map (
+      width_set_sel_g      => 4,        -- 16 sets
+      width_bit_cnt_g      => 12,       -- 512 bytes per block
+      width_img_cnt_g      => 2,        -- 4 images
+      num_bits_per_img_g   => 18,       -- 256 kByte per image
+      sd_init_g            => 1,        -- SD specific initialization
+      mmc_compat_clk_div_g => 0,        -- no MMC compatibility
+      width_mmc_clk_div_g  => 0         -- no MMC compatibility
+    )
+    port map (
+      clk_i                => clk_i,
+      reset_i              => reset_i,
+      set_sel_i            => set_sel_s,
+      spi_clk_o            => spi_clk_s,
+      spi_cs_n_o           => spi_cs_n_s,
+      spi_data_in_i        => spi_data_in_i,
+      spi_data_out_o       => spi_data_out_s,
+      spi_en_outs_o        => spi_en_outs_s,
+      start_i              => start_i,
+      mode_i               => mode_i,
+      config_n_o           => config_n_o,
+      detached_o           => detached_o,
+      cfg_init_n_i         => cfg_init_n_i,
+      cfg_done_i           => cfg_done_i,
+      dat_done_i           => dat_done_i,
+      cfg_clk_o            => cfg_clk_o,
+      cfg_dat_o            => cfg_dat_o
+    );
+
+  -----------------------------------------------------------------------------
+  -- Three state drivers for SPI outputs.
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_cs_n_o     <=   spi_cs_n_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+  spi_data_out_o <=   spi_data_out_s
+                    when spi_en_outs_s = '1' else
+                      'Z';
+
+end sd;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: chip-sd-a.vhd,v $
+-- Revision 1.6  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.5  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.4  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.3  2005/02/18 06:42:14  arniml
+-- clarify wording for images
+--
+-- Revision 1.2  2005/02/16 18:54:39  arniml
+-- added tri-state drivers for spi outputs
+--
+-- Revision 1.1  2005/02/08 20:41:32  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
new file mode 100644
index 000000000..91e41ddfb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-sd-c.vhd
@@ -0,0 +1,19 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: chip-sd-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration chip_sd_c0 of chip is
+
+  for sd
+
+    for spi_boot_b : spi_boot
+      use configuration work.spi_boot_rtl_c0;
+    end for;
+
+  end for;
+
+end chip_sd_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries
new file mode 100644
index 000000000..552a7baad
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Entries
@@ -0,0 +1,3 @@
+/ram_loader-c.vhd/1.1/Sun Apr 10 18:02:32 2005//
+/ram_loader.vhd/1.2/Sun Apr 10 17:17:23 2005//
+D
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository
new file mode 100644
index 000000000..026a73983
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/rtl/vhdl/sample
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
new file mode 100644
index 000000000..8b26c4d57
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader-c.vhd
@@ -0,0 +1,10 @@
+-------------------------------------------------------------------------------
+-- $Id: ram_loader-c.vhd,v 1.1 2005/04/10 18:02:32 arniml Exp $
+-------------------------------------------------------------------------------
+
+configuration ram_loader_rtl_c0 of ram_loader is
+
+  for rtl
+  end for;
+
+end ram_loader_rtl_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
new file mode 100644
index 000000000..c604876d7
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/sample/ram_loader.vhd
@@ -0,0 +1,355 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Sample client for loading an image to asynchronous SRAM
+--
+-- $Id: ram_loader.vhd,v 1.2 2005/04/10 17:17:23 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity ram_loader is
+
+  port (
+    -- Global Interface -------------------------------------------------------
+    clk_i      : in    std_logic;
+    reset_i    : in    std_logic;
+    lamp_o     : out   std_logic;
+    -- Config Interface -------------------------------------------------------
+    cfg_clk_i  : in    std_logic;
+    cfg_data_i : in    std_logic;
+    start_o    : out   std_logic;
+    mode_o     : out   std_logic;
+    done_o     : out   std_logic;
+    detached_i : in    std_logic;
+    -- Asynchronous RAM Interface ---------------------------------------------
+    ram_addr_o : out   std_logic_vector(15 downto 0);
+    ram_data_b : out   std_logic_vector( 7 downto 0);
+    ram_ce_no  : out   std_logic_vector( 3 downto 0);
+    ram_oe_no  : out   std_logic;
+    ram_we_no  : out   std_logic
+  );
+
+end ram_loader;
+
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of ram_loader is
+
+  signal addr_q     : unsigned(17 downto 0);
+  signal inc_addr_s : boolean;
+
+  signal shift_dat_q : std_logic_vector(7 downto 0);
+  signal ser_dat_q   : std_logic_vector(7 downto 0);
+  signal bit_q       : unsigned(2 downto 0);
+  signal bit_ovfl_q  : boolean;
+
+  type fsm_t is (IDLE,
+                 WE_ON,
+                 WE_OFF,
+                 INC_ADDR1, INC_ADDR2,
+                 FINISHED);
+  signal fsm_s,
+         fsm_q  : fsm_t;
+  signal done_q          : std_logic;
+  signal done_s          : boolean;
+  signal mode_q,
+         mode_s          : std_logic;
+
+  signal ram_we_n_q,
+         ram_we_n_s  : std_logic;
+  signal ram_ce_n_q,
+         ram_ce_n_s  : std_logic_vector(3 downto 0);
+
+  type start_fsm_t is (WAIT_DETACH,
+                       CHECK_NO_DONE,
+                       WAIT_DONE);
+  signal start_fsm_s,
+         start_fsm_q  : start_fsm_t;
+
+  signal start_s,
+         start_q         : std_logic;
+  signal enable_s,
+         enable_q        : boolean;
+
+begin
+
+  -----------------------------------------------------------------------------
+  -- Process seq
+  --
+  -- Purpose:
+  --   Implements the sequential elements clocked with cfg_clk_i.
+  --
+  seq: process (cfg_clk_i, reset_i)
+  begin
+    if reset_i = '0' then
+      addr_q      <= (others => '0');
+      shift_dat_q <= (others => '0');
+      ser_dat_q   <= (others => '0');
+      bit_q       <= (others => '0');
+      bit_ovfl_q  <= false;
+      fsm_q       <= IDLE;
+      ram_we_n_q  <= '1';
+      ram_ce_n_q  <= (others => '1');
+      done_q      <= '0';
+      mode_q      <= '0';
+
+    elsif cfg_clk_i'event and cfg_clk_i = '1' then
+      if inc_addr_s then
+        addr_q <= addr_q + 1;
+      end if;
+
+      if enable_q then
+        bit_q      <= bit_q + 1;
+        bit_ovfl_q <= bit_q = 7;
+
+        shift_dat_q(0) <= cfg_data_i;
+        shift_dat_q(7 downto 1) <= shift_dat_q(6 downto 0);
+      end if;
+
+      -- update register when 8 serial bits have been shifted in
+      if bit_ovfl_q then
+        ser_dat_q <= shift_dat_q;
+      end if;
+
+      fsm_q <= fsm_s;
+
+      ram_we_n_q <= ram_we_n_s;
+      ram_ce_n_q <= ram_ce_n_s;
+
+      -- done only settable once
+      if done_s then
+        done_q <= '1';
+      end if;
+
+      mode_q <= mode_s;
+
+    end if;
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process fsm
+  --
+  -- Purpose:
+  --   Implements the combinational logic of the RAM loader FSM.
+  --
+  fsm: process (fsm_q,
+                bit_ovfl_q,
+                start_q,
+                addr_q)
+  begin
+    -- default assignments
+    inc_addr_s      <= false;
+    ram_we_n_s      <= '1';
+    done_s          <= false;
+    fsm_s           <= IDLE;
+    lamp_o          <= '1';
+    mode_s          <= '0';
+
+    case fsm_q is
+      when IDLE =>
+        lamp_o <= '0';
+        if start_q = '1' then
+          if bit_ovfl_q then
+            fsm_s <= WE_ON;
+          end if;
+        end if;
+
+      when WE_ON =>
+        ram_we_n_s <= '0';
+        fsm_s      <= WE_OFF;
+
+      when WE_OFF =>
+        fsm_s <= INC_ADDR1;
+
+      when INC_ADDR1 =>
+        fsm_s      <= INC_ADDR2;
+
+      when INC_ADDR2 =>
+        if addr_q = "001111111111111111" then  -- load only 64k
+          fsm_s <= FINISHED;
+          done_s <= true;
+          mode_s <= '1';
+        else
+          inc_addr_s <= true;
+          fsm_s      <= IDLE;
+        end if;
+
+      when FINISHED =>
+        fsm_s  <= FINISHED;
+        lamp_o <= '1';
+        mode_s <= '1';
+
+      when others =>
+    end case;
+
+  end process fsm;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process ce_gen
+  --
+  -- Purpose:
+  --   Generates the four CE signals for the external RAM chips.
+  --
+  ce_gen: process (addr_q)
+  begin
+    ram_ce_n_s <= (others => '1');
+    ram_ce_n_s(to_integer(addr_q(17 downto 16))) <= '0';
+  end process ce_gen;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process start_seq
+  --
+  -- Purpose:
+  --   Implements the sequential elements clocked with clk_i.
+  --
+  start_seq: process (clk_i, reset_i)
+  begin
+    if reset_i = '0' then
+      start_fsm_q <= WAIT_DETACH;
+      start_q     <= '0';
+      enable_q    <= false;
+
+    elsif clk_i'event and clk_i = '1' then
+      start_fsm_q <= start_fsm_s;
+
+      enable_q    <= enable_s;
+
+      start_q     <= start_s;
+
+    end if;
+  end process start_seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process start_comb
+  --
+  -- Purpose:
+  --   Implements the combinational logic of the start FSM.
+  --
+  start_comb: process (start_fsm_q,
+                       detached_i,
+                       done_q,
+                       enable_q,
+                       start_q)
+  begin
+    -- default assignments
+    start_fsm_s <= WAIT_DETACH;
+    enable_s    <= enable_q;
+    start_s     <= start_q;
+
+    case start_fsm_q is
+      -- Wait for detached_i to become '1'
+      -- This state is entered/left twice:
+      -- 1. after reset to start the data download
+      -- 2. after data download to start the next configuration cycle
+      when WAIT_DETACH =>
+        if detached_i = '1' then
+          start_fsm_s <= CHECK_NO_DONE;
+          enable_s    <= true;
+          start_s     <= '1';
+
+        else
+          start_fsm_s <= WAIT_DETACH;
+        end if;
+
+      -- Wait until done_q is '0'
+      -- This ensures that the FSM stalls when it has started the configuration
+      -- download. There must be no further action in this case.
+      when CHECK_NO_DONE =>
+        if done_q = '0' then
+          start_fsm_s <= WAIT_DONE;
+        else
+          start_fsm_s <= CHECK_NO_DONE;
+        end if;
+
+      -- Wait until done_q is '1'
+      -- done_q is the signal that the main FSM has finished its work. We
+      -- need to start the configuration download.
+      when WAIT_DONE =>
+        if done_q = '1' then
+          start_fsm_s <= WAIT_DETACH;
+          enable_s    <= false;
+          start_s     <= '0';
+        else
+          start_fsm_s <= WAIT_DONE;
+        end if;
+
+      when others =>
+        null;
+
+    end case;
+
+  end process start_comb;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  start_o    <= start_q;
+  mode_o     <= mode_q;
+  done_o     <=   done_q
+                when start_q = '1' else
+                  '1';
+  ram_addr_o <= std_logic_vector(addr_q(15 downto 0));
+  ram_data_b <= ser_dat_q;
+  ram_oe_no  <= '1';
+  ram_ce_no  <= ram_ce_n_q;
+  ram_we_no  <= ram_we_n_q;
+
+end rtl;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
new file mode 100644
index 000000000..6f11ed34b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot-c.vhd
@@ -0,0 +1,27 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot-c.vhd,v 1.2 2005/02/18 06:42:11 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration spi_boot_rtl_c0 of spi_boot is
+
+  for rtl
+
+    for img_cnt
+      for img_cnt_b : spi_counter
+        use configuration work.spi_counter_rtl_c0;
+      end for;
+    end for;
+
+    for mmc_cnt
+      for mmc_cnt_b : spi_counter
+        use configuration work.spi_counter_rtl_c0;
+      end for;
+    end for;
+
+  end for;
+
+end spi_boot_rtl_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
new file mode 100644
index 000000000..3d2b81da7
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd
@@ -0,0 +1,979 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spi_boot is
+
+  generic (
+    -- width of set selection
+    width_set_sel_g      : integer := 4;
+    -- width of bit counter: minimum 6, maximum 12
+    width_bit_cnt_g      : integer := 6;
+    -- width of image counter: minimum 0, maximum n
+    width_img_cnt_g      : integer := 2;
+    -- number of bits required to address one image
+    num_bits_per_img_g   : integer := 18;
+    -- SD specific initialization
+    sd_init_g            : integer := 0;
+    -- clock divider to reach 400 kHz for MMC compatibility
+    mmc_compat_clk_div_g : integer := 0;
+    width_mmc_clk_div_g  : integer := 0;
+    -- active level of reset_i
+    reset_level_g        : integer := 0
+  );
+
+  port (
+    -- System Interface -------------------------------------------------------
+    clk_i          : in  std_logic;
+    reset_i        : in  std_logic;
+    set_sel_i      : in  std_logic_vector(width_set_sel_g-1 downto 0);
+    -- Card Interface ---------------------------------------------------------
+    spi_clk_o      : out std_logic;
+    spi_cs_n_o     : out std_logic;
+    spi_data_in_i  : in  std_logic;
+    spi_data_out_o : out std_logic;
+    spi_en_outs_o  : out std_logic;
+    -- FPGA Configuration Interface -------------------------------------------
+    start_i        : in  std_logic;
+    mode_i         : in  std_logic;
+    config_n_o     : out std_logic;
+    detached_o     : out std_logic;
+    cfg_init_n_i   : in  std_logic;
+    cfg_done_i     : in  std_logic;
+    dat_done_i     : in  std_logic;
+    cfg_clk_o      : out std_logic;
+    cfg_dat_o      : out std_logic
+  );
+
+end spi_boot;
+
+
+library ieee;
+use ieee.numeric_std.all;
+use work.spi_boot_pack.all;
+
+architecture rtl of spi_boot is
+
+  component spi_counter
+    generic (
+      cnt_width_g   : integer := 4;
+      cnt_max_g     : integer := 15
+    );
+    port (
+      clk_i      : in  std_logic;
+      reset_i    : in  boolean;
+      cnt_en_i   : in  boolean;
+      cnt_o      : out std_logic_vector(cnt_width_g-1 downto 0);
+      cnt_ovfl_o : out boolean
+    );
+  end component;
+
+
+  -----------------------------------------------------------------------------
+  -- States of the controller FSM
+  --
+  type ctrl_states_t is (POWER_UP1, POWER_UP2,
+                         CMD0,
+                         CMD1,
+                         CMD55, ACMD41,
+                         CMD16,
+                         WAIT_START,
+                         WAIT_INIT_LOW, WAIT_INIT_HIGH,
+                         CMD18, CMD18_DATA,
+                         CMD12,
+                         INC_IMG_CNT);
+  --
+  signal ctrl_fsm_q,
+         ctrl_fsm_s  : ctrl_states_t;
+  --
+  -----------------------------------------------------------------------------
+
+  -----------------------------------------------------------------------------
+  -- States of the command FSM
+  --
+  type cmd_states_t is (CMD, START, R1, PAUSE);
+  --
+  signal cmd_fsm_q,
+         cmd_fsm_s  : cmd_states_t;
+  --
+  -----------------------------------------------------------------------------
+
+  subtype op_r     is integer range 5 downto 0;
+  type    res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7);
+  signal  bit_cnt_q  : unsigned(width_bit_cnt_g-1 downto 0);
+  signal  res_bc_s   : res_bc_t;
+  signal  upper_bitcnt_zero_s : boolean;
+
+  signal cfg_dat_q : std_logic;
+
+  signal spi_clk_q         : std_logic;
+  signal spi_clk_rising_q  : boolean;
+  signal spi_clk_falling_q : boolean;
+  signal spi_dat_q,
+         spi_dat_s         : std_logic;
+  signal spi_cs_n_q,
+         spi_cs_n_s        : std_logic;
+
+  signal cfg_clk_q      : std_logic;
+
+  signal start_q        : std_logic;
+
+  signal img_cnt_s      : std_logic_vector(width_img_cnt_g downto 0);
+  signal cnt_en_img_s   : boolean;
+  signal mmc_cnt_ovfl_s : boolean;
+  signal mmc_compat_s   : boolean;
+
+  signal cmd_finished_s : boolean;
+
+  signal r1_result_q    : std_logic;
+  signal done_q,
+         send_cmd12_q   : boolean;
+
+  signal en_outs_s,
+         en_outs_q      : boolean;
+
+  signal reset_s        : boolean;
+
+  signal true_s         : boolean;
+
+begin
+
+  true_s <= true;
+
+  reset_s <=   true
+             when (reset_level_g = 1 and reset_i = '1') or
+                  (reset_level_g = 0 and reset_i = '0') else
+               false;
+
+  -----------------------------------------------------------------------------
+  -- Process seq
+  --
+  -- Purpose:
+  --   Implements several sequential elements.
+  --
+  seq: process (clk_i, reset_s)
+
+    variable bit_cnt_v : unsigned(1 downto 0);
+
+  begin
+    if reset_s then
+      -- reset bit counter to 63 for power up
+      bit_cnt_q       <= (others => '0');
+      bit_cnt_q(op_r) <= "111111";
+      spi_dat_q    <= '1';
+      spi_cs_n_q   <= '1';
+      cfg_dat_q    <= '1';
+      start_q      <= '0';
+      done_q       <= false;
+      send_cmd12_q <= false;
+      ctrl_fsm_q   <= POWER_UP1;
+      cmd_fsm_q    <= CMD;
+      r1_result_q  <= '0';
+      en_outs_q    <= false;
+
+    elsif clk_i'event and clk_i = '1' then
+      -- bit counter control
+      if spi_clk_rising_q then
+        case res_bc_s is
+          when NONE =>
+            bit_cnt_q       <= bit_cnt_q - 1;
+          when RES_MAX =>
+            bit_cnt_q       <= (others => '1');
+          when RES_47 =>
+            bit_cnt_q       <= (others => '0');
+            bit_cnt_q(op_r) <= "101111";
+          when RES_15 =>
+            bit_cnt_q       <= (others => '0');
+            bit_cnt_q(op_r) <= "001111";
+          when RES_7 =>
+            bit_cnt_q       <= (others => '0');
+            bit_cnt_q(op_r) <= "000111";
+          when others =>
+            bit_cnt_q       <= (others => '0');
+        end case;
+      end if;
+
+      -- Card data output register
+      -- spi_clk_falling_q acts as enable during MMC clock compatibility mode.
+      -- As soon as this mode is left, the register must start latching.
+      -- There is no explicit relation to spi_clk_q anymore in normal mode.
+      -- Instead, spi_dat_s is operated by bit_cnt_q above which changes its
+      -- value after the rising edge of spi_clk_q.
+      --   -> spi_dat_q changes upon falling edge of spi_clk_q
+      if spi_clk_falling_q or not mmc_compat_s then
+        spi_dat_q <= spi_dat_s;
+      end if;
+
+      -- config data output register
+      -- a new value is loaded when config clock is high,
+      -- i.e. input data is sampled with rising spi_clk
+      -- while output value changes on falling edge of cfg_clk
+      if cfg_clk_q = '1' and spi_clk_rising_q then
+        cfg_dat_q <= spi_data_in_i;
+      end if;
+
+      -- Controller FSM state
+      ctrl_fsm_q <= ctrl_fsm_s;
+
+      -- Command FSM state
+      cmd_fsm_q <= cmd_fsm_s;
+
+      -- CS signal for SPI card
+      if spi_clk_q = '1' then
+        spi_cs_n_q <= spi_cs_n_s;
+      end if;
+
+      -- Extract flags from R1 response
+      if cmd_fsm_q = R1 then
+        bit_cnt_v := bit_cnt_q(1 downto 0);
+        case bit_cnt_v(1 downto 0) is
+          when "10" =>
+            -- always save "Illegal Command" flag
+            r1_result_q <= to_X01(spi_data_in_i);
+          when "00" =>
+            -- overwrite with "Idle State" flag when not in CMD55
+            if ctrl_fsm_q /= CMD55 then
+              r1_result_q <= to_X01(spi_data_in_i);
+            end if;
+          when others =>
+            null;
+        end case;
+      end if;
+
+      -- Start trigger register for rising edge detection
+      -- the reset value is '0' thus a rising edge will always be detected
+      -- after reset even though start_i is tied to '1'
+      if start_i = '0' then
+        start_q <= '0';
+      elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then
+        start_q <= start_i;
+      end if;
+
+      -- Marker for cfg_done and dat_done
+      if ctrl_fsm_q = CMD18_DATA then
+        if cfg_done_i = '1' and dat_done_i = '1' then
+          done_q       <= true;
+        end if;
+
+        if done_q and
+           (not upper_bitcnt_zero_s or cmd_fsm_q = START) then
+          -- activate sending of CMD12 when it is safe:
+          -- * upper bits of bit counter are not zero
+          --   -> transmission of CMD12 is not running
+          -- * cmd FSM is in START state
+          --   -> also no transmission running
+          send_cmd12_q <= true;
+        end if;
+      elsif ctrl_fsm_q = WAIT_START then
+        -- reset done_q when WAIT_START has been reached
+        -- this is necessary to let the stop transmission process come to
+        -- an end without interruption or generation of unwanted cfg_clk_q
+        done_q         <= false;
+        send_cmd12_q   <= false;
+      end if;
+
+      -- output enable
+      if spi_clk_rising_q then
+        en_outs_q <= en_outs_s;
+      end if;
+
+    end if;
+
+  end process seq;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process upper_bits
+  --
+  -- Purpose:
+  --   Detects that the upper bits of the bit counter are zero.
+  --   Upper bits = n downto 6, i.e. the optional part that is not required for
+  --   commands but for extension of data blocks.
+  --
+  upper_bits: process (bit_cnt_q)
+    variable zero_v : boolean;
+  begin
+
+    zero_v     := true;
+    for i in bit_cnt_q'high downto 6 loop
+      if bit_cnt_q(i) = '1' then
+        zero_v := false;
+      end if;
+    end loop;
+
+    upper_bitcnt_zero_s <= zero_v;
+
+  end process upper_bits;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process clk_gen
+  --
+  -- Purpose:
+  --   Generates clocks for card and FPGA configuration.
+  --   The card clock is free running with a divide by two of clk_i.
+  --   The clock for FPGA config has an enable and is stopped on high level.
+  --   There is a phase shift of half a period between spi_clk and cfg_clk.
+  --
+  clk_gen: process (clk_i, reset_s)
+  begin
+    if reset_s then
+      spi_clk_q        <= '0';
+      cfg_clk_q        <= '1';
+
+    elsif clk_i'event and clk_i = '1' then
+
+      -- spi_clk_q rises according to the flag
+      -- it falls with overflow indication
+      -- the resulting duty cycle is not exactly 50:50,
+      -- high time is a bit longer
+      if mmc_compat_s then
+        -- MMC clock compatibility mode:
+        -- spi_clk_q rises when flagged by spi_clk_rising_q
+        if spi_clk_rising_q then
+          spi_clk_q <= '1';
+        elsif mmc_cnt_ovfl_s then
+          -- upon counter overflow spi_clk_q falls in case it does not rise
+          spi_clk_q <= '0';
+        end if;
+      else
+        -- normal mode
+        -- spi_clk_q follows spi_clk_rising_q
+        if spi_clk_rising_q then
+          spi_clk_q <= '1';
+        else
+          spi_clk_q <= '0';
+        end if;
+      end if;
+
+      -- clock for FPGA config must be enabled and follows spi_clk
+      if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and
+         not done_q then
+        cfg_clk_q <= spi_clk_q;
+      else
+        cfg_clk_q <= '1';
+      end if;
+
+    end if;
+
+  end process clk_gen;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Indication flags for rising and falling spi_clk_q.
+  -- Essential for MMC clock compatibility mode.
+  -----------------------------------------------------------------------------
+  mmc_comap: if mmc_compat_clk_div_g > 0 generate
+    mmc_compat_sig: process (clk_i, reset_s)
+    begin
+      if reset_s then
+        spi_clk_rising_q  <= false;
+        spi_clk_falling_q <= false;
+
+      elsif clk_i'event and clk_i = '1' then
+        if mmc_compat_s then
+          -- MMC clock compatibility mode:
+          -- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q
+          -- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q
+          if mmc_cnt_ovfl_s then
+            spi_clk_rising_q  <= spi_clk_q = '0';
+            spi_clk_falling_q <= spi_clk_q = '1';
+          else
+            spi_clk_rising_q  <= false;
+            spi_clk_falling_q <= false;
+          end if;
+        else
+          -- normal mode
+          spi_clk_rising_q  <= not spi_clk_rising_q;
+          spi_clk_falling_q <= true;
+        end if;
+
+      end if;
+    end process mmc_compat_sig;
+  end generate;
+
+  no_mmc_compat: if mmc_compat_clk_div_g = 0 generate
+    -- SPI clock rising whenever spi_clk_q is '0'
+    spi_clk_rising_q  <= spi_clk_q = '0';
+    -- SPI clock falling whenever spi_clk_q is '1'
+    spi_clk_falling_q <= spi_clk_q = '1';
+  end generate;
+
+
+  -----------------------------------------------------------------------------
+  -- Process ctrl_fsm
+  --
+  -- Purpose:
+  --   Implements the controller FSM.
+  --
+  ctrl_fsm: process (ctrl_fsm_q,
+                     cmd_finished_s, r1_result_q,
+                     start_i, start_q, mode_i,
+                     cfg_init_n_i)
+
+    variable mmc_compat_v : boolean;
+
+  begin
+    -- default assignments
+    ctrl_fsm_s   <= POWER_UP1;
+    config_n_o   <= '1';
+    cnt_en_img_s <= false;
+    spi_cs_n_s   <= '0';
+    mmc_compat_v := false;
+    en_outs_s    <= true;
+
+    case ctrl_fsm_q is
+      -- Let card finish power up, step 1 -------------------------------------
+      when POWER_UP1 =>
+        mmc_compat_v := true;
+        spi_cs_n_s   <= '1';
+        if cmd_finished_s then
+          ctrl_fsm_s <= POWER_UP2;
+        else
+          ctrl_fsm_s <= POWER_UP1;
+        end if;
+
+
+      -- Let card finish power up, step 2 -------------------------------------
+      when POWER_UP2 =>
+        mmc_compat_v := true;
+        if cmd_finished_s then
+          ctrl_fsm_s <= CMD0;
+        else
+          spi_cs_n_s <= '1';
+          ctrl_fsm_s <= POWER_UP2;
+        end if;
+
+
+      -- Issue CMD0: GO_IDLE_STATE --------------------------------------------
+      when CMD0 =>
+        mmc_compat_v   := true;
+        if cmd_finished_s then
+          if sd_init_g = 1 then
+            ctrl_fsm_s <= CMD55;
+          else
+            ctrl_fsm_s <= CMD1;
+          end if;
+        else
+          ctrl_fsm_s   <= CMD0;
+        end if;
+
+
+      -- Issue CMD55: APP_CMD -------------------------------------------------
+      when CMD55 =>
+        if sd_init_g = 1 then
+
+          mmc_compat_v   := true;
+          if cmd_finished_s then
+            if r1_result_q = '0' then
+              -- command accepted, it's an SD card
+              ctrl_fsm_s <= ACMD41;
+            else
+              -- command rejected, it's an MMC card
+              ctrl_fsm_s <= CMD1;
+            end if;
+          else
+            ctrl_fsm_s   <= CMD55;
+          end if;
+
+        end if;
+
+
+      -- Issue ACMD41: SEND_OP_COND -------------------------------------------
+      when ACMD41 =>
+        if sd_init_g = 1 then
+
+          mmc_compat_v   := true;
+          if cmd_finished_s then
+            if r1_result_q = '0' then
+              ctrl_fsm_s <= CMD16;
+            else
+              ctrl_fsm_s <= CMD55;
+            end if;
+          else
+            ctrl_fsm_s   <= ACMD41;
+          end if;
+
+        end if;
+
+
+      -- Issue CMD1: SEND_OP_COND ---------------------------------------------
+      when CMD1 =>
+        mmc_compat_v   := true;
+        if cmd_finished_s then
+          if r1_result_q = '0' then
+            ctrl_fsm_s <= CMD16;
+          else
+            ctrl_fsm_s <= CMD1;
+          end if;
+        else
+          ctrl_fsm_s   <= CMD1;
+        end if;
+
+
+      -- Issue CMD16: SET_BLOCKLEN --------------------------------------------
+      when CMD16 =>
+        if cmd_finished_s then
+          ctrl_fsm_s <= WAIT_START;
+        else
+          ctrl_fsm_s <= CMD16;
+        end if;
+
+
+      -- Wait for configuration start request ---------------------------------
+      when WAIT_START =>
+        spi_cs_n_s     <= '1';
+
+        -- detect rising edge of start_i
+        if start_i = '1' and start_q = '0' then
+          -- decide which mode is requested
+          if cmd_finished_s then
+            if mode_i = '0' then
+              ctrl_fsm_s <= CMD18;
+            else
+              ctrl_fsm_s <= WAIT_INIT_LOW;
+            end if;
+          else
+            en_outs_s    <= false;
+            ctrl_fsm_s   <= WAIT_START;
+          end if;
+        else
+          en_outs_s      <= false;
+          ctrl_fsm_s     <= WAIT_START;
+        end if;
+
+
+      -- Wait for INIT to become low ------------------------------------------
+      when WAIT_INIT_LOW =>
+        spi_cs_n_s   <= '1';
+        -- activate FPGA configuration
+        config_n_o   <= '0';
+
+        if cfg_init_n_i = '0' then
+          ctrl_fsm_s <= WAIT_INIT_HIGH;
+        else
+          ctrl_fsm_s <= WAIT_INIT_LOW;
+        end if;
+
+
+      -- Wait for INIT to become high -----------------------------------------
+      when WAIT_INIT_HIGH =>
+        spi_cs_n_s   <= '1';
+
+        if cfg_init_n_i = '1' and cmd_finished_s then
+          ctrl_fsm_s <= CMD18;
+        else
+          ctrl_fsm_s <= WAIT_INIT_HIGH;
+        end if;
+
+
+      -- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------
+      when CMD18 =>
+        if cmd_finished_s then
+          ctrl_fsm_s <= CMD18_DATA;
+        else
+          ctrl_fsm_s <= CMD18;
+        end if;
+      --
+      -- receive a data block
+      when CMD18_DATA =>
+        if cmd_finished_s then
+          ctrl_fsm_s   <= CMD12;
+        else
+          ctrl_fsm_s   <= CMD18_DATA;
+        end if;
+
+
+       -- Issued CMD12: STOP_TRANSMISSION --------------------------------------
+       when CMD12 =>
+         if cmd_finished_s then
+           ctrl_fsm_s <= INC_IMG_CNT;
+         else
+           ctrl_fsm_s <= CMD12;
+         end if;
+
+
+      -- Increment Image Counter ----------------------------------------------
+      when INC_IMG_CNT =>
+        spi_cs_n_s   <= '1';
+        ctrl_fsm_s   <= WAIT_START;
+        cnt_en_img_s <= true;
+
+
+
+      when others =>
+        null;
+
+    end case;
+
+    -- mmc_compat_s is suppressed if MMC clock compatibility is not required
+    if mmc_compat_clk_div_g > 0 then
+      mmc_compat_s <= mmc_compat_v;
+    else
+      mmc_compat_s <= false;
+    end if;
+
+  end process ctrl_fsm;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process cmd_fsm
+  --
+  -- Purpose:
+  --   Implements the command FSM.
+  --
+  cmd_fsm: process (spi_clk_rising_q,
+                    spi_data_in_i,
+                    bit_cnt_q,
+                    ctrl_fsm_q,
+                    cmd_fsm_q,
+                    send_cmd12_q)
+
+    variable cnt_zero_v     : boolean;
+    variable spi_data_low_v : boolean;
+    variable no_startbit_v  : boolean;
+
+  begin
+    -- default assignments
+    cmd_finished_s <= false;
+    cmd_fsm_s      <= CMD;
+    res_bc_s       <= NONE;
+
+    cnt_zero_v     := spi_clk_rising_q and bit_cnt_q = 0;
+    spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0';
+
+    -- these are no real commands thus there will be no startbit
+    case ctrl_fsm_q is
+      when POWER_UP1  | POWER_UP2 |
+           WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW =>
+        no_startbit_v := true;
+      when others =>
+        no_startbit_v := false;
+    end case;
+
+
+    case cmd_fsm_q is
+      -- Send the command -----------------------------------------------------
+      when CMD =>
+        if cnt_zero_v then
+          if ctrl_fsm_q /= CMD18_DATA then
+            -- normal commands including CMD12 require startbit of R1 response
+            cmd_fsm_s <= START;
+          else
+            if not send_cmd12_q then
+              -- CMD18_DATA needs to read CRC
+              cmd_fsm_s <= R1;
+              res_bc_s <= RES_15;
+            else
+              -- CMD18_DATA finished, scan for startbit of response
+              cmd_finished_s <= true;
+              cmd_fsm_s      <= START;
+            end if;
+          end if;
+        else
+          cmd_fsm_s <= CMD;
+        end if;
+
+      -- Wait for startbit of response ----------------------------------------
+      when START =>
+        -- startbit detection or skip of this check
+        if no_startbit_v and spi_clk_rising_q then
+          cmd_fsm_s   <= R1;
+          res_bc_s    <= RES_7;
+        elsif spi_data_low_v then
+          if ctrl_fsm_q /= CMD18_DATA then
+            cmd_fsm_s <= R1;
+          else
+            -- CMD18_DATA startbit detected, read payload
+            cmd_fsm_s <= CMD;
+            res_bc_s  <= RES_MAX;
+          end if;
+        else
+          cmd_fsm_s   <= START;
+          res_bc_s    <= RES_7;
+        end if;
+
+      -- Read R1 response -----------------------------------------------------
+      when R1 =>
+        if cnt_zero_v then
+          res_bc_s  <= RES_7;
+
+          if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then
+            cmd_fsm_s        <= PAUSE;
+          else
+            -- CMD18 needs another startbit detection for the data token.
+            -- CMD18_DATA needs a startbit after having received the CRC, either
+            --   * next data token
+            --   * R1 response of CMD12
+            cmd_fsm_s        <= START;
+
+            if ctrl_fsm_q = CMD18 then
+              -- CMD18 response received -> advance to CMD18_DATA
+              cmd_finished_s <= true;
+            end if;
+          end if;
+        else
+          cmd_fsm_s <= R1;
+        end if;
+
+      -- PAUSE state -> required for Nrc, card response to host command -------
+      when PAUSE =>
+        if cnt_zero_v then
+          cmd_fsm_s <= CMD;
+          res_bc_s  <= RES_47;
+          cmd_finished_s <= true;
+        else
+          cmd_fsm_s <= PAUSE;
+        end if;
+
+      when others =>
+        null;
+
+    end case;
+
+  end process cmd_fsm;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Process transmit
+  --
+  -- Purpose:
+  --   Generates the serial data output values based on the current FSM state
+  --
+  --   The local variable cmd_v is 64 bits wide in contrast to an SPI command
+  --   with 48 bits. There are two reasons for this:
+  --   * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit
+  --     counter will start from 3F on its lowest 6 bits. Therefore, it is
+  --     necessary to provide all 64 positions in cmd_v.
+  --   * Reduces logic.
+  --
+  transmit: process (ctrl_fsm_q,
+                     cmd_fsm_q,
+                     bit_cnt_q,
+                     img_cnt_s,
+                     send_cmd12_q,
+                     set_sel_i,
+                     upper_bitcnt_zero_s)
+
+    subtype cmd_r is natural range 47 downto 0;
+    subtype cmd_t is std_logic_vector(cmd_r);
+    subtype ext_cmd_t is std_logic_vector(63 downto 0);
+    --                            STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS
+    constant cmd0_c   : cmd_t := "010000000000000000000000000000000000000010010101";
+    constant cmd1_c   : cmd_t := "0100000100000000000000000000000000000000-------1";
+    constant cmd12_c  : cmd_t := "0100110000000000000000000000000000000000-------1";
+    constant cmd16_c  : cmd_t := "0101000000000000000000000000000000000000-------1";
+    constant cmd18_c  : cmd_t := "0101001000000000000000000000000000000000-------1";
+    constant cmd55_c  : cmd_t := "0111011100000000000000000000000000000000-------1";
+    constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1";
+
+    variable cmd_v      : ext_cmd_t;
+    variable tx_v       : boolean;
+
+  begin
+    -- default assignments
+    spi_dat_s    <= '1';
+    cmd_v        := (others => '1');
+    tx_v         := false;
+
+    if cmd_fsm_q = CMD then
+      case ctrl_fsm_q is
+        when CMD0 =>
+          cmd_v(cmd_r) := cmd0_c;
+          tx_v := true;
+        when CMD1 =>
+          cmd_v(cmd_r) := cmd1_c;
+          tx_v := true;
+        when CMD16 =>
+          cmd_v(cmd_r) := cmd16_c;
+          cmd_v(8 + width_bit_cnt_g-3) := '1';
+          tx_v := true;
+        when CMD18 =>
+          cmd_v(cmd_r) := cmd18_c;
+          -- insert image counter
+          cmd_v(8 + num_bits_per_img_g + width_img_cnt_g
+                downto 8 + num_bits_per_img_g) := img_cnt_s;
+          -- insert set selection
+          cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1
+                downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i;
+          tx_v := true;
+        when CMD18_DATA =>
+          cmd_v(cmd_r) := cmd12_c;
+
+          if send_cmd12_q and upper_bitcnt_zero_s then
+            tx_v := true;
+          end if;
+        when CMD55 =>
+          cmd_v(cmd_r) := cmd55_c;
+          tx_v := true;
+        when ACMD41 =>
+          cmd_v(cmd_r) := acmd41_c;
+          tx_v := true;
+
+        when others =>
+          null;
+      end case;
+    end if;
+
+    if tx_v then
+      spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0)));
+    end if;
+
+  end process transmit;
+  --
+  -----------------------------------------------------------------------------
+
+
+  -----------------------------------------------------------------------------
+  -- Optional Image Counter
+  -----------------------------------------------------------------------------
+  img_cnt: if width_img_cnt_g > 0 generate
+    img_cnt_b : spi_counter
+      generic map (
+        cnt_width_g   => width_img_cnt_g,
+        cnt_max_g     => 2**width_img_cnt_g - 1
+      )
+      port map (
+        clk_i         => clk_i,
+        reset_i       => reset_s,
+        cnt_en_i      => cnt_en_img_s,
+        cnt_o         => img_cnt_s(width_img_cnt_g-1 downto 0),
+        cnt_ovfl_o    => open
+      );
+    img_cnt_s(width_img_cnt_g) <= '0';
+  end generate;
+
+  no_img_cnt: if width_img_cnt_g = 0 generate
+    img_cnt_s <= (others => '0');
+  end generate;
+
+
+  -----------------------------------------------------------------------------
+  -- Optional MMC compatibility counter
+  -----------------------------------------------------------------------------
+  mmc_cnt: if mmc_compat_clk_div_g > 0 generate
+    mmc_cnt_b : spi_counter
+      generic map (
+        cnt_width_g   => width_mmc_clk_div_g,
+        cnt_max_g     => mmc_compat_clk_div_g
+      )
+      port map (
+        clk_i         => clk_i,
+        reset_i       => reset_s,
+        cnt_en_i      => true_s,
+        cnt_o         => open,
+        cnt_ovfl_o    => mmc_cnt_ovfl_s
+      );
+  end generate;
+
+  no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate
+    mmc_cnt_ovfl_s <= true;
+  end generate;
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  spi_clk_o      <=   spi_clk_q;
+  spi_cs_n_o     <=   spi_cs_n_q;
+  spi_data_out_o <=   spi_dat_q;
+  spi_en_outs_o  <=   '1'
+                    when en_outs_q else
+                      '0';
+  cfg_clk_o      <= cfg_clk_q;
+  cfg_dat_o      <= cfg_dat_q;
+  detached_o     <=   '0'
+                    when en_outs_q else
+                      '1';
+
+end rtl;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: spi_boot.vhd,v $
+-- Revision 1.9  2007/02/25 18:24:12  arniml
+-- fix type handling of resets
+--
+-- Revision 1.8  2006/09/11 23:03:36  arniml
+-- disable outputs with reset
+--
+-- Revision 1.7  2005/04/07 20:44:23  arniml
+-- add new port detached_o
+--
+-- Revision 1.6  2005/03/09 19:48:34  arniml
+-- invert level of set_sel input
+--
+-- Revision 1.5  2005/03/08 22:07:12  arniml
+-- added set selection
+--
+-- Revision 1.4  2005/02/18 06:42:08  arniml
+-- clarify wording for images
+--
+-- Revision 1.3  2005/02/16 18:59:10  arniml
+-- include output enable control for SPI outputs
+--
+-- Revision 1.2  2005/02/13 17:25:51  arniml
+-- major update to fix several problems
+-- configuration/data download of multiple sets works now
+--
+-- Revision 1.1  2005/02/08 20:41:33  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
new file mode 100644
index 000000000..ac8b544f9
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot_pack-p.vhd
@@ -0,0 +1,54 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_boot_pack-p.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package spi_boot_pack is
+
+  function "=" (a : std_logic; b : integer) return boolean;
+
+end spi_boot_pack;
+
+package body spi_boot_pack is
+
+  function "=" (a : std_logic; b : integer) return boolean is
+    variable result_v : boolean;
+  begin
+    result_v := false;
+
+    case a is
+      when '0' =>
+        if b = 0 then
+          result_v := true;
+        end if;
+
+      when '1' =>
+        if b = 1 then
+          result_v := true;
+        end if;
+
+      when others =>
+        null;
+
+    end case;
+
+    return result_v;
+  end;
+
+end spi_boot_pack;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: spi_boot_pack-p.vhd,v $
+-- Revision 1.1  2005/02/08 20:41:33  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
new file mode 100644
index 000000000..d81e20db6
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter-c.vhd
@@ -0,0 +1,14 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+--
+-- $Id: spi_counter-c.vhd,v 1.1 2005/02/08 20:41:33 arniml Exp $
+--
+-------------------------------------------------------------------------------
+
+configuration spi_counter_rtl_c0 of spi_counter is
+
+  for rtl
+  end for;
+
+end spi_counter_rtl_c0;
diff --git a/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
new file mode 100644
index 000000000..8ec7357ea
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_counter.vhd
@@ -0,0 +1,118 @@
+-------------------------------------------------------------------------------
+--
+-- SD/MMC Bootloader
+-- Generic counter module
+--
+-- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $
+--
+-- Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+--
+-- All rights reserved, see COPYING.
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/projects.cgi/web/spi_boot/overview
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+
+entity spi_counter is
+
+  generic (
+    cnt_width_g   : integer := 4;
+    cnt_max_g     : integer := 15
+  );
+
+  port (
+    clk_i      : in  std_logic;
+    reset_i    : in  boolean;
+    cnt_en_i   : in  boolean;
+    cnt_o      : out std_logic_vector(cnt_width_g-1 downto 0);
+    cnt_ovfl_o : out boolean
+  );
+
+end spi_counter;
+
+
+library ieee;
+use ieee.numeric_std.all;
+use work.spi_boot_pack.all;
+
+architecture rtl of spi_counter is
+
+  signal cnt_q      : unsigned(cnt_width_g-1 downto 0);
+  signal cnt_ovfl_s : boolean;
+
+begin
+
+  cnt: process (clk_i, reset_i)
+  begin
+    if reset_i then
+      cnt_q <= (others => '0');
+
+    elsif clk_i'event and clk_i = '1' then
+      if cnt_en_i then
+        if not cnt_ovfl_s then
+          cnt_q <= cnt_q + 1;
+        else
+          cnt_q <= (others => '0');
+        end if;
+      end if;
+    end if;
+  end process cnt;
+
+  cnt_ovfl_s <= cnt_q = cnt_max_g;
+
+
+  -----------------------------------------------------------------------------
+  -- Output Mapping
+  -----------------------------------------------------------------------------
+  cnt_ovfl_o <= cnt_ovfl_s;
+  cnt_o      <= std_logic_vector(cnt_q);
+
+end rtl;
+
+
+-------------------------------------------------------------------------------
+-- File History:
+--
+-- $Log: spi_counter.vhd,v $
+-- Revision 1.2  2007/02/25 18:24:12  arniml
+-- fix type handling of resets
+--
+-- Revision 1.1  2005/02/08 20:41:33  arniml
+-- initial check-in
+--
+-------------------------------------------------------------------------------
diff --git a/fpga/usrp2/opencores/spi_boot/sim/CVS/Entries b/fpga/usrp2/opencores/spi_boot/sim/CVS/Entries
new file mode 100644
index 000000000..9487498ad
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/CVS/Entries
@@ -0,0 +1 @@
+D/rtl_sim////
diff --git a/fpga/usrp2/opencores/spi_boot/sim/CVS/Repository b/fpga/usrp2/opencores/spi_boot/sim/CVS/Repository
new file mode 100644
index 000000000..4e2e09740
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/sim
diff --git a/fpga/usrp2/opencores/spi_boot/sim/CVS/Root b/fpga/usrp2/opencores/spi_boot/sim/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/sim/CVS/Template b/fpga/usrp2/opencores/spi_boot/sim/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries
new file mode 100644
index 000000000..e3d0dc145
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Entries
@@ -0,0 +1,2 @@
+/Makefile/1.2/Sun Apr 10 18:14:19 2005//
+D
diff --git a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository
new file mode 100644
index 000000000..114ab862f
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/sim/rtl_sim
diff --git a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile
new file mode 100644
index 000000000..46fb3c635
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sim/rtl_sim/Makefile
@@ -0,0 +1,159 @@
+##############################################################################
+#
+# Makefile for the spi_boot project.
+#
+# The dependencies for all VHDL source files are stored here.
+#
+# Copyright (c) 2005, Arnim Laeuger (arniml@opencores.org)
+#
+# All rights reserved
+#
+##############################################################################
+
+
+PROJECT_DIR = ../..
+RTL_DIR     = $(PROJECT_DIR)/rtl/vhdl
+BENCH_DIR   = $(PROJECT_DIR)/bench/vhdl
+
+
+
+ANALYZE=ghdl -a --std=87 --workdir=work
+ELABORATE=ghdl -e --std=87 --workdir=work
+
+.PHONY: all
+all: work elaborate
+
+work:
+	mkdir work
+
+work/spi_boot_pack-p.o: $(RTL_DIR)/spi_boot_pack-p.vhd
+	$(ANALYZE) $(RTL_DIR)/spi_boot_pack-p.vhd
+
+work/spi_counter.o: $(RTL_DIR)/spi_counter.vhd \
+                    work/spi_boot_pack-p.o
+	$(ANALYZE) $(RTL_DIR)/spi_counter.vhd
+work/spi_counter-c.o: $(RTL_DIR)/spi_counter-c.vhd \
+                      work/spi_counter.o
+	$(ANALYZE) $(RTL_DIR)/spi_counter-c.vhd
+
+work/spi_boot.o: $(RTL_DIR)/spi_boot.vhd \
+                 work/spi_boot_pack-p.o
+	$(ANALYZE) $(RTL_DIR)/spi_boot.vhd
+work/spi_boot-c.o: $(RTL_DIR)/spi_boot-c.vhd \
+                   work/spi_boot.o           \
+                   work/spi_counter-c.o
+	$(ANALYZE) $(RTL_DIR)/spi_boot-c.vhd
+
+work/chip-e.o: $(RTL_DIR)/chip-e.vhd
+	$(ANALYZE) $(RTL_DIR)/chip-e.vhd
+
+work/chip-full-a.o: $(RTL_DIR)/chip-full-a.vhd \
+                    work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-full-a.vhd
+work/chip-full-c.o: $(RTL_DIR)/chip-full-c.vhd \
+                    work/chip-full-a.o         \
+                    work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-full-c.vhd
+
+work/chip-mmc-a.o: $(RTL_DIR)/chip-mmc-a.vhd \
+                   work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-mmc-a.vhd
+work/chip-mmc-c.o: $(RTL_DIR)/chip-mmc-c.vhd \
+                   work/chip-mmc-a.o         \
+                   work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-mmc-c.vhd
+
+work/chip-sd-a.o: $(RTL_DIR)/chip-sd-a.vhd \
+                  work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-sd-a.vhd
+work/chip-sd-c.o: $(RTL_DIR)/chip-sd-c.vhd \
+                  work/chip-sd-a.o           \
+                  work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-sd-c.vhd
+
+work/chip-minimal-a.o: $(RTL_DIR)/chip-minimal-a.vhd \
+                       work/chip-e.o
+	$(ANALYZE) $(RTL_DIR)/chip-minimal-a.vhd
+work/chip-minimal-c.o: $(RTL_DIR)/chip-minimal-c.vhd \
+                       work/chip-minimal-a.o           \
+                       work/spi_boot-c.o
+	$(ANALYZE) $(RTL_DIR)/chip-minimal-c.vhd
+
+work/ram_loader.o: $(RTL_DIR)/sample/ram_loader.vhd
+	$(ANALYZE) $(RTL_DIR)/sample/ram_loader.vhd
+work/ram_loader-c.o: $(RTL_DIR)/sample/ram_loader-c.vhd \
+                     work/ram_loader.o
+	$(ANALYZE) $(RTL_DIR)/sample/ram_loader-c.vhd
+
+work/tb_pack-p.o: $(BENCH_DIR)/tb_pack-p.vhd
+	$(ANALYZE) $(BENCH_DIR)/tb_pack-p.vhd
+
+work/card.o: $(BENCH_DIR)/card.vhd \
+             work/tb_pack-p.o
+	$(ANALYZE) $(BENCH_DIR)/card.vhd
+work/card-c.o: $(BENCH_DIR)/card-c.vhd \
+               work/card.o
+	$(ANALYZE) $(BENCH_DIR)/card-c.vhd
+
+work/tb_elem.o: $(BENCH_DIR)/tb_elem.vhd \
+                work/spi_boot_pack-p.o   \
+                work/tb_pack-p.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem.vhd
+work/tb_elem-full-c.o: $(BENCH_DIR)/tb_elem-full-c.vhd \
+                       work/tb_elem.o                  \
+                       work/chip-full-c.o              \
+                       work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-full-c.vhd
+work/tb_elem-mmc-c.o: $(BENCH_DIR)/tb_elem-mmc-c.vhd \
+                      work/tb_elem.o                 \
+                      work/chip-mmc-c.o              \
+                      work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-mmc-c.vhd
+work/tb_elem-sd-c.o: $(BENCH_DIR)/tb_elem-sd-c.vhd \
+                     work/tb_elem.o                \
+                     work/chip-sd-c.o              \
+                     work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-sd-c.vhd
+work/tb_elem-minimal-c.o: $(BENCH_DIR)/tb_elem-minimal-c.vhd \
+                          work/tb_elem.o                     \
+                          work/chip-minimal-c.o              \
+                          work/card-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_elem-minimal-c.vhd
+
+work/tb.o: $(BENCH_DIR)/tb.vhd
+	$(ANALYZE) $(BENCH_DIR)/tb.vhd
+work/tb-c.o: $(BENCH_DIR)/tb-c.vhd    \
+             work/tb.o                \
+             work/tb_elem-full-c.o    \
+             work/tb_elem-mmc-c.o     \
+             work/tb_elem-sd-c.o      \
+             work/tb_elem-minimal-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb-c.vhd
+
+work/tb_rl.o: $(BENCH_DIR)/tb_rl.vhd
+	$(ANALYZE) $(BENCH_DIR)/tb_rl.vhd
+work/tb_rl-c.o: $(BENCH_DIR)/tb_rl-c.vhd \
+                work/tb_rl.o             \
+                work/chip-full-c.o       \
+                work/card-c.o            \
+                work/ram_loader-c.o
+	$(ANALYZE) $(BENCH_DIR)/tb_rl-c.vhd
+
+
+.PHONY: elaborate
+elaborate: tb_behav_c0 tb_rl_behav_c0
+
+tb_behav_c0: work/tb-c.o
+	$(ELABORATE) tb_behav_c0; \
+	strip tb_behav_c0
+
+tb_rl_behav_c0: work/tb_rl-c.o
+	$(ELABORATE) tb_rl_behav_c0; \
+	strip tb_rl_behav_c0
+
+.PHONY: analyze
+analyze: work/tb-c.o work/tb_rl-c.o
+
+.PHONY: clean
+clean:
+	rm -rf work tb_behav_c0 tb_rl_behav_c0 *~
diff --git a/fpga/usrp2/opencores/spi_boot/sw/CVS/Entries b/fpga/usrp2/opencores/spi_boot/sw/CVS/Entries
new file mode 100644
index 000000000..0f2bd88d4
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/CVS/Entries
@@ -0,0 +1 @@
+D/misc////
diff --git a/fpga/usrp2/opencores/spi_boot/sw/CVS/Repository b/fpga/usrp2/opencores/spi_boot/sw/CVS/Repository
new file mode 100644
index 000000000..98d181ecb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/sw
diff --git a/fpga/usrp2/opencores/spi_boot/sw/CVS/Root b/fpga/usrp2/opencores/spi_boot/sw/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/sw/CVS/Template b/fpga/usrp2/opencores/spi_boot/sw/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Entries b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Entries
new file mode 100644
index 000000000..e46425fde
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Entries
@@ -0,0 +1,2 @@
+/bit_reverse.c/1.1/Sun May 21 11:58:00 2006/-ko/
+D
diff --git a/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Repository b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Repository
new file mode 100644
index 000000000..0519f4b59
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Repository
@@ -0,0 +1 @@
+spi_boot/sw/misc
diff --git a/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Root b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Template b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/misc/CVS/Template
diff --git a/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c b/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c
new file mode 100644
index 000000000..9defb106a
--- /dev/null
+++ b/fpga/usrp2/opencores/spi_boot/sw/misc/bit_reverse.c
@@ -0,0 +1,74 @@
+// Altera requires configuration bytes to be sent LSB first but the
+// SD Card reads bytes MSB first
+// This code reverses the bits of the altera bitstream so
+// it will come out correct when read from the SD card
+// $Log: bit_reverse.c,v $
+// Revision 1.1  2006/01/06 14:44:17  mbl
+// initial version
+//
+
+
+
+#include "stdio.h"
+#include "string.h"
+
+FILE*   fileOut;
+FILE*   fileIn;
+
+void    outIOerror(char* pfn);
+void    inIOerror(char* pfn);
+
+int main(int argc, char* arg[])
+{
+	unsigned char input, output;
+	unsigned char in_mask, out_mask;
+	int i;
+
+	fileOut = fopen(arg[2],"wb");
+	if (fileOut == NULL)
+	{
+	    outIOerror(arg[2]);
+	    exit(-1);
+	}
+
+	printf("Opening input file %s\n", arg[1]);
+        fileIn = fopen(arg[1],"rb");
+        if (fileIn == NULL)
+        {
+            inIOerror(arg[1]);
+            exit(-1);
+        }
+
+        while (!feof(fileIn) && fgets((char*)&input, 2 ,fileIn) != NULL)
+        {
+    	    in_mask = 1;
+    	    out_mask = 0x80;
+	    output = 0;
+
+    	    for ( i=0; i < 8; ++i )
+     	    {
+       		if (input & in_mask) 
+       		{
+        	    output |= out_mask;
+       		}
+       		out_mask = out_mask >> 1;
+       		in_mask = in_mask << 1;
+     	    }
+	    fwrite((void*)&output,sizeof(char),1,fileOut);
+	}
+
+	fclose(fileIn);
+	fclose(fileOut);
+	printf("\n%s has been created\n", arg[2]);
+	exit(0);
+}
+
+void outIOerror(char *pfn)
+{
+	printf("I/O Error while writing to file=%s\n",pfn);
+}
+
+void inIOerror(char *pfn)
+{
+	printf("I/O Error while reading file=%s\n",pfn);
+}
diff --git a/fpga/usrp2/opencores/wb_zbt/CVS/Entries b/fpga/usrp2/opencores/wb_zbt/CVS/Entries
new file mode 100644
index 000000000..ef78b4f27
--- /dev/null
+++ b/fpga/usrp2/opencores/wb_zbt/CVS/Entries
@@ -0,0 +1,2 @@
+/wb_zbt.v/1.1/Tue Feb  5 22:31:22 2008//
+D
diff --git a/fpga/usrp2/opencores/wb_zbt/CVS/Repository b/fpga/usrp2/opencores/wb_zbt/CVS/Repository
new file mode 100644
index 000000000..ca9c641d0
--- /dev/null
+++ b/fpga/usrp2/opencores/wb_zbt/CVS/Repository
@@ -0,0 +1 @@
+wb_zbt
diff --git a/fpga/usrp2/opencores/wb_zbt/CVS/Root b/fpga/usrp2/opencores/wb_zbt/CVS/Root
new file mode 100644
index 000000000..44b2aa23b
--- /dev/null
+++ b/fpga/usrp2/opencores/wb_zbt/CVS/Root
@@ -0,0 +1 @@
+:pserver:anonymous@cvs.opencores.org:/cvsroot/anonymous
diff --git a/fpga/usrp2/opencores/wb_zbt/CVS/Template b/fpga/usrp2/opencores/wb_zbt/CVS/Template
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/fpga/usrp2/opencores/wb_zbt/CVS/Template
diff --git a/fpga/usrp2/opencores/wb_zbt/wb_zbt.v b/fpga/usrp2/opencores/wb_zbt/wb_zbt.v
new file mode 100644
index 000000000..8f9232752
--- /dev/null
+++ b/fpga/usrp2/opencores/wb_zbt/wb_zbt.v
@@ -0,0 +1,149 @@
+/*
+ * Multi-port ZBT SRAM WISHBONE controller
+ * Copyright (C) 2008 Sebastien Bourdeauducq - http://lekernel.net
+ * This file is part of Milkymist.
+ *
+ * Milkymist is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Library General Public License as published
+ * by the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Library General Public License for more details.
+ *
+ * You should have received a copy of the GNU Library General Public
+ * License along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
+ * USA.
+ */
+
+module wb_zbt(
+	input               clk,
+	input               rst,
+	// Wishbone bus A, highest priority, with prefetch
+	input      [31:0]   wbA_adr_i,
+	input      [31:0]   wbA_dat_i,
+	output     [31:0]   wbA_dat_o,
+	input      [ 3:0]   wbA_sel_i,
+	input               wbA_cyc_i,
+	input               wbA_stb_i,
+	output              wbA_ack_o,
+	input               wbA_we_i,
+	// Wishbone bus B, lower priority
+	input      [31:0]   wbB_adr_i,
+	input      [31:0]   wbB_dat_i,
+	output     [31:0]   wbB_dat_o,
+	input      [ 3:0]   wbB_sel_i,
+	input               wbB_cyc_i,
+	input               wbB_stb_i,
+	output              wbB_ack_o,
+	input               wbB_we_i,
+	// Memory connection
+	output              sram_clk,
+	output     [17:0]   sram_a,
+	inout      [31:0]   sram_d,
+	output              sram_we,
+	output     [ 3:0]   sram_bw,
+	output              sram_adv,
+	output              sram_ce,
+	output              sram_oe,
+	output              sram_mode,
+	output              sram_zz
+);
+
+assign sram_clk = clk;
+assign sram_oe = 1'b0;
+assign sram_ce = 1'b0;
+assign sram_adv = 1'b0;
+assign sram_mode = 1'b0;
+assign sram_zz = 1'b0;
+
+/* Wishbone decoding */
+
+wire busA_active;
+wire busB_active;
+
+assign busA_active = wbA_cyc_i & wbA_stb_i;
+assign busB_active = wbB_cyc_i & wbB_stb_i;
+
+/* Those are used to represent the state of the SRAM pipeline
+ * Bit 0 = Write Enable
+ * Bits 18..1 = Address
+ */
+wire [18:0] pipeline_in;
+reg [18:0] pipeline_internal;
+reg [18:0] pipeline_out;
+
+always @(posedge clk or posedge rst) begin
+	if(rst) begin
+		pipeline_internal <= 0;
+		pipeline_out <= 0;
+	end else begin
+		pipeline_internal <= pipeline_in;
+		pipeline_out <= pipeline_internal;
+	end
+end
+
+/* Pipeline contents decode */
+
+wire inprogressA;
+wire inprogressB;
+
+assign inprogressA = (pipeline_internal[18:1] == wbA_adr_i[19:2]) & (pipeline_internal[0] == wbA_we_i);
+assign inprogressB = (pipeline_internal[18:1] == wbB_adr_i[19:2]) & (pipeline_internal[0] == wbB_we_i);
+
+wire hitA;
+wire hitB;
+
+assign hitA = (pipeline_out[18:1] == wbA_adr_i[19:2]) & (pipeline_out[0] == wbA_we_i);
+assign hitB = (pipeline_out[18:1] == wbB_adr_i[19:2]) & (pipeline_out[0] == wbB_we_i);
+
+/* Access arbitration */
+
+wire [1:0] bus_request;
+
+assign bus_request[0] = busA_active & ~inprogressA & ~hitA;
+assign bus_request[1] = busB_active & ~inprogressB & ~hitB;
+
+wire prefetch_enable;
+reg [17:0] prefetch_address;
+
+assign prefetch_enable = ~bus_request[0] & ~bus_request[1];
+always @(posedge clk) begin
+	if(prefetch_enable)
+		prefetch_address <= wbA_adr_i[19:2] + 2;
+	else
+		prefetch_address <= wbA_adr_i[19:2] + 1;
+end
+
+wire [1:0] bus_selected;
+
+assign bus_selected[0] = bus_request[0];
+assign bus_selected[1] = bus_request[1] & ~bus_request[0];
+
+assign pipeline_in[18:1] = ({18{bus_selected[0]}} & wbA_adr_i[19:2])
+	| ({18{bus_selected[1]}} & wbB_adr_i[19:2])
+	| ({18{prefetch_enable}} & prefetch_address);
+assign pipeline_in[0] = (bus_selected[0] & wbA_we_i)|(bus_selected[1] & wbB_we_i);
+
+/* SRAM control */
+
+assign sram_a = pipeline_in[18:1];
+assign sram_bw = ~(({4{bus_selected[0]}} & wbA_sel_i)|({4{bus_selected[1]}} & wbB_sel_i));
+assign sram_we = ~pipeline_in[0];
+
+/* SRAM data */
+
+wire [31:0] bus_wdata;
+
+assign wbA_ack_o = busA_active & hitA;
+assign wbB_ack_o = busB_active & hitB;
+
+assign bus_wdata = ({32{hitA}} & wbA_dat_i)|({32{hitB}} & wbB_dat_i);
+assign sram_d = pipeline_out[0] ? bus_wdata : 32'hzzzzzzzz;
+assign wbA_dat_o = sram_d;
+assign wbB_dat_o = sram_d;
+
+endmodule
diff --git a/fpga/usrp2/sdr_lib/.gitignore b/fpga/usrp2/sdr_lib/.gitignore
new file mode 100644
index 000000000..3c782d589
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/.gitignore
@@ -0,0 +1,3 @@
+/a.out
+/db
+/*.vcd
diff --git a/fpga/usrp2/sdr_lib/HB.sav b/fpga/usrp2/sdr_lib/HB.sav
new file mode 100644
index 000000000..c5087e8a6
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/HB.sav
@@ -0,0 +1,56 @@
+[size] 1400 967
+[pos] -1 -1
+*-46.395245 2565000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] hb_dec_tb.
+@420
+hb_dec_tb.data_in[17:0]
+@28
+hb_dec_tb.strobe_in
+hb_dec_tb.strobe_out
+hb_dec_tb.uut.write_even
+@22
+hb_dec_tb.uut.addr_even[3:0]
+@420
+hb_dec_tb.uut.data_even[17:0]
+hb_dec_tb.uut.data_odd_a[17:0]
+hb_dec_tb.uut.data_odd_b[17:0]
+hb_dec_tb.uut.data_odd_c[17:0]
+hb_dec_tb.uut.data_odd_d[17:0]
+@28
+hb_dec_tb.uut.write_odd
+@420
+hb_dec_tb.uut.prod1[35:0]
+hb_dec_tb.uut.prod2[35:0]
+@24
+hb_dec_tb.uut.phase[2:0]
+@28
+hb_dec_tb.uut.stb_in
+hb_dec_tb.uut.stb_out
+@420
+hb_dec_tb.uut.sum2[17:0]
+hb_dec_tb.uut.stb_out_pre[15:0]
+@28
+hb_dec_tb.uut.do_acc
+hb_dec_tb.uut.clear
+@420
+hb_dec_tb.uut.sum1[17:0]
+hb_dec_tb.uut.coeff1[17:0]
+hb_dec_tb.uut.prod1[35:0]
+hb_dec_tb.uut.prod2[35:0]
+hb_dec_tb.uut.final_sum[17:0]
+hb_dec_tb.uut.coeff2[17:0]
+hb_dec_tb.uut.sum_of_prod[21:0]
+hb_dec_tb.data_out[17:0]
+@28
+hb_dec_tb.uut.do_acc
+hb_dec_tb.uut.clear
+@24
+hb_dec_tb.uut.addr_odd_a[3:0]
+hb_dec_tb.uut.addr_odd_b[3:0]
+hb_dec_tb.uut.addr_odd_c[3:0]
+hb_dec_tb.uut.addr_odd_d[3:0]
+@28
+hb_dec_tb.uut.write_odd
+hb_dec_tb.uut.write_even
+@22
+hb_dec_tb.uut.data_even[17:0]
diff --git a/fpga/usrp2/sdr_lib/SMALL_HB.sav b/fpga/usrp2/sdr_lib/SMALL_HB.sav
new file mode 100644
index 000000000..96ba00636
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/SMALL_HB.sav
@@ -0,0 +1,40 @@
+[size] 1400 967
+[pos] -1 -1
+*-11.608687 1834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] small_hb_dec_tb.
+[treeopen] small_hb_dec_tb.uut.
+@28
+small_hb_dec_tb.uut.clk
+small_hb_dec_tb.uut.phase
+@10421
+small_hb_dec_tb.uut.data_in[17:0]
+@420
+small_hb_dec_tb.uut.d1[17:0]
+small_hb_dec_tb.uut.d2[17:0]
+small_hb_dec_tb.uut.d3[17:0]
+small_hb_dec_tb.uut.d4[17:0]
+small_hb_dec_tb.uut.d5[17:0]
+small_hb_dec_tb.uut.d6[17:0]
+small_hb_dec_tb.uut.coeff[17:0]
+small_hb_dec_tb.uut.sum[17:0]
+small_hb_dec_tb.uut.prod[35:0]
+small_hb_dec_tb.uut.accum_rnd[17:0]
+@28
+small_hb_dec_tb.uut.stb_in
+@420
+small_hb_dec_tb.uut.final_sum[17:0]
+@28
+small_hb_dec_tb.uut.go
+small_hb_dec_tb.uut.go_d1
+small_hb_dec_tb.uut.go_d2
+small_hb_dec_tb.uut.go_d3
+small_hb_dec_tb.uut.go_d4
+small_hb_dec_tb.uut.stb_out
+@420
+small_hb_dec_tb.uut.data_out[17:0]
+small_hb_dec_tb.uut.prod[35:0]
+small_hb_dec_tb.uut.accum_rnd[17:0]
+small_hb_dec_tb.uut.final_sum[17:0]
+@10421
+small_hb_dec_tb.uut.round_acc.out[17:0]
+small_hb_dec_tb.uut.data_out[17:0]
diff --git a/fpga/usrp2/sdr_lib/acc.v b/fpga/usrp2/sdr_lib/acc.v
new file mode 100644
index 000000000..a2da9c86d
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/acc.v
@@ -0,0 +1,28 @@
+
+module acc
+  #(parameter IWIDTH=16, OWIDTH=30)
+    (input clk,
+     input clear,
+     input acc,
+     input [IWIDTH-1:0] in,
+     output reg [OWIDTH-1:0] out);
+
+   wire [OWIDTH-1:0] in_signext;
+   sign_extend #(.bits_in(IWIDTH),.bits_out(OWIDTH)) 
+     acc_signext (.in(in),.out(in_signext));
+   
+   //  CLEAR & ~ACC  -->  clears the accumulator
+   //  CLEAR & ACC -->    loads the accumulator
+   //  ~CLEAR & ACC -->   accumulates
+   //  ~CLEAR & ~ACC -->  hold
+   
+   wire [OWIDTH-1:0] addend1 = clear ? 0 : out;
+   wire [OWIDTH-1:0] addend2 = ~acc ? 0 : in_signext;
+   wire [OWIDTH-1:0] sum_int = addend1 + addend2;
+
+   always @(posedge clk)
+     out <= sum_int;
+   
+endmodule // acc
+
+
diff --git a/fpga/usrp2/sdr_lib/add2.v b/fpga/usrp2/sdr_lib/add2.v
new file mode 100644
index 000000000..13fff803e
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/add2.v
@@ -0,0 +1,11 @@
+
+module add2
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign 		sum = sum_int[WIDTH:1];  // Note -- will have some bias
+   
+endmodule // add2
diff --git a/fpga/usrp2/sdr_lib/add2_and_round.v b/fpga/usrp2/sdr_lib/add2_and_round.v
new file mode 100644
index 000000000..146af28da
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/add2_and_round.v
@@ -0,0 +1,11 @@
+
+module add2_and_round
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0] 	sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign 		sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]);
+   
+endmodule // add2_and_round
diff --git a/fpga/usrp2/sdr_lib/add2_and_round_reg.v b/fpga/usrp2/sdr_lib/add2_and_round_reg.v
new file mode 100644
index 000000000..e7fcbf1a1
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/add2_and_round_reg.v
@@ -0,0 +1,16 @@
+
+module add2_and_round_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     sum <= sum_int;
+   
+endmodule // add2_and_round_reg
diff --git a/fpga/usrp2/sdr_lib/add2_reg.v b/fpga/usrp2/sdr_lib/add2_reg.v
new file mode 100644
index 000000000..456cf315b
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/add2_reg.v
@@ -0,0 +1,17 @@
+
+module add2_reg
+  #(parameter WIDTH=16)
+    (input clk,
+     input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output reg [WIDTH-1:0] sum);
+
+   wire [WIDTH-1:0] sum_int;
+   
+   add2 #(.WIDTH(WIDTH)) add2 (.in1(in1),.in2(in2),.sum(sum_int));
+
+   always @(posedge clk)
+     sum <= sum_int;
+   
+endmodule // add2_reg
+
diff --git a/fpga/usrp2/sdr_lib/cic_dec_shifter.v b/fpga/usrp2/sdr_lib/cic_dec_shifter.v
new file mode 100644
index 000000000..aa5ac895b
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cic_dec_shifter.v
@@ -0,0 +1,106 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+// NOTE   This only works for N=4, max decim rate of 128
+// NOTE   signal "rate" is EQUAL TO the actual rate, no more -1 BS
+
+module cic_dec_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 28;
+
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+	// Exact Cases -- N*log2(rate)
+	8'd1 : bitgain = 0;
+	8'd2 : bitgain = 4;
+	8'd4 : bitgain = 8;
+	8'd8 : bitgain = 12;
+	8'd16 : bitgain = 16;
+	8'd32 : bitgain = 20;
+	8'd64 : bitgain = 24;
+	8'd128 : bitgain = 28;
+	
+	// Nearest without overflow -- ceil(N*log2(rate))
+	8'd3 : bitgain = 7;
+	8'd5 : bitgain = 10;
+	8'd6 : bitgain = 11;
+	8'd7 : bitgain = 12;
+	8'd9 : bitgain = 13;
+	8'd10,8'd11 : bitgain = 14;
+	8'd12,8'd13 : bitgain = 15;
+	8'd14,8'd15 : bitgain = 16;
+	8'd17,8'd18,8'd19 : bitgain = 17;
+	8'd20,8'd21,8'd22 : bitgain = 18;
+	8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
+	8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
+	8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
+	8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
+	8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
+	8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
+	8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
+	8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
+	8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
+	default : bitgain = 28;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] 	  shift = bitgain(rate);
+   
+   // We should be able to do this, but can't ....
+   // assign 	  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd4  : signal_out = signal_in[4+bw-1:4];
+       5'd7  : signal_out = signal_in[7+bw-1:7];
+       5'd8  : signal_out = signal_in[8+bw-1:8];
+       5'd10 : signal_out = signal_in[10+bw-1:10];
+       5'd11 : signal_out = signal_in[11+bw-1:11];
+       5'd12 : signal_out = signal_in[12+bw-1:12];
+       5'd13 : signal_out = signal_in[13+bw-1:13];
+       5'd14 : signal_out = signal_in[14+bw-1:14];
+       5'd15 : signal_out = signal_in[15+bw-1:15];
+       5'd16 : signal_out = signal_in[16+bw-1:16];
+       5'd17 : signal_out = signal_in[17+bw-1:17];
+       5'd18 : signal_out = signal_in[18+bw-1:18];
+       5'd19 : signal_out = signal_in[19+bw-1:19];
+       5'd20 : signal_out = signal_in[20+bw-1:20];
+       5'd21 : signal_out = signal_in[21+bw-1:21];
+       5'd22 : signal_out = signal_in[22+bw-1:22];
+       5'd23 : signal_out = signal_in[23+bw-1:23];
+       5'd24 : signal_out = signal_in[24+bw-1:24];
+       5'd25 : signal_out = signal_in[25+bw-1:25];
+       5'd26 : signal_out = signal_in[26+bw-1:26];
+       5'd27 : signal_out = signal_in[27+bw-1:27];
+       5'd28 : signal_out = signal_in[28+bw-1:28];
+       
+       default : signal_out = signal_in[28+bw-1:28];
+     endcase // case(shift)
+
+endmodule // cic_dec_shifter
+
diff --git a/fpga/usrp2/sdr_lib/cic_decim.v b/fpga/usrp2/sdr_lib/cic_decim.v
new file mode 100755
index 000000000..9a03081b0
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cic_decim.v
@@ -0,0 +1,88 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+module cic_decim
+  #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
+    (input clock,
+     input reset,
+     input enable,
+     input [7:0] rate,
+     input strobe_in,
+     input strobe_out,
+     input [bw-1:0] signal_in,
+     output reg [bw-1:0] signal_out);
+
+   localparam 	     maxbitgain = N * log2_of_max_rate;
+   
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0]  integrator [0:N-1];
+   reg [bw+maxbitgain-1:0]  differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0]  pipeline [0:N-1];
+   reg [bw+maxbitgain-1:0]  sampler;
+   
+   integer 		    i;
+   
+   sign_extend #(bw,bw+maxbitgain) 
+     ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   always @(posedge clock)
+     if(reset)
+       for(i=0;i<N;i=i+1)
+	 integrator[i] <= 0;
+     else if (enable && strobe_in)
+       begin
+	  integrator[0] <= integrator[0] + signal_in_ext;
+	  for(i=1;i<N;i=i+1)
+	    integrator[i] <= integrator[i] + integrator[i-1];
+       end	
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+	  sampler <= 0;
+	  for(i=0;i<N;i=i+1)
+	    begin
+	       pipeline[i] <= 0;
+	       differentiator[i] <= 0;
+	    end
+       end
+     else if (enable && strobe_out)
+       begin
+	  sampler <= integrator[N-1];
+	  differentiator[0] <= sampler;
+	  pipeline[0] <= sampler - differentiator[0];
+	  for(i=1;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= pipeline[i-1];
+	       pipeline[i] <= pipeline[i-1] - differentiator[i];
+	    end
+       end // if (enable && strobe_out)
+   
+   wire [bw-1:0] signal_out_unreg;
+   
+   cic_dec_shifter #(bw)
+     cic_dec_shifter(rate,pipeline[N-1],signal_out_unreg);
+
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
+   
+endmodule // cic_decim
diff --git a/fpga/usrp2/sdr_lib/cic_int_shifter.v b/fpga/usrp2/sdr_lib/cic_int_shifter.v
new file mode 100644
index 000000000..18587fa8b
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cic_int_shifter.v
@@ -0,0 +1,100 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+// NOTE   This only works for N=4, max interp rate of 128
+// NOTE   signal "rate" is EQUAL TO the actual rate (no more -1 BS)
+
+module cic_int_shifter(rate,signal_in,signal_out);
+   parameter bw = 16;
+   parameter maxbitgain = 21;
+   
+   input [7:0] rate;
+   input       wire [bw+maxbitgain-1:0] signal_in;
+   output      reg [bw-1:0] signal_out;
+
+   function [4:0] bitgain;
+      input [7:0] rate;
+      case(rate)
+	// Exact Cases
+	8'd1 : bitgain = 0;
+	8'd2 : bitgain = 3;
+	8'd4 : bitgain = 6;
+	8'd8 : bitgain = 9;
+	8'd16 : bitgain = 12;
+	8'd32 : bitgain = 15;
+	8'd64 : bitgain = 18;
+	8'd128 : bitgain = 21;
+	
+	// Nearest without overflow	
+	8'd3 : bitgain = 5;
+	8'd5 : bitgain = 7;
+	8'd6 : bitgain = 8;
+	8'd7 : bitgain = 9;
+	8'd9,8'd10 : bitgain = 10;
+	8'd11,8'd12 : bitgain = 11;
+	8'd13,8'd14,8'd15 : bitgain = 12;
+	8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
+	8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
+	8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
+	8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
+	8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
+	8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
+	8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
+	8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
+	
+	default : bitgain = 21;
+      endcase // case(rate)
+   endfunction // bitgain
+   
+   wire [4:0] 	  shift = bitgain(rate);
+   
+   // We should be able to do this, but can't ....
+   // assign 	  signal_out = signal_in[shift+bw-1:shift];
+   
+   always @*
+     case(shift)
+       5'd0  : signal_out = signal_in[0+bw-1:0];
+       5'd3  : signal_out = signal_in[3+bw-1:3];
+       5'd6  : signal_out = signal_in[6+bw-1:6];
+       5'd9  : signal_out = signal_in[9+bw-1:9];
+       5'd12 : signal_out = signal_in[12+bw-1:12];
+       5'd15 : signal_out = signal_in[15+bw-1:15];
+       5'd18 : signal_out = signal_in[18+bw-1:18];
+       5'd21 : signal_out = signal_in[21+bw-1:21];
+       
+       5'd5  : signal_out = signal_in[5+bw-1:5];
+       5'd7  : signal_out = signal_in[7+bw-1:7];
+       5'd8  : signal_out = signal_in[8+bw-1:8];
+       5'd10 : signal_out = signal_in[10+bw-1:10];
+       5'd11 : signal_out = signal_in[11+bw-1:11];
+       5'd13 : signal_out = signal_in[13+bw-1:13];
+       5'd14 : signal_out = signal_in[14+bw-1:14];
+       5'd16 : signal_out = signal_in[16+bw-1:16];
+       5'd17 : signal_out = signal_in[17+bw-1:17];
+       5'd19 : signal_out = signal_in[19+bw-1:19];
+       5'd20 : signal_out = signal_in[20+bw-1:20];
+       
+       default : signal_out = signal_in[21+bw-1:21];
+     endcase // case(shift)
+
+endmodule // cic_int_shifter
+
diff --git a/fpga/usrp2/sdr_lib/cic_interp.v b/fpga/usrp2/sdr_lib/cic_interp.v
new file mode 100755
index 000000000..9b6928aa1
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cic_interp.v
@@ -0,0 +1,87 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+module cic_interp
+  #(parameter bw = 16, parameter N = 4, parameter log2_of_max_rate = 7)
+    (input clock,
+     input reset,
+     input enable,
+     input [7:0] rate,
+     input strobe_in,
+     input strobe_out,
+     input [bw-1:0] signal_in,
+     output reg [bw-1:0] signal_out);
+   
+   integer 	     i;
+   localparam 	     maxbitgain = (N-1)*log2_of_max_rate;
+
+   wire [bw+maxbitgain-1:0] signal_in_ext;
+   reg [bw+maxbitgain-1:0]  integrator [0:N-1];
+   reg [bw+maxbitgain-1:0]  differentiator [0:N-1];
+   reg [bw+maxbitgain-1:0]  pipeline [0:N-1];
+   
+   sign_extend #(bw,bw+maxbitgain) 
+     ext_input (.in(signal_in),.out(signal_in_ext));
+   
+   //FIXME Note that this section has pipe and diff reversed
+   // It still works, but is confusing
+   always @(posedge clock)
+     if(reset | ~enable)
+       for(i=0;i<N;i=i+1)
+	 integrator[i] <= 0;
+     else if (enable & strobe_out)
+       begin
+	  if(strobe_in)
+	    integrator[0] <= integrator[0] + pipeline[N-1];
+	  for(i=1;i<N;i=i+1)
+	    integrator[i] <= integrator[i] + integrator[i-1];
+       end
+   
+   always @(posedge clock)
+     if(reset | ~enable)
+       begin
+	  for(i=0;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= 0;
+	       pipeline[i] <= 0;
+ 	    end
+       end
+     else if (enable && strobe_in)
+       begin
+	  differentiator[0] <= signal_in_ext;
+	  pipeline[0] <= signal_in_ext - differentiator[0];
+	  for(i=1;i<N;i=i+1)
+	    begin
+	       differentiator[i] <= pipeline[i-1];
+	       pipeline[i] <= pipeline[i-1] - differentiator[i];
+	    end
+       end
+
+   wire [bw-1:0] signal_out_unreg;
+   cic_int_shifter #(bw)
+     cic_int_shifter(rate,integrator[N-1],signal_out_unreg);
+   
+   always @(posedge clock)
+     signal_out <= signal_out_unreg;
+   
+endmodule // cic_interp
+
diff --git a/fpga/usrp2/sdr_lib/cic_strober.v b/fpga/usrp2/sdr_lib/cic_strober.v
new file mode 100644
index 000000000..40d76bdd9
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cic_strober.v
@@ -0,0 +1,45 @@
+//
+//  USRP2 - Universal Software Radio Peripheral Mk II
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module cic_strober
+  #(parameter WIDTH=8)
+    ( input clock,
+      input reset,
+      input enable,
+      input [WIDTH-1:0] rate, // Rate should EQUAL to your desired divide ratio, no more -1 BS
+      input strobe_fast,
+      output wire strobe_slow );
+   
+   reg [WIDTH-1:0] counter;
+   wire      now = (counter==1);
+   assign    strobe_slow = now && enable && strobe_fast;
+   
+   always @(posedge clock)
+     if(reset)
+       counter <= 0; 
+     else if (~enable)
+       counter <= rate;
+     else if(strobe_fast)
+       if(now)
+	 counter <= rate;
+       else 
+	 counter <= counter - 1;
+   
+endmodule // cic_strober
diff --git a/fpga/usrp2/sdr_lib/clip.v b/fpga/usrp2/sdr_lib/clip.v
new file mode 100644
index 000000000..3e6b3a2e2
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/clip.v
@@ -0,0 +1,36 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+   
+   wire 		   overflow = |in[bits_in-1:bits_out-1] & ~(&in[bits_in-1:bits_out-1]);   
+   assign 		   out = overflow ? 
+			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
+			   in[bits_out-1:0];
+   
+endmodule // clip
+
diff --git a/fpga/usrp2/sdr_lib/clip_and_round.v b/fpga/usrp2/sdr_lib/clip_and_round.v
new file mode 100644
index 000000000..4546283a3
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/clip_and_round.v
@@ -0,0 +1,43 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_and_round
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter clip_bits=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+
+   wire [bits_out-1:0] 	   rounded;
+   
+   round #(.bits_in(bits_in-clip_bits),.bits_out(bits_out))
+     round (.in(in[bits_in-clip_bits-1:0]),.out(rounded));
+   
+   wire 		   overflow = |in[bits_in-1:bits_in-clip_bits-1] 
+			   & ~(&in[bits_in-1:bits_in-clip_bits-1]);
+   
+   assign 		   out = overflow ? 
+			   (in[bits_in-1] ? {1'b1,{(bits_out-1){1'b0}}} : {1'b0,{(bits_out-1){1'b1}}}) :
+			   rounded;
+   
+endmodule // clip_and_round
diff --git a/fpga/usrp2/sdr_lib/clip_and_round_reg.v b/fpga/usrp2/sdr_lib/clip_and_round_reg.v
new file mode 100644
index 000000000..66fb155fb
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/clip_and_round_reg.v
@@ -0,0 +1,40 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_and_round_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0,
+    parameter clip_bits=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out);
+
+   wire [bits_out-1:0] 	   temp;
+
+   clip_and_round #(.bits_in(bits_in),.bits_out(bits_out),.clip_bits(clip_bits))
+     clip_and_round (.in(in),.out(temp));
+
+   always@(posedge clk)
+     out <= temp;
+   
+endmodule // clip_and_round_reg
diff --git a/fpga/usrp2/sdr_lib/clip_reg.v b/fpga/usrp2/sdr_lib/clip_reg.v
new file mode 100644
index 000000000..d5e98d982
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/clip_reg.v
@@ -0,0 +1,38 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Clipping "macro", keeps the bottom bits
+
+module clip_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out);
+   
+   wire [bits_out-1:0] temp;
+
+   clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));
+   always @(posedge clk)
+     out <= temp;
+   
+endmodule // clip_reg
+
diff --git a/fpga/usrp2/sdr_lib/cordic.v b/fpga/usrp2/sdr_lib/cordic.v
new file mode 100755
index 000000000..b73e7acf1
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cordic.v
@@ -0,0 +1,109 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003, 2007 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module cordic(clock, reset, enable, xi, yi, zi, xo, yo, zo );
+   parameter bitwidth = 16;
+   parameter zwidth = 16;
+   
+   input clock;
+   input reset;
+   input enable;
+   input [bitwidth-1:0] xi, yi;
+   output [bitwidth-1:0] xo, yo;
+   input [zwidth-1:0] zi;
+   output [zwidth-1:0] zo;
+   
+   reg [bitwidth+1:0] 	 x0,y0;
+   reg [zwidth-2:0] 	 z0;
+   wire [bitwidth+1:0] 	 x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12;
+   wire [bitwidth+1:0] 	 y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12;
+   wire [zwidth-2:0] z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12;
+   
+   wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
+   wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
+
+   // Compute consts.  Would be easier if vlog had atan...
+   // see gen_cordic_consts.py
+   
+   localparam 	       c00 = 15'd8192;
+   localparam 	       c01 = 15'd4836;
+   localparam 	       c02 = 15'd2555;
+   localparam 	       c03 = 15'd1297;
+   localparam 	       c04 = 15'd651;
+   localparam 	       c05 = 15'd326;
+   localparam 	       c06 = 15'd163;
+   localparam 	       c07 = 15'd81;
+   localparam 	       c08 = 15'd41;
+   localparam 	       c09 = 15'd20;
+   localparam 	       c10 = 15'd10;
+   localparam 	       c11 = 15'd5;
+   localparam 	       c12 = 15'd3;
+   localparam 	       c13 = 15'd1;
+   localparam 	       c14 = 15'd1;
+   localparam 	       c15 = 15'd0;
+   localparam 	       c16 = 15'd0;
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+	  x0   <= 0; y0   <= 0;  z0   <= 0;
+       end
+     else// if(enable)
+       begin
+	  z0 <= zi[zwidth-2:0];
+	  case (zi[zwidth-1:zwidth-2])
+	    2'b00, 2'b11 : 
+	      begin
+		 x0 <= xi_ext;
+		 y0 <= yi_ext;
+	      end
+	    2'b01, 2'b10 :
+	      begin
+		 x0 <= -xi_ext;
+		 y0 <= -yi_ext;
+	      end
+	  endcase // case(zi[zwidth-1:zwidth-2])
+       end // else: !if(reset)
+   
+   // FIXME need to handle variable number of stages
+   // FIXME should be able to narrow zwidth but quartus makes it bigger...
+   // This would be easier if arrays worked better in vlog...
+   cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,c00,x1,y1,z1);
+   cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,c01,x2,y2,z2);
+   cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,c02,x3,y3,z3);
+   cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,c03,x4,y4,z4);
+   cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,c04,x5,y5,z5);
+   cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,c05,x6,y6,z6);
+   cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,c06,x7,y7,z7);
+   cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,c07,x8,y8,z8);
+   cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,c08,x9,y9,z9);
+   cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,c09,x10,y10,z10);
+   cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,c10,x11,y11,z11);
+   cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,c11,x12,y12,z12);
+
+   assign xo = x12[bitwidth:1];  
+   assign yo = y12[bitwidth:1];
+   //assign xo = x12[bitwidth+1:2];  // CORDIC gain is ~1.6, plus gain from rotating vectors
+   //assign yo = y12[bitwidth+1:2];
+   assign zo = z12;		  
+
+endmodule // cordic
+
diff --git a/fpga/usrp2/sdr_lib/cordic_stage.v b/fpga/usrp2/sdr_lib/cordic_stage.v
new file mode 100755
index 000000000..641ff9108
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cordic_stage.v
@@ -0,0 +1,60 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module cordic_stage( clock, reset, enable, xi,yi,zi,constant,xo,yo,zo);
+   parameter bitwidth = 16;
+   parameter zwidth = 16;
+   parameter shift = 1;
+   
+   input     clock;
+   input     reset;
+   input     enable;
+   input [bitwidth-1:0] xi,yi;
+   input [zwidth-1:0] zi;
+   input [zwidth-1:0] constant;
+   output [bitwidth-1:0] xo,yo;
+   output [zwidth-1:0] zo;
+   
+   wire z_is_pos = ~zi[zwidth-1];
+
+   reg [bitwidth-1:0] 	 xo,yo;
+   reg [zwidth-1:0] zo;
+   
+   always @(posedge clock)
+     if(reset)
+       begin
+	  xo <= 0;
+	  yo <= 0;
+	  zo <= 0;
+       end
+     else //if(enable)
+       begin
+	  xo <= z_is_pos ?   
+		xi - {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]} :
+		xi + {{shift+1{yi[bitwidth-1]}},yi[bitwidth-2:shift]};
+	  yo <= z_is_pos ?   
+		yi + {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]} :
+		yi - {{shift+1{xi[bitwidth-1]}},xi[bitwidth-2:shift]};
+	  zo <= z_is_pos ?   
+		zi - constant :
+		zi + constant;
+       end
+endmodule
diff --git a/fpga/usrp2/sdr_lib/cordic_z24.v b/fpga/usrp2/sdr_lib/cordic_z24.v
new file mode 100644
index 000000000..cf668d5ec
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/cordic_z24.v
@@ -0,0 +1,126 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003, 2007 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module cordic_z24(clock, reset, enable, xi, yi, zi, xo, yo, zo );
+   parameter bitwidth = 16;
+   parameter stages = 19;
+   localparam zwidth = 24;
+   
+   input clock;
+   input reset;
+   input enable;
+   input [bitwidth-1:0] xi, yi;
+   output [bitwidth-1:0] xo, yo;
+   input [zwidth-1:0] zi;
+   output [zwidth-1:0] zo;
+   
+   reg [bitwidth+1:0] 	 x0,y0;
+   reg [zwidth-2:0] 	 z0;
+   wire [bitwidth+1:0] 	 x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17,x18,x19,x20;
+   wire [bitwidth+1:0] 	 y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17,y18,y19,y20;
+   wire [zwidth-2:0] 	 z1,z2,z3,z4,z5,z6,z7,z8,z9,z10,z11,z12,z13,z14,z15,z16,z17,z18,z19,z20;
+   
+   wire [bitwidth+1:0] xi_ext = {{2{xi[bitwidth-1]}},xi};
+   wire [bitwidth+1:0] yi_ext = {{2{yi[bitwidth-1]}},yi};
+
+   // Compute consts.  Would be easier if vlog had atan...
+   // see gen_cordic_consts.py
+
+   // constants for 24 bit wide phase
+   localparam 	       c00 = 24'd2097152;
+   localparam 	       c01 = 24'd1238021;
+   localparam 	       c02 = 24'd654136;
+   localparam 	       c03 = 24'd332050;
+   localparam 	       c04 = 24'd166669;
+   localparam 	       c05 = 24'd83416;
+   localparam 	       c06 = 24'd41718;
+   localparam 	       c07 = 24'd20860;
+   localparam 	       c08 = 24'd10430;
+   localparam 	       c09 = 24'd5215;
+   localparam 	       c10 = 24'd2608;
+   localparam 	       c11 = 24'd1304;
+   localparam 	       c12 = 24'd652;
+   localparam 	       c13 = 24'd326;
+   localparam 	       c14 = 24'd163;
+   localparam 	       c15 = 24'd81;
+   localparam 	       c16 = 24'd41;
+   localparam 	       c17 = 24'd20;
+   localparam 	       c18 = 24'd10;
+   localparam 	       c19 = 24'd5;
+   localparam 	       c20 = 24'd3;
+   localparam 	       c21 = 24'd1;
+   localparam 	       c22 = 24'd1;
+   localparam 	       c23 = 24'd0;
+
+   always @(posedge clock)
+     if(reset)
+       begin
+	  x0   <= 0; y0   <= 0;  z0   <= 0;
+       end
+     else// if(enable)
+       begin
+	  z0 <= zi[zwidth-2:0];
+	  case (zi[zwidth-1:zwidth-2])
+	    2'b00, 2'b11 : 
+	      begin
+		 x0 <= xi_ext;
+		 y0 <= yi_ext;
+	      end
+	    2'b01, 2'b10 :
+	      begin
+		 x0 <= -xi_ext;
+		 y0 <= -yi_ext;
+	      end
+	  endcase // case(zi[zwidth-1:zwidth-2])
+       end // else: !if(reset)
+   
+   // FIXME need to handle variable number of stages
+   // This would be easier if arrays worked better in vlog...
+   
+   cordic_stage #(bitwidth+2,zwidth-1,0) cordic_stage0 (clock,reset,enable,x0,y0,z0,c00,x1,y1,z1);
+   cordic_stage #(bitwidth+2,zwidth-1,1) cordic_stage1 (clock,reset,enable,x1,y1,z1,c01,x2,y2,z2);
+   cordic_stage #(bitwidth+2,zwidth-1,2) cordic_stage2 (clock,reset,enable,x2,y2,z2,c02,x3,y3,z3);
+   cordic_stage #(bitwidth+2,zwidth-1,3) cordic_stage3 (clock,reset,enable,x3,y3,z3,c03,x4,y4,z4);
+   cordic_stage #(bitwidth+2,zwidth-1,4) cordic_stage4 (clock,reset,enable,x4,y4,z4,c04,x5,y5,z5);
+   cordic_stage #(bitwidth+2,zwidth-1,5) cordic_stage5 (clock,reset,enable,x5,y5,z5,c05,x6,y6,z6);
+   cordic_stage #(bitwidth+2,zwidth-1,6) cordic_stage6 (clock,reset,enable,x6,y6,z6,c06,x7,y7,z7);
+   cordic_stage #(bitwidth+2,zwidth-1,7) cordic_stage7 (clock,reset,enable,x7,y7,z7,c07,x8,y8,z8);
+   cordic_stage #(bitwidth+2,zwidth-1,8) cordic_stage8 (clock,reset,enable,x8,y8,z8,c08,x9,y9,z9);
+   cordic_stage #(bitwidth+2,zwidth-1,9) cordic_stage9 (clock,reset,enable,x9,y9,z9,c09,x10,y10,z10);
+   cordic_stage #(bitwidth+2,zwidth-1,10) cordic_stage10 (clock,reset,enable,x10,y10,z10,c10,x11,y11,z11);
+   cordic_stage #(bitwidth+2,zwidth-1,11) cordic_stage11 (clock,reset,enable,x11,y11,z11,c11,x12,y12,z12);
+   cordic_stage #(bitwidth+2,zwidth-1,12) cordic_stage12 (clock,reset,enable,x12,y12,z12,c12,x13,y13,z13);
+   cordic_stage #(bitwidth+2,zwidth-1,13) cordic_stage13 (clock,reset,enable,x13,y13,z13,c13,x14,y14,z14);
+   cordic_stage #(bitwidth+2,zwidth-1,14) cordic_stage14 (clock,reset,enable,x14,y14,z14,c14,x15,y15,z15);
+   cordic_stage #(bitwidth+2,zwidth-1,15) cordic_stage15 (clock,reset,enable,x15,y15,z15,c15,x16,y16,z16);
+   cordic_stage #(bitwidth+2,zwidth-1,16) cordic_stage16 (clock,reset,enable,x16,y16,z16,c16,x17,y17,z17);
+   cordic_stage #(bitwidth+2,zwidth-1,17) cordic_stage17 (clock,reset,enable,x17,y17,z17,c17,x18,y18,z18);
+   cordic_stage #(bitwidth+2,zwidth-1,18) cordic_stage18 (clock,reset,enable,x18,y18,z18,c18,x19,y19,z19);
+   cordic_stage #(bitwidth+2,zwidth-1,19) cordic_stage19 (clock,reset,enable,x19,y19,z19,c19,x20,y20,z20);
+
+   assign xo = x20[bitwidth:1];  
+   assign yo = y20[bitwidth:1];
+   assign zo = z20;		  
+   //assign xo = x20[bitwidth+1:2];  // CORDIC gain is ~1.6, plus gain from rotating vectors
+   //assign yo = y20[bitwidth+1:2];
+
+endmodule // cordic
+
diff --git a/fpga/usrp2/sdr_lib/ddc.v b/fpga/usrp2/sdr_lib/ddc.v
new file mode 100755
index 000000000..0d4da9bbc
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/ddc.v
@@ -0,0 +1,97 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+
+// DDC block
+
+module ddc(input clock,
+			input reset,
+			input enable,
+			input [3:0] rate1,
+			input [3:0] rate2,
+			output strobe,
+			input [31:0] freq,
+			input [15:0] i_in,
+			input [15:0] q_in,
+			output [15:0] i_out,
+			output [15:0] q_out
+			);
+   parameter bw = 16;
+   parameter zw = 16;
+
+	wire [15:0] i_cordic_out, q_cordic_out;
+	wire [31:0] phase;
+
+	wire strobe1, strobe2;
+	reg [3:0] strobe_ctr1,strobe_ctr2;
+
+	always @(posedge clock)
+		if(reset | ~enable)
+			strobe_ctr2 <= #1 4'd0;
+		else if(strobe2)
+			strobe_ctr2 <= #1 4'd0;
+		else	
+			strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
+				
+	always @(posedge clock)
+		if(reset | ~enable)
+			strobe_ctr1 <= #1 4'd0;
+		else if(strobe1)
+			strobe_ctr1 <= #1 4'd0;
+		else if(strobe2)
+			strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
+				
+
+	assign strobe2 = enable & ( strobe_ctr2 == rate2 );
+	assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
+
+	assign strobe = strobe1;
+
+	function [2:0] log_ceil;
+	input [3:0] val;
+	
+		log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; 
+	endfunction	
+	
+	wire [2:0] shift1 = log_ceil(rate1);
+	wire [2:0] shift2 = log_ceil(rate2);
+	
+	cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
+		cordic(.clock(clock), .reset(reset), .enable(enable),
+			.xi(i_in), .yi(q_in), .zi(phase[31:32-zw]), 
+			.xo(i_cordic_out), .yo(q_cordic_out), .zo()  );
+		
+	cic_decim_2stage #(.bw(bw),.N(4)) 
+		decim_i(.clock(clock),.reset(reset),.enable(enable),
+			.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
+			.signal_in(i_cordic_out),.signal_out(i_out));
+			
+	cic_decim_2stage #(.bw(bw),.N(4)) 
+		decim_q(.clock(clock),.reset(reset),.enable(enable),
+			.strobe1(1'b1),.strobe2(strobe2),.strobe3(strobe1),.shift1(shift2),.shift2(shift1),
+			.signal_in(q_cordic_out),.signal_out(q_out));
+	
+	phase_acc #(.resolution(32))
+		nco (.clk(clock),.reset(reset),.enable(enable),
+			.freq(freq),.phase(phase));
+		
+endmodule
diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx.v b/fpga/usrp2/sdr_lib/dsp_core_rx.v
new file mode 100644
index 000000000..2ac429630
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/dsp_core_rx.v
@@ -0,0 +1,179 @@
+
+module dsp_core_rx
+  #(parameter BASE = 160)
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   input [15:0] io_rx,
+
+   output [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg [13:0] adc_i, adc_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [35:0] prod_i, prod_q;
+   wire [23:0] i_cordic, q_cordic;
+   wire [23:0] i_cic, q_cic;
+   wire [17:0] i_cic_scaled, q_cic_scaled;
+   wire [17:0] i_hb1, q_hb1;
+   wire [17:0] i_hb2, q_hb2;
+   wire [15:0] i_out, q_out;
+
+   wire        strobe_cic, strobe_hb1, strobe_hb2;
+   wire        enable_hb1, enable_hb2;
+   wire [7:0]  cic_decim_rate;
+   
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+
+   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(BASE+5)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+
+   wire [1:0] gpio_ena;
+   setting_reg #(.my_addr(BASE+6)) sr_9
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(gpio_ena),.changed());
+
+   // The TVRX connects to what is called adc_b, thus A and B are
+   // swapped throughout the design.
+   //
+   // In the interest of expediency and keeping the s/w sane, we just remap them here.
+   // The I & Q fields are mapped the same:
+   // 0 -> "the real A" (as determined by the TVRX)
+   // 1 -> "the real B"
+   // 2 -> const zero
+   
+   always @(posedge clk)
+     case(muxctrl[1:0])		// The I mapping
+       0: adc_i <= adc_b_ofs;	// "the real A"
+       1: adc_i <= adc_a_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])		// The Q mapping
+       0: adc_q <= adc_b_ofs;	// "the real A"
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+       
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
+   
+   cordic_z24 #(.bitwidth(24))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]),
+	    .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
+			   .strobe_fast(1),.strobe_slow(strobe_cic) );
+
+   cic_decim #(.bw(24))
+     decim_i (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(i_cordic),.signal_out(i_cic));
+   
+   cic_decim #(.bw(24))
+     decim_q (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(q_cordic),.signal_out(q_cic));
+
+   round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
+   round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
+   reg 	       strobe_cic_d1;
+   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
+   
+   small_hb_dec #(.WIDTH(18)) small_hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+      .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1));
+   
+   small_hb_dec #(.WIDTH(18)) small_hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+      .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
+
+   wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
+   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+      .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
+
+   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+      .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
+
+   round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
+   round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
+
+   // Streaming GPIO
+   //
+   // io_rx[15] => I channel LSB if gpio_ena[0] high
+   // io_rx[14] => Q channel LSB if gpio_ena[1] high
+
+   reg [31:0] sample_reg;
+   always @(posedge clk)
+     begin
+	sample_reg[31:17] <= i_out[15:1];
+	sample_reg[15:1]  <= q_out[15:1];
+	sample_reg[16]    <= gpio_ena[0] ? io_rx[15] : i_out[0]; 
+	sample_reg[0]     <= gpio_ena[1] ? io_rx[14] : q_out[0];
+     end
+   
+   assign      sample = sample_reg;
+   assign      strobe = strobe_hb2;
+   assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
+   
+endmodule // dsp_core_rx
diff --git a/fpga/usrp2/sdr_lib/dsp_core_tx.v b/fpga/usrp2/sdr_lib/dsp_core_tx.v
new file mode 100644
index 000000000..22d3d44a3
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/dsp_core_tx.v
@@ -0,0 +1,151 @@
+
+module dsp_core_tx
+  #(parameter BASE=0)
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b,
+
+   // To tx_control
+   input [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] i, q, scale_i, scale_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+   wire [7:0]  interp_rate;
+   wire [3:0]  dacmux_a, dacmux_b;
+   wire        enable_hb1, enable_hb2;
+
+   setting_reg #(.my_addr(BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+
+   setting_reg #(.my_addr(BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
+
+   setting_reg #(.my_addr(BASE+4)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({dacmux_b,dacmux_a}),.changed());
+
+   // Strobes are all now delayed by 1 cycle for timing reasons
+   wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
+   reg 	       strobe_cic = 1;
+   reg 	       strobe_hb1 = 1;
+   reg 	       strobe_hb2 = 1;
+   
+   cic_strober #(.WIDTH(8))
+     cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+		 .strobe_fast(1),.strobe_slow(strobe_cic_pre) );
+   cic_strober #(.WIDTH(2))
+     hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 : 1),
+		 .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
+   cic_strober #(.WIDTH(2))
+     hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 : 1),
+		 .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
+   
+   always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
+   always @(posedge clk) strobe_hb2 <= strobe_hb2_pre;
+   always @(posedge clk) strobe_cic <= strobe_cic_pre;
+
+   // NCO
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+   
+   wire        signed [17:0] da, db;
+   wire        signed [35:0] prod_i, prod_q;
+
+   wire [17:0] bb_i = {sample[31:16],2'b0};
+   wire [17:0] bb_q = {sample[15:0],2'b0};
+   wire [17:0] i_interp, q_interp;
+
+   wire [17:0] hb1_i, hb1_q, hb2_i, hb2_q;
+
+   wire [7:0]  cpo = enable_hb2 ? ({interp_rate,1'b0}) : interp_rate;
+   // Note that max CIC rate is 128, which would give an overflow on cpo if enable_hb2 is true,
+   //   but the default case inside hb_interp handles this
+   
+   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_i),.stb_out(strobe_hb2),.data_out(hb1_i));
+   hb_interp #(.IWIDTH(18),.OWIDTH(18),.ACCWIDTH(24)) hb_interp_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.cpo(cpo),.stb_in(strobe_hb1),.data_in(bb_q),.stb_out(strobe_hb2),.data_out(hb1_q));
+   
+   small_hb_int #(.WIDTH(18)) small_hb_interp_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_i),
+      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_i));
+   small_hb_int #(.WIDTH(18)) small_hb_interp_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.stb_in(strobe_hb2),.data_in(hb1_q),
+      .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
+   
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
+     cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+		  .strobe_in(strobe_cic),.strobe_out(1),
+		  .signal_in(hb2_i),.signal_out(i_interp));
+   
+   cic_interp  #(.bw(18),.N(4),.log2_of_max_rate(7))
+     cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+		  .strobe_in(strobe_cic),.strobe_out(1),
+		  .signal_in(hb2_q),.signal_out(q_interp));
+
+   assign      strobe = strobe_hb1;
+
+   localparam  cwidth = 24;  // was 18
+   localparam  zwidth = 24;  // was 16
+
+   wire [cwidth-1:0] da_c, db_c;
+   
+   cordic_z24 #(.bitwidth(cwidth))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi({i_interp,{(cwidth-18){1'b0}}}),.yi({q_interp,{(cwidth-18){1'b0}}}),
+	    .zi(phase[31:32-zwidth]),
+	    .xo(da_c),.yo(db_c),.zo() );
+   
+   MULT18X18S MULT18X18S_inst 
+     (.P(prod_i),    // 36-bit multiplier output
+      .A(da_c[cwidth-1:cwidth-18]),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+   
+   MULT18X18S MULT18X18S_inst_2 
+     (.P(prod_q),    // 36-bit multiplier output
+      .A(db_c[cwidth-1:cwidth-18]),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+   
+   always @(posedge clk)
+     case(dacmux_a)
+       0 : dac_a <= prod_i[28:13];
+       1 : dac_a <= prod_q[28:13];
+       default : dac_a <= 0;
+     endcase // case(dacmux_a)
+   
+   always @(posedge clk)
+     case(dacmux_b)
+       0 : dac_b <= prod_i[28:13];
+       1 : dac_b <= prod_q[28:13];
+       default : dac_b <= 0;
+     endcase // case(dacmux_b)
+   
+   assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
+
+endmodule // dsp_core
diff --git a/fpga/usrp2/sdr_lib/duc.v b/fpga/usrp2/sdr_lib/duc.v
new file mode 100755
index 000000000..6dac95b49
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/duc.v
@@ -0,0 +1,95 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// DUC block
+
+module duc(input clock,
+			input reset,
+			input enable,
+			input [3:0] rate1,
+			input [3:0] rate2,
+			output strobe,
+			input [31:0] freq,
+			input [15:0] i_in,
+			input [15:0] q_in,
+			output [15:0] i_out,
+			output [15:0] q_out
+			);
+   parameter bw = 16;
+   parameter zw = 16;
+   
+	wire [15:0] i_interp_out, q_interp_out;
+	wire [31:0] phase;
+
+	wire strobe1, strobe2;
+	reg [3:0] strobe_ctr1,strobe_ctr2;
+
+	always @(posedge clock)
+		if(reset | ~enable)
+			strobe_ctr2 <= #1 4'd0;
+		else if(strobe2)
+			strobe_ctr2 <= #1 4'd0;
+		else	
+			strobe_ctr2 <= #1 strobe_ctr2 + 4'd1;
+				
+	always @(posedge clock)
+		if(reset | ~enable)
+			strobe_ctr1 <= #1 4'd0;
+		else if(strobe1)
+			strobe_ctr1 <= #1 4'd0;
+		else if(strobe2)
+			strobe_ctr1 <= #1 strobe_ctr1 + 4'd1;
+				
+
+	assign strobe2 = enable & ( strobe_ctr2 == rate2 );
+	assign strobe1 = strobe2 & ( strobe_ctr1 == rate1 );
+
+	assign strobe = strobe1;
+
+	function [2:0] log_ceil;
+	input [3:0] val;
+	
+		log_ceil = val[3] ? 3'd4 : val[2] ? 3'd3 : val[1] ? 3'd2 : 3'd1; 
+	endfunction	
+	
+	wire [2:0] shift1 = log_ceil(rate1);
+	wire [2:0] shift2 = log_ceil(rate2);
+	
+	cordic #(.bitwidth(bw),.zwidth(zw),.stages(16))
+		cordic(.clock(clock), .reset(reset), .enable(enable),
+			.xi(i_interp_out), .yi(q_interp_out), .zi(phase[31:32-zw]), 
+			.xo(i_out), .yo(q_out), .zo()  );
+		
+	cic_interp_2stage #(.bw(bw),.N(4)) 
+		interp_i(.clock(clock),.reset(reset),.enable(enable),
+			.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
+			.signal_in(i_in),.signal_out(i_interp_out));
+
+	cic_interp_2stage #(.bw(bw),.N(4)) 
+		interp_q(.clock(clock),.reset(reset),.enable(enable),
+			.strobe1(strobe1),.strobe2(strobe2),.strobe3(1'b1),.shift1(shift1),.shift2(shift2),
+			.signal_in(q_in),.signal_out(q_interp_out));
+	
+	phase_acc #(.resolution(32))
+		nco (.clk(clock),.reset(reset),.enable(enable),
+			.freq(freq),.phase(phase));
+		
+endmodule
diff --git a/fpga/usrp2/sdr_lib/dummy_rx.v b/fpga/usrp2/sdr_lib/dummy_rx.v
new file mode 100644
index 000000000..99290ecec
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/dummy_rx.v
@@ -0,0 +1,62 @@
+
+`define DSP_CORE_RX_BASE 160
+module dummy_rx
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   output [31:0] sample,
+   input run,
+   output strobe
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [23:0] i_decim, q_decim;
+   wire [7:0]  decim_rate;
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(decim_rate),.changed());
+   
+   strobe_gen strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
+			 .strobe_in(1),.strobe(strobe) );
+
+   reg [15:0] i_out, q_out;
+   assign      sample = {i_out,q_out};
+
+   always @(posedge clk)
+     if(rst)
+       i_out <= 0;
+     else if(~run)
+       i_out <= 0;
+     else if(strobe)
+       i_out <= i_out + 1;
+
+   reg 	       run_d1;
+   always @(posedge clk)
+     if(rst)
+       run_d1 <= 0;
+     else
+       run_d1 <= run;
+
+   always @(posedge clk)
+     if(rst)
+       q_out <= 0;
+     else if (run & ~run_d1)
+       q_out <= q_out + 1;
+       
+   
+endmodule // dsp_core_rx
diff --git a/fpga/usrp2/sdr_lib/gen_cordic_consts.py b/fpga/usrp2/sdr_lib/gen_cordic_consts.py
new file mode 100755
index 000000000..261e8c223
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/gen_cordic_consts.py
@@ -0,0 +1,10 @@
+#!/usr/bin/env python
+
+import math
+
+zwidth = 24
+
+for i in range(24):
+    c = math.atan (1.0/(2**i)) / (2 * math.pi) * (1 << zwidth)
+    print "localparam c%02d = %d'd%d;" % (i, zwidth, round (c))
+    
diff --git a/fpga/usrp2/sdr_lib/halfband_ideal.v b/fpga/usrp2/sdr_lib/halfband_ideal.v
new file mode 100644
index 000000000..484cfff2a
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/halfband_ideal.v
@@ -0,0 +1,84 @@
+module halfband_ideal (
+    input                           clock,
+    input                           reset,
+    input                           enable,
+    input                           strobe_in,
+    input   wire    signed  [17:0]  data_in,
+    output  reg                     strobe_out,
+    output  reg     signed  [17:0]  data_out
+) ;
+
+    parameter                       decim   = 1 ;
+    parameter                       rate    = 2 ;
+
+    reg signed              [40:0]  temp ;
+    reg signed              [17:0]  delay[30:0] ;
+    reg signed              [17:0]  coeffs[30:0] ;
+    reg                     [7:0]   count ;
+    integer                         i ;
+
+    initial begin
+        for( i = 0 ; i < 31 ; i = i + 1 ) begin
+            coeffs[i] = 18'd0 ;
+        end
+        coeffs[0]   = -1390 ;
+        coeffs[2]   = 1604 ;
+        coeffs[4]   = -1896 ;
+        coeffs[6]   = 2317 ;
+        coeffs[8]   = -2979 ;
+        coeffs[10]  = 4172 ;
+        coeffs[12]  = -6953 ;
+        coeffs[14]  = 20860 ;
+        coeffs[15]  = 32768 ;
+        coeffs[16]  = 20860 ;
+        coeffs[18]  = -6953 ;
+        coeffs[20]  = 4172 ;
+        coeffs[22]  = -2979 ;
+        coeffs[24]  = 2317 ;
+        coeffs[26]  = -1896 ;
+        coeffs[28]  = 1604 ;
+        coeffs[30]  = -1390 ;
+    end
+
+    always @(posedge clock) begin
+        if( reset ) begin
+            count <= 0 ;
+            for( i = 0 ; i < 31 ; i = i + 1 ) begin
+                delay[i] <= 18'd0 ;
+            end
+            temp        <= 41'd0 ;
+            data_out    <= 18'd0 ;
+            strobe_out  <= 1'b0 ;
+        end else if( enable ) begin
+
+            if( (decim && (count == rate-1)) || !decim ) 
+                strobe_out <= strobe_in ;
+            else
+                strobe_out <= 1'b0 ;
+            
+
+            if( strobe_in ) begin
+                // Increment decimation count
+                count <= count + 1 ;
+
+                // Shift the input
+                for( i = 30 ; i > 0 ; i = i - 1 ) begin
+                    delay[i] = delay[i-1] ;
+                end
+                delay[0] = data_in ;
+
+                // clear the temp reg
+                temp = 18'd0 ;
+                if( (decim && (count == rate-1)) || !decim ) begin
+                    count <= 0 ;
+                    for( i = 0 ; i < 31 ; i = i + 1 ) begin
+                        // Multiply Accumulate
+                        temp = temp + delay[i]*coeffs[i] ;
+                    end
+                    // Assign data output
+                    data_out <= temp >>> 15 ;
+                end
+            end
+        end
+    end
+endmodule
diff --git a/fpga/usrp2/sdr_lib/halfband_tb.v b/fpga/usrp2/sdr_lib/halfband_tb.v
new file mode 100644
index 000000000..231dd00d7
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/halfband_tb.v
@@ -0,0 +1,120 @@
+module halfband_tb( ) ;
+    
+    // Parameters for instantiation
+    parameter               clocks  = 2 ; // Number of clocks per input
+    parameter               decim   = 0 ; // Sets the filter to decimate
+    parameter               rate    = 2 ; // Sets the decimation rate
+
+    reg                     clock ;
+    reg                     reset ;
+    reg                     enable ;
+    reg                     strobe_in ;
+    reg     signed  [17:0]  data_in ;
+    wire                    strobe_out ;
+    wire    signed  [17:0]  data_out ;
+
+    // Setup the clock
+    initial clock = 1'b0 ;
+    always #5 clock <= ~clock ;
+
+    // Come out of reset after a while
+    initial reset = 1'b1 ;
+    initial #100 reset = 1'b0 ;
+
+    // Enable the entire system
+    initial enable = 1'b1 ;
+
+    // Instantiate UUT
+    halfband_ideal 
+      #(
+        .decim      ( decim         ),
+        .rate       ( rate          )
+      ) uut(
+        .clock      ( clock         ),
+        .reset      ( reset         ),
+        .enable     ( enable        ),
+        .strobe_in  ( strobe_in     ),
+        .data_in    ( data_in       ),
+        .strobe_out ( strobe_out    ),
+        .data_out   ( data_out      )
+      ) ;
+    
+    integer i, ri, ro, infile, outfile ;
+
+    // Setup file IO
+    initial begin
+        infile = $fopen("input.dat","r") ;
+        outfile = $fopen("output.dat","r") ;
+        $timeformat(-9, 2, " ns", 10) ;
+    end
+
+    reg                 endofsim ;
+    reg signed  [17:0]  compare ;
+    integer             noe ;
+    initial             noe = 0 ;
+
+    initial begin
+        // Initialize inputs
+        strobe_in <= 1'd0 ;
+        data_in <= 18'd0 ;
+
+        // Wait for reset to go away
+        @(negedge reset) #0 ;
+        
+        // While we're still simulating ...
+        while( !endofsim ) begin
+
+            // Write the input from the file or 0 if EOF...
+            @( posedge clock ) begin
+                #1 ;
+                strobe_in <= 1'b1 ;
+                if( !$feof(infile) )
+                    ri = $fscanf( infile, "%d", data_in ) ;
+                else
+                    data_in <= 18'd0 ;
+            end
+
+            // Clocked in - set the strobe to 0 if the number of
+            // clocks per sample is greater than 1
+            if( clocks > 1 ) begin
+                @(posedge clock) begin
+                    strobe_in <= 1'b0  ;
+                end
+
+                // Wait for the specified number of cycles
+                for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
+                    @(posedge clock) #1 ;
+                end
+            end
+        end
+
+        // Print out the number of errors that occured
+        if( noe )
+            $display( "FAILED: %d errors during simulation", noe ) ;
+        else
+            $display( "PASSED: Simulation successful" ) ;
+
+        $stop ;
+    end
+
+    // Output comparison of simulated values versus known good values
+    always @ (posedge clock) begin
+        if( reset )
+            endofsim <= 1'b0 ;
+        else begin
+            if( !$feof(outfile) ) begin
+                if( strobe_out ) begin
+                    ro = $fscanf( outfile, "%d\n", compare ) ;
+                    if( compare != data_out ) begin
+                        $display( "%t: %d != %d", $realtime, data_out, compare ) ;
+                        noe = noe + 1 ;
+                    end
+                end
+            end else begin
+                // Signal end of simulation when no more outputs
+                endofsim <= 1'b1 ;
+            end
+        end
+    end     
+
+endmodule
diff --git a/fpga/usrp2/sdr_lib/hb/acc.v b/fpga/usrp2/sdr_lib/hb/acc.v
new file mode 100644
index 000000000..195d5ea94
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/acc.v
@@ -0,0 +1,22 @@
+
+
+module acc (input clock, input reset, input clear, input enable_in, output reg enable_out,
+	    input signed [30:0] addend, output reg signed [33:0] sum );
+
+   always @(posedge clock)
+     if(reset)
+       sum <= #1 34'd0;
+     //else if(clear & enable_in)
+     //  sum <= #1 addend;
+     //else if(clear)
+     //  sum <= #1 34'd0;
+     else if(clear)
+       sum <= #1 addend;
+     else if(enable_in)
+       sum <= #1 sum + addend;
+
+   always @(posedge clock)
+     enable_out <= #1 enable_in;
+   
+endmodule // acc
+
diff --git a/fpga/usrp2/sdr_lib/hb/coeff_ram.v b/fpga/usrp2/sdr_lib/hb/coeff_ram.v
new file mode 100644
index 000000000..65460822f
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/coeff_ram.v
@@ -0,0 +1,26 @@
+
+
+module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data);
+
+   always @(posedge clock)
+     case (rd_addr)
+       4'd0 : rd_data <= #1 -16'd16;
+       4'd1 : rd_data <= #1 16'd74;
+       4'd2 : rd_data <= #1 -16'd254;
+       4'd3 : rd_data <= #1 16'd669;
+       4'd4 : rd_data <= #1 -16'd1468;
+       4'd5 : rd_data <= #1 16'd2950;
+       4'd6 : rd_data <= #1 -16'd6158;
+       4'd7 : rd_data <= #1 16'd20585;
+       4'd8 : rd_data <= #1 16'd20585;
+       4'd9 : rd_data <= #1 -16'd6158;
+       4'd10 : rd_data <= #1 16'd2950;
+       4'd11 : rd_data <= #1 -16'd1468;
+       4'd12 : rd_data <= #1 16'd669;
+       4'd13 : rd_data <= #1 -16'd254;
+       4'd14 : rd_data <= #1 16'd74;
+       4'd15 : rd_data <= #1 -16'd16;
+       default : rd_data <= #1 16'd0;
+     endcase // case(rd_addr)
+   
+endmodule // ram
diff --git a/fpga/usrp2/sdr_lib/hb/coeff_rom.v b/fpga/usrp2/sdr_lib/hb/coeff_rom.v
new file mode 100644
index 000000000..7f8886b4e
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/coeff_rom.v
@@ -0,0 +1,19 @@
+
+
+module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data);
+
+   always @(posedge clock)
+     case (addr)
+       3'd0 : data <= #1 -16'd49;
+       3'd1 : data <= #1 16'd165;
+       3'd2 : data <= #1 -16'd412;
+       3'd3 : data <= #1 16'd873;
+       3'd4 : data <= #1 -16'd1681;
+       3'd5 : data <= #1 16'd3135;
+       3'd6 : data <= #1 -16'd6282;
+       3'd7 : data <= #1 16'd20628;
+     endcase // case(addr)
+      
+endmodule // coeff_rom
+
+
diff --git a/fpga/usrp2/sdr_lib/hb/halfband_decim.v b/fpga/usrp2/sdr_lib/hb/halfband_decim.v
new file mode 100644
index 000000000..dff4d902c
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/halfband_decim.v
@@ -0,0 +1,163 @@
+/* -*- verilog -*-
+ * 
+ *  USRP - Universal Software Radio Peripheral
+ * 
+ *  Copyright (C) 2005 Matt Ettus
+ * 
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ * 
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ * 
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+ */
+
+/*
+ * This implements a 31-tap halfband filter that decimates by two.
+ * The coefficients are symmetric, and with the exception of the middle tap,
+ * every other coefficient is zero.  The middle section of taps looks like this:
+ *
+ *  ..., -1468, 0, 2950, 0, -6158, 0, 20585, 32768, 20585, 0, -6158, 0, 2950, 0, -1468, ...
+ *                                             |
+ *                           middle tap -------+
+ *
+ * See coeff_rom.v for the full set.  The taps are scaled relative to 32768,
+ * thus the middle tap equals 1.0.  Not counting the middle tap, there are 8
+ * non-zero taps on each side, and they are symmetric.  A naive implementation
+ * requires a mulitply for each non-zero tap.  Because of symmetry, we can
+ * replace 2 multiplies with 1 add and 1 multiply.  Thus, to compute each output
+ * sample, we need to perform 8 multiplications.  Since the middle tap is 1.0,
+ * we just add the corresponding delay line value.
+ *
+ * About timing: We implement this with a single multiplier, so it takes
+ * 8 cycles to compute a single output.  However, since we're decimating by two 
+ * we can accept a new input value every 4 cycles.  strobe_in is asserted when
+ * there's a new input sample available.  Depending on the overall decimation
+ * rate, strobe_in may be asserted less frequently than once every 4 clocks.
+ * On the output side, we assert strobe_out when output contains a new sample.
+ *
+ * Implementation: Every time strobe_in is asserted we store the new data into
+ * the delay line.  We split the delay line into two components, one for the
+ * even samples, and one for the odd samples.  ram16_odd is the delay line for
+ * the odd samples.  This ram is written on each odd assertion of strobe_in, and
+ * is read on each clock when we're computing the dot product.  ram16_even is
+ * similar, although because it holds the even samples we must be able to read
+ * two samples from different addresses at the same time, while writing the incoming
+ * even samples. Thus it's "triple-ported".
+ */
+
+module halfband_decim
+  (input clock, input reset, input enable, input strobe_in, output wire strobe_out,
+   input wire [15:0] data_in, output reg [15:0] data_out,output wire [15:0] debugctrl);
+
+   reg [3:0] rd_addr1;
+   reg [3:0] rd_addr2;
+   reg [3:0] phase;
+   reg [3:0] base_addr;
+
+   wire      signed [15:0] mac_out,middle_data, sum, coeff;
+   wire      signed [30:0] product;
+   wire      signed [33:0] sum_even;
+   wire      clear;
+   reg 	     store_odd;
+   
+   always @(posedge clock)
+     if(reset)
+       store_odd <= #1 1'b0;
+     else
+       if(strobe_in)
+	 store_odd <= #1 ~store_odd;
+
+   wire      start = strobe_in & store_odd;
+   always @(posedge clock)
+     if(reset)
+       base_addr <= #1 4'd0;
+     else if(start)
+       base_addr <= #1 base_addr + 4'd1;
+
+   always @(posedge clock)
+     if(reset)
+       phase <= #1 4'd8;
+     else if (start)
+       phase <= #1 4'd0;
+     else if(phase != 4'd8)
+       phase <= #1 phase + 4'd1;
+
+   reg 	     start_d1,start_d2,start_d3,start_d4,start_d5,start_d6,start_d7,start_d8,start_d9,start_dA,start_dB,start_dC,start_dD;
+   always @(posedge clock)
+     begin
+	start_d1 <= #1 start;
+	start_d2 <= #1 start_d1;
+	start_d3 <= #1 start_d2;
+	start_d4 <= #1 start_d3;
+	start_d5 <= #1 start_d4;
+	start_d6 <= #1 start_d5;
+	start_d7 <= #1 start_d6;
+	start_d8 <= #1 start_d7;
+	start_d9 <= #1 start_d8;
+	start_dA <= #1 start_d9;
+	start_dB <= #1 start_dA;
+	start_dC <= #1 start_dB;
+	start_dD <= #1 start_dC;
+     end // always @ (posedge clock)
+   
+   reg 	  mult_en, mult_en_pre;
+   always @(posedge clock)
+     begin
+	mult_en_pre <= #1 phase!=8;
+	mult_en <= #1 mult_en_pre;
+     end
+   
+   assign clear = start_d4; // was dC
+   wire   latch_result = start_d4; // was dC
+   assign strobe_out = start_d5; // was dD
+   wire   acc_en;
+   
+   always @*
+     case(phase[2:0])
+       3'd0 : begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
+       3'd1 : begin rd_addr1 = base_addr + 4'd1; rd_addr2 = base_addr + 4'd14; end
+       3'd2 : begin rd_addr1 = base_addr + 4'd2; rd_addr2 = base_addr + 4'd13; end
+       3'd3 : begin rd_addr1 = base_addr + 4'd3; rd_addr2 = base_addr + 4'd12; end
+       3'd4 : begin rd_addr1 = base_addr + 4'd4; rd_addr2 = base_addr + 4'd11; end
+       3'd5 : begin rd_addr1 = base_addr + 4'd5; rd_addr2 = base_addr + 4'd10; end
+       3'd6 : begin rd_addr1 = base_addr + 4'd6; rd_addr2 = base_addr + 4'd9; end
+       3'd7 : begin rd_addr1 = base_addr + 4'd7; rd_addr2 = base_addr + 4'd8; end
+       default: begin rd_addr1 = base_addr + 4'd0; rd_addr2 = base_addr + 4'd15; end
+     endcase // case(phase)
+   
+   coeff_rom coeff_rom (.clock(clock),.addr(phase[2:0]-3'd1),.data(coeff));
+   
+   ram16_2sum ram16_even (.clock(clock),.write(strobe_in & ~store_odd),
+			  .wr_addr(base_addr),.wr_data(data_in),
+			  .rd_addr1(rd_addr1),.rd_addr2(rd_addr2),
+			  .sum(sum));
+
+   ram16 ram16_odd (.clock(clock),.write(strobe_in & store_odd),  // Holds middle items
+		    .wr_addr(base_addr),.wr_data(data_in),
+		    //.rd_addr(base_addr+4'd7),.rd_data(middle_data));
+		    .rd_addr(base_addr+4'd6),.rd_data(middle_data));
+
+   mult mult(.clock(clock),.x(coeff),.y(sum),.product(product),.enable_in(mult_en),.enable_out(acc_en));
+
+   acc acc(.clock(clock),.reset(reset),.enable_in(acc_en),.enable_out(),
+	   .clear(clear),.addend(product),.sum(sum_even));
+
+   wire signed [33:0] dout = sum_even + {{4{middle_data[15]}},middle_data,14'b0}; // We already divided product by 2!!!!
+
+   always @(posedge clock)
+     if(reset)
+       data_out <= #1 16'd0;
+     else if(latch_result)
+       data_out <= #1 dout[30:15] + (dout[33]& |dout[14:0]);
+
+   assign  debugctrl = { clock,reset,acc_en,mult_en,clear,latch_result,store_odd,strobe_in,strobe_out,phase};
+   
+endmodule // halfband_decim
diff --git a/fpga/usrp2/sdr_lib/hb/halfband_interp.v b/fpga/usrp2/sdr_lib/hb/halfband_interp.v
new file mode 100644
index 000000000..cdb11c1f6
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/halfband_interp.v
@@ -0,0 +1,121 @@
+
+
+module halfband_interp 
+  (input clock, input reset, input enable,
+   input strobe_in, input strobe_out,
+   input [15:0] signal_in_i, input [15:0] signal_in_q, 
+   output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
+   output wire [12:0] debug);
+   
+   wire [15:0] 	coeff_ram_out;
+   wire [15:0] 	data_ram_out_i;
+   wire [15:0] 	data_ram_out_q;
+
+   wire [3:0] 	data_rd_addr;
+   reg [3:0] 	data_wr_addr;
+   reg [2:0] 	coeff_rd_addr;
+
+   wire 		filt_done;
+   
+   wire [15:0] 	mac_out_i;
+   wire [15:0] 	mac_out_q;
+   reg [15:0] 	delayed_middle_i, delayed_middle_q;
+   wire [7:0] 	shift = 8'd9;
+
+   reg 		stb_out_happened;
+
+   wire [15:0] 	data_ram_out_i_b;
+   
+   always @(posedge clock)
+     if(strobe_in)
+       stb_out_happened <= #1 1'b0;
+     else if(strobe_out)
+       stb_out_happened <= #1 1'b1;
+   
+assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
+
+   wire [15:0] 	signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
+   wire [15:0] 	signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
+
+/*   always @(posedge clock)
+     if(reset)
+       begin
+	  signal_out_i <= #1 16'd0;
+	  signal_out_q <= #1 16'd0;
+       end
+     else if(strobe_in)
+       begin
+	  signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
+	  signal_out_q <= #1 delayed_middle_q;
+       end
+     //else if(filt_done&stb_out_happened)
+     else if(stb_out_happened)
+       begin
+	  signal_out_i <= #1 mac_out_i;
+	  signal_out_q <= #1 mac_out_q;
+       end
+*/
+   
+   always @(posedge clock)
+     if(reset)
+       coeff_rd_addr <= #1 3'd0;
+     else if(coeff_rd_addr != 3'd0)
+       coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
+     else if(strobe_in)
+       coeff_rd_addr <= #1 3'd1;
+
+   reg filt_done_d1;
+   always@(posedge clock)
+     filt_done_d1 <= #1 filt_done;
+   
+   always @(posedge clock)
+     if(reset)
+       data_wr_addr <= #1 4'd0;
+   //else if(strobe_in)
+     else if(filt_done & ~filt_done_d1)
+       data_wr_addr <= #1 data_wr_addr + 4'd1;
+
+   always @(posedge clock)
+     if(coeff_rd_addr == 3'd7)
+       begin
+	  delayed_middle_i <= #1 data_ram_out_i_b;
+	//  delayed_middle_q <= #1 data_ram_out_q_b;
+       end
+   
+//   always @(posedge clock)
+//     if(reset)
+//       data_rd_addr <= #1 4'd0;
+//     else if(strobe_in)
+//       data_rd_addr <= #1 data_wr_addr + 4'd1;
+//     else if(!filt_done)
+//       data_rd_addr <= #1 data_rd_addr + 4'd1;
+//     else
+//       data_rd_addr <= #1 data_wr_addr;
+  
+   wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
+   wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
+//   always @(posedge clock)
+//     if(reset)
+//       filt_done <= #1 1'b1;
+//     else if(strobe_in)
+ //      filt_done <= #1 1'b0;
+//     else if(coeff_rd_addr == 4'd0)
+//       filt_done <= #1 1'b1;
+
+   assign filt_done = (coeff_rd_addr == 3'd0);
+   
+   coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
+   
+   ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
+		      .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
+   
+   ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
+		      .rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
+   
+   mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
+	      .x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
+   
+   mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
+	      .x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
+
+endmodule // halfband_interp
diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/HBD b/fpga/usrp2/sdr_lib/hb/hbd_tb/HBD
new file mode 100644
index 000000000..574fbba91
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/hbd_tb/HBD
@@ -0,0 +1,80 @@
+*-6.432683 5736 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@28
+test_hbd.clock
+test_hbd.reset
+@420
+test_hbd.halfband_decim.middle_data[15:0]
+@22
+test_hbd.halfband_decim.sum_even[33:0]
+test_hbd.halfband_decim.base_addr[3:0]
+@420
+test_hbd.i_in[15:0]
+@24
+test_hbd.halfband_decim.phase[3:0]
+test_hbd.halfband_decim.ram16_even.rd_addr1[3:0]
+test_hbd.halfband_decim.ram16_even.rd_addr2[3:0]
+test_hbd.halfband_decim.ram16_even.wr_addr[3:0]
+test_hbd.halfband_decim.ram16_even.wr_data[15:0]
+@28
+test_hbd.halfband_decim.ram16_even.write
+@420
+test_hbd.halfband_decim.sum[15:0]
+test_hbd.halfband_decim.product[30:0]
+test_hbd.halfband_decim.dout[33:0]
+test_hbd.halfband_decim.sum_even[33:0]
+@22
+test_hbd.halfband_decim.acc.addend[30:0]
+@28
+test_hbd.halfband_decim.acc.reset
+@420
+test_hbd.halfband_decim.acc.sum[33:0]
+test_hbd.halfband_decim.mult.x[15:0]
+test_hbd.halfband_decim.mult.y[15:0]
+@28
+test_hbd.halfband_decim.acc.clear
+test_hbd.strobe_in
+test_hbd.strobe_out
+test_hbd.halfband_decim.acc_en
+@420
+test_hbd.i_out[15:0]
+@28
+test_hbd.halfband_decim.mult_en
+test_hbd.halfband_decim.latch_result
+@420
+test_hbd.halfband_decim.sum[15:0]
+test_hbd.halfband_decim.sum_even[33:0]
+test_hbd.halfband_decim.dout[33:0]
+test_hbd.halfband_decim.data_out[15:0]
+@22
+test_hbd.halfband_decim.data_out[15:0]
+@28
+test_hbd.halfband_decim.dout[33:0]
+@29
+test_hbd.halfband_decim.acc_en
+@22
+test_hbd.halfband_decim.base_addr[3:0]
+@28
+test_hbd.halfband_decim.clear
+test_hbd.halfband_decim.latch_result
+test_hbd.halfband_decim.mult_en
+test_hbd.halfband_decim.mult_en_pre
+@22
+test_hbd.halfband_decim.phase[3:0]
+@28
+test_hbd.halfband_decim.start
+test_hbd.halfband_decim.start_d1
+test_hbd.halfband_decim.start_d2
+test_hbd.halfband_decim.start_d3
+test_hbd.halfband_decim.start_d4
+test_hbd.halfband_decim.start_d5
+test_hbd.halfband_decim.start_d6
+test_hbd.halfband_decim.start_d7
+test_hbd.halfband_decim.start_d8
+test_hbd.halfband_decim.start_d9
+test_hbd.halfband_decim.start_dA
+test_hbd.halfband_decim.start_dB
+test_hbd.halfband_decim.start_dC
+test_hbd.halfband_decim.start_dD
+test_hbd.halfband_decim.store_odd
+test_hbd.halfband_decim.strobe_in
+test_hbd.halfband_decim.strobe_out
diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/really_golden b/fpga/usrp2/sdr_lib/hb/hbd_tb/really_golden
new file mode 100644
index 000000000..2d24a9e14
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/hbd_tb/really_golden
@@ -0,0 +1,142 @@
+VCD info: dumpfile test_hbd.vcd opened for output.
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    x
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+ 8192
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+    0
+-     4
+   18
+-    63
+  167
+-   367
+  737
+-  1539
+ 5146
+ 5146
+-  1539
+  737
+-   367
+  167
+-    63
+   18
+-     4
+    0
+    0
+    0
+    0
+    0
+-     4
+   14
+-    49
+  118
+-   249
+  488
+ 7141
+12287
+17433
+15894
+16631
+16264
+16432
+16368
+16387
+16383
+16383
+16383
+16383
+16383
+16387
+16368
+16432
+16264
+16631
+15894
+ 9241
+ 4095
+-  1051
+  488
+-   249
+  118
+-    49
+   14
+-     4
+    0
+    0
+    0
+    0
+    0
+-     4
+   14
+-    49
+  118
+-   249
+  488
+-  1051
+12287
+17433
+15894
+16631
+16264
+16432
+16368
+16387
+16383
+16383
+16383
+16383
+16383
+16387
+16368
+16432
+16264
+16631
+15894
+17433
+ 4095
+-  1051
+  488
+-   249
+  118
+-    49
+   14
+-     4
+    0
+    0
+    0
+    0
diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/regression b/fpga/usrp2/sdr_lib/hb/hbd_tb/regression
new file mode 100644
index 000000000..fc279c2f2
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/hbd_tb/regression
@@ -0,0 +1,95 @@
+echo "Baseline 1000"
+iverilog -y .. -o test_hbd -DRATE=1000 test_hbd.v  ; ./test_hbd >golden
+diff golden really_golden
+
+echo
+echo "Test 100"
+iverilog -y .. -o test_hbd -DRATE=100 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 50"
+iverilog -y .. -o test_hbd -DRATE=50 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 40"
+iverilog -y .. -o test_hbd -DRATE=40 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 30"
+iverilog -y .. -o test_hbd -DRATE=30 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 25"
+iverilog -y .. -o test_hbd -DRATE=25 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 20"
+iverilog -y .. -o test_hbd -DRATE=20 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 19"
+iverilog -y .. -o test_hbd -DRATE=19 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 18"
+iverilog -y .. -o test_hbd -DRATE=18 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 17"
+iverilog -y .. -o test_hbd -DRATE=17 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 16"
+iverilog -y .. -o test_hbd -DRATE=16 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 15"
+iverilog -y .. -o test_hbd -DRATE=15 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 14"
+iverilog -y .. -o test_hbd -DRATE=14 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 13"
+iverilog -y .. -o test_hbd -DRATE=13 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 12"
+iverilog -y .. -o test_hbd -DRATE=12 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 11"
+iverilog -y .. -o test_hbd -DRATE=11 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 10"
+iverilog -y .. -o test_hbd -DRATE=10 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 9"
+iverilog -y .. -o test_hbd -DRATE=9 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 8"
+iverilog -y .. -o test_hbd -DRATE=8 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 7"
+iverilog -y .. -o test_hbd -DRATE=7 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 6"
+iverilog -y .. -o test_hbd -DRATE=6 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 5"
+iverilog -y .. -o test_hbd -DRATE=5 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 4"
+iverilog -y .. -o test_hbd -DRATE=4 test_hbd.v  ; ./test_hbd >output ; diff output golden
+
+echo
+echo "Test 3"
+iverilog -y .. -o test_hbd -DRATE=3 test_hbd.v  ; ./test_hbd >output ; diff output golden
diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/run_hbd b/fpga/usrp2/sdr_lib/hb/hbd_tb/run_hbd
new file mode 100755
index 000000000..b8aec7574
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/hbd_tb/run_hbd
@@ -0,0 +1,4 @@
+#!/bin/sh
+
+iverilog -y .. -o test_hbd test_hbd.v
+./test_hbd
diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v b/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v
new file mode 100644
index 000000000..01ab5e7e0
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v
@@ -0,0 +1,75 @@
+
+
+module test_hbd();
+
+   reg clock;
+   initial clock = 1'b0;
+   always #5 clock <= ~clock;
+
+   reg reset;
+   initial reset = 1'b1;
+   initial #1000 reset = 1'b0;
+   
+   initial $dumpfile("test_hbd.vcd");
+   initial $dumpvars(0,test_hbd);
+
+   reg [15:0] i_in, q_in;
+   wire [15:0] i_out, q_out;
+
+   reg 	       strobe_in;
+   wire        strobe_out;
+   reg 	       coeff_write;
+   reg [15:0]  coeff_data;
+   reg [4:0]   coeff_addr;
+   
+   halfband_decim halfband_decim 
+     ( .clock(clock),.reset(reset),.enable(),.strobe_in(strobe_in),.strobe_out(strobe_out),
+       .data_in(i_in),.data_out(i_out) );
+   
+   always @(posedge strobe_out)
+     if(i_out[15])
+       $display("-%d",65536-i_out);
+     else
+       $display("%d",i_out);
+
+   initial
+     begin
+	strobe_in = 1'b0;
+	@(negedge reset);
+	@(posedge clock);
+	while(1)
+	  begin
+	     strobe_in <= #1 1'b1;
+	     @(posedge clock);
+	     strobe_in <= #1 1'b0;
+	     repeat (`RATE)
+	       @(posedge clock);
+	  end
+     end
+
+   initial #10000000 $finish;    // Just in case...
+
+   initial
+     begin
+	i_in <= #1 16'd0;
+	repeat (40) @(posedge strobe_in);
+	i_in <= #1 16'd16384;
+	@(posedge strobe_in);
+	i_in <= #1 16'd0;
+	repeat (40) @(posedge strobe_in);
+	i_in <= #1 16'd16384;
+	@(posedge strobe_in);
+	i_in <= #1 16'd0;
+	repeat (40) @(posedge strobe_in);
+	i_in <= #1 16'd16384;
+	repeat (40) @(posedge strobe_in);
+	i_in <= #1 16'd0;
+	repeat (41) @(posedge strobe_in);
+	i_in <= #1 16'd16384;
+	repeat (40) @(posedge strobe_in);
+	i_in <= #1 16'd0;
+	repeat (40) @(posedge strobe_in);
+	repeat (7) @(posedge clock);
+	$finish;
+     end // initial begin
+endmodule // test_hb
diff --git a/fpga/usrp2/sdr_lib/hb/mac.v b/fpga/usrp2/sdr_lib/hb/mac.v
new file mode 100644
index 000000000..5a270bc73
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/mac.v
@@ -0,0 +1,58 @@
+
+
+module mac (input clock, input reset, input enable, input clear,
+	    input signed [15:0] x, input signed [15:0] y,
+	    input [7:0] shift, output [15:0] z );
+
+   reg signed [30:0] product;
+   reg signed [39:0] z_int;
+   reg signed [15:0] z_shift;
+
+   reg enable_d1;
+   always @(posedge clock)
+     enable_d1 <= #1 enable;
+   
+   always @(posedge clock)
+     if(reset | clear)
+       z_int <= #1 40'd0;
+     else if(enable_d1)
+       z_int <= #1 z_int + {{9{product[30]}},product};
+
+   always @(posedge clock)
+     product <= #1 x*y;
+
+   always @*   // FIXME full case? parallel case?
+     case(shift)
+       //8'd0 : z_shift <= z_int[39:24];
+       //8'd1 : z_shift <= z_int[38:23];
+       //8'd2 : z_shift <= z_int[37:22];
+       //8'd3 : z_shift <= z_int[36:21];
+       //8'd4 : z_shift <= z_int[35:20];
+       //8'd5 : z_shift <= z_int[34:19];
+       8'd6 : z_shift <= z_int[33:18];
+       8'd7 : z_shift <= z_int[32:17];
+       8'd8 : z_shift <= z_int[31:16];
+       8'd9 : z_shift <= z_int[30:15];
+       8'd10 : z_shift <= z_int[29:14];
+       8'd11 : z_shift <= z_int[28:13];
+       //8'd12 : z_shift <= z_int[27:12];
+       //8'd13 : z_shift <= z_int[26:11];
+       //8'd14 : z_shift <= z_int[25:10];
+       //8'd15 : z_shift <= z_int[24:9];
+       //8'd16 : z_shift <= z_int[23:8];
+       //8'd17 : z_shift <= z_int[22:7];
+       //8'd18 : z_shift <= z_int[21:6];
+       //8'd19 : z_shift <= z_int[20:5];
+       //8'd20 : z_shift <= z_int[19:4];
+       //8'd21 : z_shift <= z_int[18:3];
+       //8'd22 : z_shift <= z_int[17:2];
+       //8'd23 : z_shift <= z_int[16:1];
+       //8'd24 : z_shift <= z_int[15:0];
+       default : z_shift <= z_int[15:0];
+     endcase // case(shift)
+   
+   // FIXME do we need to saturate?
+   //assign z = z_shift;
+   assign z = z_int[15:0];
+   
+endmodule // mac
diff --git a/fpga/usrp2/sdr_lib/hb/mult.v b/fpga/usrp2/sdr_lib/hb/mult.v
new file mode 100644
index 000000000..a8d4cb1b7
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/mult.v
@@ -0,0 +1,16 @@
+
+
+module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product,
+	     input enable_in, output reg enable_out );
+
+   always @(posedge clock)
+     if(enable_in)
+       product <= #1 x*y;
+     else
+       product <= #1 31'd0;
+   
+   always @(posedge clock)
+     enable_out <= #1 enable_in;
+   
+endmodule // mult
+
diff --git a/fpga/usrp2/sdr_lib/hb/ram16_2port.v b/fpga/usrp2/sdr_lib/hb/ram16_2port.v
new file mode 100644
index 000000000..e1761a926
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/ram16_2port.v
@@ -0,0 +1,22 @@
+
+
+module ram16_2port (input clock, input write, 
+		    input [3:0] wr_addr, input [15:0] wr_data,
+		    input [3:0] rd_addr1, output reg [15:0] rd_data1,
+		    input [3:0] rd_addr2, output reg [15:0] rd_data2);
+   
+   reg [15:0] 			ram_array [0:31];
+   
+   always @(posedge clock)
+     rd_data1 <= #1 ram_array[rd_addr1];
+   
+   always @(posedge clock)
+     rd_data2 <= #1 ram_array[rd_addr2];
+   
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+   
+endmodule // ram16_2port
+
+
diff --git a/fpga/usrp2/sdr_lib/hb/ram16_2sum.v b/fpga/usrp2/sdr_lib/hb/ram16_2sum.v
new file mode 100644
index 000000000..559b06fd5
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/ram16_2sum.v
@@ -0,0 +1,27 @@
+
+
+module ram16_2sum (input clock, input write, 
+		   input [3:0] wr_addr, input [15:0] wr_data,
+		   input [3:0] rd_addr1, input [3:0] rd_addr2,
+                   output reg [15:0] sum);
+   
+   reg signed [15:0] 	  ram_array [0:15];
+   reg signed [15:0] 	  a,b;
+   wire signed [16:0] 	  sum_int;
+   
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+      
+   always @(posedge clock)
+     begin
+	a <= #1 ram_array[rd_addr1];
+	b <= #1 ram_array[rd_addr2];
+     end
+   
+   assign sum_int = {a[15],a} + {b[15],b};
+   
+   always @(posedge clock)
+     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+     
+endmodule // ram16_2sum
diff --git a/fpga/usrp2/sdr_lib/hb/ram32_2sum.v b/fpga/usrp2/sdr_lib/hb/ram32_2sum.v
new file mode 100644
index 000000000..d1f55b7d0
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb/ram32_2sum.v
@@ -0,0 +1,22 @@
+
+
+module ram32_2sum (input clock, input write, 
+		   input [4:0] wr_addr, input [15:0] wr_data,
+		   input [4:0] rd_addr1, input [4:0] rd_addr2,
+		   output reg [15:0] sum);
+   
+   reg [15:0] 			ram_array [0:31];
+   wire [16:0] 			sum_int;
+   
+   always @(posedge clock)
+     if(write)
+       ram_array[wr_addr] <= #1 wr_data;
+
+   assign sum_int = ram_array[rd_addr1] + ram_array[rd_addr2];
+
+   always @(posedge clock)
+     sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
+
+   
+endmodule // ram32_2sum
+
diff --git a/fpga/usrp2/sdr_lib/hb_dec.v b/fpga/usrp2/sdr_lib/hb_dec.v
new file mode 100644
index 000000000..8fb5ba222
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb_dec.v
@@ -0,0 +1,171 @@
+// Final halfband decimator 
+// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
+// Strobe in cannot come faster than every 2nd clock cycle
+// These taps designed by halfgen4 from ldoolittle
+// myfilt = round(2^18 * halfgen4(.7/4,8))
+
+module hb_dec
+  #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=24)
+    (input clk,
+     input rst,
+     input bypass,
+     input run,
+     input [8:0] cpi,  // Clocks per input -- equal to the decimation ratio ahead of this block
+     input stb_in,
+     input [IWIDTH-1:0] data_in,
+     output reg stb_out,
+     output reg [OWIDTH-1:0] data_out);
+
+   // Control
+   reg [3:0] 		addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d;
+   wire 		write_odd, write_even, do_mult;
+   reg 			odd;
+   reg [2:0] 		phase, phase_d1;
+   reg 			stb_out_int;
+   wire 		clear, do_acc;
+   assign 		do_mult = 1;
+   
+   always @(posedge clk)
+     if(rst | ~run)
+       odd <= 0;
+     else if(stb_in)
+       odd <= ~odd;
+
+   assign 		write_odd = stb_in & odd;
+   assign 		write_even = stb_in & ~odd;
+
+   always @(posedge clk)
+     if(rst | ~run)
+       phase <= 0;
+     else if(stb_in & odd)
+       phase <= 1;
+     else if(phase == 4)
+       phase <= 0;
+     else if(phase != 0)
+       phase <= phase + 1;
+
+   always @(posedge clk)
+     phase_d1 <= phase;
+   
+   reg [15:0] 		stb_out_pre;
+   always @(posedge clk)
+     if(rst)
+       stb_out_pre <= 0;
+     else
+       stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)};
+
+   always @*
+     case(phase)
+       1 : begin addr_odd_a = 0; addr_odd_b = 15; end
+       2 : begin addr_odd_a = 1; addr_odd_b = 14; end
+       3 : begin addr_odd_a = 2; addr_odd_b = 13; end
+       4 : begin addr_odd_a = 3; addr_odd_b = 12; end
+       default : begin addr_odd_a = 0; addr_odd_b = 15; end
+     endcase // case(phase)
+
+   always @*
+     case(phase)
+       1 : begin addr_odd_c = 4; addr_odd_d = 11; end
+       2 : begin addr_odd_c = 5; addr_odd_d = 10; end
+       3 : begin addr_odd_c = 6; addr_odd_d = 9; end
+       4 : begin addr_odd_c = 7; addr_odd_d = 8; end
+       default : begin addr_odd_c = 4; addr_odd_d = 11; end
+     endcase // case(phase)
+
+   assign do_acc = |stb_out_pre[6:3];
+   assign clear = stb_out_pre[3];
+   
+   // Data
+   wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
+   wire [IWIDTH-1:0] sum1, sum2;	
+   wire [OWIDTH-1:0] final_sum;
+   reg [CWIDTH-1:0]  coeff1, coeff2;
+   wire [35:0] 	     prod1, prod2;
+
+   always @*            // Outer coeffs
+     case(phase_d1)
+       1 : coeff1 = -107;
+       2 : coeff1 = 445;
+       3 : coeff1 = -1271;
+       4 : coeff1 = 2959;
+       default : coeff1 = -107;
+     endcase // case(phase)
+   
+   always @*            //  Inner coeffs
+     case(phase_d1)
+       1 : coeff2 = -6107;
+       2 : coeff2 = 11953;
+       3 : coeff2 = -24706;
+       4 : coeff2 = 82359;
+       default : coeff2 = -6107;
+     endcase // case(phase)
+   
+   srl #(.WIDTH(IWIDTH)) srl_odd_a
+     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a));
+   srl #(.WIDTH(IWIDTH)) srl_odd_b
+     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b));
+   srl #(.WIDTH(IWIDTH)) srl_odd_c
+     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c));
+   srl #(.WIDTH(IWIDTH)) srl_odd_d
+     (.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d));
+
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
+
+   wire [IWIDTH-1:0] data_even;
+   reg [3:0] 	     addr_even;
+
+   always @(posedge clk)
+     case(cpi)
+       //  1 is an error
+       2 : addr_even <= 9;  // Maximum speed (overall decim by 4)
+       3, 4, 5, 6, 7 : addr_even <= 8;
+       default : addr_even <= 7;
+     endcase // case(cpi)
+   
+   srl #(.WIDTH(IWIDTH)) srl_even
+     (.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even));
+
+   localparam 		MWIDTH = ACCWIDTH-2;   
+   wire [MWIDTH-1:0] 	sum_of_prod;
+
+   MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) );
+   MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) );
+   add2_and_round_reg #(.WIDTH(MWIDTH)) 
+     add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod));
+
+   wire [ACCWIDTH-1:0] 	acc_out;
+   
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) 
+     acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));
+
+   localparam 		SHIFT_FACTOR = ACCWIDTH-IWIDTH-5;
+   wire [ACCWIDTH-1:0] 	data_even_signext;
+   wire [ACCWIDTH:0] 	final_sum_unrounded;
+
+   sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR))
+     signext_data_even (.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
+   assign 		data_even_signext[SHIFT_FACTOR-1:0] = 0;
+   
+   add2_reg /* add2_and_round_reg */ #(.WIDTH(ACCWIDTH+1)) 
+     final_adder (.clk(clk), .in1({acc_out,1'b0}), .in2({data_even_signext,1'b0}), .sum(final_sum_unrounded));
+
+   round_reg #(.bits_in(ACCWIDTH-4),.bits_out(OWIDTH))
+     final_round (.clk(clk),.in(final_sum_unrounded[ACCWIDTH-5:0]),.out(final_sum));
+
+   // Output
+   always @(posedge clk)
+     if(bypass)
+       data_out <= data_in;
+     else if(stb_out_pre[9])
+       data_out <= final_sum;
+
+   always @(posedge clk)
+     if(rst)
+       stb_out <= 0;
+     else if(bypass)
+       stb_out <= stb_in;
+     else
+       stb_out <= stb_out_pre[9];
+ 
+endmodule // hb_dec
diff --git a/fpga/usrp2/sdr_lib/hb_dec_tb.v b/fpga/usrp2/sdr_lib/hb_dec_tb.v
new file mode 100644
index 000000000..3e5faa80a
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb_dec_tb.v
@@ -0,0 +1,140 @@
+module hb_dec_tb( ) ;
+   
+    // Parameters for instantiation
+    parameter               clocks  = 9'd2 ; // Number of clocks per input
+    parameter               decim   = 1 ; // Sets the filter to decimate
+    parameter               rate    = 2 ; // Sets the decimation rate
+
+    reg                     clock ;
+    reg                     reset ;
+    reg                     enable ;
+    reg                     strobe_in ;
+    reg     signed  [17:0]  data_in ;
+    wire                    strobe_out ;
+    wire    signed  [17:0]  data_out ;
+
+   initial
+     begin
+	$dumpfile("hb_dec_tb.vcd");
+	$dumpvars(0,hb_dec_tb);
+     end
+   
+    // Setup the clock
+    initial clock = 1'b0 ;
+    always #5 clock <= ~clock ;
+
+    // Come out of reset after a while
+    initial reset = 1'b1 ;
+    initial #1000 reset = 1'b0 ;
+
+    // Enable the entire system
+    initial enable = 1'b1 ;
+
+    // Instantiate UUT
+   /*
+    halfband_ideal 
+      #(
+        .decim      ( decim         ),
+        .rate       ( rate          )
+      ) uut(
+        .clock      ( clock         ),
+        .reset      ( reset         ),
+        .enable     ( enable        ),
+        .strobe_in  ( strobe_in     ),
+        .data_in    ( data_in       ),
+        .strobe_out ( strobe_out    ),
+        .data_out   ( data_out      )
+      ) ;
+    */
+
+   
+   hb_dec #(.IWIDTH(18),.OWIDTH(18),.CWIDTH(18),.ACCWIDTH(24)) uut
+     (.clk(clock),.rst(reset),.bypass(0),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in),
+      .stb_out(strobe_out),.data_out(data_out) );
+   
+    integer i, ri, ro, infile, outfile ;
+
+   always @(posedge clock)
+     begin
+	if(strobe_out)
+	  $display(data_out);
+     end
+   
+    // Setup file IO
+    initial begin
+        infile = $fopen("input.dat","r") ;
+        outfile = $fopen("output.dat","r") ;
+        $timeformat(-9, 2, " ns", 10) ;
+    end
+
+    reg                 endofsim ;
+    reg signed  [17:0]  compare ;
+    integer             noe ;
+    initial             noe = 0 ;
+
+    initial begin
+        // Initialize inputs
+        strobe_in <= 1'd0 ;
+        data_in <= 18'd0 ;
+
+        // Wait for reset to go away
+        @(negedge reset) #0 ;
+        
+        // While we're still simulating ...
+        while( !endofsim ) begin
+
+            // Write the input from the file or 0 if EOF...
+            @( posedge clock ) begin
+               //#1 ;
+                strobe_in <= 1'b1 ;
+                if( !$feof(infile) )
+                    ri = $fscanf( infile, "%d", data_in ) ;
+                else
+                    data_in <= 18'd0 ;
+            end
+
+            // Clocked in - set the strobe to 0 if the number of
+            // clocks per sample is greater than 1
+            if( clocks > 1 ) begin
+                @(posedge clock) begin
+                    strobe_in <= 1'b0  ;
+                end
+
+                // Wait for the specified number of cycles
+                for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
+                    @(posedge clock) #1 ;
+                end
+            end
+        end
+
+        // Print out the number of errors that occured
+        if( noe )
+            $display( "FAILED: %d errors during simulation", noe ) ;
+        else
+            $display( "PASSED: Simulation successful" ) ;
+
+        $finish ;
+    end
+
+   // Output comparison of simulated values versus known good values
+   always @ (posedge clock) begin
+      if( reset )
+        endofsim <= 1'b0 ;
+      else begin
+         if( !$feof(outfile) ) begin
+            if( strobe_out ) begin
+               ro = $fscanf( outfile, "%d\n", compare ) ;
+               if( compare != data_out ) begin
+                  //$display( "%t: %d != %d", $realtime, data_out, compare ) ;
+                  noe = noe + 1 ;
+               end
+            end
+         end else begin
+            // Signal end of simulation when no more outputs
+            endofsim <= 1'b1 ;
+         end
+      end
+   end     
+
+endmodule // hb_dec_tb
+
diff --git a/fpga/usrp2/sdr_lib/hb_interp.v b/fpga/usrp2/sdr_lib/hb_interp.v
new file mode 100644
index 000000000..d16807e15
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb_interp.v
@@ -0,0 +1,157 @@
+// First halfband iterpolator 
+// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A]
+// Strobe in cannot come faster than every 4th clock cycle, 
+// Strobe out cannot come faster than every 2nd clock cycle
+
+// These taps designed by halfgen4 from ldoolittle
+// myfilt = round(2^18 * halfgen4(.7/4,8))
+
+module hb_interp
+  #(parameter IWIDTH=18, OWIDTH=18, ACCWIDTH=24)
+    (input clk,
+     input rst,
+     input bypass,
+     input [7:0] cpo, //  Clocks per output, must be at least 2
+     input stb_in,
+     input [IWIDTH-1:0] data_in,
+     input stb_out,
+     output reg [OWIDTH-1:0] data_out);
+
+   localparam MWIDTH = ACCWIDTH-2;
+   localparam CWIDTH = 18;
+
+   reg [CWIDTH-1:0] coeff1, coeff2;
+   reg [3:0] 	    addr_a, addr_b, addr_c, addr_d, addr_e;
+   wire [IWIDTH-1:0] data_a, data_b, data_c, data_d, data_e, sum1, sum2;
+   wire [35:0] 	     prod1, prod2;
+
+   reg [2:0] 	     phase, phase_d1, phase_d2, phase_d3, phase_d4, phase_d5;
+
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else
+       if(stb_in)
+	 phase <= 1;
+       else if(phase==4)
+	 phase <= 0;
+       else if(phase!=0)
+	 phase <= phase + 1;
+   always @(posedge clk) phase_d1 <= phase;
+   always @(posedge clk) phase_d2 <= phase_d1;
+   always @(posedge clk) phase_d3 <= phase_d2;
+   always @(posedge clk) phase_d4 <= phase_d3;
+   always @(posedge clk) phase_d5 <= phase_d4;     
+   
+   srl #(.WIDTH(IWIDTH)) srl_a
+     (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_a),.out(data_a));
+   srl #(.WIDTH(IWIDTH)) srl_b
+     (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_b),.out(data_b));
+   srl #(.WIDTH(IWIDTH)) srl_c
+     (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_c),.out(data_c));
+   srl #(.WIDTH(IWIDTH)) srl_d
+     (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_d),.out(data_d));
+   srl #(.WIDTH(IWIDTH)) srl_e
+     (.clk(clk),.write(stb_in),.in(data_in),.addr(addr_e),.out(data_e));
+
+   always @*
+     case(phase)
+       1 : begin addr_a = 0; addr_b = 15; end
+       2 : begin addr_a = 1; addr_b = 14; end
+       3 : begin addr_a = 2; addr_b = 13; end
+       4 : begin addr_a = 3; addr_b = 12; end
+       default : begin addr_a = 0; addr_b = 15; end
+     endcase // case(phase)
+
+   always @*
+     case(phase)
+       1 : begin addr_c = 4; addr_d = 11; end
+       2 : begin addr_c = 5; addr_d = 10; end
+       3 : begin addr_c = 6; addr_d = 9; end
+       4 : begin addr_c = 7; addr_d = 8; end
+       default : begin addr_c = 4; addr_d = 11; end
+     endcase // case(phase)
+
+   always @*
+     case(cpo)
+       2 : addr_e <= 9;
+       3,4,5,6,7,8 : addr_e <= 8;
+       default : addr_e <= 7;  // This case works for 256, which = 0 due to overflow outside this block
+     endcase // case(cpo)
+   
+   always @*            // Outer coeffs
+     case(phase_d1)
+       1 : coeff1 = -107;
+       2 : coeff1 = 445;
+       3 : coeff1 = -1271;
+       4 : coeff1 = 2959;
+       default : coeff1 = -107;
+     endcase // case(phase)
+   
+   always @*            //  Inner coeffs
+     case(phase_d1)
+       1 : coeff2 = -6107;
+       2 : coeff2 = 11953;
+       3 : coeff2 = -24706;
+       4 : coeff2 = 82359;
+       default : coeff2 = -6107;
+     endcase // case(phase)
+
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 (.clk(clk),.in1(data_a),.in2(data_b),.sum(sum1));
+   add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 (.clk(clk),.in1(data_c),.in2(data_d),.sum(sum2));
+   // sum1, sum2 available on phase_d1
+
+   wire do_mult = 1;
+   MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), .B(sum1) );
+   MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), .B(sum2) );
+   // prod1, prod2 available on phase_d2
+   
+   wire [MWIDTH-1:0] sum_of_prod;
+   
+   add2_and_round_reg #(.WIDTH(MWIDTH)) 
+     add3 (.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod));
+   // sum_of_prod available on phase_d3
+   
+   wire [ACCWIDTH-1:0] acc_out;
+   wire [OWIDTH-1:0]   acc_round;
+
+   wire 	       clear = (phase_d3 == 1);
+   wire 	       do_acc = (phase_d3 != 0);
+   
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) 
+     acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));   
+   // acc_out available on phase_d4
+   
+   wire [ACCWIDTH-6:0] clipped_acc;
+   clip #(.bits_in(ACCWIDTH),.bits_out(ACCWIDTH-5)) final_clip(.in(acc_out),.out(clipped_acc));
+   
+   reg [ACCWIDTH-6:0]   clipped_reg;
+   always @(posedge clk)
+     if(phase_d4 == 4)
+       clipped_reg <= clipped_acc;
+   // clipped_reg available on phase_d5
+   
+   wire [OWIDTH-1:0]   data_out_round;
+   round #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH)) final_round (.in(clipped_reg),.out(data_out_round));
+
+   reg 		      odd;
+   always @(posedge clk)
+     if(rst)
+       odd <= 0;
+     else if(stb_in)
+       odd <= 0;
+     else if(stb_out)
+       odd <= 1;
+
+   always @(posedge clk)
+     if(bypass)
+       data_out <= data_in;
+     else if(stb_out)
+       if(odd)
+	 data_out <= data_e;
+       else
+	 data_out <= data_out_round;
+
+   // data_out available on phase_d6
+   
+endmodule // hb_interp
diff --git a/fpga/usrp2/sdr_lib/hb_interp_tb.v b/fpga/usrp2/sdr_lib/hb_interp_tb.v
new file mode 100644
index 000000000..52f137f28
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb_interp_tb.v
@@ -0,0 +1,132 @@
+module hb_interp_tb( ) ;
+   
+   // Parameters for instantiation
+   parameter               clocks  = 8'd2 ; // Number of clocks per output
+   parameter               decim   = 1 ; // Sets the filter to decimate
+   parameter               rate    = 2 ; // Sets the decimation rate
+   
+   reg                     clock ;
+   reg                     reset ;
+   reg                     enable ;
+   wire 		   strobe_in ;
+   reg 			   signed  [17:0]  data_in ;
+   wire                    strobe_out ;
+   wire 		   signed  [17:0]  data_out ;
+   
+   initial
+     begin
+	$dumpfile("hb_interp_tb.vcd");
+	$dumpvars(0,hb_interp_tb);
+     end
+   
+   // Setup the clock
+   initial clock = 1'b0 ;
+   always #5 clock <= ~clock ;
+   
+   // Come out of reset after a while
+   initial reset = 1'b1 ;
+   initial #1000 reset = 1'b0 ;
+
+   always @(posedge clock)
+     enable <= ~reset;
+   
+   // Instantiate UUT
+   /*
+    halfband_ideal 
+      #(
+        .decim      ( decim         ),
+        .rate       ( rate          )
+      ) uut(
+        .clock      ( clock         ),
+        .reset      ( reset         ),
+        .enable     ( enable        ),
+        .strobe_in  ( strobe_in     ),
+        .data_in    ( data_in       ),
+        .strobe_out ( strobe_out    ),
+        .data_out   ( data_out      )
+      ) ;
+    */
+
+   cic_strober #(.WIDTH(8))
+     out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks),
+		 .strobe_fast(1),.strobe_slow(strobe_out) );
+   
+   cic_strober #(.WIDTH(8))
+     in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2),
+		.strobe_fast(strobe_out),.strobe_slow(strobe_in) );
+   
+   hb_interp #() uut
+     (.clk(clock),.rst(reset),.bypass(0),.cpo(clocks),.stb_in(strobe_in),.data_in(data_in),
+      .stb_out(strobe_out),/* .output_rate(clocks), */ .data_out(data_out) );
+   
+   integer i, ri, ro, infile, outfile ;
+   
+   always @(posedge clock)
+     begin
+	if(strobe_out)
+	  $display(data_out);
+     end
+   
+   // Setup file IO
+   initial begin
+      infile = $fopen("input.dat","r") ;
+      outfile = $fopen("output.dat","r") ;
+      $timeformat(-9, 2, " ns", 10) ;
+   end
+   
+   reg                 endofsim ;
+   reg 		       signed  [17:0]  compare ;
+   integer             noe ;
+   initial             noe = 0 ;
+   
+   initial begin
+      // Initialize inputs
+      data_in <= 18'd0 ;
+      
+      // Wait for reset to go away
+      @(negedge reset) #0 ;
+      
+      // While we're still simulating ...
+      while( !endofsim ) begin
+	 
+         // Write the input from the file or 0 if EOF...
+         @( negedge clock ) begin
+            if(strobe_in)
+              if( !$feof(infile) )
+                ri <= #1 $fscanf( infile, "%d", data_in ) ;
+              else
+                data_in <= 18'd0 ;
+         end
+      end
+      
+      // Print out the number of errors that occured
+      if( noe )
+        $display( "FAILED: %d errors during simulation", noe ) ;
+      else
+        $display( "PASSED: Simulation successful" ) ;
+      
+      $finish ;
+   end
+   
+   // Output comparison of simulated values versus known good values
+   always @ (posedge clock) begin
+      if( reset )
+        endofsim <= 1'b0 ;
+      else begin
+         if( !$feof(outfile) ) begin
+            if( strobe_out ) begin
+               ro = $fscanf( outfile, "%d\n", compare ) ;
+               if( compare != data_out ) begin
+                  //$display( "%t: %d != %d", $realtime, data_out, compare ) ;
+                  noe = noe + 1 ;
+               end
+            end
+         end else begin
+            // Signal end of simulation when no more outputs
+	    if($feof(infile))
+              endofsim <= 1'b1 ;
+         end
+      end
+   end     
+   
+endmodule // small_hb_int_tb
diff --git a/fpga/usrp2/sdr_lib/hb_tb.v b/fpga/usrp2/sdr_lib/hb_tb.v
new file mode 100644
index 000000000..7e960fd13
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/hb_tb.v
@@ -0,0 +1,155 @@
+
+module hb_tb();
+
+   localparam SWIDTH = 17;
+   localparam CWIDTH = 18;
+   localparam TWIDTH = 20;
+   localparam ACC_WIDTH = 40;
+   
+   reg clk = 0, rst = 1;
+   wire strobe_in, strobe_out;
+   reg [SWIDTH-1:0] sample_in;
+   wire signed [SWIDTH:0] sample_out;
+
+   reg 	       set_stb;
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+
+   localparam  DECIM = 3;
+   
+   initial $dumpfile("hb_tb.vcd");
+   initial $dumpvars(0,hb_tb);
+
+   always #5 clk <= ~clk;
+   initial 
+     begin
+	@(posedge clk);
+	@(negedge clk);
+	rst <= 0;
+     end
+
+   reg [7:0] stb_counter;
+   always @(posedge clk)
+     if(rst)
+       stb_counter <= 0;
+     else
+       if(stb_counter == 0)
+	 stb_counter <= DECIM;
+       else
+	 stb_counter <= stb_counter - 1;
+   assign    strobe_in = (stb_counter == 0);
+   
+   hb_decim #(.SWIDTH(SWIDTH),.CWIDTH(CWIDTH),
+	      .TWIDTH(TWIDTH),.ACC_WIDTH(ACC_WIDTH)) hb_decim
+     (.clk(clk), .rst(rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .sample_in(sample_in),
+      .strobe_in(strobe_in),
+      .sample_out(sample_out),
+      .strobe_out(strobe_out)
+      );
+
+   initial
+     begin : load_coeffs
+	@(negedge rst);
+	@(posedge clk);
+	set_addr <= 124;   // load coeffs
+	set_stb <= 1;
+	set_data <= -18'd49;
+	@(posedge clk);
+	set_data <= 18'd165;
+	@(posedge clk);
+	set_data <= -18'd412;
+	@(posedge clk);
+	set_data <= 18'd873;
+	@(posedge clk);
+	set_data <= -18'd1681;
+	@(posedge clk);
+	set_data <= 18'd3135;
+	@(posedge clk);
+	set_data <= -18'd6282;
+	@(posedge clk);
+	set_data <= 18'd20628;
+	@(posedge clk);
+	set_addr <=125;  // load table
+	// { stb_out, accum, load_accum, done, even_addr, odd_addr_a, odd_addr_b, coeff_addr }
+	set_data <= {1'b1,1'b1,1'b0,1'b1,4'd15,4'd15,4'd0,4'd0}; // Phase 8
+	@(posedge clk);
+	set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd14,4'd1,4'd1}; // Phase 7
+	@(posedge clk);
+	set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd13,4'd2,4'd2}; // Phase 6
+	@(posedge clk);
+	set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd12,4'd3,4'd3}; // Phase 5
+	@(posedge clk);
+	set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd11,4'd4,4'd4}; // Phase 4
+	@(posedge clk);
+	set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd10,4'd5,4'd5}; // Phase 3
+	@(posedge clk);
+	set_data <= {1'b0,1'b1,1'b0,1'b0,4'd15,4'd9,4'd6,4'd6};  // Phase 2
+	@(posedge clk);
+	set_data <= {1'b0,1'b0,1'b1,1'b0,4'd15,4'd8,4'd7,4'd7};   // Phase 1
+	@(posedge clk);
+	set_data <= {1'b0,1'b0,1'b0,1'b0,4'd15,4'd8,4'd7,4'd7};   // Phase 0
+	@(posedge clk);
+	set_stb <= 0;
+     end // block: load_coeffs
+   
+   initial
+     begin
+	sample_in <= 0;
+	repeat(40)
+	  @(posedge strobe_in);
+	$display("EVEN");
+	sample_in <= 0;
+	repeat(10)
+	  @(posedge strobe_in);
+	sample_in <= 1;
+	@(posedge strobe_in);
+	sample_in <= 0;
+	repeat(40)
+	  @(posedge strobe_in);
+	sample_in <= 1;
+	repeat(40)
+	  @(posedge strobe_in);
+	sample_in <= 0;
+	repeat(60)
+	  @(posedge strobe_in);
+	sample_in <= 1;
+	repeat(2)
+	  @(posedge strobe_in);
+	sample_in <= 0;
+	repeat(60)
+	  @(posedge strobe_in);
+	$display("ODD");
+	sample_in <= 0;
+	repeat(10)
+	  @(posedge strobe_in);
+	sample_in <= 1;
+	@(posedge strobe_in);
+	sample_in <= 0;
+	repeat(40)
+	  @(posedge strobe_in);
+	sample_in <= 1;
+	repeat(40)
+	  @(posedge strobe_in);
+	sample_in <= 0;
+	repeat(60)
+	  @(posedge strobe_in);
+	sample_in <= 1;
+	repeat(2)
+	  @(posedge strobe_in);
+	sample_in <= 0;
+	repeat(60)
+	  @(posedge strobe_in);
+	$finish;
+     end
+
+   always @(posedge clk)
+     if(strobe_in)
+       $display(sample_in);
+   
+      always @(posedge clk)
+	if(strobe_out)
+	  $display("\t",sample_out);
+
+endmodule // hb_tb
diff --git a/fpga/usrp2/sdr_lib/input.dat b/fpga/usrp2/sdr_lib/input.dat
new file mode 100644
index 000000000..1e649ac2e
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/input.dat
@@ -0,0 +1,341 @@
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diff --git a/fpga/usrp2/sdr_lib/integrate.v b/fpga/usrp2/sdr_lib/integrate.v
new file mode 100644
index 000000000..db33de979
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/integrate.v
@@ -0,0 +1,38 @@
+module integrate
+  #(parameter INPUTW = 16,
+    parameter ACCUMW = 32,
+    parameter OUTPUTW = 16)
+
+   (input clk_i,
+    input rst_i,
+    input ena_i,
+
+    input dump_i,
+    input [INPUTW-1:0] data_i,
+
+    output reg stb_o,
+    output reg [OUTPUTW-1:0] integ_o
+   );
+   
+   wire [ACCUMW-1:0] data_ext = {{ACCUMW-INPUTW{data_i[INPUTW-1]}},data_i};
+   reg  [ACCUMW-1:0] accum;
+
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+	  accum <= 0;
+	  integ_o <= 0;
+       end
+     else
+       if (dump_i)
+	 begin
+	    integ_o <= accum[ACCUMW-1:ACCUMW-OUTPUTW];
+	    accum <= data_ext;
+	 end
+       else
+	 accum <= accum + data_ext;
+
+   always @(posedge clk_i)
+     stb_o <= dump_i;
+   
+endmodule // integrate
diff --git a/fpga/usrp2/sdr_lib/med_hb_int.v b/fpga/usrp2/sdr_lib/med_hb_int.v
new file mode 100644
index 000000000..bc8066509
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/med_hb_int.v
@@ -0,0 +1,95 @@
+// Medium halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0 C 0 D 0.5 D 0 C 0 B 0 A]
+//
+// These taps designed by halfgen_test:
+//   2 * 131072 * halfgen_test(.8/8,4,1)
+// -597, 0, 4283, 0, -17516, 0, 79365, 131072, 79365, 0, -17516, 0, 4283, 0, -597
+
+
+module med_hb_int
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     input [7:0] output_rate,
+     input stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+   localparam coeff_a = -597;
+   localparam coeff_b = 4283;
+   localparam coeff_c = -17516;
+   localparam coeff_d = 79365;
+   
+   reg 	      phase;
+   reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6, d7, d8;
+   
+   localparam 	   MWIDTH = 36;
+   wire [MWIDTH-1:0] prod;
+   
+   reg [6:0] 	     stbin_d;
+   
+   always @(posedge clk)
+     stbin_d <= {stbin_d[5:0],stb_in};
+   
+   always @(posedge clk)
+     if(stb_in)
+       begin
+	  d1 <= data_in;
+	  d2 <= d1;
+	  d3 <= d2;
+	  d4 <= d3;
+	  d5 <= d4;
+	  d6 <= d5;
+	  d7 <= d6;
+	  d8 <= d7;
+       end
+
+   wire [WIDTH-1:0] sum_a, sum_b, sum_c, sum_d;
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_a (.clk(clk),.in1(d1),.in2(d8),.sum(sum_a));
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_b (.clk(clk),.in1(d2),.in2(d7),.sum(sum_b));
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_c (.clk(clk),.in1(d3),.in2(d6),.sum(sum_c));
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_d (.clk(clk),.in1(d4),.in2(d5),.sum(sum_d));
+
+   MULT18X18S mult1(.C(clk), .CE(1), .R(rst), .P(prod1), .A(stbin_d[1] ? coeff_a : coeff_b), 
+		    .B(stbin_d[1] ? sum_a : sum_b) );
+   MULT18X18S mult2(.C(clk), .CE(1), .R(rst), .P(prod2), .A(stbin_d[1] ? coeff_c : coeff_d), 
+		    .B(stbin_d[1] ? sum_c : sum_d) );
+
+   wire [MWIDTH:0] accum;
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) 
+     acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum));
+   
+   wire [WIDTH+2:0] 	 accum_rnd;
+   round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3))
+     final_round (.clk(clk),.in(accum),.out(accum_rnd));
+
+   wire [WIDTH-1:0] 	 clipped;
+   clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH))
+     final_clip (.clk(clk),.in(accum_rnd),.out(clipped));
+
+   reg [WIDTH-1:0] 	 saved, saved_d3;
+   always @(posedge clk)
+     if(stbin_d[6])
+       saved <= clipped;
+
+   always @(posedge clk)
+     if(stbin_d[3])
+       saved_d3 <= d3;
+	   
+   always @(posedge clk)
+     if(bypass)
+       data_out <= data_in;
+     else if(stb_in & stb_out)
+       case(output_rate)
+	 1 : data_out <= d6; 
+	 2 : data_out <= d4;
+	 3, 4, 5, 6, 7 : data_out <= d3;
+	 default : data_out <= d2;
+       endcase // case(output_rate)
+     else if(stb_out)
+       data_out <= saved;
+
+endmodule // small_hb_int
+
diff --git a/fpga/usrp2/sdr_lib/output.dat b/fpga/usrp2/sdr_lib/output.dat
new file mode 100644
index 000000000..15db3ced4
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/output.dat
@@ -0,0 +1,130 @@
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diff --git a/fpga/usrp2/sdr_lib/round.v b/fpga/usrp2/sdr_lib/round.v
new file mode 100644
index 000000000..c4f9ec9cd
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/round.v
@@ -0,0 +1,33 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp round to zero (unbiased truncation)
+
+module round
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input [bits_in-1:0] in,
+     output [bits_out-1:0] out);
+
+   assign out = in[bits_in-1:bits_in-bits_out] + (in[bits_in-1] & |in[bits_in-bits_out-1:0]);
+   
+endmodule // round
diff --git a/fpga/usrp2/sdr_lib/round_reg.v b/fpga/usrp2/sdr_lib/round_reg.v
new file mode 100644
index 000000000..aa0972dab
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/round_reg.v
@@ -0,0 +1,39 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2008 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Rounding "macro"
+// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero)
+
+module round_reg
+  #(parameter bits_in=0,
+    parameter bits_out=0)
+    (input clk,
+     input [bits_in-1:0] in,
+     output reg [bits_out-1:0] out);
+
+   wire [bits_out-1:0] temp;
+
+   round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp));
+   
+   always @(posedge clk)
+     out <= temp;
+   
+endmodule // round
diff --git a/fpga/usrp2/sdr_lib/rssi.v b/fpga/usrp2/sdr_lib/rssi.v
new file mode 100644
index 000000000..e45e2148c
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/rssi.v
@@ -0,0 +1,30 @@
+
+
+module rssi (input clock, input reset, input enable,
+	     input [11:0] adc, output [15:0] rssi, output [15:0] over_count);
+
+   wire 		  over_hi = (adc == 12'h7FF);
+   wire 		  over_lo = (adc == 12'h800);
+   wire 		  over = over_hi | over_lo;
+
+   reg [25:0] 		  over_count_int;
+   always @(posedge clock)
+     if(reset | ~enable)
+       over_count_int <= #1 26'd0;
+     else
+       over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10];
+   
+   assign      over_count = over_count_int[25:10];
+   
+   wire [11:0] abs_adc = adc[11] ? ~adc : adc;
+
+   reg [25:0]  rssi_int;
+   always @(posedge clock)
+     if(reset | ~enable)
+       rssi_int <= #1 26'd0;
+     else
+       rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
+
+   assign      rssi = rssi_int[25:10];
+   
+endmodule // rssi
diff --git a/fpga/usrp2/sdr_lib/rx_control.v b/fpga/usrp2/sdr_lib/rx_control.v
new file mode 100644
index 000000000..0adeb0794
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/rx_control.v
@@ -0,0 +1,180 @@
+
+`define DSP_CORE_RX_BASE 160
+
+module rx_control
+  #(parameter FIFOSIZE = 10)
+    (input clk, input rst,
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     
+     input [31:0] master_time,
+     output overrun,
+     
+     // To FIFO interface of Buffer Pool
+     output [31:0] wr_dat_o,
+     output [3:0] wr_flags_o,
+     input wr_ready_i,
+     output wr_ready_o,
+
+     // From DSP Core
+     input [31:0] sample,
+     output run,
+     input strobe,
+
+     // FIFO Levels
+     output [15:0] fifo_occupied,
+     output fifo_full,
+     output fifo_empty,
+     
+     // Debug
+     output [31:0] debug_rx
+     );
+
+   wire [31:0] 	   new_time, new_command;
+   wire 	   sc_pre1, clear_overrun;
+   wire [31:0] 	   rcvtime_pre;
+   reg [31:0] 	   rcvtime;
+   wire [8:0] 	   lines_per_frame;
+   wire [20:0] 	   numlines;
+   wire 	   send_imm_pre, chain_pre;
+   reg 		   send_imm, chain;
+   wire 	   full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(new_time),.changed(sc_pre1));
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+4)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(new_command),.changed());
+
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+5)) sr_5
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_overrun));
+
+   reg 	       sc_pre2;
+   always @(posedge clk)
+     sc_pre2 <= sc_pre1;
+   assign      write_ctrl = sc_pre1 & ~sc_pre2;
+   
+   shortfifo #(.WIDTH(64)) commandfifo
+     (.clk(clk),.rst(rst),.clear(clear_overrun),
+      .datain({new_command,new_time}), .write(write_ctrl), .full(full_ctrl),
+      .dataout({send_imm_pre,chain_pre,numlines,lines_per_frame,rcvtime_pre}), 
+      .read(read_ctrl), .empty(empty_ctrl) );
+
+   // Buffer interface to internal FIFO
+   wire        have_space, write;
+   wire [35:0] fifo_line;
+   
+   // Internal FIFO, size 9 is 2K, size 10 is 4K
+   fifo_cascade #(.WIDTH(36),.SIZE(FIFOSIZE)) rxfifo
+     (.clk(clk),.reset(rst),.clear(clear_overrun),
+      .datain(fifo_line), .src_rdy_i(write), .dst_rdy_o(have_space),
+      .dataout({wr_flags_o,wr_dat_o}), .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i),
+      .space(),.occupied(fifo_occupied) );
+   assign      fifo_full = ~have_space;
+   assign      fifo_empty = ~wr_ready_o;
+
+   // Internal FIFO to DSP interface
+   reg [22:0] lines_left;
+   reg [8:0]  lines_left_frame;
+   localparam IBS_IDLE = 0;
+   localparam IBS_WAITING = 1;
+   localparam IBS_FIRSTLINE = 2;
+   localparam IBS_RUNNING = 3;
+   localparam IBS_OVERRUN = 4;
+   
+   reg [2:0] ibs_state;
+  
+   wire [32:0] delta_time = {1'b0,rcvtime}-{1'b0,master_time};
+   wire        too_late = (delta_time[32:31] == 2'b11) & ~send_imm;
+   wire        go_now = send_imm | ( master_time == rcvtime );
+ 
+   always @(posedge clk)
+     if(rst)
+       begin
+	  ibs_state <= IBS_IDLE;
+	  lines_left <= 0;
+	  lines_left_frame <= 0;
+	  rcvtime <= 0;
+	  send_imm <= 0;
+	  chain <= 0;
+       end
+     else
+       if(clear_overrun)
+	 begin
+	  ibs_state <= IBS_IDLE;
+	  lines_left <= 0;
+	  lines_left_frame <= 0;
+	  rcvtime <= 0;
+	  send_imm <= 0;
+	  chain <= 0;
+	 end
+       else 
+	 case(ibs_state)
+	   IBS_IDLE :
+	     if(~empty_ctrl)
+	       begin
+		  lines_left <= numlines;
+		  lines_left_frame <= lines_per_frame;
+		  rcvtime <= rcvtime_pre;
+		  ibs_state <= IBS_WAITING;
+		  send_imm <= send_imm_pre;
+		  chain <= chain_pre;
+	       end
+	   IBS_WAITING :
+	     if(go_now)
+	       ibs_state <= IBS_FIRSTLINE;
+	     else if(too_late)
+	       ibs_state <= IBS_OVERRUN;
+	   IBS_FIRSTLINE :
+	     if(~have_space | strobe)
+	       ibs_state <= IBS_OVERRUN;
+	     else
+	       ibs_state <= IBS_RUNNING;
+	   IBS_RUNNING :
+	     if(strobe)
+	       if(~have_space)
+		 ibs_state <= IBS_OVERRUN;
+	       else
+		 begin
+		    lines_left <= lines_left - 1;
+		    if(lines_left == 1)
+		      if(~chain)
+			ibs_state <= IBS_IDLE;
+		      else if(empty_ctrl)
+			ibs_state <= IBS_OVERRUN;
+		      else
+			begin
+			   lines_left <= numlines;
+			   lines_left_frame <= lines_per_frame;
+			   rcvtime <= rcvtime_pre;
+			   ibs_state <= IBS_FIRSTLINE;
+			   send_imm <= send_imm_pre;
+			   chain <= chain_pre;
+			end
+		    else if(lines_left_frame == 1)
+		      begin
+			 lines_left_frame <= lines_per_frame;
+			 ibs_state <= IBS_FIRSTLINE;
+		      end
+		    else
+		      lines_left_frame <= lines_left_frame - 1;
+		 end // else: !if(~have_space)
+	 endcase // case(ibs_state)
+   
+   assign fifo_line = (ibs_state == IBS_FIRSTLINE) ? {2'b0,1'b0,1'b1,master_time} :
+		      {2'b0,((lines_left==1)|(lines_left_frame==1)),1'b0,sample};
+   
+   assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & have_space;  // & (ibs_state == IBS_RUNNING) should strobe only when running
+   assign overrun = (ibs_state == IBS_OVERRUN);
+   assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE);
+   assign read_ctrl = ( (ibs_state == IBS_IDLE) | 
+			((ibs_state == IBS_RUNNING) & strobe & have_space & (lines_left==1) & chain) )
+	  & ~empty_ctrl;
+   
+   assign debug_rx = { 8'd0,
+		       1'd0, send_imm, chain, wr_ready_i,wr_ready_o, 2'b0, run,
+		       write,have_space,wr_flags_o[1:0],write_ctrl,full_ctrl,read_ctrl,empty_ctrl,
+		       sc_pre1, clear_overrun, go_now, too_late, overrun, ibs_state[2:0] };
+endmodule // rx_control
diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset.v b/fpga/usrp2/sdr_lib/rx_dcoffset.v
new file mode 100644
index 000000000..bedbd40e6
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/rx_dcoffset.v
@@ -0,0 +1,43 @@
+
+
+module rx_dcoffset 
+  #(parameter WIDTH=14,
+    parameter ADDR=8'd0)
+    (input clk, input rst, 
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     input signed [WIDTH-1:0] adc_in, output signed [WIDTH-1:0] adc_out);
+
+   // Because of some extra delays to make timing easier, the transfer function is:
+   //     (z-1)/(z^2-z-alpha)  where alpha is 1/2^n
+   
+   wire 	       set_now = set_stb & (ADDR == set_addr);
+   
+   reg 		       fixed;  // uses fixed offset
+   wire 	       signed [WIDTH-1:0] fixed_dco;
+   reg 		       signed [31:0] integrator;
+
+   always @(posedge clk)
+     if(rst)
+       begin
+	  fixed <= 0;
+	  integrator <= 32'd0;
+       end
+     else if(set_now)
+       begin
+	  integrator <= {set_data[WIDTH-1:0],{(32-WIDTH){1'b0}}};
+	  fixed <= set_data[31];
+       end
+     else if(~fixed)
+       integrator <= integrator + adc_out;
+   
+   wire [WIDTH:0] scaled_integrator;
+   
+   round #(.bits_in(33),.bits_out(15)) round (.in({integrator[31],integrator}),.out(scaled_integrator));
+   
+   wire [WIDTH:0]      adc_out_int = {adc_in[WIDTH-1],adc_in} - scaled_integrator;
+
+   clip_reg #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip_adc
+     (.clk(clk),.in(adc_out_int),.out(adc_out));
+   
+
+endmodule // rx_dcoffset
diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
new file mode 100644
index 000000000..a8b4ec20f
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v
@@ -0,0 +1,25 @@
+
+`timescale 1ns/1ns
+module rx_dcoffset_tb();
+   
+   reg clk, rst;
+
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #5 clk = ~clk;
+   
+   initial $dumpfile("rx_dcoffset_tb.vcd");
+   initial $dumpvars(0,rx_dcoffset_tb);
+
+   reg [13:0] adc_in = 7;
+   wire [13:0] adc_out;
+
+   always @(posedge clk)
+     $display("%d\t%d",adc_in,adc_out);
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(0))
+     rx_dcoffset(.clk(clk),.rst(rst),.set_stb(0),.set_addr(0),.set_data(0),
+		 .adc_in(adc_in),.adc_out(adc_out));
+   
+endmodule // longfifo_tb
diff --git a/fpga/usrp2/sdr_lib/sign_extend.v b/fpga/usrp2/sdr_lib/sign_extend.v
new file mode 100644
index 000000000..eae67faf2
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/sign_extend.v
@@ -0,0 +1,35 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+
+// Sign extension "macro"
+// bits_out should be greater than bits_in
+
+module sign_extend (in,out);
+	parameter bits_in=0;  // FIXME Quartus insists on a default
+	parameter bits_out=0;
+	
+	input [bits_in-1:0] in;
+	output [bits_out-1:0] out;
+	
+	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
+	
+endmodule
diff --git a/fpga/usrp2/sdr_lib/small_hb_dec.v b/fpga/usrp2/sdr_lib/small_hb_dec.v
new file mode 100644
index 000000000..8519b628a
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/small_hb_dec.v
@@ -0,0 +1,111 @@
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+//   2 * 131072 * halfgen4(.75/8,2)
+module small_hb_dec
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input run,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     output reg stb_out,
+     output [WIDTH-1:0] data_out);
+
+   reg 			stb_in_d1;
+   reg [WIDTH-1:0] 	data_in_d1;
+   always @(posedge clk) stb_in_d1 <= stb_in;
+   always @(posedge clk) data_in_d1 <= data_in;
+   
+   wire 		go;
+   reg 			phase, go_d1, go_d2, go_d3, go_d4;
+   always @(posedge clk)
+     if(rst | ~run)
+       phase <= 0;
+     else if(stb_in_d1)
+       phase <= ~phase;
+   assign 		go = stb_in_d1 & phase;
+   always @(posedge clk) 
+     if(rst | ~run)
+       begin
+	  go_d1 <= 0;
+	  go_d2 <= 0;
+	  go_d3 <= 0;
+	  go_d4 <= 0;
+       end
+     else
+       begin
+	  go_d1 <= go;
+	  go_d2 <= go_d1;
+	  go_d3 <= go_d2;
+	  go_d4 <= go_d3;
+       end
+
+   wire [17:0] 		coeff_a = -10690;
+   wire [17:0] 		coeff_b = 75809;
+   
+   reg [WIDTH-1:0] 	d1, d2, d3, d4 , d5, d6;
+   always @(posedge clk)
+     if(stb_in_d1 | rst)
+       begin
+	  d1 <= data_in_d1;
+	  d2 <= d1;
+	  d3 <= d2;
+	  d4 <= d3;
+	  d5 <= d4;
+	  d6 <= d5;
+       end
+
+   reg [17:0] sum_a, sum_b, middle, middle_d1;
+   wire [17:0] sum_a_unreg, sum_b_unreg;
+   add2 #(.WIDTH(18)) add2_a (.in1(data_in_d1),.in2(d6),.sum(sum_a_unreg));
+   add2 #(.WIDTH(18)) add2_b (.in1(d2),.in2(d4),.sum(sum_b_unreg));
+   
+   always @(posedge clk)
+     if(go)
+       begin
+	  sum_a <= sum_a_unreg;
+	  sum_b <= sum_b_unreg;
+	  middle <= d3;
+       end
+
+   always @(posedge clk)
+     if(go_d1)
+       middle_d1 <= middle;
+   
+   wire [17:0] sum = go_d1 ? sum_b : sum_a;
+   wire [17:0] coeff = go_d1 ? coeff_b : coeff_a;
+   wire [35:0] 	 prod;   
+   MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) );
+   
+   reg [35:0] 	 accum;
+   always @(posedge clk)
+     if(rst)
+       accum <= 0;
+     else if(go_d2)
+       accum <= {middle_d1[17],middle_d1[17],middle_d1,16'd0} + {prod};
+     else if(go_d3)
+       accum <= accum + {prod};
+   
+   wire [17:0] 	 accum_rnd;
+   round #(.bits_in(36),.bits_out(18)) round_acc (.in(accum),.out(accum_rnd));
+
+   reg [17:0] 	 final_sum;
+   always @(posedge clk)
+     if(bypass)
+       final_sum <= data_in_d1;
+     else if(go_d4)
+       final_sum <= accum_rnd;
+
+   assign 	 data_out = final_sum;
+
+   always @(posedge clk)
+     if(rst)
+       stb_out <= 0;
+     else if(bypass)
+       stb_out <= stb_in_d1;
+     else
+       stb_out <= go_d4;
+endmodule // small_hb_dec
diff --git a/fpga/usrp2/sdr_lib/small_hb_dec_tb.v b/fpga/usrp2/sdr_lib/small_hb_dec_tb.v
new file mode 100644
index 000000000..0d6a0689e
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/small_hb_dec_tb.v
@@ -0,0 +1,140 @@
+module hb_dec_tb( ) ;
+   
+    // Parameters for instantiation
+    parameter               clocks  = 9'd2 ; // Number of clocks per input
+    parameter               decim   = 1 ; // Sets the filter to decimate
+    parameter               rate    = 2 ; // Sets the decimation rate
+
+    reg                     clock ;
+    reg                     reset ;
+    reg                     enable ;
+    reg                     strobe_in ;
+    reg     signed  [17:0]  data_in ;
+    wire                    strobe_out ;
+    wire    signed  [17:0]  data_out ;
+
+   initial
+     begin
+	$dumpfile("hb_dec_tb.vcd");
+	$dumpvars(0,hb_dec_tb);
+     end
+   
+    // Setup the clock
+    initial clock = 1'b0 ;
+    always #5 clock <= ~clock ;
+
+    // Come out of reset after a while
+    initial reset = 1'b1 ;
+    initial #1000 reset = 1'b0 ;
+
+    // Enable the entire system
+    initial enable = 1'b1 ;
+
+    // Instantiate UUT
+   /*
+    halfband_ideal 
+      #(
+        .decim      ( decim         ),
+        .rate       ( rate          )
+      ) uut(
+        .clock      ( clock         ),
+        .reset      ( reset         ),
+        .enable     ( enable        ),
+        .strobe_in  ( strobe_in     ),
+        .data_in    ( data_in       ),
+        .strobe_out ( strobe_out    ),
+        .data_out   ( data_out      )
+      ) ;
+    */
+
+   
+   small_hb_dec #(.WIDTH(18)) uut
+     (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in),
+      .stb_out(strobe_out),.data_out(data_out) );
+   
+    integer i, ri, ro, infile, outfile ;
+
+   always @(posedge clock)
+     begin
+	if(strobe_out)
+	  $display(data_out);
+     end
+   
+    // Setup file IO
+    initial begin
+        infile = $fopen("input.dat","r") ;
+        outfile = $fopen("output.dat","r") ;
+        $timeformat(-9, 2, " ns", 10) ;
+    end
+
+    reg                 endofsim ;
+    reg signed  [17:0]  compare ;
+    integer             noe ;
+    initial             noe = 0 ;
+
+    initial begin
+        // Initialize inputs
+        strobe_in <= 1'd0 ;
+        data_in <= 18'd0 ;
+
+        // Wait for reset to go away
+        @(negedge reset) #0 ;
+        
+        // While we're still simulating ...
+        while( !endofsim ) begin
+
+            // Write the input from the file or 0 if EOF...
+            @( posedge clock ) begin
+               //#1 ;
+                strobe_in <= 1'b1 ;
+                if( !$feof(infile) )
+                    ri = $fscanf( infile, "%d", data_in ) ;
+                else
+                    data_in <= 18'd0 ;
+            end
+
+            // Clocked in - set the strobe to 0 if the number of
+            // clocks per sample is greater than 1
+            if( clocks > 1 ) begin
+                @(posedge clock) begin
+                    strobe_in <= 1'b0  ;
+                end
+
+                // Wait for the specified number of cycles
+                for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
+                    @(posedge clock) #1 ;
+                end
+            end
+        end
+
+        // Print out the number of errors that occured
+        if( noe )
+            $display( "FAILED: %d errors during simulation", noe ) ;
+        else
+            $display( "PASSED: Simulation successful" ) ;
+
+        $finish ;
+    end
+
+   // Output comparison of simulated values versus known good values
+   always @ (posedge clock) begin
+      if( reset )
+        endofsim <= 1'b0 ;
+      else begin
+         if( !$feof(outfile) ) begin
+            if( strobe_out ) begin
+               ro = $fscanf( outfile, "%d\n", compare ) ;
+               if( compare != data_out ) begin
+                  //$display( "%t: %d != %d", $realtime, data_out, compare ) ;
+                  noe = noe + 1 ;
+               end
+            end
+         end else begin
+            // Signal end of simulation when no more outputs
+            endofsim <= 1'b1 ;
+         end
+      end
+   end     
+
+endmodule // hb_dec_tb
+
diff --git a/fpga/usrp2/sdr_lib/small_hb_int.v b/fpga/usrp2/sdr_lib/small_hb_int.v
new file mode 100644
index 000000000..f80d3cac3
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/small_hb_int.v
@@ -0,0 +1,85 @@
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+//   2 * 131072 * halfgen4(.75/8,2)
+
+module small_hb_int
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     input [7:0] output_rate,
+     input stb_out,
+     output reg [WIDTH-1:0] data_out);
+
+   reg 		   phase;
+   reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6;
+
+   localparam 	   MWIDTH = 36;
+   wire [MWIDTH-1:0] prod;
+
+   reg [6:0] 	     stbin_d;
+   
+   always @(posedge clk)
+     stbin_d <= {stbin_d[5:0],stb_in};
+   
+   always @(posedge clk)
+     if(stb_in)
+       begin
+	  d1 <= data_in;
+	  d2 <= d1;
+	  d3 <= d2;
+	  d4 <= d3;
+	  d5 <= d4;
+	  d6 <= d5;
+       end
+
+   wire [WIDTH-1:0] sum_outer, sum_inner;
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer));
+   add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner));
+
+   wire [17:0] 	   coeff_outer = -10690;
+   wire [17:0] 	   coeff_inner = 75809;
+
+   MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner), 
+		   .B(stbin_d[1] ? sum_outer : sum_inner) );
+
+   wire [MWIDTH:0] accum;
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1)) 
+     acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum));
+   
+   wire [WIDTH+2:0] 	 accum_rnd;
+   round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3))
+     final_round (.clk(clk),.in(accum),.out(accum_rnd));
+
+   wire [WIDTH-1:0] 	 clipped;
+   clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH))
+     final_clip (.clk(clk),.in(accum_rnd),.out(clipped));
+
+   reg [WIDTH-1:0] 	 saved, saved_d3;
+   always @(posedge clk)
+     if(stbin_d[6])
+       saved <= clipped;
+
+   always @(posedge clk)
+     if(stbin_d[3])
+       saved_d3 <= d3;
+	   
+   always @(posedge clk)
+     if(bypass)
+       data_out <= data_in;
+     else if(stb_in & stb_out)
+       case(output_rate)
+	 1 : data_out <= d6; 
+	 2 : data_out <= d4;
+	 3, 4, 5, 6, 7 : data_out <= d3;
+	 default : data_out <= d2;
+       endcase // case(output_rate)
+     else if(stb_out)
+       data_out <= saved;
+
+endmodule // small_hb_int
+
diff --git a/fpga/usrp2/sdr_lib/small_hb_int_tb.v b/fpga/usrp2/sdr_lib/small_hb_int_tb.v
new file mode 100644
index 000000000..71d77f0a8
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/small_hb_int_tb.v
@@ -0,0 +1,132 @@
+module small_hb_int_tb( ) ;
+   
+   // Parameters for instantiation
+   parameter               clocks  = 8'd1 ; // Number of clocks per output
+   parameter               decim   = 1 ; // Sets the filter to decimate
+   parameter               rate    = 2 ; // Sets the decimation rate
+   
+   reg                     clock ;
+   reg                     reset ;
+   reg                     enable ;
+   wire 		   strobe_in ;
+   reg 			   signed  [17:0]  data_in ;
+   wire                    strobe_out ;
+   wire 		   signed  [17:0]  data_out ;
+   
+   initial
+     begin
+	$dumpfile("small_hb_int_tb.vcd");
+	$dumpvars(0,small_hb_int_tb);
+     end
+   
+   // Setup the clock
+   initial clock = 1'b0 ;
+   always #5 clock <= ~clock ;
+   
+   // Come out of reset after a while
+   initial reset = 1'b1 ;
+   initial #1000 reset = 1'b0 ;
+
+   always @(posedge clock)
+     enable <= ~reset;
+   
+   // Instantiate UUT
+   /*
+    halfband_ideal 
+      #(
+        .decim      ( decim         ),
+        .rate       ( rate          )
+      ) uut(
+        .clock      ( clock         ),
+        .reset      ( reset         ),
+        .enable     ( enable        ),
+        .strobe_in  ( strobe_in     ),
+        .data_in    ( data_in       ),
+        .strobe_out ( strobe_out    ),
+        .data_out   ( data_out      )
+      ) ;
+    */
+
+   cic_strober #(.WIDTH(8))
+     out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks),
+		 .strobe_fast(1),.strobe_slow(strobe_out) );
+   
+   cic_strober #(.WIDTH(8))
+     in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2),
+		.strobe_fast(strobe_out),.strobe_slow(strobe_in) );
+   
+   small_hb_int #(.WIDTH(18)) uut
+     (.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in),
+      .stb_out(strobe_out),.output_rate(clocks),.data_out(data_out) );
+   
+   integer i, ri, ro, infile, outfile ;
+   
+   always @(posedge clock)
+     begin
+	if(strobe_out)
+	  $display(data_out);
+     end
+   
+   // Setup file IO
+   initial begin
+      infile = $fopen("input.dat","r") ;
+      outfile = $fopen("output.dat","r") ;
+      $timeformat(-9, 2, " ns", 10) ;
+   end
+   
+   reg                 endofsim ;
+   reg 		       signed  [17:0]  compare ;
+   integer             noe ;
+   initial             noe = 0 ;
+   
+   initial begin
+      // Initialize inputs
+      data_in <= 18'd0 ;
+      
+      // Wait for reset to go away
+      @(negedge reset) #0 ;
+      
+      // While we're still simulating ...
+      while( !endofsim ) begin
+	 
+         // Write the input from the file or 0 if EOF...
+         @( negedge clock ) begin
+            if(strobe_in)
+              if( !$feof(infile) )
+                ri <= #1 $fscanf( infile, "%d", data_in ) ;
+              else
+                data_in <= 18'd0 ;
+         end
+      end
+      
+      // Print out the number of errors that occured
+      if( noe )
+        $display( "FAILED: %d errors during simulation", noe ) ;
+      else
+        $display( "PASSED: Simulation successful" ) ;
+      
+      $finish ;
+   end
+   
+   // Output comparison of simulated values versus known good values
+   always @ (posedge clock) begin
+      if( reset )
+        endofsim <= 1'b0 ;
+      else begin
+         if( !$feof(outfile) ) begin
+            if( strobe_out ) begin
+               ro = $fscanf( outfile, "%d\n", compare ) ;
+               if( compare != data_out ) begin
+                  //$display( "%t: %d != %d", $realtime, data_out, compare ) ;
+                  noe = noe + 1 ;
+               end
+            end
+         end else begin
+            // Signal end of simulation when no more outputs
+	    if($feof(infile))
+              endofsim <= 1'b1 ;
+         end
+      end
+   end     
+   
+endmodule // small_hb_int_tb
diff --git a/fpga/usrp2/sdr_lib/tx_control.v b/fpga/usrp2/sdr_lib/tx_control.v
new file mode 100644
index 000000000..e5fed0b93
--- /dev/null
+++ b/fpga/usrp2/sdr_lib/tx_control.v
@@ -0,0 +1,168 @@
+
+`define DSP_CORE_TX_BASE 128
+
+module tx_control
+  #(parameter FIFOSIZE = 10)
+    (input clk, input rst,
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     
+     input [31:0] master_time, 
+     output underrun,
+     
+     // To FIFO interface from Buffer Pool
+     input [31:0] rd_dat_i,
+     input [3:0] rd_flags_i,
+     input rd_ready_i,
+     output rd_ready_o,
+     
+     // To DSP Core
+     output [31:0] sample,
+     output run,
+     input strobe,
+
+     // FIFO Levels
+     output [15:0] fifo_occupied,
+     output fifo_full,
+     output fifo_empty,
+
+     // Debug
+     output [31:0] debug
+     );
+
+   wire 	   rd_sop_i  = rd_flags_i[0];  // Unused
+   wire 	   rd_eop_i  = rd_flags_i[1];
+   wire 	   rd_occ_i = rd_flags_i[3:2]; // Unused, should always be 0
+
+   // Buffer interface to internal FIFO
+   wire     write_data, write_ctrl, full_data, full_ctrl;
+   wire     read_data, read_ctrl, empty_data, empty_ctrl;
+   wire     clear_state;
+   reg [1:0] xfer_state;
+   reg [2:0] held_flags;
+   
+   localparam XFER_IDLE = 0;
+   localparam XFER_CTRL = 1;
+   localparam XFER_PKT = 2;
+   // Add underrun state?
+   
+   always @(posedge clk)
+     if(rst)
+       xfer_state <= XFER_IDLE;
+     else if(clear_state)
+       xfer_state <= XFER_IDLE;
+     else
+       if(rd_ready_i & rd_ready_o)
+	 case(xfer_state)
+	   XFER_IDLE :
+	     begin
+		xfer_state <= XFER_CTRL;
+		held_flags <= rd_dat_i[2:0];
+	     end
+	   XFER_CTRL :
+	     xfer_state <= XFER_PKT;
+	   XFER_PKT :
+	     if(rd_eop_i)
+	       xfer_state <= XFER_IDLE;
+	 endcase // case(xfer_state)
+
+   wire have_data_space;
+   assign full_data   = ~have_data_space;
+   
+   assign write_data  = (xfer_state == XFER_PKT) & rd_ready_i & rd_ready_o;
+   assign write_ctrl  = (xfer_state == XFER_CTRL) & rd_ready_i & rd_ready_o;
+
+   assign rd_ready_o  = ~full_data & ~full_ctrl;
+   
+   wire [31:0] data_o;
+   wire        eop_o, eob, sob, send_imm;
+   wire [31:0] sendtime;
+   wire [4:0]  occ_ctrl;
+/*   
+   cascadefifo2 #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo
+     (.clk(clk),.rst(rst),.clear(clear_state),
+      .datain({rd_eop_i,rd_dat_i[31:0]}), .write(write_data), .full(full_data),
+      .dataout({eop_o,data_o}), .read(read_data), .empty(empty_data),
+      .space(), .occupied(fifo_occupied) );
+*/
+   wire        have_data;
+   assign empty_data  = ~have_data;
+   
+   fifo_cascade #(.WIDTH(33),.SIZE(FIFOSIZE)) txctrlfifo
+     (.clk(clk),.reset(rst),.clear(clear_state),
+      .datain({rd_eop_i,rd_dat_i[31:0]}), .src_rdy_i(write_data), .dst_rdy_o(have_data_space),
+      .dataout({eop_o,data_o}), .src_rdy_o(have_data), .dst_rdy_i(read_data),
+      .space(), .occupied(fifo_occupied) );
+   assign      fifo_full = full_data;
+   assign      fifo_empty = empty_data;
+
+   shortfifo #(.WIDTH(35)) ctrlfifo
+     (.clk(clk),.rst(rst),.clear(clear_state),
+      .datain({held_flags[2:0],rd_dat_i[31:0]}), .write(write_ctrl), .full(full_ctrl),
+      .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), .empty(empty_ctrl),
+      .space(), .occupied(occ_ctrl) );
+
+   // Internal FIFO to DSP interface
+   reg [2:0]   ibs_state;
+   
+   localparam  IBS_IDLE = 0;
+   localparam  IBS_WAIT = 1;
+   localparam  IBS_RUNNING = 2;
+   localparam  IBS_CONT_BURST = 3;
+   localparam  IBS_UNDERRUN = 7;
+
+   wire [32:0] delta_time = {1'b0,sendtime}-{1'b0,master_time};
+   
+   wire        too_late = (delta_time[32:31] == 2'b11);
+   wire        go_now = ( master_time == sendtime );
+   
+   always @(posedge clk)
+     if(rst)
+       ibs_state <= IBS_IDLE;
+     else
+       case(ibs_state)
+	 IBS_IDLE :
+	   if(~empty_ctrl & ~empty_data)
+	     ibs_state <= IBS_WAIT;
+	 IBS_WAIT :
+	   if(send_imm)
+	     ibs_state <= IBS_RUNNING;
+	   else if(too_late)
+	     ibs_state <= IBS_UNDERRUN;
+	   else if(go_now)
+	     ibs_state <= IBS_RUNNING;
+	 IBS_RUNNING :
+	   if(strobe)
+	     if(empty_data)
+	       ibs_state <= IBS_UNDERRUN;
+	     else if(eop_o)
+	       if(eob)
+		 ibs_state <= IBS_IDLE;
+	       else
+		 ibs_state <= IBS_CONT_BURST;
+	 IBS_CONT_BURST :
+	   if(~empty_ctrl)  //  & ~empty_data)
+	     ibs_state <= IBS_RUNNING;
+	   else if(strobe)
+	     ibs_state <= IBS_UNDERRUN;
+	 IBS_UNDERRUN :   // FIXME Should probably clean everything out
+	   if(clear_state)
+	     ibs_state <= IBS_IDLE;
+       endcase // case(ibs_state)
+
+   assign      read_ctrl = (ibs_state == IBS_RUNNING) & strobe & eop_o;  // & ~empty_ctrl;
+   assign      read_data = (ibs_state == IBS_RUNNING) & strobe & ~empty_data;
+   assign      run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_CONT_BURST);
+   assign      underrun = (ibs_state == IBS_UNDERRUN);
+
+   wire [7:0]  interp_rate;
+   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_state));
+
+   assign      sample = data_o;
+
+   assign      debug = { {16'b0},
+			 { read_data, write_data, read_ctrl, write_ctrl, xfer_state[1:0],full_ctrl,empty_ctrl },
+			 { occ_ctrl, eop_o, clear_state, underrun} };
+   
+endmodule // tx_control
diff --git a/fpga/usrp2/serdes/serdes.v b/fpga/usrp2/serdes/serdes.v
new file mode 100644
index 000000000..17049bfe6
--- /dev/null
+++ b/fpga/usrp2/serdes/serdes.v
@@ -0,0 +1,63 @@
+
+// SERDES TX and RX along with all flow control logic
+
+module serdes
+  #(parameter TXFIFOSIZE = 9,
+    parameter RXFIFOSIZE = 9)
+    (input clk, input rst,
+     // TX side
+     output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb,
+     input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i,
+     // RX side
+     input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb,
+     output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i,
+
+     output [15:0] tx_occupied, output tx_full, output tx_empty,
+     output [15:0] rx_occupied, output rx_full, output rx_empty,
+
+     output serdes_link_up,
+     
+     output [31:0] debug0, 
+     output [31:0] debug1);
+
+   wire [15:0] fifo_space;
+   wire        xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent;
+   wire [31:0] debug_rx, debug_tx;
+
+   serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx
+     (.clk(clk),.rst(rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i),
+      .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent),
+      .fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty),
+      .debug(debug_tx) );
+   
+   serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
+     (.clk(clk),.rst(rst),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i),
+      .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd),
+      .fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty),
+      .serdes_link_up(serdes_link_up), .debug(debug_rx) );
+
+   serdes_fc_tx serdes_fc_tx
+     (.clk(clk),.rst(rst),
+      .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) );
+
+   serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx
+     (.clk(clk),.rst(rst),
+      .fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) );
+
+   //assign      debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] };
+   //assign      debug = debug_rx;
+
+   assign      debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]},
+			  { debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb},
+			  { ser_t[15:8] },
+			  { ser_t[7:0] } };
+   
+   assign      debug1 = { { debug_rx[7:0] }, /*  odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */
+			  { wr_flags_o[1:0], wr_ready_i, wr_ready_o,  xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
+			  { ser_r[15:8] },
+			  { ser_r[7:0] } };
+endmodule // serdes
diff --git a/fpga/usrp2/serdes/serdes_fc_rx.v b/fpga/usrp2/serdes/serdes_fc_rx.v
new file mode 100644
index 000000000..4dd46e27f
--- /dev/null
+++ b/fpga/usrp2/serdes/serdes_fc_rx.v
@@ -0,0 +1,62 @@
+
+
+module serdes_fc_rx
+  #(parameter LWMARK = 64,
+    parameter HWMARK = 320)
+    (input clk, input rst,
+     input [15:0] fifo_space, 
+     output reg send_xon,
+     output reg send_xoff,
+     input sent);
+    
+   reg [15:0] 	  countdown;
+   reg 		  send_xon_int, send_xoff_int;
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  send_xon_int <= 0;
+	  send_xoff_int <= 0;
+	  countdown <= 0;
+       end
+     else 
+       begin
+	  send_xon_int <= 0;
+	  send_xoff_int <= 0;
+	  if(countdown == 0)
+	    if(fifo_space < LWMARK)
+	      begin
+		 send_xoff_int <= 1;
+		 countdown <= 240;
+	      end
+	    else
+	      ;
+	  else
+	    if(fifo_space > HWMARK)
+	      begin
+		 send_xon_int <= 1;
+		 countdown <= 0;
+	      end
+	    else
+	      countdown <= countdown - 1;
+       end // else: !if(rst)
+
+   // If we are between the high and low water marks, we let the countdown expire
+
+   always @(posedge clk)
+     if(rst)
+       send_xon <= 0;
+     else if(send_xon_int)
+       send_xon <= 1;
+     else if(sent)
+       send_xon <= 0;
+
+   always @(posedge clk)
+     if(rst)
+       send_xoff <= 0;
+     else if(send_xoff_int)
+       send_xoff <= 1;
+     else if(sent)
+       send_xoff <= 0;
+   
+endmodule // serdes_fc_rx
diff --git a/fpga/usrp2/serdes/serdes_fc_tx.v b/fpga/usrp2/serdes/serdes_fc_tx.v
new file mode 100644
index 000000000..2fe967c8d
--- /dev/null
+++ b/fpga/usrp2/serdes/serdes_fc_tx.v
@@ -0,0 +1,24 @@
+
+
+module serdes_fc_tx
+  (input clk, input rst,
+   input xon_rcvd, input xoff_rcvd, output reg inhibit_tx);
+
+   // XOFF means stop sending, XON means start sending
+   // clock domain stuff happens elsewhere, everything here is on main clk
+
+   reg [15:0] state;
+   always @(posedge clk)
+     if(rst)
+       state <= 0;
+     else if(xoff_rcvd)
+       state <= 255;
+     else if(xon_rcvd)
+       state <= 0;
+     else if(state !=0)
+       state <= state - 1;
+
+   always @(posedge clk)
+     inhibit_tx <= (state != 0);
+   
+endmodule // serdes_fc_tx
diff --git a/fpga/usrp2/serdes/serdes_rx.v b/fpga/usrp2/serdes/serdes_rx.v
new file mode 100644
index 000000000..afefccaa1
--- /dev/null
+++ b/fpga/usrp2/serdes/serdes_rx.v
@@ -0,0 +1,292 @@
+
+// SERDES Interface
+
+// LS-Byte is sent first, MS-Byte is second
+// Invalid K Codes
+//  K0.0  000-00000  Error detected
+//  K31.7 111-11111  Loss of input signal
+
+// Valid K Codes
+//  K28.0 000-11100
+//  K28.1 001-11100  Alternate COMMA?
+//  K28.2 010-11100
+//  K28.3 011-11100
+//  K28.4 100-11100
+//  K28.5 101-11100  Standard COMMA?
+//  K28.6 110-11100
+//  K28.7 111-11100  Bad COMMA?
+//  K23.7 111-10111
+//  K27.7 111-11011
+//  K29.7 111-11101
+//  K30.7 111-11110
+
+module serdes_rx
+  #(parameter FIFOSIZE = 9)
+    (input clk,
+     input rst,
+     
+     // RX HW Interface
+     input ser_rx_clk,
+     input [15:0] ser_r,
+     input ser_rklsb,
+     input ser_rkmsb,
+     
+     output [31:0] wr_dat_o,
+     output [3:0] wr_flags_o,
+     input wr_ready_i,
+     output wr_ready_o,
+     
+     output [15:0] fifo_space,
+     output xon_rcvd, output xoff_rcvd,
+
+     output [15:0] fifo_occupied, output fifo_full, output fifo_empty,
+     output reg serdes_link_up,
+     output [31:0] debug
+     );
+
+   localparam K_COMMA = 8'b101_11100;     // 0xBC K28.5
+   localparam K_IDLE = 8'b001_11100;      // 0x3C K28.1
+   localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
+   localparam K_PKT_END = 8'b100_11100;   // 0x9C K28.4
+   localparam K_XON = 8'b010_11100;       // 0x5C K28.2
+   localparam K_XOFF = 8'b011_11100;      // 0x7C K28.3
+   localparam K_LOS = 8'b111_11111;       // 0xFF K31.7
+   localparam K_ERROR = 8'b000_00000;     // 0x00 K00.0
+   localparam D_56 = 8'b110_00101;        // 0xC5 D05.6
+   
+   localparam IDLE = 3'd0;
+   localparam FIRSTLINE1 = 3'd1;
+   localparam FIRSTLINE2 = 3'd2;
+   localparam PKT1 = 3'd3;
+   localparam PKT2 = 3'd4;
+   localparam CRC_CHECK = 3'd5;
+   localparam ERROR = 3'd6;
+   localparam DONE = 3'd7;
+   
+   wire [17:0] even_data;
+   reg [17:0]  odd_data;
+   wire [17:0] chosen_data;
+   reg 	       odd;
+   
+   reg [31:0]  line_i;
+   reg 	       sop_i, eop_i, error_i;
+   wire        error_o, sop_o, eop_o, write;
+   reg [15:0]  halfline;
+   reg [8:0]   holder;
+   wire [31:0] line_o;
+   
+   reg [2:0]   state;
+
+   reg [15:0]  CRC;
+   wire [15:0] nextCRC;
+   reg 	       write_d;
+
+   wire        rst_rxclk;
+   wire        have_space;
+
+   oneshot_2clk rst_1s(.clk_in(clk),.in(rst),.clk_out(ser_rx_clk),.out(rst_rxclk));
+
+   assign      even_data = {ser_rkmsb,ser_rklsb,ser_r};
+   
+   always @(posedge ser_rx_clk)
+     if(rst_rxclk)
+       holder <= 9'd0;
+     else
+       holder <= {even_data[17],even_data[15:8]};
+   
+   always @(posedge ser_rx_clk)
+     if(rst_rxclk)
+       odd_data <= 18'd0;
+     else
+       odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]};
+   
+   assign      chosen_data = odd ? odd_data : even_data;
+
+   // Transfer xon and xoff info to the main system clock for flow control purposes
+   reg 	       xon_rcvd_rxclk, xoff_rcvd_rxclk;
+   always @(posedge ser_rx_clk)
+     xon_rcvd_rxclk = ({1'b1,K_XON} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XON} == {ser_rklsb,ser_r[7:0]} );
+   always @(posedge ser_rx_clk)
+     xoff_rcvd_rxclk = ({1'b1,K_XOFF} == {ser_rkmsb,ser_r[15:8]}) | ({1'b1,K_XOFF} == {ser_rklsb,ser_r[7:0]} );
+   
+   oneshot_2clk xon_1s(.clk_in(ser_rx_clk),.in(xon_rcvd_rxclk),.clk_out(clk),.out(xon_rcvd));
+   oneshot_2clk xoff_1s(.clk_in(ser_rx_clk),.in(xoff_rcvd_rxclk),.clk_out(clk),.out(xoff_rcvd));
+
+   // If the other side is sending xon or xoff, or is flow controlled (b/c we told them to be), don't fill the fifos
+   wire        wait_here = ((chosen_data == {2'b10,K_COMMA,D_56})||
+			    (chosen_data == {2'b11,K_XON,K_XON})||
+			    (chosen_data == {2'b11,K_XOFF,K_XOFF}) );
+
+   always @(posedge ser_rx_clk)
+     if(rst_rxclk) sop_i <= 0;
+     else if(state == FIRSTLINE1) sop_i <= 1;
+     else if(write_d) sop_i <= 0;
+   
+   reg 	       write_pre;
+   always @(posedge ser_rx_clk)
+     if(rst_rxclk)
+       begin
+	  state <= IDLE;
+	  odd <= 0;
+	  halfline <= 0;
+	  line_i <= 0;
+	  eop_i <= 0;
+	  error_i <= 0;
+	  write_pre <= 0;
+       end
+     else
+       case(state)
+	 IDLE :
+	   begin
+	      error_i <= 0;
+	      write_pre <= 0;
+	      if(even_data == {2'b11,K_PKT_START,K_PKT_START})
+		begin
+		   state <= FIRSTLINE1;
+		   odd <= 0;
+		end
+	      else if(odd_data == {2'b11,K_PKT_START,K_PKT_START})
+		begin
+		   state <= FIRSTLINE1;
+		   odd <= 1;
+		end
+	   end
+
+	 FIRSTLINE1 :
+	   if(chosen_data[17:16] == 0)
+	     begin
+		halfline <= chosen_data[15:0];
+		state <= FIRSTLINE2;
+	     end
+	   else if(wait_here)
+	     ;  // Flow Controlled, so wait here and do nothing
+	   else
+	     state <= ERROR;
+
+	 FIRSTLINE2 :
+	   if(chosen_data[17:16] == 0)
+	     begin
+		line_i <= {chosen_data[15:0],halfline};
+		if(~have_space)  // No space to write to!  Should have been avoided by flow control
+		  state <= ERROR;
+		else
+		  begin
+		     state <= PKT1;
+		     write_pre <= 1;
+		  end
+	     end // if (chosen_data[17:16] == 0)
+	   else if(wait_here)
+	     ;  // Flow Controlled, so wait here and do nothing
+	   else
+	     state <= ERROR;
+	 
+	 PKT1 :
+	   begin
+	      write_pre <= 0;
+	      if(chosen_data[17:16] == 0)
+		begin
+		   halfline <= chosen_data[15:0];
+		   state <= PKT2;
+		end
+	      else if(wait_here)
+		;  // Flow Controlled
+	      else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END})
+	  	state <= CRC_CHECK;
+	      else
+		state <= ERROR;
+	   end // case: PKT1
+	 
+	 PKT2 :
+	   if(chosen_data[17:16] == 0)
+	     begin
+		line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline};
+		if(~have_space)  // No space to write to!
+		  state <= ERROR;
+		else
+		  begin
+		     state <= PKT1;
+		     write_pre <= 1;
+		  end
+	     end // if (chosen_data[17:16] == 0)
+	   else if(wait_here)
+	     ;  // Flow Controlled
+	   else
+	     state <= ERROR;
+	   
+	 CRC_CHECK :
+	   if(chosen_data[17:0] == {2'b00,CRC})
+	     begin
+		if(~have_space)
+		  state <= ERROR;
+		else
+		  begin
+		     eop_i <= 1;
+		     state <= DONE;
+		  end
+	     end
+	   else if(wait_here)
+	     ;
+	   else
+	     state <= ERROR;
+	 
+	 ERROR :
+	   begin
+	      error_i <= 1;
+	      if(have_space)
+		state <= IDLE;
+	   end
+	 DONE :
+	   begin
+	      state <= IDLE;
+	      eop_i <= 0;
+	   end
+	      
+       endcase // case(state)
+   
+   
+   always @(posedge ser_rx_clk)
+     if(rst_rxclk)
+       CRC <= 16'hFFFF;
+     else if(state == IDLE)
+       CRC <= 16'hFFFF;
+     else if(chosen_data[17:16] == 2'b00)
+       CRC <= nextCRC;
+
+   CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC);
+
+   always @(posedge ser_rx_clk)
+     if(rst_rxclk) write_d <= 0;
+     else write_d <= write_pre;
+
+   // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
+   assign write = eop_i | (error_i & have_space) | (write_d & (state != CRC_CHECK));
+
+   fifo_2clock_cascade #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
+     (.arst(rst),
+      .wclk(ser_rx_clk),.datain({error_i,sop_i,eop_i,line_i}), 
+      .src_rdy_i(write), .dst_rdy_o(have_space), .space(fifo_space), 
+      .rclk(clk),.dataout({error_o,sop_o,eop_o,line_o}), 
+      .src_rdy_o(wr_ready_o), .dst_rdy_i(wr_ready_i), .occupied(fifo_occupied) );
+
+   assign 	       fifo_full = ~have_space;   // Note -- in the wrong clock domain
+   assign 	       fifo_empty = ~wr_ready_o;
+   
+   // Internal FIFO to Buffer interface
+   assign wr_dat_o 		      = line_o;
+   assign wr_flags_o = { 2'b00, eop_o | error_o, sop_o | error_o };
+   
+   wire slu = ~(({2'b11,K_ERROR,K_ERROR}=={ser_rkmsb,ser_rklsb,ser_r}) ||
+		       ({2'b11,K_LOS,K_LOS}=={ser_rkmsb,ser_rklsb,ser_r}));
+   
+   reg [3:0]   slu_reg;
+   
+   always @(posedge clk)
+     if(rst) slu_reg <= 0;
+     else slu_reg <= {slu_reg[2:0],slu};
+
+   always @(posedge clk)
+     serdes_link_up <= &slu_reg[3:1];
+   
+   assign      debug = { have_space, wr_ready_o, odd, sop_i, eop_i, error_i, state[2:0] };
+   
+endmodule // serdes_rx
diff --git a/fpga/usrp2/serdes/serdes_tb.v b/fpga/usrp2/serdes/serdes_tb.v
new file mode 100644
index 000000000..eb8e019fc
--- /dev/null
+++ b/fpga/usrp2/serdes/serdes_tb.v
@@ -0,0 +1,328 @@
+
+// FIXME need to add flow control
+
+module serdes_tb();
+   
+   reg clk, rst;
+   wire ser_rx_clk, ser_tx_clk;
+   wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb;
+   wire [15:0] ser_r, ser_t;
+   
+   initial clk = 0;
+   initial rst = 1;
+   initial #1000 rst = 0;
+   always #100 clk = ~clk;
+   
+   // Wishbone
+   reg [31:0]  wb_dat_i;
+   wire [31:0] wb_dat_o_rx, wb_dat_o_tx;
+   reg 	       wb_we, wb_en_rx, wb_en_tx;
+   reg [8:0]   wb_adr;
+
+   // Buffer Control
+   reg 	       go, clear, read, write;
+   reg [3:0]   buf_num;
+   wire [31:0] ctrl_word = {buf_num,3'b0,clear,write,read,step,lastline,firstline};
+   reg [8:0]   firstline = 0, lastline = 0;
+   reg [3:0]   step = 1;
+   reg 	       first_tx = 1, first_rx = 1;  // for verif
+   
+   // TX Side
+   reg 	       wb_we_tx;
+   wire        en_tx, we_tx;
+   wire [8:0]  addr_tx;
+   wire [31:0] f2r_tx, r2f_tx;
+   wire [31:0] data_tx;
+   wire        read_tx, done_tx, error_tx, sop_tx, eop_tx;
+   
+   wire        fdone_tx, ferror_tx;
+   
+   reg 	       even;
+   reg 	       channel_error = 0;
+   
+   serdes_tx serdes_tx
+     (.clk(clk),.rst(rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(data_tx),.rd_read_o(read_tx),.rd_done_o(done_tx),
+      .rd_error_o(error_tx),.rd_sop_i(sop_tx),.rd_eop_i(eop_tx) );
+   
+   ram_2port #(.DWIDTH(32),.AWIDTH(9))
+     ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we_tx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx),
+            .clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx));
+   
+   buffer_int #(.BUFF_NUM(1)) buffer_int_tx
+     (.clk(clk),.rst(rst),
+      .ctrl_word(ctrl_word),.go(go),
+      .done(fdone_tx),.error(ferror_tx),
+      
+      .en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx),
+      
+      .wr_dat_i(0),.wr_write_i(0),.wr_done_i(0),
+      .wr_error_i(0),.wr_ready_o(),.wr_full_o(),
+      
+      .rd_dat_o(data_tx),.rd_read_i(read_tx),.rd_done_i(done_tx),
+      .rd_error_i(error_tx),.rd_sop_o(sop_tx),.rd_eop_o(eop_tx) );
+
+
+   // RX Side
+   reg 	       wb_we_rx;
+   wire        en_rx, we_rx;
+   wire [8:0]  addr_rx;
+   wire [31:0] f2r_rx, r2f_rx;
+   wire [31:0] data_rx;
+   wire        write_rx, done_rx, error_rx, ready_rx, empty_rx;
+   
+   wire        fdone_rx, ferror_rx;
+   
+   serdes_rx serdes_rx
+     (.clk(clk),.rst(rst),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(data_rx),.wr_write_o(write_rx),.wr_done_o(done_rx),
+      .wr_error_o(error_rx),.wr_ready_i(ready_rx),.wr_full_i(full_rx) );
+
+   ram_2port #(.DWIDTH(32),.AWIDTH(9))
+     ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we_rx),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx),
+            .clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx) );
+   
+   buffer_int #(.BUFF_NUM(0)) buffer_int_rx
+     (.clk(clk),.rst(rst),
+      .ctrl_word(ctrl_word),.go(go),
+      .done(fdone_rx),.error(ferror_rx),
+      
+      .en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx),
+      
+      .wr_dat_i(data_rx),.wr_write_i(write_rx),.wr_done_i(done_rx),
+      .wr_error_i(error_rx),.wr_ready_o(ready_rx),.wr_full_o(full_rx),
+      
+      .rd_dat_o(),.rd_read_i(0),.rd_done_i(0),
+      .rd_error_i(0),.rd_sop_o(),.rd_eop_o() );
+
+   // Simulate the connection
+   serdes_model serdes_model
+     (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t),
+      .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r),
+      .even(even), .error(channel_error) );
+   
+   initial begin
+      wb_en_rx <= 0;
+      wb_en_tx <=0;
+      wb_we_tx <= 0;
+      wb_we_rx <= 0;
+      wb_adr <= 0;
+      wb_dat_i <= 0;
+      go <= 0;
+      even <= 0;
+      @(negedge rst);
+      @(posedge clk);
+      FillTXRAM;
+      ClearRXRAM;
+      ResetBuffer(0);
+      ResetBuffer(1);
+
+      // receive a full buffer
+      ReceiveSERDES(0,10);
+      SendSERDES(0,10);
+
+      // Receive a partial buffer
+      SendSERDES(11,20);
+      ReceiveSERDES(11,50);
+
+      // Receive too many for buffer
+      SendSERDES(21,100);
+      ReceiveSERDES(21,30);
+
+      // Send 3 packets, then wait to receive them, so they stack up in the rx fifo
+      SendSERDES(31,40);
+      SendSERDES(41,50);
+      SendSERDES(51,60);
+      repeat (10)
+	@(posedge clk);
+      ReceiveSERDES(31,40);
+      ReceiveSERDES(41,50);
+      repeat (1000)
+	@(posedge clk);
+      ReceiveSERDES(51,60);
+
+      // Overfill the FIFO, should get an error on 3rd packet
+      SendSERDES(1,400);
+      SendSERDES(1,400);
+      
+      
+      WaitForTX;
+      //WaitForRX;
+      
+
+      repeat(1000)
+	@(posedge clk);
+      ReceiveSERDES(101,500);
+      ReceiveSERDES(101,500);
+      ReadRAM(80);
+      $finish;
+   end // initial begin
+
+   always @(posedge clk)
+     if(write_rx)
+       $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx, ready_rx, full_rx);
+   
+   always @(posedge clk)
+     if(read_tx)
+       $display("SERDES TX, FIFO READ %x, SOP %d, EOP %d",data_tx, sop_tx, eop_tx);
+   
+   initial begin
+      $dumpfile("serdes_tb.vcd");
+      $dumpvars(0,serdes_tb);
+   end
+
+   initial #10000000 $finish;
+
+   initial #259300 channel_error <= 1;
+   initial #259500 channel_error <= 0;
+   
+   task FillTXRAM;
+      begin
+	 wb_adr <= 0;
+	 wb_dat_i <= 32'h10802000;
+	 wb_we_tx <= 1;
+	 wb_en_tx <= 1;
+	 @(posedge clk);
+	 repeat(511) begin
+	    wb_dat_i <= wb_dat_i + 32'h00010001;
+	    wb_adr <= wb_adr + 1;
+	    @(posedge clk);
+	 end // repeat (511)
+	 wb_we_tx <= 0;
+	 wb_en_tx <= 0;
+	 @(posedge clk);
+	 $display("Done entering Data into TX RAM\n");
+      end
+   endtask // FillTXRAM
+   
+   task ClearRXRAM;
+      begin
+	 wb_adr <= 0;
+	 wb_dat_i <= 0;
+	 wb_we_rx <= 1;
+	 wb_en_rx <= 1;
+	 wb_dat_i <= 0;
+	 @(posedge clk);
+	 repeat(511) begin
+	    wb_adr <= wb_adr + 1;
+	    @(posedge clk);
+	 end // repeat (511)
+	 wb_we_rx <= 0;
+	 wb_en_rx <= 0;
+	 @(posedge clk);
+	 $display("Done clearing RX RAM\n");
+      end
+   endtask // FillRAM
+   
+   task ReadRAM;
+      input [8:0] lastline;
+      begin
+	 wb_en_rx <= 1;
+	 wb_adr <= 0;
+	 @(posedge clk);
+	 @(posedge clk);
+	 repeat(lastline) begin
+	    $display("ADDR: %h  DATA %h", wb_adr, wb_dat_o_rx);
+	    wb_adr <= wb_adr + 1;
+	    @(posedge clk);
+	    @(posedge clk);
+	 end // repeat (511)
+	 $display("ADDR: %h  DATA %h", wb_adr, wb_dat_o_rx);
+	 wb_en_rx <= 0;
+	 @(posedge clk);
+	 $display("Done reading out RX RAM\n");
+      end
+   endtask // FillRAM
+   
+   task ResetBuffer;
+      input [3:0] buffer_num;
+      begin
+	 buf_num <= buffer_num;
+	 clear <= 1; read <= 0; write <= 0;
+	 go <= 1;
+	 @(posedge clk);
+	 go <= 0;
+	 @(posedge clk);
+	 $display("Buffer Reset");
+      end
+   endtask // ClearBuffer
+   
+   task SetBufferWrite;
+      input [3:0] buffer_num;
+      input [8:0] start;
+      input [8:0] stop;
+      begin
+	 buf_num <= buffer_num;
+	 clear <= 0; read <= 0; write <= 1;
+	 firstline <= start;
+	 lastline <= stop;
+	 go <= 1;
+	 @(posedge clk);
+	 go <= 0;
+	 @(posedge clk);
+	 $display("Buffer Set for Write");
+      end
+   endtask // SetBufferWrite
+   
+   task SetBufferRead;
+      input [3:0] buffer_num;
+      input [8:0] start;
+      input [8:0] stop;
+      begin
+	 buf_num <= buffer_num;
+	 clear <= 0; read <= 1; write <= 0;
+	 firstline <= start;
+	 lastline <= stop;
+	 go <= 1;
+	 @(posedge clk);
+	 go <= 0;
+	 @(posedge clk);
+	 $display("Buffer Set for Read");
+      end
+   endtask // SetBufferRead
+
+   task WaitForTX;
+      begin
+	 while (!(fdone_tx | ferror_tx))
+	   @(posedge clk);
+      end
+   endtask // WaitForTX
+   
+   task WaitForRX;
+      begin
+	 while (!(fdone_rx | ferror_rx))
+	   @(posedge clk);
+      end
+   endtask // WaitForRX
+   
+   task SendSERDES;
+      input [8:0] start;
+      input [8:0] stop;
+      begin
+	 if(~first_tx)
+	   WaitForTX;
+	 else
+	   first_tx <= 0;
+	 ResetBuffer(1);
+	 SetBufferRead(1,start,stop);
+	 $display("Here");
+      end
+   endtask // SendSERDES
+   
+   task ReceiveSERDES;
+      input [8:0] start;
+      input [8:0] stop;
+      begin
+	 if(~first_rx)
+	   WaitForRX;
+	 else
+	   first_rx <= 0;
+	 ResetBuffer(0);
+	 SetBufferWrite(0,start,stop);
+	 $display("Here2");
+      end
+   endtask // ReceiveSERDES
+   
+endmodule // serdes_tb
diff --git a/fpga/usrp2/serdes/serdes_tx.v b/fpga/usrp2/serdes/serdes_tx.v
new file mode 100644
index 000000000..2e5e3bd80
--- /dev/null
+++ b/fpga/usrp2/serdes/serdes_tx.v
@@ -0,0 +1,186 @@
+
+// SERDES Interface
+
+// LS-Byte is sent first, MS-Byte is second
+// Invalid K Codes
+//  K0.0  000-00000  Error detected
+//  K31.7 111-11111  Loss of input signal
+
+// Valid K Codes
+//  K28.0 000-11100
+//  K28.1 001-11100  Alternate COMMA?
+//  K28.2 010-11100
+//  K28.3 011-11100
+//  K28.4 100-11100
+//  K28.5 101-11100  Standard COMMA?
+//  K28.6 110-11100
+//  K28.7 111-11100  Bad COMMA?
+//  K23.7 111-10111
+//  K27.7 111-11011
+//  K29.7 111-11101
+//  K30.7 111-11110
+
+module serdes_tx
+  #(parameter FIFOSIZE = 9)
+    (input clk,
+     input rst,
+     
+     // TX HW Interface
+     output ser_tx_clk,
+     output reg [15:0] ser_t,
+     output reg ser_tklsb,
+     output reg ser_tkmsb,
+     
+     // TX Stream Interface
+     input [31:0] rd_dat_i,
+     input [3:0] rd_flags_i,
+     output rd_ready_o,
+     input rd_ready_i,
+
+     // Flow control interface
+     input inhibit_tx,
+     input send_xon,
+     input send_xoff,
+     output sent,
+
+     // FIFO Levels
+     output [15:0] fifo_occupied,
+     output fifo_full,
+     output fifo_empty,
+
+     // DEBUG
+     output [31:0] debug
+     );
+
+   localparam K_COMMA = 8'b101_11100;     // 0xBC K28.5
+   localparam K_IDLE = 8'b001_11100;      // 0x3C K28.1
+   localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
+   localparam K_PKT_END = 8'b100_11100;   // 0x9C K28.4
+   localparam K_XON = 8'b010_11100;       // 0x5C K28.2
+   localparam K_XOFF = 8'b011_11100;      // 0x7C K28.3
+   localparam K_LOS = 8'b111_11111;       // 0xFF K31.7
+   localparam K_ERROR = 8'b000_00000;     // 0x00 K00.0
+   localparam D_56 = 8'b110_00101;        // 0xC5 D05.6
+   assign     ser_tx_clk = clk;
+   
+   localparam IDLE = 3'd0;
+   localparam RUN1 = 3'd1;
+   localparam RUN2 = 3'd2;
+   localparam DONE = 3'd3;
+   localparam SENDCRC = 3'd4;
+   localparam WAIT = 3'd5;
+   
+   reg [2:0]  state;
+   
+   reg [15:0] CRC;
+   wire [15:0] nextCRC;
+   reg [3:0]   wait_count;
+   
+   // Internal FIFO, size 9 is 2K, size 10 is 4K bytes
+   wire        sop_o, eop_o;
+   wire [31:0] data_o;
+
+   wire        rd_sop_i  = rd_flags_i[0];
+   wire        rd_eop_i  = rd_flags_i[1];
+   wire [1:0]  rd_occ_i = rd_flags_i[3:2];  // Unused
+
+   wire        have_data, empty, read;
+   fifo_cascade #(.WIDTH(34),.SIZE(FIFOSIZE)) serdes_tx_fifo
+     (.clk(clk),.reset(rst),.clear(0),
+      .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .src_rdy_i(rd_ready_i), .dst_rdy_o(rd_ready_o),
+      .dataout({sop_o,eop_o,data_o}), .dst_rdy_i(read), .src_rdy_o(have_data),
+      .space(), .occupied(fifo_occupied) );
+   
+   assign fifo_full   = ~rd_ready_o;
+   assign empty       = ~have_data;
+   assign fifo_empty  = empty;
+   
+   // FIXME Implement flow control   
+   reg [15:0]  second_word;
+   reg [33:0]  pipeline;
+   
+   assign      read = (~send_xon & ~send_xoff & (state==RUN2)) | ((state==IDLE) & ~empty & ~sop_o);
+   assign      sent = send_xon | send_xoff;
+   // 2nd half of above probably not necessary.  Just in case we get junk between packets
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  state <= IDLE;
+	  wait_count <= 0;
+	  {ser_tkmsb,ser_tklsb,ser_t} <= 18'd0;
+			//{2'b10,K_COMMA,K_COMMA};  
+	  // make tkmsb and tklsb different so they can go in IOFFs
+       end
+     else
+       if(send_xon)
+	 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XON,K_XON};
+       else if(send_xoff)
+	 {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_XOFF,K_XOFF};
+       else
+	 case(state)
+	   IDLE :
+	     begin
+		if(sop_o & ~empty & ~inhibit_tx)
+		  begin
+		     {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_START,K_PKT_START};
+		     state <= RUN1;
+		  end
+		else
+		  {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
+	     end
+	   RUN1 :
+	     begin
+		if(empty | inhibit_tx)
+		  {ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
+		else
+		  begin
+		     {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[15:0]};
+		     state <= RUN2;
+		  end
+	     end
+	   RUN2 :
+	     begin
+		{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,data_o[31:16]};
+		if(eop_o)
+		  state <= DONE;
+		else
+		  state <= RUN1;
+	     end
+	   DONE :
+	     begin
+		{ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_PKT_END,K_PKT_END};
+		state <= SENDCRC;
+	     end
+	   SENDCRC :
+	     begin
+		{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC};
+		state <= WAIT;
+		wait_count <= 4'd15;
+	     end
+	   WAIT :
+	     begin
+		{ser_tkmsb,ser_tklsb,ser_t} <= {2'b10,K_COMMA,D_56};
+		if(wait_count == 0)
+		  state <= IDLE;
+		else
+		  wait_count <= wait_count - 1;
+	     end
+	   default
+	     state <= IDLE;
+	 endcase // case(state)
+   
+   always @(posedge clk)
+     if(rst)
+       CRC <= 16'hFFFF;
+     else if(state == IDLE)
+       CRC <= 16'hFFFF;
+     else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) )
+       CRC <= nextCRC;
+   
+   CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, nextCRC);
+
+   assign debug = { 28'd0, state[2:0] };
+   
+endmodule // serdes_tx
+
diff --git a/fpga/usrp2/simple_gemac/.gitignore b/fpga/usrp2/simple_gemac/.gitignore
new file mode 100644
index 000000000..17f35e962
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/.gitignore
@@ -0,0 +1,4 @@
+/a.out
+/*.vcd
+simple_gemac_wrapper_tb
+
diff --git a/fpga/usrp2/simple_gemac/address_filter.v b/fpga/usrp2/simple_gemac/address_filter.v
new file mode 100644
index 000000000..50a52b954
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/address_filter.v
@@ -0,0 +1,35 @@
+
+
+module address_filter
+  (input clk,
+   input reset,
+   input go,
+   input [7:0] data,
+   input [47:0] address,
+   output match,
+   output done);
+
+   reg [2:0] af_state;
+
+   always @(posedge clk)
+     if(reset)
+       af_state     <= 0;
+     else
+       if(go)
+	 af_state <= (data == address[47:40]) ? 1 : 7;
+       else
+	 case(af_state)
+	   1 : af_state <= (data == address[39:32]) ? 2 : 7;
+	   2 : af_state <= (data == address[31:24]) ? 3 : 7;
+	   3 : af_state <= (data == address[23:16]) ? 4 : 7;
+	   4 : af_state <= (data == address[15:8])  ? 5 : 7;
+	   5 : af_state <= (data == address[7:0]) ? 6 : 7;
+	   6, 7 : af_state <= 0;
+	 endcase // case (af_state)
+
+   assign match  = (af_state==6);
+   assign done 	 = (af_state==6)|(af_state==7);
+   
+endmodule // address_filter
+
+   
diff --git a/fpga/usrp2/simple_gemac/crc.v b/fpga/usrp2/simple_gemac/crc.v
new file mode 100644
index 000000000..ac019083a
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/crc.v
@@ -0,0 +1,66 @@
+

+module crc

+  (input clk, 

+   input reset,

+   input clear, 

+   input [7:0] data,

+   input calc,

+   output [31:0] crc_out,

+   output match);

+   

+   function[31:0]  NextCRC;

+      input[7:0]      D;

+      input[31:0]     C;

+      reg[31:0]       NewCRC;

+      begin

+	 NewCRC[0]   = C[24]^C[30]^D[1]^D[7];

+	 NewCRC[1]   = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];

+	 NewCRC[2]   = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];

+	 NewCRC[3]   = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

+	 NewCRC[4]   = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];

+	 NewCRC[5]   = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];

+	 NewCRC[6]   = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

+	 NewCRC[7]   = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];

+	 NewCRC[8]   = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];

+	 NewCRC[9]   = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];

+	 NewCRC[10]  = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];

+	 NewCRC[11]  = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];

+	 NewCRC[12]  = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];

+	 NewCRC[13]  = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

+	 NewCRC[14]  = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];

+	 NewCRC[15]  = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];

+	 NewCRC[16]  = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];

+	 NewCRC[17]  = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];

+	 NewCRC[18]  = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];

+	 NewCRC[19]  = C[11]^C[31]^D[0]^C[27]^D[4];

+	 NewCRC[20]  = C[12]^C[28]^D[3];

+	 NewCRC[21]  = C[13]^C[29]^D[2];

+	 NewCRC[22]  = C[14]^C[24]^D[7];

+	 NewCRC[23]  = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];

+	 NewCRC[24]  = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];

+	 NewCRC[25]  = C[17]^C[27]^D[4]^C[26]^D[5];

+	 NewCRC[26]  = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];

+	 NewCRC[27]  = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];

+	 NewCRC[28]  = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];

+	 NewCRC[29]  = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];

+	 NewCRC[30]  = C[22]^C[31]^D[0]^C[28]^D[3];

+	 NewCRC[31]  = C[23]^C[29]^D[2];

+	 NextCRC     = NewCRC;

+      end

+   endfunction

+

+   reg [31:0] crc_reg;

+   always @ (posedge clk)

+     if (reset | clear)

+       crc_reg 	    <= 32'hffffffff;

+     else if (calc)

+       crc_reg 	    <= NextCRC(data,crc_reg);

+        

+   assign crc_out    = ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31],

+		      crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23],

+		      crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15],

+		      crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7] };

+

+   assign match  = (crc_reg == 32'hc704_dd7b);

+		    

+endmodule // crc

diff --git a/fpga/usrp2/simple_gemac/delay_line.v b/fpga/usrp2/simple_gemac/delay_line.v
new file mode 100644
index 000000000..d371bb9c5
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/delay_line.v
@@ -0,0 +1,21 @@
+
+
+module delay_line
+  #(parameter WIDTH=32)
+   (input clk,
+    input [3:0] delay,
+    input [WIDTH-1:0] din,
+    output [WIDTH-1:0] dout);
+    
+   genvar 	       i;
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_delay
+	   SRL16E
+	     srl16e(.Q(dout[i]),
+		    .A0(delay[0]),.A1(delay[1]),.A2(delay[2]),.A3(delay[3]),
+		    .CE(1),.CLK(clk),.D(din[i]));
+	end
+   endgenerate
+
+endmodule // delay_line
diff --git a/fpga/usrp2/simple_gemac/eth_tasks.v b/fpga/usrp2/simple_gemac/eth_tasks.v
new file mode 100644
index 000000000..d49f30e24
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/eth_tasks.v
@@ -0,0 +1,156 @@
+
+
+task SendFlowCtrl;
+   input [15:0] fc_len;
+   begin
+      $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+      pause_time <= fc_len;
+      @(posedge clk);
+      pause_req <= 1;
+      @(posedge clk);
+      pause_req <= 0;
+      $display("Sent Flow Control");
+   end
+endtask // SendFlowCtrl
+
+task SendPacket2MAC;
+   input tx_clk;
+   input [7:0] data_start;
+   input [31:0] data_len;
+   output [7:0] tx_data;
+   output tx_valid;
+   output tx_error;
+   input tx_ack;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count <= 1;
+      tx_data  <= data_start;
+      tx_error <= 0;
+      tx_valid <= 1;
+      while(~tx_ack)
+	@(posedge tx_clk);
+      $display("Packet Accepted, %d", $time);
+      while(count < data_len)
+	begin
+	   tx_data <= tx_data + 1;
+	   count   <= count + 1;
+	   @(posedge clk);
+	end
+      tx_valid <= 0;
+      @(posedge tx_clk);
+   end
+endtask // SendPacket2MAC
+
+task SendPacket_to_ll8;
+   input [7:0] data_start;
+   input [15:0] data_len;
+//   output [7:0] tx_data;
+//   output tx_sof;
+//   output tx_eof;
+//   output tx_src_rdy;
+//   input tx_dst_rdy;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count   <= 2;
+      tx_ll_data2 <= data_start;
+      tx_ll_src_rdy2 <= 1;
+      tx_ll_sof2  <= 1;
+      tx_ll_eof2  <= 0;
+      #1;
+      while(count < data_len)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   @(posedge clk);
+	   tx_ll_data2 = tx_ll_data2 + 1;
+	   count   = count + 1;
+	   tx_ll_sof2 <= 0;
+	end
+      tx_ll_eof2 	   <= 1;
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask // SendPacket_to_ll8
+
+
+task SendPacketFromFile;
+   input clk;
+   input [31:0] data_len;
+   output [7:0] tx_data;
+   output tx_valid;
+   output tx_error;
+   input tx_ack;
+   reg [15:0] count;
+   begin
+      $display("Sending Packet From File Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+      count 	  = 0;
+      tx_data  = pkt_rom[count];
+      tx_error = 0;
+      tx_valid = 1;
+      while(~tx_ack)
+	@(posedge clk);
+      $display("Packet Accepted, %d",$time);
+      count = 1;
+      while(count < data_len)
+	begin
+	   tx_data = pkt_rom[count];
+	   count   = count + 1;
+	   @(posedge clk);
+	end
+      tx_valid <= 0;
+      @(posedge clk);
+   end
+endtask // SendPacketFromFile
+
+task Waiter;
+   input [31:0] wait_length;
+   begin
+      tx_ll_src_rdy2 <= 0;
+      repeat(wait_length)
+	@(posedge clk);
+      tx_ll_src_rdy2 <= 1;
+   end
+endtask // Waiter
+
+task SendPacketFromFile_ll8;
+   input [31:0] data_len;
+   input [31:0] wait_length;
+   input [31:0] wait_time;
+   
+   integer count;
+   begin
+      $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_data2 <= pkt_rom[0];
+      tx_ll_src_rdy2 <= 1;
+      tx_ll_sof2     <= 1;
+      tx_ll_eof2     <= 0;
+      @(posedge clk);
+      
+      for(i=1;i<data_len-1;i=i+1)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   tx_ll_data2 <= pkt_rom[i];
+	   tx_ll_sof2  <= 0;
+	   @(posedge clk);
+	   if(i==wait_time)
+	     Waiter(wait_length);
+	end
+      
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_eof2 <= 1;
+      tx_ll_data2 <= pkt_rom[data_len-1];
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask // SendPacketFromFile_ll8
diff --git a/fpga/usrp2/simple_gemac/eth_tasks_f19.v b/fpga/usrp2/simple_gemac/eth_tasks_f19.v
new file mode 100644
index 000000000..ff3ae5407
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/eth_tasks_f19.v
@@ -0,0 +1,92 @@
+
+
+task SendFlowCtrl;
+   input [15:0] fc_len;
+   begin
+      $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+      pause_time <= fc_len;
+      @(posedge eth_clk);
+      pause_req <= 1;
+      @(posedge eth_clk);
+      pause_req <= 0;
+      $display("Sent Flow Control");
+   end
+endtask // SendFlowCtrl
+
+task SendPacket_to_fifo19;
+   input [31:0] data_start;
+   input [15:0] data_len;
+   reg [15:0] 	count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count   <= 2;
+      tx_f19_data <= {2'b0, 1'b0, 1'b1, data_start};
+      tx_f19_src_rdy  <= 1;
+      #1;
+      while(count < data_len)
+	begin
+	   while(~tx_f19_dst_rdy)
+	     @(posedge sys_clk);
+	   @(posedge sys_clk);
+	   //tx_f19_data[31:0] = tx_f19_data[31:0] + 32'h0101_0101;
+	   count 	   = count + 4;
+	   //tx_f19_data[32] <= 0;
+	end
+      //tx_f19_data[33] 	  <= 1;
+      while(~tx_f19_dst_rdy)
+	@(posedge sys_clk);
+      @(posedge sys_clk);
+      tx_f19_src_rdy <= 0;
+   end
+endtask // SendPacket_to_fifo19
+
+/*
+task Waiter;
+   input [31:0] wait_length;
+   begin
+      tx_ll_src_rdy2 <= 0;
+      repeat(wait_length)
+	@(posedge clk);
+      tx_ll_src_rdy2 <= 1;
+   end
+endtask // Waiter
+*/
+
+/*
+task SendPacketFromFile_f19;
+   input [31:0] data_len;
+   input [31:0] wait_length;
+   input [31:0] wait_time;
+   
+   integer count;
+   begin
+      $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+
+      while(~tx_f19_dst_rdy)
+	@(posedge clk);
+      tx_f19_data <= pkt_rom[0];
+      tx_f19_src_rdy <= 1;
+      tx_f19_eof     <= 0;
+      @(posedge clk);
+      
+      for(i=1;i<data_len-1;i=i+1)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   tx_ll_data2 <= pkt_rom[i];
+	   tx_ll_sof2  <= 0;
+	   @(posedge clk);
+//	   if(i==wait_time)
+//	     Waiter(wait_length);
+	end
+      
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_eof2 <= 1;
+      tx_ll_data2 <= pkt_rom[data_len-1];
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask
+*/
diff --git a/fpga/usrp2/simple_gemac/eth_tasks_f36.v b/fpga/usrp2/simple_gemac/eth_tasks_f36.v
new file mode 100644
index 000000000..efd72778b
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/eth_tasks_f36.v
@@ -0,0 +1,92 @@
+
+
+task SendFlowCtrl;
+   input [15:0] fc_len;
+   begin
+      $display("Sending Flow Control, quanta = %d, time = %d", fc_len,$time);
+      pause_time <= fc_len;
+      @(posedge eth_clk);
+      pause_req <= 1;
+      @(posedge eth_clk);
+      pause_req <= 0;
+      $display("Sent Flow Control");
+   end
+endtask // SendFlowCtrl
+
+task SendPacket_to_fifo36;
+   input [31:0] data_start;
+   input [15:0] data_len;
+   reg [15:0] 	count;
+   begin
+      $display("Sending Packet Len=%d, %d", data_len, $time);
+      count   <= 2;
+      tx_f36_data <= {2'b0, 1'b0, 1'b1, data_start};
+      tx_f36_src_rdy  <= 1;
+      #1;
+      while(count < data_len)
+	begin
+	   while(~tx_f36_dst_rdy)
+	     @(posedge sys_clk);
+	   @(posedge sys_clk);
+	   tx_f36_data[31:0] = tx_f36_data[31:0] + 32'h0101_0101;
+	   count 	   = count + 4;
+	   tx_f36_data[32] <= 0;
+	end
+      tx_f36_data[33] 	  <= 1;
+      while(~tx_f36_dst_rdy)
+	@(posedge sys_clk);
+      @(posedge sys_clk);
+      tx_f36_src_rdy <= 0;
+   end
+endtask // SendPacket_to_fifo36
+
+/*
+task Waiter;
+   input [31:0] wait_length;
+   begin
+      tx_ll_src_rdy2 <= 0;
+      repeat(wait_length)
+	@(posedge clk);
+      tx_ll_src_rdy2 <= 1;
+   end
+endtask // Waiter
+*/
+
+/*
+task SendPacketFromFile_f36;
+   input [31:0] data_len;
+   input [31:0] wait_length;
+   input [31:0] wait_time;
+   
+   integer count;
+   begin
+      $display("Sending Packet From File to LL8 Len=%d, %d",data_len,$time);
+      $readmemh("test_packet.mem",pkt_rom );     
+
+      while(~tx_f36_dst_rdy)
+	@(posedge clk);
+      tx_f36_data <= pkt_rom[0];
+      tx_f36_src_rdy <= 1;
+      tx_f36_eof     <= 0;
+      @(posedge clk);
+      
+      for(i=1;i<data_len-1;i=i+1)
+	begin
+	   while(~tx_ll_dst_rdy2)
+	     @(posedge clk);
+	   tx_ll_data2 <= pkt_rom[i];
+	   tx_ll_sof2  <= 0;
+	   @(posedge clk);
+//	   if(i==wait_time)
+//	     Waiter(wait_length);
+	end
+      
+      while(~tx_ll_dst_rdy2)
+	@(posedge clk);
+      tx_ll_eof2 <= 1;
+      tx_ll_data2 <= pkt_rom[data_len-1];
+      @(posedge clk);
+      tx_ll_src_rdy2 <= 0;
+   end
+endtask
+*/
diff --git a/fpga/usrp2/simple_gemac/flow_ctrl_rx.v b/fpga/usrp2/simple_gemac/flow_ctrl_rx.v
new file mode 100644
index 000000000..d09bf377f
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/flow_ctrl_rx.v
@@ -0,0 +1,61 @@
+

+// RX side of flow control -- when we are running out of RX space, send a PAUSE

+

+module flow_ctrl_rx

+  (input pause_request_en, input [15:0] pause_time, input [15:0] pause_thresh,

+   input rx_clk, input rx_reset, input [15:0] rx_fifo_space,

+   input tx_clk, input tx_reset, output reg pause_req, output reg [15:0] pause_time_req

+   );

+   

+   // ******************************************************************************        

+   // Force our TX to send a PAUSE frame because our RX is nearly full

+   // ******************************************************************************

+

+   // RX Clock Domain

+   reg xon, xoff;

+   reg [21:0] countdown;

+

+   wire [15:0] pause_low_thresh = pause_thresh;

+   wire [15:0] pause_hi_thresh = 16'hFFFF;

+   wire [21:0] pq_reduced = {pause_time,6'd0} - 1700;

+   

+   always @(posedge rx_clk)

+     if(rx_reset)

+       xoff <= 0;

+     else

+       xoff <= (pause_request_en & (countdown==0) & (rx_fifo_space < pause_low_thresh));

+   

+   always @(posedge rx_clk)

+     if(rx_reset)

+       xon  <= 0;

+     else

+       xon  <= ((countdown!=0) & (rx_fifo_space > pause_hi_thresh));

+   

+   always @(posedge rx_clk)

+     if(rx_reset)

+       countdown <= 0;

+     else if(xoff)

+       countdown <= pq_reduced;

+     else if(xon)

+       countdown <= 0;

+     else if(countdown != 0)

+       countdown <= countdown - 1;

+

+   // Cross clock domains

+   wire        xon_tx, xoff_tx;

+   oneshot_2clk send_xon (.clk_in(rx_clk), .in(xon), .clk_out(tx_clk), .out(xon_tx));

+   oneshot_2clk send_xoff (.clk_in(rx_clk), .in(xoff), .clk_out(tx_clk), .out(xoff_tx));

+   

+   always @(posedge tx_clk)

+     if(xoff_tx)

+       pause_time_req <= pause_time;

+     else if(xon_tx)

+       pause_time_req <= 0;

+

+   always @(posedge tx_clk)

+     if(tx_reset)

+       pause_req      <= 0;

+     else 

+       pause_req      <= xon_tx | xoff_tx;

+   

+endmodule // flow_ctrl_rx

diff --git a/fpga/usrp2/simple_gemac/flow_ctrl_tx.v b/fpga/usrp2/simple_gemac/flow_ctrl_tx.v
new file mode 100644
index 000000000..f80f5a76d
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/flow_ctrl_tx.v
@@ -0,0 +1,39 @@
+

+// TX side of flow control -- when other side sends PAUSE, we wait

+

+module flow_ctrl_tx

+  (input        rst,

+   input        tx_clk,

+   //host processor

+   input        tx_pause_en,

+   // From MAC_rx_ctrl

+   input [15:0] pause_quanta,

+   input        pause_quanta_val,

+   // MAC_tx_ctrl

+   output       pause_apply,

+   input        paused);

+     

+   // ******************************************************************************        

+   // Inhibit our TX from transmitting because they sent us a PAUSE frame

+   // ******************************************************************************

+

+   // Pauses are in units of 512 bit times, or 64 bytes/clock cycles, and can be

+   //   as big as 16 bits, so 22 bits are needed for the counter

+   

+   reg [15+6:0] pause_quanta_counter;

+   reg 		pqval_d1, pqval_d2;		

+

+   always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;

+   always @(posedge tx_clk) pqval_d2 <= pqval_d1;

+

+   always @ (posedge tx_clk or posedge rst)

+     if (rst)

+       pause_quanta_counter <= 0;

+     else if (pqval_d1 & ~pqval_d2)

+       pause_quanta_counter <= {pause_quanta, 6'b0}; 

+     else if((pause_quanta_counter!=0) & paused)

+       pause_quanta_counter <= pause_quanta_counter - 1;

+

+   assign	pause_apply = tx_pause_en & (pause_quanta_counter != 0);

+   

+endmodule // flow_ctrl

diff --git a/fpga/usrp2/simple_gemac/ll8_to_txmac.v b/fpga/usrp2/simple_gemac/ll8_to_txmac.v
new file mode 100644
index 000000000..3530a0c59
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/ll8_to_txmac.v
@@ -0,0 +1,43 @@
+
+module ll8_to_txmac
+  (input clk, input reset, input clear,
+   input [7:0] ll_data, input ll_sof, input ll_eof, input ll_src_rdy, output ll_dst_rdy,
+   output [7:0] tx_data, output tx_valid, output tx_error, input tx_ack );
+
+   reg [2:0] xfer_state;
+
+   localparam XFER_IDLE      = 0;
+   localparam XFER_ACTIVE    = 1;
+   localparam XFER_WAIT1     = 2;
+   localparam XFER_UNDERRUN  = 3;
+   localparam XFER_DROP      = 4;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       xfer_state 	    <= XFER_IDLE;
+     else
+       case(xfer_state)
+	 XFER_IDLE :
+	   if(tx_ack)
+	     xfer_state <= XFER_ACTIVE;
+	 XFER_ACTIVE :
+	   if(~ll_src_rdy)
+	     xfer_state <= XFER_UNDERRUN;
+	   else if(ll_eof)
+	     xfer_state <= XFER_WAIT1;
+	 XFER_WAIT1 :
+	   xfer_state <= XFER_IDLE;
+	 XFER_UNDERRUN :
+	   xfer_state <= XFER_DROP;
+	 XFER_DROP :
+	   if(ll_eof)
+	     xfer_state <= XFER_IDLE;
+       endcase // case (xfer_state)
+
+   assign ll_dst_rdy 	 = (xfer_state == XFER_ACTIVE) | tx_ack | (xfer_state == XFER_DROP);
+   assign tx_valid 	 = (ll_src_rdy & (xfer_state == XFER_IDLE))|(xfer_state == XFER_ACTIVE);
+   assign tx_data 	 = ll_data;
+   assign tx_error 	 = (xfer_state == XFER_UNDERRUN);
+   
+endmodule // ll8_to_txmac
+
diff --git a/fpga/usrp2/simple_gemac/miim/eth_clockgen.v b/fpga/usrp2/simple_gemac/miim/eth_clockgen.v
new file mode 100644
index 000000000..9da732f7f
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_clockgen.v
@@ -0,0 +1,141 @@
+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+////  eth_clockgen.v                                              ////

+////                                                              ////

+////  This file is part of the Ethernet IP core project           ////

+////  http://www.opencores.org/projects/ethmac/                   ////

+////                                                              ////

+////  Author(s):                                                  ////

+////      - Igor Mohor (igorM@opencores.org)                      ////

+////                                                              ////

+////  All additional information is avaliable in the Readme.txt   ////

+////  file.                                                       ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+//// Copyright (C) 2001 Authors                                   ////

+////                                                              ////

+//// This source file may be used and distributed without         ////

+//// restriction provided that this copyright statement is not    ////

+//// removed from the file and that any derivative work contains  ////

+//// the original copyright notice and the associated disclaimer. ////

+////                                                              ////

+//// This source file is free software; you can redistribute it   ////

+//// and/or modify it under the terms of the GNU Lesser General   ////

+//// Public License as published by the Free Software Foundation; ////

+//// either version 2.1 of the License, or (at your option) any   ////

+//// later version.                                               ////

+////                                                              ////

+//// This source is distributed in the hope that it will be       ////

+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

+//// PURPOSE.  See the GNU Lesser General Public License for more ////

+//// details.                                                     ////

+////                                                              ////

+//// You should have received a copy of the GNU Lesser General    ////

+//// Public License along with this source; if not, download it   ////

+//// from http://www.opencores.org/lgpl.shtml                     ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+//

+// CVS Revision History

+//

+// $Log: eth_clockgen.v,v $

+// Revision 1.2  2005/12/13 12:54:49  maverickist

+// first simulation passed

+//

+// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator

+// no message

+//

+// Revision 1.2  2005/04/27 15:58:45  Administrator

+// no message

+//

+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator

+// no message

+//

+// Revision 1.3  2002/01/23 10:28:16  mohor

+// Link in the header changed.

+//

+// Revision 1.2  2001/10/19 08:43:51  mohor

+// eth_timescale.v changed to timescale.v This is done because of the

+// simulation of the few cores in a one joined project.

+//

+// Revision 1.1  2001/08/06 14:44:29  mohor

+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).

+// Include files fixed to contain no path.

+// File names and module names changed ta have a eth_ prologue in the name.

+// File eth_timescale.v is used to define timescale

+// All pin names on the top module are changed to contain _I, _O or _OE at the end.

+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O

+// and Mdo_OE. The bidirectional signal must be created on the top level. This

+// is done due to the ASIC tools.

+//

+// Revision 1.1  2001/07/30 21:23:42  mohor

+// Directory structure changed. Files checked and joind together.

+//

+// Revision 1.3  2001/06/01 22:28:55  mohor

+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.

+//

+//

+

+module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);

+

+//parameter Tp=1;

+

+input       Clk;              // Input clock (Host clock)

+input       Reset;            // Reset signal

+input [7:0] Divider;          // Divider (input clock will be divided by the Divider[7:0])

+

+output      Mdc;              // Output clock

+output      MdcEn;            // Enable signal is asserted for one Clk period before Mdc rises.

+output      MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.

+

+reg         Mdc;

+reg   [7:0] Counter;

+

+wire        CountEq0;

+wire  [7:0] CounterPreset;

+wire  [7:0] TempDivider;

+

+

+assign TempDivider[7:0]   = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2

+assign CounterPreset[7:0] = (TempDivider[7:0]>>1) -1;               // We are counting half of period

+

+

+// Counter counts half period

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    Counter[7:0] <= 8'h1;

+  else

+    begin

+      if(CountEq0)

+        begin

+          Counter[7:0] <= CounterPreset[7:0];

+        end

+      else

+        Counter[7:0] <= Counter - 8'h1;

+    end

+end

+

+

+// Mdc is asserted every other half period

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    Mdc <= 1'b0;

+  else

+    begin

+      if(CountEq0)

+        Mdc <= ~Mdc;

+    end

+end

+

+

+assign CountEq0 = Counter == 8'h0;

+assign MdcEn = CountEq0 & ~Mdc;

+assign MdcEn_n = CountEq0 & Mdc;

+

+endmodule

+

+

diff --git a/fpga/usrp2/simple_gemac/miim/eth_miim.v b/fpga/usrp2/simple_gemac/miim/eth_miim.v
new file mode 100644
index 000000000..a15c94205
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_miim.v
@@ -0,0 +1,470 @@
+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+////  eth_miim.v                                                  ////

+////                                                              ////

+////  This file is part of the Ethernet IP core project           ////

+////  http://www.opencores.org/projects/ethmac/                   ////

+////                                                              ////

+////  Author(s):                                                  ////

+////      - Igor Mohor (igorM@opencores.org)                      ////

+////                                                              ////

+////  All additional information is avaliable in the Readme.txt   ////

+////  file.                                                       ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+//// Copyright (C) 2001 Authors                                   ////

+////                                                              ////

+//// This source file may be used and distributed without         ////

+//// restriction provided that this copyright statement is not    ////

+//// removed from the file and that any derivative work contains  ////

+//// the original copyright notice and the associated disclaimer. ////

+////                                                              ////

+//// This source file is free software; you can redistribute it   ////

+//// and/or modify it under the terms of the GNU Lesser General   ////

+//// Public License as published by the Free Software Foundation; ////

+//// either version 2.1 of the License, or (at your option) any   ////

+//// later version.                                               ////

+////                                                              ////

+//// This source is distributed in the hope that it will be       ////

+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

+//// PURPOSE.  See the GNU Lesser General Public License for more ////

+//// details.                                                     ////

+////                                                              ////

+//// You should have received a copy of the GNU Lesser General    ////

+//// Public License along with this source; if not, download it   ////

+//// from http://www.opencores.org/lgpl.shtml                     ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+//

+// CVS Revision History

+//

+// $Log: eth_miim.v,v $

+// Revision 1.3  2006/01/19 14:07:53  maverickist

+// verification is complete.

+//

+// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator

+// no message

+//

+// Revision 1.4  2005/08/16 12:07:57  Administrator

+// no message

+//

+// Revision 1.3  2005/05/19 07:04:29  Administrator

+// no message

+//

+// Revision 1.2  2005/04/27 15:58:46  Administrator

+// no message

+//

+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator

+// no message

+//

+// Revision 1.5  2003/05/16 10:08:27  mohor

+// Busy was set 2 cycles too late. Reported by Dennis Scott.

+//

+// Revision 1.4  2002/08/14 18:32:10  mohor

+// - Busy signal was not set on time when scan status operation was performed

+// and clock was divided with more than 2.

+// - Nvalid remains valid two more clocks (was previously cleared too soon).

+//

+// Revision 1.3  2002/01/23 10:28:16  mohor

+// Link in the header changed.

+//

+// Revision 1.2  2001/10/19 08:43:51  mohor

+// eth_timescale.v changed to timescale.v This is done because of the

+// simulation of the few cores in a one joined project.

+//

+// Revision 1.1  2001/08/06 14:44:29  mohor

+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).

+// Include files fixed to contain no path.

+// File names and module names changed ta have a eth_ prologue in the name.

+// File eth_timescale.v is used to define timescale

+// All pin names on the top module are changed to contain _I, _O or _OE at the end.

+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O

+// and Mdo_OE. The bidirectional signal must be created on the top level. This

+// is done due to the ASIC tools.

+//

+// Revision 1.2  2001/08/02 09:25:31  mohor

+// Unconnected signals are now connected.

+//

+// Revision 1.1  2001/07/30 21:23:42  mohor

+// Directory structure changed. Files checked and joind together.

+//

+// Revision 1.3  2001/06/01 22:28:56  mohor

+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.

+//

+//

+

+module eth_miim

+(

+  Clk,

+  Reset,

+  Divider,

+  NoPre,

+  CtrlData,

+  Rgad,

+  Fiad,

+  WCtrlData,

+  RStat,

+  ScanStat,

+  Mdio,

+  Mdc,

+  Busy,

+  Prsd,

+  LinkFail,

+  Nvalid,

+  WCtrlDataStart,

+  RStatStart,

+  UpdateMIIRX_DATAReg

+);

+

+input         Clk;                // Host Clock

+input         Reset;              // General Reset

+input   [7:0] Divider;            // Divider for the host clock

+input  [15:0] CtrlData;           // Control Data (to be written to the PHY reg.)

+input   [4:0] Rgad;               // Register Address (within the PHY)

+input   [4:0] Fiad;               // PHY Address

+input         NoPre;              // No Preamble (no 32-bit preamble)

+input         WCtrlData;          // Write Control Data operation

+input         RStat;              // Read Status operation

+input         ScanStat;           // Scan Status operation

+inout         Mdio;                // MII Management Data In

+

+output        Mdc;                // MII Management Data Clock

+

+output        Busy;               // Busy Signal

+output        LinkFail;           // Link Integrity Signal

+output        Nvalid;             // Invalid Status (qualifier for the valid scan result)

+

+output [15:0] Prsd;               // Read Status Data (data read from the PHY)

+

+output        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register

+output        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register

+output        UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data

+

+//parameter Tp = 1;

+

+

+reg           Nvalid;

+reg           EndBusy_d;          // Pre-end Busy signal

+reg           EndBusy;            // End Busy signal (stops the operation in progress)

+

+reg           WCtrlData_q1;       // Write Control Data operation delayed 1 Clk cycle

+reg           WCtrlData_q2;       // Write Control Data operation delayed 2 Clk cycles

+reg           WCtrlData_q3;       // Write Control Data operation delayed 3 Clk cycles

+reg           WCtrlDataStart;     // Start Write Control Data Command (positive edge detected)

+reg           WCtrlDataStart_q;

+reg           WCtrlDataStart_q1;  // Start Write Control Data Command delayed 1 Mdc cycle

+reg           WCtrlDataStart_q2;  // Start Write Control Data Command delayed 2 Mdc cycles

+

+reg           RStat_q1;           // Read Status operation delayed 1 Clk cycle

+reg           RStat_q2;           // Read Status operation delayed 2 Clk cycles

+reg           RStat_q3;           // Read Status operation delayed 3 Clk cycles

+reg           RStatStart;         // Start Read Status Command (positive edge detected)

+reg           RStatStart_q1;      // Start Read Status Command delayed 1 Mdc cycle

+reg           RStatStart_q2;      // Start Read Status Command delayed 2 Mdc cycles

+

+reg           ScanStat_q1;        // Scan Status operation delayed 1 cycle

+reg           ScanStat_q2;        // Scan Status operation delayed 2 cycles

+reg           SyncStatMdcEn;      // Scan Status operation delayed at least cycles and synchronized to MdcEn

+

+wire          WriteDataOp;        // Write Data Operation (positive edge detected)

+wire          ReadStatusOp;       // Read Status Operation (positive edge detected)

+wire          ScanStatusOp;       // Scan Status Operation (positive edge detected)

+wire          StartOp;            // Start Operation (start of any of the preceding operations)

+wire          EndOp;              // End of Operation

+

+reg           InProgress;         // Operation in progress

+reg           InProgress_q1;      // Operation in progress delayed 1 Mdc cycle

+reg           InProgress_q2;      // Operation in progress delayed 2 Mdc cycles

+reg           InProgress_q3;      // Operation in progress delayed 3 Mdc cycles

+

+reg           WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)

+reg     [6:0] BitCounter;         // Bit Counter

+

+

+wire    [3:0] ByteSelect;         // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.

+wire          MdcEn;              // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.

+wire          ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal

+

+

+wire          LatchByte1_d2;

+wire          LatchByte0_d2;

+reg           LatchByte1_d;

+reg           LatchByte0_d;

+reg     [1:0] LatchByte;          // Latch Byte selects which part of Read Status Data is updated from the shift register

+

+reg           UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data

+

+wire        Mdo;                // MII Management Data Output

+wire        MdoEn;              // MII Management Data Output Enable

+wire		Mdi;

+

+assign  Mdi=Mdio;

+assign  Mdio=MdoEn?Mdo:1'bz;

+

+

+

+// Generation of the EndBusy signal. It is used for ending the MII Management operation.

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    begin

+      EndBusy_d <= 1'b0;

+      EndBusy <= 1'b0;

+    end

+  else

+    begin

+      EndBusy_d <= ~InProgress_q2 & InProgress_q3;

+      EndBusy   <= EndBusy_d;

+    end

+end

+

+

+// Update MII RX_DATA register

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    UpdateMIIRX_DATAReg <= 0;

+  else

+  if(EndBusy & ~WCtrlDataStart_q)

+    UpdateMIIRX_DATAReg <= 1;

+  else

+    UpdateMIIRX_DATAReg <= 0;    

+end

+

+

+

+// Generation of the delayed signals used for positive edge triggering.

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    begin

+      WCtrlData_q1 <= 1'b0;

+      WCtrlData_q2 <= 1'b0;

+      WCtrlData_q3 <= 1'b0;

+      

+      RStat_q1 <= 1'b0;

+      RStat_q2 <= 1'b0;

+      RStat_q3 <= 1'b0;

+

+      ScanStat_q1  <= 1'b0;

+      ScanStat_q2  <= 1'b0;

+      SyncStatMdcEn <= 1'b0;

+    end

+  else

+    begin

+      WCtrlData_q1 <= WCtrlData;

+      WCtrlData_q2 <= WCtrlData_q1;

+      WCtrlData_q3 <= WCtrlData_q2;

+

+      RStat_q1 <= RStat;

+      RStat_q2 <= RStat_q1;

+      RStat_q3 <= RStat_q2;

+

+      ScanStat_q1  <= ScanStat;

+      ScanStat_q2  <= ScanStat_q1;

+      if(MdcEn)

+        SyncStatMdcEn  <= ScanStat_q2;

+    end

+end

+

+

+// Generation of the Start Commands (Write Control Data or Read Status)

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    begin

+      WCtrlDataStart <= 1'b0;

+      WCtrlDataStart_q <= 1'b0;

+      RStatStart <= 1'b0;

+    end

+  else

+    begin

+      if(EndBusy)

+        begin

+          WCtrlDataStart <= 1'b0;

+          RStatStart <= 1'b0;

+        end

+      else

+        begin

+          if(WCtrlData_q2 & ~WCtrlData_q3)

+            WCtrlDataStart <= 1'b1;

+          if(RStat_q2 & ~RStat_q3)

+            RStatStart <= 1'b1;

+          WCtrlDataStart_q <= WCtrlDataStart;

+        end

+    end

+end 

+

+

+// Generation of the Nvalid signal (indicates when the status is invalid)

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    Nvalid <= 1'b0;

+  else

+    begin

+      if(~InProgress_q2 & InProgress_q3)

+        begin

+          Nvalid <= 1'b0;

+        end

+      else

+        begin

+          if(ScanStat_q2  & ~SyncStatMdcEn)

+            Nvalid <= 1'b1;

+        end

+    end

+end 

+

+// Signals used for the generation of the Operation signals (positive edge)

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    begin

+      WCtrlDataStart_q1 <= 1'b0;

+      WCtrlDataStart_q2 <= 1'b0;

+

+      RStatStart_q1 <= 1'b0;

+      RStatStart_q2 <= 1'b0;

+

+      InProgress_q1 <= 1'b0;

+      InProgress_q2 <= 1'b0;

+      InProgress_q3 <= 1'b0;

+

+  	  LatchByte0_d <= 1'b0;

+  	  LatchByte1_d <= 1'b0;

+

+  	  LatchByte <= 2'b00;

+    end

+  else

+    begin

+      if(MdcEn)

+        begin

+          WCtrlDataStart_q1 <= WCtrlDataStart;

+          WCtrlDataStart_q2 <= WCtrlDataStart_q1;

+

+          RStatStart_q1 <= RStatStart;

+          RStatStart_q2 <= RStatStart_q1;

+

+          LatchByte[0] <= LatchByte0_d;

+          LatchByte[1] <= LatchByte1_d;

+

+          LatchByte0_d <= LatchByte0_d2;

+          LatchByte1_d <= LatchByte1_d2;

+

+          InProgress_q1 <= InProgress;

+          InProgress_q2 <= InProgress_q1;

+          InProgress_q3 <= InProgress_q2;

+        end

+    end

+end 

+

+

+// Generation of the Operation signals

+assign WriteDataOp  = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;    

+assign ReadStatusOp = RStatStart_q1     & ~RStatStart_q2;

+assign ScanStatusOp = SyncStatMdcEn     & ~InProgress & ~InProgress_q1 & ~InProgress_q2;

+assign StartOp      = WriteDataOp | ReadStatusOp | ScanStatusOp;

+

+// Busy

+reg		Busy;

+always @ (posedge Clk or posedge Reset)

+	if (Reset)

+		Busy	<=0;

+	else if(WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid)

+		Busy	<=1;

+	else

+		Busy	<=0;

+		

+//assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;

+

+

+// Generation of the InProgress signal (indicates when an operation is in progress)

+// Generation of the WriteOp signal (indicates when a write is in progress)

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    begin

+      InProgress <= 1'b0;

+      WriteOp <= 1'b0;

+    end

+  else

+    begin

+      if(MdcEn)

+        begin

+          if(StartOp)

+            begin

+              if(~InProgress)

+                WriteOp <= WriteDataOp;

+              InProgress <= 1'b1;

+            end

+          else

+            begin

+              if(EndOp)

+                begin

+                  InProgress <= 1'b0;

+                  WriteOp <= 1'b0;

+                end

+            end

+        end

+    end

+end

+

+

+

+// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    BitCounter[6:0] <= 7'h0;

+  else

+    begin

+      if(MdcEn)

+        begin

+          if(InProgress)

+            begin

+              if(NoPre & ( BitCounter == 7'h0 ))

+                BitCounter[6:0] <= 7'h21;

+              else

+                BitCounter[6:0] <= BitCounter[6:0] + 1'b1;

+            end

+          else

+            BitCounter[6:0] <= 7'h0;

+        end

+    end

+end

+

+

+// Operation ends when the Bit Counter reaches 63

+assign EndOp = BitCounter==63;

+

+assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));

+assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);

+assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);

+assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);

+

+

+// Latch Byte selects which part of Read Status Data is updated from the shift register

+assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;

+assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;

+

+wire MdcEn_n;

+

+// Connecting the Clock Generator Module

+eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) 

+                   );

+

+// Connecting the Shift Register Module

+eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), 

+                    .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), 

+                    .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)

+                   );

+

+// Connecting the Output Control Module

+eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), 

+                          .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), 

+                          .Mdo(Mdo), .MdoEn(MdoEn)

+                         );

+

+endmodule

diff --git a/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v b/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v
new file mode 100644
index 000000000..3df6c560a
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_outputcontrol.v
@@ -0,0 +1,158 @@
+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+////  eth_outputcontrol.v                                         ////

+////                                                              ////

+////  This file is part of the Ethernet IP core project           ////

+////  http://www.opencores.org/projects/ethmac/                   ////

+////                                                              ////

+////  Author(s):                                                  ////

+////      - Igor Mohor (igorM@opencores.org)                      ////

+////                                                              ////

+////  All additional information is avaliable in the Readme.txt   ////

+////  file.                                                       ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+//// Copyright (C) 2001 Authors                                   ////

+////                                                              ////

+//// This source file may be used and distributed without         ////

+//// restriction provided that this copyright statement is not    ////

+//// removed from the file and that any derivative work contains  ////

+//// the original copyright notice and the associated disclaimer. ////

+////                                                              ////

+//// This source file is free software; you can redistribute it   ////

+//// and/or modify it under the terms of the GNU Lesser General   ////

+//// Public License as published by the Free Software Foundation; ////

+//// either version 2.1 of the License, or (at your option) any   ////

+//// later version.                                               ////

+////                                                              ////

+//// This source is distributed in the hope that it will be       ////

+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

+//// PURPOSE.  See the GNU Lesser General Public License for more ////

+//// details.                                                     ////

+////                                                              ////

+//// You should have received a copy of the GNU Lesser General    ////

+//// Public License along with this source; if not, download it   ////

+//// from http://www.opencores.org/lgpl.shtml                     ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+//

+// CVS Revision History

+//

+// $Log: eth_outputcontrol.v,v $

+// Revision 1.2  2005/12/13 12:54:49  maverickist

+// first simulation passed

+//

+// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator

+// no message

+//

+// Revision 1.2  2005/04/27 15:58:46  Administrator

+// no message

+//

+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator

+// no message

+//

+// Revision 1.4  2002/07/09 20:11:59  mohor

+// Comment removed.

+//

+// Revision 1.3  2002/01/23 10:28:16  mohor

+// Link in the header changed.

+//

+// Revision 1.2  2001/10/19 08:43:51  mohor

+// eth_timescale.v changed to timescale.v This is done because of the

+// simulation of the few cores in a one joined project.

+//

+// Revision 1.1  2001/08/06 14:44:29  mohor

+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).

+// Include files fixed to contain no path.

+// File names and module names changed ta have a eth_ prologue in the name.

+// File eth_timescale.v is used to define timescale

+// All pin names on the top module are changed to contain _I, _O or _OE at the end.

+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O

+// and Mdo_OE. The bidirectional signal must be created on the top level. This

+// is done due to the ASIC tools.

+//

+// Revision 1.1  2001/07/30 21:23:42  mohor

+// Directory structure changed. Files checked and joind together.

+//

+// Revision 1.3  2001/06/01 22:28:56  mohor

+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.

+//

+//

+

+module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);

+

+input         Clk;                // Host Clock

+input         Reset;              // General Reset

+input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)

+input         NoPre;              // No Preamble (no 32-bit preamble)

+input         InProgress;         // Operation in progress

+input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal

+input   [6:0] BitCounter;         // Bit Counter

+input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.

+

+output        Mdo;                // MII Management Data Output

+output        MdoEn;              // MII Management Data Output Enable

+

+wire          SerialEn;

+

+reg           MdoEn_2d;

+reg           MdoEn_d;

+reg           MdoEn;

+

+reg           Mdo_2d;

+reg           Mdo_d;

+reg           Mdo;                // MII Management Data Output

+

+

+

+// Generation of the Serial Enable signal (enables the serialization of the data)

+assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )

+                | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));

+

+

+// Generation of the MdoEn signal

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    begin

+      MdoEn_2d <= 1'b0;

+      MdoEn_d <= 1'b0;

+      MdoEn <= 1'b0;

+    end

+  else

+    begin

+      if(MdcEn_n)

+        begin

+          MdoEn_2d <= SerialEn | InProgress & BitCounter<32;

+          MdoEn_d <= MdoEn_2d;

+          MdoEn <= MdoEn_d;

+        end

+    end

+end

+

+

+// Generation of the Mdo signal.

+always @ (posedge Clk or posedge Reset)

+begin

+  if(Reset)

+    begin

+      Mdo_2d <= 1'b0;

+      Mdo_d <= 1'b0;

+      Mdo <= 1'b0;

+    end

+  else

+    begin

+      if(MdcEn_n)

+        begin

+          Mdo_2d <= ~SerialEn & BitCounter<32;

+          Mdo_d <= ShiftedBit | Mdo_2d;

+          Mdo <= Mdo_d;

+        end

+    end

+end

+

+

+

+endmodule

diff --git a/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v b/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v
new file mode 100644
index 000000000..0b97bb7bc
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/miim/eth_shiftreg.v
@@ -0,0 +1,159 @@
+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+////  eth_shiftreg.v                                              ////

+////                                                              ////

+////  This file is part of the Ethernet IP core project           ////

+////  http://www.opencores.org/projects/ethmac/                   ////

+////                                                              ////

+////  Author(s):                                                  ////

+////      - Igor Mohor (igorM@opencores.org)                      ////

+////                                                              ////

+////  All additional information is avaliable in the Readme.txt   ////

+////  file.                                                       ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+////                                                              ////

+//// Copyright (C) 2001 Authors                                   ////

+////                                                              ////

+//// This source file may be used and distributed without         ////

+//// restriction provided that this copyright statement is not    ////

+//// removed from the file and that any derivative work contains  ////

+//// the original copyright notice and the associated disclaimer. ////

+////                                                              ////

+//// This source file is free software; you can redistribute it   ////

+//// and/or modify it under the terms of the GNU Lesser General   ////

+//// Public License as published by the Free Software Foundation; ////

+//// either version 2.1 of the License, or (at your option) any   ////

+//// later version.                                               ////

+////                                                              ////

+//// This source is distributed in the hope that it will be       ////

+//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

+//// PURPOSE.  See the GNU Lesser General Public License for more ////

+//// details.                                                     ////

+////                                                              ////

+//// You should have received a copy of the GNU Lesser General    ////

+//// Public License along with this source; if not, download it   ////

+//// from http://www.opencores.org/lgpl.shtml                     ////

+////                                                              ////

+//////////////////////////////////////////////////////////////////////

+//

+// CVS Revision History

+//

+// $Log: eth_shiftreg.v,v $

+// Revision 1.2  2005/12/13 12:54:49  maverickist

+// first simulation passed

+//

+// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator

+// no message

+//

+// Revision 1.2  2005/04/27 15:58:47  Administrator

+// no message

+//

+// Revision 1.1.1.1  2004/12/15 06:38:54  Administrator

+// no message

+//

+// Revision 1.5  2002/08/14 18:16:59  mohor

+// LinkFail signal was not latching appropriate bit.

+//

+// Revision 1.4  2002/03/02 21:06:01  mohor

+// LinkFail signal was not latching appropriate bit.

+//

+// Revision 1.3  2002/01/23 10:28:16  mohor

+// Link in the header changed.

+//

+// Revision 1.2  2001/10/19 08:43:51  mohor

+// eth_timescale.v changed to timescale.v This is done because of the

+// simulation of the few cores in a one joined project.

+//

+// Revision 1.1  2001/08/06 14:44:29  mohor

+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).

+// Include files fixed to contain no path.

+// File names and module names changed ta have a eth_ prologue in the name.

+// File eth_timescale.v is used to define timescale

+// All pin names on the top module are changed to contain _I, _O or _OE at the end.

+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O

+// and Mdo_OE. The bidirectional signal must be created on the top level. This

+// is done due to the ASIC tools.

+//

+// Revision 1.1  2001/07/30 21:23:42  mohor

+// Directory structure changed. Files checked and joind together.

+//

+// Revision 1.3  2001/06/01 22:28:56  mohor

+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.

+//

+//

+

+module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect, 

+                    LatchByte, ShiftedBit, Prsd, LinkFail);

+

+

+input       Clk;              // Input clock (Host clock)

+input       Reset;            // Reset signal

+input       MdcEn_n;          // Enable signal is asserted for one Clk period before Mdc falls.

+input       Mdi;              // MII input data

+input [4:0] Fiad;             // PHY address

+input [4:0] Rgad;             // Register address (within the selected PHY)

+input [15:0]CtrlData;         // Control data (data to be written to the PHY)

+input       WriteOp;          // The current operation is a PHY register write operation

+input [3:0] ByteSelect;       // Byte select

+input [1:0] LatchByte;        // Byte select for latching (read operation)

+

+output      ShiftedBit;       // Bit shifted out of the shift register

+output[15:0]Prsd;             // Read Status Data (data read from the PHY)

+output      LinkFail;         // Link Integrity Signal

+

+reg   [7:0] ShiftReg;         // Shift register for shifting the data in and out

+reg   [15:0]Prsd;

+reg         LinkFail;

+

+

+

+

+// ShiftReg[7:0] :: Shift Register Data

+always @ (posedge Clk or posedge Reset) 

+begin

+  if(Reset)

+    begin

+      ShiftReg[7:0] <= 8'h0;

+      Prsd[15:0] <= 16'h0;

+      LinkFail <= 1'b0;

+    end

+  else

+    begin

+      if(MdcEn_n)

+        begin 

+          if(|ByteSelect)

+            begin

+              case (ByteSelect[3:0])

+                4'h1 :    ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};

+                4'h2 :    ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};

+                4'h4 :    ShiftReg[7:0] <= CtrlData[15:8];

+                4'h8 :    ShiftReg[7:0] <= CtrlData[7:0];

+                default : ShiftReg[7:0] <= 8'h0;

+              endcase

+            end 

+          else

+            begin

+              ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};

+              if(LatchByte[0])

+                begin

+                  Prsd[7:0] <= {ShiftReg[6:0], Mdi};

+                  if(Rgad == 5'h01)

+                    LinkFail <= ~ShiftReg[1];  // this is bit [2], because it is not shifted yet

+                end

+              else

+                begin

+                  if(LatchByte[1])

+                    Prsd[15:8] <= {ShiftReg[6:0], Mdi};

+                end

+            end

+        end

+    end

+end

+

+

+assign ShiftedBit = ShiftReg[7];

+

+

+endmodule

diff --git a/fpga/usrp2/simple_gemac/rxmac_to_ll8.v b/fpga/usrp2/simple_gemac/rxmac_to_ll8.v
new file mode 100644
index 000000000..5ec233d95
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/rxmac_to_ll8.v
@@ -0,0 +1,54 @@
+
+module rxmac_to_ll8
+  (input clk, input reset, input clear,
+   input [7:0] rx_data, input rx_valid, input rx_error, input rx_ack,
+   output [7:0] ll_data, output ll_sof, output ll_eof, output ll_error, output ll_src_rdy, input ll_dst_rdy );
+
+   reg [2:0] xfer_state;
+
+   localparam XFER_IDLE     = 0;
+   localparam XFER_ACTIVE   = 1;
+   localparam XFER_ERROR    = 2;
+   localparam XFER_ERROR2   = 3;
+   localparam XFER_OVERRUN  = 4;
+   localparam XFER_OVERRUN2 = 5;
+      
+   assign ll_data 	    = rx_data;
+   assign ll_src_rdy 	    = ((rx_valid & (xfer_state != XFER_OVERRUN2) )
+			       | (xfer_state == XFER_ERROR) 
+			       | (xfer_state == XFER_OVERRUN));
+   assign ll_sof 	    = ((xfer_state==XFER_IDLE)|(xfer_state==XFER_ERROR)|(xfer_state==XFER_OVERRUN));
+   assign ll_eof 	    = (rx_ack | (xfer_state==XFER_ERROR) | (xfer_state==XFER_OVERRUN));
+   assign ll_error 	    = (xfer_state == XFER_ERROR)|(xfer_state==XFER_OVERRUN);
+   
+   always @(posedge clk)
+     if(reset | clear)
+       xfer_state 	   <= XFER_IDLE;
+     else
+       case(xfer_state)
+	 XFER_IDLE :
+	   if(rx_valid)
+	     xfer_state <= XFER_ACTIVE;
+	 XFER_ACTIVE :
+	   if(rx_error)
+	     xfer_state <= XFER_ERROR;
+	   else if(~rx_valid)
+	     xfer_state <= XFER_IDLE;
+	   else if(~ll_dst_rdy)
+	     xfer_state <= XFER_OVERRUN;
+	 XFER_ERROR :
+	   if(ll_dst_rdy)
+	     xfer_state <= XFER_ERROR2;
+	 XFER_ERROR2 :
+	   if(~rx_error)
+	     xfer_state <= XFER_IDLE;
+	 XFER_OVERRUN :
+	   if(ll_dst_rdy)
+	     xfer_state <= XFER_OVERRUN2;
+	 XFER_OVERRUN2 :
+	   if(~rx_valid)
+	     xfer_state <= XFER_IDLE;
+       endcase // case (xfer_state)
+
+   
+endmodule // rxmac_to_ll8
diff --git a/fpga/usrp2/simple_gemac/simple_gemac.v b/fpga/usrp2/simple_gemac/simple_gemac.v
new file mode 100644
index 000000000..2dd8deb99
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac.v
@@ -0,0 +1,64 @@
+
+module simple_gemac
+  (input clk125, input reset,
+   // GMII
+   output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+   input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+
+   // Flow Control Interface
+   input pause_req, input [15:0] pause_time_req, input pause_respect_en,
+
+   // Settings
+   input [47:0] ucast_addr, input [47:0] mcast_addr,
+   input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
+   
+   // RX Client Interface
+   output rx_clk, output [7:0] rx_data, output rx_valid, output rx_error, output rx_ack,
+
+   // TX Client Interface
+   output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack,
+
+   output [31:0] debug
+   );
+
+   localparam SGE_IFG 		     = 8'd12;  // 12 should be the absolute minimum
+
+   wire rst_rxclk, rst_txclk;   
+   reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(rst_txclk));
+   reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rst_rxclk));
+
+   wire [15:0] pause_quanta_rcvd;
+   wire        pause_rcvd, pause_apply, paused;
+   
+   simple_gemac_tx simple_gemac_tx
+     (.clk125(clk125),.reset(rst_txclk),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .tx_clk(tx_clk), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .ifg(SGE_IFG), .mac_addr(ucast_addr),
+      .pause_req(pause_req), .pause_time(pause_time_req),  // We request flow control
+      .pause_apply(pause_apply), .paused(paused)  // We respect flow control
+      );
+
+   simple_gemac_rx simple_gemac_rx
+     (.reset(rst_rxclk),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), 
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .pause_quanta_rcvd(pause_quanta_rcvd), .pause_rcvd(pause_rcvd),
+      .debug(debug)
+      );
+
+   flow_ctrl_tx flow_ctrl_tx
+     (.rst(rst_txclk), .tx_clk(tx_clk),
+      .tx_pause_en(pause_respect_en),
+      .pause_quanta(pause_quanta_rcvd), // 16 bit value
+      .pause_quanta_val(pause_rcvd),
+      .pause_apply(pause_apply),
+      .paused(paused)
+      );
+
+endmodule // simple_gemac
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_rx.v b/fpga/usrp2/simple_gemac/simple_gemac_rx.v
new file mode 100644
index 000000000..b02bb0758
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_rx.v
@@ -0,0 +1,177 @@
+
+
+module simple_gemac_rx
+  (input reset,
+   input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+   output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
+   input [47:0] ucast_addr, input [47:0] mcast_addr, 
+   input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
+   output reg [15:0] pause_quanta_rcvd, output pause_rcvd,
+   output [31:0] debug );
+
+   localparam RX_IDLE 		  = 0;
+   localparam RX_PREAMBLE 	  = 1;
+   localparam RX_FRAME 		  = 2;
+   localparam RX_GOODFRAME 	  = 3;
+   localparam RX_DO_PAUSE 	  = 4;
+   localparam RX_ERROR 		  = 5;
+   localparam RX_DROP 		  = 6;
+
+   localparam RX_PAUSE 		  = 16;
+   localparam RX_PAUSE_CHK88 	  = RX_PAUSE + 5;
+   localparam RX_PAUSE_CHK08 	  = RX_PAUSE_CHK88 + 1;
+   localparam RX_PAUSE_CHK00 	  = RX_PAUSE_CHK08 + 1;
+   localparam RX_PAUSE_CHK01 	  = RX_PAUSE_CHK00 + 1;
+   localparam RX_PAUSE_STORE_MSB  = RX_PAUSE_CHK01 + 1;
+   localparam RX_PAUSE_STORE_LSB  = RX_PAUSE_STORE_MSB + 1;
+   localparam RX_PAUSE_WAIT_CRC   = RX_PAUSE_STORE_LSB + 1;
+   
+   reg [7:0] 	     rxd_d1;
+   reg rx_dv_d1, rx_er_d1;
+   assign rx_clk     = GMII_RX_CLK;
+   
+   always @(posedge rx_clk)
+     begin
+	rx_dv_d1    <= GMII_RX_DV;
+	rx_er_d1    <= GMII_RX_ER;
+	rxd_d1 	    <= GMII_RXD;
+     end
+
+   reg [7:0] rx_state;
+   wire [7:0] rxd_del;
+   wire rx_dv_del, rx_er_del;
+   reg go_filt;
+   
+   wire match_crc;
+   wire clear_crc 	 = rx_state == RX_IDLE;
+   wire calc_crc 	 = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
+
+   localparam DELAY  = 6;
+   delay_line #(.WIDTH(10)) rx_delay
+     (.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del}));
+
+   always @(posedge rx_clk)
+     if(reset)
+       rx_ack 	   <= 0;
+     else
+       rx_ack <= (rx_state == RX_GOODFRAME);
+
+   wire is_ucast, is_bcast, is_mcast, is_pause;
+   wire keep_packet  = (pass_ucast & is_ucast) | (pass_mcast & is_mcast) | 
+	(pass_bcast & is_bcast) | (pass_pause & is_pause) | pass_all;
+   
+   assign rx_data   = rxd_del;
+   assign rx_error  = (rx_state == RX_ERROR);
+
+   always @(posedge rx_clk)
+     if(reset)
+       rx_valid <= 0;
+     else if(keep_packet)
+       rx_valid <= 1;
+     else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR))
+       rx_valid <= 0;
+   
+   address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(ucast_addr), .match(is_ucast), .done());
+   address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(mcast_addr), .match(is_mcast), .done());
+   address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done());
+   address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
+			    .address(48'h0180_c200_0001), .match(is_pause), .done());
+
+   always @(posedge rx_clk)
+     go_filt 			 <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
+
+   reg [15:0] pkt_len_ctr;
+   always @(posedge rx_clk)
+     if(reset |(rx_state == RX_IDLE))
+       pkt_len_ctr 	<= 0;
+     else
+       pkt_len_ctr 	<= pkt_len_ctr + 1;
+
+   localparam MIN_PAUSE_LEN = 71;  // 6
+   wire pkt_long_enough  = (pkt_len_ctr >= MIN_PAUSE_LEN);
+   always @(posedge rx_clk)
+     if(reset)
+       rx_state 	<= RX_IDLE;
+     else
+       if(rx_er_d1) // | (~pkt_long_enough & ~rx_dv_d1) & (rx_state != RX_IDLE))
+	 rx_state 	<= RX_ERROR;
+       else
+	 case(rx_state)
+	   RX_IDLE :
+	     if(rx_dv_d1)
+	       if(rxd_d1 == 8'h55)
+		 rx_state   <= RX_PREAMBLE;
+	       else
+		 rx_state   <= RX_ERROR;
+	   RX_PREAMBLE :
+	     if(~rx_dv_d1)
+	       rx_state   <= RX_ERROR;
+	     else if(rxd_d1 == 8'hD5)
+	       rx_state   <= RX_FRAME;
+	     else if(rxd_d1 != 8'h55)
+	       rx_state   <= RX_ERROR;
+	   RX_FRAME :
+	     if(is_pause)
+	       rx_state <= RX_PAUSE;
+	     else if(~rx_dv_d1)
+	       if(match_crc)
+		 rx_state <= RX_GOODFRAME;
+	       else
+		 rx_state <= RX_ERROR;
+	   RX_PAUSE_CHK88 :
+	     if(rxd_d1 != 8'h88)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_CHK08;
+	   RX_PAUSE_CHK08 :
+	     if(rxd_d1 != 8'h08)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_CHK00;
+	   RX_PAUSE_CHK00 :
+	     if(rxd_d1 != 8'h00)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_CHK01;
+	   RX_PAUSE_CHK01 :
+	     if(rxd_d1 != 8'h01)
+	       rx_state <= RX_DROP;
+	     else
+	       rx_state <= RX_PAUSE_STORE_MSB;
+	   RX_PAUSE_WAIT_CRC :
+	     if(pkt_long_enough)
+	       if(match_crc)
+		 rx_state <= RX_DO_PAUSE;
+	       else
+		 rx_state <= RX_DROP;
+	   RX_DO_PAUSE :
+	     rx_state <= RX_IDLE;
+	   RX_GOODFRAME :
+	     rx_state <= RX_IDLE;
+	   RX_DROP, RX_ERROR :
+	     if(~rx_dv_d1)
+	       rx_state <= RX_IDLE;
+	   default
+	     rx_state <= rx_state + 1;
+	 endcase // case (rx_state)
+
+   assign pause_rcvd = (rx_state == RX_DO_PAUSE);
+   crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc),
+		 .data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc));
+
+   always @(posedge rx_clk)
+     if(reset)
+       pause_quanta_rcvd <= 0;
+     else if(rx_state == RX_PAUSE_STORE_MSB)
+       pause_quanta_rcvd[15:8] <= rxd_d1;
+     else if(rx_state == RX_PAUSE_STORE_LSB)
+       pause_quanta_rcvd[7:0] <= rxd_d1;
+   
+   assign rx_clk 	  = GMII_RX_CLK;
+
+   assign debug = rx_state;
+   
+endmodule // simple_gemac_rx
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_tb.v
new file mode 100644
index 000000000..6091751a7
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_tb.v
@@ -0,0 +1,200 @@
+
+
+module simple_gemac_tb;
+`include "eth_tasks.v"
+     
+   reg clk = 0;
+   reg reset = 1;
+
+   initial #1000 reset = 0;
+   always #50 clk = ~clk;
+
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+   wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6;
+   wire [47:0] mcast_addr = 0;
+   wire        pass_ucast  =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0;
+   
+   simple_gemac simple_gemac
+     (.clk125(clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .rx_clk(rx_clk), .rx_data(rx_data),
+      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .tx_clk(tx_clk), .tx_data(tx_data), 
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+      );
+
+   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
+   reg rx_ll_dst_rdy2 = 1;
+   wire [7:0] rx_ll_data, rx_ll_data2;
+   wire rx_ll_error, rx_ll_error2;
+   
+   rxmac_to_ll8 rx_adapt
+     (.clk(clk), .reset(reset), .clear(0),
+      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+   ll8_shortfifo rx_sfifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   reg tx_ll_sof2=0, tx_ll_eof2=0;
+   reg tx_ll_src_rdy2 = 0;
+   wire tx_ll_dst_rdy2;
+   wire [7:0] tx_ll_data;
+   reg [7:0] tx_ll_data2 = 0;
+   wire tx_ll_error;
+   wire tx_ll_error2 = 0;
+
+   ll8_shortfifo tx_sfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+   
+   ll8_to_txmac ll8_to_txmac
+     (.clk(clk), .reset(reset), .clear(clear),
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+
+   initial $dumpfile("simple_gemac_tb.vcd");
+   initial $dumpvars(0,simple_gemac_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge clk);
+	#30000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0009);  // Increas flow control before it expires
+	#10000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge clk); 
+
+	SendPacket_to_ll8(8'hAA,10);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_ll8(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_ll8(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_ll8(100,0,30);
+	#10000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge clk);
+	FORCE_ERR <= 1;
+	@(posedge clk);
+	FORCE_ERR <= 0;
+     end
+
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+   
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames
+   
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   
+endmodule // simple_gemac_tb
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_tx.v b/fpga/usrp2/simple_gemac/simple_gemac_tx.v
new file mode 100644
index 000000000..dd870d04d
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_tx.v
@@ -0,0 +1,254 @@
+
+module simple_gemac_tx
+  (input clk125, input reset,
+   output GMII_GTX_CLK, output reg GMII_TX_EN, output reg GMII_TX_ER, output reg [7:0] GMII_TXD,
+   output tx_clk, input [7:0] tx_data, input tx_valid, input tx_error, output tx_ack,
+   input [7:0] ifg, input [47:0] mac_addr,
+   input pause_req, input [15:0] pause_time,
+   input pause_apply, output reg paused
+   );
+
+   reg tx_en_pre, tx_er_pre;
+   reg [7:0] txd_pre;
+   
+   assign GMII_GTX_CLK 	= clk125;
+   assign tx_clk 	= clk125;
+   
+   reg [7:0] tx_state;
+   reg [7:0] ifg_ctr;
+   reg [15:0] frame_len_ctr;
+   reg [7:0] pause_ctr, pause_dat;
+
+   wire in_ifg 		     = (ifg_ctr != 0);
+
+   wire [31:0] crc_out;
+   
+   localparam TX_IDLE 	     = 0;
+   localparam TX_PREAMBLE    = 1;
+   localparam TX_SOF_DEL     = TX_PREAMBLE + 7;
+   localparam TX_FIRSTBYTE   = TX_SOF_DEL + 1;
+   localparam TX_IN_FRAME    = TX_FIRSTBYTE + 1;
+   localparam TX_IN_FRAME_2  = TX_IN_FRAME + 1;
+   localparam TX_PAD 	     = TX_IN_FRAME_2 + 1;
+   localparam TX_CRC_0 	     = 16;
+   localparam TX_CRC_1 	     = TX_CRC_0 + 1;
+   localparam TX_CRC_2 	     = TX_CRC_0 + 2;
+   localparam TX_CRC_3 	     = TX_CRC_0 + 3;
+   localparam TX_ERROR 	     = 32;
+   localparam TX_PAUSE 	     = 55;
+   localparam TX_PAUSE_SOF   = TX_PAUSE + 7;
+   localparam TX_PAUSE_FIRST = TX_PAUSE_SOF + 1;
+   localparam TX_PAUSE_END   = TX_PAUSE_SOF + 18;
+
+   localparam MIN_FRAME_LEN  = 64 + 8 - 4; // Min frame length includes preamble but not CRC
+   localparam MAX_FRAME_LEN  = 8192;       // How big are the jumbo frames we want to handle?
+   always @(posedge tx_clk)
+     if(reset |(tx_state == TX_IDLE))
+       frame_len_ctr 	    <= 0;
+     else
+       frame_len_ctr 	    <= frame_len_ctr + 1;
+   
+   reg send_pause;
+   reg [15:0] pause_time_held;
+
+   always @(posedge tx_clk)
+     if(reset)
+       send_pause      <= 0;
+     else if(pause_req)
+       send_pause      <= 1;
+     else if(tx_state == TX_PAUSE)
+       send_pause      <= 0;
+
+   always @(posedge tx_clk)
+     if(pause_req)
+       pause_time_held <= pause_time;
+   
+   always @(posedge tx_clk)
+     if(reset)
+       tx_state        <= TX_IDLE;
+     else 
+       case(tx_state)
+	 TX_IDLE :
+	   if(~in_ifg)
+	     if(send_pause)
+	       tx_state <= TX_PAUSE;
+	     else if(tx_valid & ~pause_apply)
+	       tx_state <= TX_PREAMBLE;
+	 TX_FIRSTBYTE :
+	   if(tx_error)
+	     tx_state <= TX_ERROR;   // underrun
+	   else if(~tx_valid)
+	     tx_state <= TX_PAD;
+	   else
+	     tx_state <= TX_IN_FRAME;
+	 TX_IN_FRAME :
+	   if(tx_error)
+	     tx_state <= TX_ERROR;   // underrun
+	   else if(~tx_valid)
+	     tx_state <= TX_PAD;
+	   else if(frame_len_ctr == MIN_FRAME_LEN - 1)
+	     tx_state <= TX_IN_FRAME_2;
+	 TX_IN_FRAME_2 :
+	   if(tx_error)
+	     tx_state <= TX_ERROR;   // underrun
+	   else if(~tx_valid)
+	     tx_state <= TX_CRC_0;
+	 TX_PAD :
+	   if(frame_len_ctr == MIN_FRAME_LEN)
+	     tx_state <= TX_CRC_0;
+	 TX_CRC_3 :
+	   tx_state <= TX_IDLE;
+	 TX_ERROR :
+	   tx_state <= TX_IDLE;
+	 TX_PAUSE_END :
+	   tx_state <= TX_PAD;
+	 default :
+	   tx_state <= tx_state + 1;
+       endcase // case (tx_state)
+
+   always @(posedge tx_clk)
+     if(reset)
+       begin
+	  tx_en_pre <= 0;
+	  tx_er_pre <= 0;
+	  txd_pre   <= 0;
+       end
+     else
+       casex(tx_state)
+	 TX_IDLE :
+	   begin
+	      tx_en_pre <= 0;
+	      tx_er_pre <= 0;
+	      txd_pre <= 0;
+	   end
+	 TX_PREAMBLE, TX_PAUSE :
+	   begin
+	      txd_pre 	 <= 8'h55;
+	      tx_en_pre <= 1;
+	   end
+	 TX_SOF_DEL, TX_PAUSE_SOF :
+	   txd_pre <= 8'hD5;
+	 TX_FIRSTBYTE, TX_IN_FRAME, TX_IN_FRAME_2 :
+	   txd_pre <= tx_valid ? tx_data : 0;
+	 TX_ERROR :
+	   begin
+	      tx_er_pre <= 1;
+	      txd_pre 	 <= 0;
+	   end
+	 TX_CRC_3 :
+	   tx_en_pre <= 0;
+	 TX_PAD :
+	   txd_pre <= 0;
+	 TX_PAUSE_FIRST, 8'b01xx_xxxx :  // In Pause Frame
+	   txd_pre <= pause_dat;
+       endcase // case (tx_state)
+
+   localparam SGE_FLOW_CTRL_ADDR  = 48'h01_80_C2_00_00_01;
+   always @(posedge tx_clk)
+     case(tx_state)
+       TX_PAUSE_SOF :
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[47:40];  // Note everything must be 1 cycle early
+       TX_PAUSE_SOF + 1:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[39:32];
+       TX_PAUSE_SOF + 2:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[31:24];
+       TX_PAUSE_SOF + 3:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[23:16];
+       TX_PAUSE_SOF + 4:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[15:8];
+       TX_PAUSE_SOF + 5:
+	 pause_dat    <= SGE_FLOW_CTRL_ADDR[7:0];
+       TX_PAUSE_SOF + 6:
+	 pause_dat    <= mac_addr[47:40];
+       TX_PAUSE_SOF + 7:
+	 pause_dat    <= mac_addr[39:32];
+       TX_PAUSE_SOF + 8:
+	 pause_dat    <= mac_addr[31:24];
+       TX_PAUSE_SOF + 9:
+	 pause_dat    <= mac_addr[23:16];
+       TX_PAUSE_SOF + 10:
+	 pause_dat    <= mac_addr[15:8];
+       TX_PAUSE_SOF + 11:
+	 pause_dat <= mac_addr[7:0];
+       TX_PAUSE_SOF + 12:
+	 pause_dat <= 8'h88;   // Type = 8808 = MAC ctrl frame
+       TX_PAUSE_SOF + 13:
+	 pause_dat <= 8'h08;
+       TX_PAUSE_SOF + 14:
+	 pause_dat <= 8'h00;   // Opcode = 0001 = PAUSE
+       TX_PAUSE_SOF + 15:
+	 pause_dat <= 8'h01;
+       TX_PAUSE_SOF + 16:
+	 pause_dat <= pause_time_held[15:8];
+       TX_PAUSE_SOF + 17:
+	 pause_dat <= pause_time_held[7:0];
+     endcase // case (tx_state)
+   
+   wire start_ifg   = (tx_state == TX_CRC_3);
+   always @(posedge tx_clk)
+     if(reset)
+       ifg_ctr 	   <= 100;
+     else if(start_ifg)
+       ifg_ctr 	   <= ifg;
+     else if(ifg_ctr != 0)
+       ifg_ctr 	   <= ifg_ctr - 1;
+
+   wire clear_crc   = (tx_state == TX_IDLE);
+
+   wire calc_crc    = 
+	(tx_state==TX_IN_FRAME) |
+	(tx_state==TX_IN_FRAME_2) |
+	(tx_state==TX_PAD) |
+	(tx_state[6]);
+
+   crc crc(.clk(tx_clk), .reset(reset), .clear(clear_crc),
+	    .data(txd_pre), .calc(calc_crc), .crc_out(crc_out));
+
+   assign tx_ack    = (tx_state == TX_FIRSTBYTE);
+
+   always @(posedge tx_clk) 
+     begin
+	GMII_TX_EN <= tx_en_pre;
+	GMII_TX_ER <= tx_er_pre;
+	case(tx_state)
+	  TX_CRC_0 :
+	    GMII_TXD <= crc_out[31:24];
+	  TX_CRC_1 :
+	    GMII_TXD <= crc_out[23:16];
+	  TX_CRC_2 :
+	    GMII_TXD <= crc_out[15:8];
+	  TX_CRC_3 :
+	    GMII_TXD <= crc_out[7:0];
+	  default :
+	    GMII_TXD <= txd_pre;
+	endcase // case (tx_state)
+     end
+
+   // report that we are paused only when we get back to IDLE
+   always @(posedge tx_clk)
+     if(reset)
+       paused 	     <= 0;
+     else if(~pause_apply)
+       paused 	     <= 0;
+     else if(tx_state == TX_IDLE)
+       paused 	     <= 1;
+   
+endmodule // simple_gemac_tx
+
+// Testing code
+/*
+    reg [7:0] crc_ctr;
+   reg calc_crc_d1;
+   always @(posedge tx_clk) 
+     calc_crc_d1 <= calc_crc;
+   
+   always @(posedge tx_clk)
+     if(reset)
+       crc_ctr 	 <= 0;
+     else if(calc_crc)
+       crc_ctr 	 <= crc_ctr+1;
+     else if(calc_crc_d1)
+       $display("CRC COUNT = %d",crc_ctr);
+     else
+       crc_ctr <= 0;
+*/
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wb.v b/fpga/usrp2/simple_gemac/simple_gemac_wb.v
new file mode 100644
index 000000000..6df277e3e
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wb.v
@@ -0,0 +1,161 @@
+
+module wb_reg
+  #(parameter ADDR=0,
+    parameter DEFAULT=0)
+   (input clk, input rst, 
+    input [5:0] adr, input wr_acc,
+    input [31:0] dat_i, output reg [31:0] dat_o);
+
+   always @(posedge clk)
+     if(rst)
+       dat_o <= DEFAULT;
+     else if(wr_acc & (adr == ADDR))
+       dat_o <= dat_i;
+   
+endmodule // wb_reg
+
+   
+
+module simple_gemac_wb
+  (input wb_clk, input wb_rst,
+   input wb_cyc, input wb_stb, output reg wb_ack, input wb_we,
+   input [7:0] wb_adr, input [31:0] wb_dat_i, output reg [31:0] wb_dat_o,
+   
+   inout mdio, output mdc,
+   output [47:0] ucast_addr, output [47:0] mcast_addr,
+   output pass_ucast, output pass_mcast, output pass_bcast,
+   output pass_pause, output pass_all, 
+   output pause_respect_en, output pause_request_en, 
+   output [15:0] pause_time, output [15:0] pause_thresh  );
+
+   wire   acc 	  = wb_cyc & wb_stb;
+   wire   wr_acc  = wb_cyc & wb_stb & wb_we;
+   wire   rd_acc  = wb_cyc & wb_stb & ~wb_we;
+
+   always @(posedge wb_clk)
+     if(wb_rst)
+       wb_ack 	 <= 0;
+     else
+       wb_ack 	 <= acc & ~wb_ack;
+       
+   wire [6:0] misc_settings;
+   assign {pause_request_en, pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_respect_en} = misc_settings;
+
+   wb_reg #(.ADDR(0),.DEFAULT(7'b0111001))
+   wb_reg_settings (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		    .dat_i(wb_dat_i), .dat_o(misc_settings) );
+   wb_reg #(.ADDR(1),.DEFAULT(0))
+   wb_reg_ucast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		   .dat_i(wb_dat_i), .dat_o(ucast_addr[47:32]) );
+   wb_reg #(.ADDR(2),.DEFAULT(0))
+   wb_reg_ucast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		   .dat_i(wb_dat_i), .dat_o(ucast_addr[31:0]) );
+   wb_reg #(.ADDR(3),.DEFAULT(0))
+   wb_reg_mcast_h (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		   .dat_i(wb_dat_i), .dat_o(mcast_addr[47:32]) );
+   wb_reg #(.ADDR(4),.DEFAULT(0))
+   wb_reg_mcast_l (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		   .dat_i(wb_dat_i), .dat_o(mcast_addr[31:0]) );
+
+   //MII to CPU 
+   wire [7:0] Divider;            // Divider for the host clock
+   wire [15:0] CtrlData;          // Control Data (to be written to the PHY reg.)
+   wire [4:0]  Rgad;               // Register Address (within the PHY)
+   wire [4:0]  Fiad;               // PHY Address
+   wire        NoPre;              // No Preamble (no 32-bit preamble)
+   wire        WCtrlData;          // Write Control Data operation
+   wire        RStat;              // Read Status operation
+   wire        ScanStat;           // Scan Status operation
+   wire        Busy;               // Busy Signal
+   wire        LinkFail;           // Link Integrity Signal
+   wire        Nvalid;             // Invalid Status (qualifier for the valid scan result)
+   wire [15:0] Prsd;               // Read Status Data (data read from the PHY)
+   wire        WCtrlDataStart;     // This signals resets the WCTRLDATA bit in the MIIM Command register
+   wire        RStatStart;         // This signal resets the RSTAT BIT in the MIIM Command register
+   wire        UpdateMIIRX_DATAReg; // Updates MII RX_DATA register with read data
+   
+   // registers for controlling the MII interface
+   reg [2:0]   MIICOMMAND;
+   wire [12:0] MIIADDRESS;
+   reg [15:0]  MIIRX_DATA;
+   wire [2:0]  MIISTATUS;
+
+   wb_reg #(.ADDR(5),.DEFAULT(0))
+   wb_reg_miimoder (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		    .dat_i(wb_dat_i), .dat_o({NoPre,Divider}) );
+   
+   wb_reg #(.ADDR(6),.DEFAULT(0))
+   wb_reg_miiaddr (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		   .dat_i(wb_dat_i), .dat_o(MIIADDRESS) );
+   
+   wb_reg #(.ADDR(7),.DEFAULT(0))
+   wb_reg_miidata (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		   .dat_i(wb_dat_i), .dat_o(CtrlData) );
+   
+   // MIICOMMAND register - needs special treatment because of auto-resetting bits
+   always @ (posedge wb_clk)
+     if (wb_rst)
+       MIICOMMAND <= 0;
+     else
+       if (wr_acc & (wb_adr[7:2] == 6'd8))
+         MIICOMMAND <= wb_dat_i;
+       else
+         begin
+            if ( WCtrlDataStart )
+              MIICOMMAND[2] <= 0;
+            if ( RStatStart )
+              MIICOMMAND[1] <= 0;
+         end
+   
+   // MIIRX_DATA register
+   always @(posedge wb_clk)
+     if (wb_rst)
+       MIIRX_DATA <= 0;
+     else
+       if (UpdateMIIRX_DATAReg )
+         MIIRX_DATA <= Prsd;
+
+   // MIICOMMAND
+   assign WCtrlData  = MIICOMMAND[2];
+   assign RStat      = MIICOMMAND[1];
+   assign ScanStat   = MIICOMMAND[0];
+   // MIIADDRESS
+   assign Rgad 	     = MIIADDRESS[12:8];
+   assign Fiad 	     = MIIADDRESS[4:0];
+   // MIISTATUS
+   assign MIISTATUS[2:0] = { Nvalid, Busy, LinkFail };
+   
+   eth_miim eth_miim
+     (.Clk(wb_clk), .Reset(wb_rst), 
+      .Divider(Divider), .NoPre(NoPre), .CtrlData(CtrlData), .Rgad(Rgad), .Fiad(Fiad), 
+      .WCtrlData(WCtrlData), .RStat(RStat), .ScanStat(ScanStat), .Mdio(mdio), .Mdc(mdc), 
+      .Busy(Busy), .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(Nvalid), 
+      .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), 
+      .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg) );
+
+   wb_reg #(.ADDR(11),.DEFAULT(0))
+   wb_reg_pausetime (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		     .dat_i(wb_dat_i), .dat_o(pause_time) );
+   
+   wb_reg #(.ADDR(12),.DEFAULT(0))
+   wb_reg_pausethresh (.clk(wb_clk), .rst(wb_rst), .adr(wb_adr[7:2]), .wr_acc(wr_acc),
+		       .dat_i(wb_dat_i), .dat_o(pause_thresh) );
+   
+   always @(posedge wb_clk)
+     case(wb_adr[7:2])
+       0 : wb_dat_o <= misc_settings;
+       1 : wb_dat_o <= ucast_addr[47:32];
+       2 : wb_dat_o <= ucast_addr[31:0];
+       3 : wb_dat_o <= mcast_addr[47:32];
+       4 : wb_dat_o <= mcast_addr[31:0];
+       5 : wb_dat_o <= {NoPre,Divider};
+       6 : wb_dat_o <= MIIADDRESS;
+       7 : wb_dat_o <= CtrlData;
+       8 : wb_dat_o <= MIICOMMAND;
+       9 : wb_dat_o <= MIISTATUS;
+       10: wb_dat_o <= MIIRX_DATA;
+       11: wb_dat_o <= pause_time;
+       12: wb_dat_o <= pause_thresh;
+     endcase // case (wb_adr[7:2])
+   
+endmodule // simple_gemac_wb
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
new file mode 100755
index 000000000..30f65ab17
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper_tb simple_gemac_wrapper_tb.v
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
new file mode 100644
index 000000000..efcf89276
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
@@ -0,0 +1,165 @@
+
+module simple_gemac_wrapper
+  #(parameter RXFIFOSIZE=9,
+    parameter TXFIFOSIZE=6)
+   (input clk125, input reset,
+    // GMII
+    output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+    input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+    
+    // Client FIFO Interfaces
+    input sys_clk,
+    output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
+    input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy,
+    
+    // Wishbone Interface
+    input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
+    input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
+    
+    // MIIM
+    inout mdio, output mdc,
+    output [31:0] debug);
+
+   wire 	  clear = 0;
+   wire [7:0] 	  rx_data, tx_data;
+   wire 	  tx_clk, tx_valid, tx_error, tx_ack;
+   wire 	  rx_clk, rx_valid, rx_error, rx_ack;
+   
+   wire [47:0] 	  ucast_addr, mcast_addr;
+   wire 	  pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
+   wire 	  pause_req;
+   wire 	  pause_request_en, pause_respect_en;
+   wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
+   
+   wire 	  tx_reset, rx_reset;
+   reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
+   reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
+   
+   simple_gemac simple_gemac
+     (.clk125(clk125),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time_req(pause_time_req), 
+      .pause_respect_en(pause_respect_en),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .rx_clk(rx_clk), .rx_data(rx_data),
+      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .tx_clk(tx_clk), .tx_data(tx_data), 
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+      );
+   
+   simple_gemac_wb simple_gemac_wb
+     (.wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+      .mdio(mdio), .mdc(mdc),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all), 
+      .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
+      .pause_time(pause_time), .pause_thresh(pause_thresh) );
+
+   // RX FIFO Chain
+   wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   
+   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
+   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
+   
+   wire [7:0] 	  rx_ll_data, rx_ll_data2;
+   
+   wire [35:0] 	  rx_f36_data_int1;
+   wire 	  rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+   
+   rxmac_to_ll8 rx_adapt
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+   ll8_shortfifo rx_sfifo
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
+   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
+   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
+   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
+   
+   ll8_to_fifo36 ll8_to_fifo36
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
+      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
+
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+     (.wclk(rx_clk), .datain(rx_f36_data_int1), 
+      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
+      .rclk(sys_clk), .dataout(rx_f36_data), 
+      .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
+   
+   // TX FIFO Chain
+   wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
+   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
+   wire [7:0] 	  tx_ll_data, tx_ll_data2;
+   wire [35:0] 	  tx_f36_data_int1;
+   wire 	  tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
+   
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
+     (.wclk(sys_clk), .datain(tx_f36_data), 
+      .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
+      .rclk(tx_clk), .dataout(tx_f36_data_int1), 
+      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
+   
+   fifo36_to_ll8 fifo36_to_ll8
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
+      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
+      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+
+   assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
+   assign tx_ll_eof2 	    = ~tx_ll_eof2_n;
+   assign tx_ll_src_rdy2    = ~tx_ll_src_rdy2_n;
+   assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
+   
+   ll8_shortfifo tx_sfifo
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+   
+   ll8_to_txmac ll8_to_txmac
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+
+   flow_ctrl_rx flow_ctrl_rx
+     (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
+      .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
+      .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
+   
+   wire [31:0] 	  debug_tx, debug_rx;
+   
+   assign debug_tx  = { { tx_ll_data },
+			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
+			  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
+			{ tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
+			{ tx_data} };
+   assign debug_rx  = { { rx_ll_data },
+			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
+			  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
+			{ rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
+			{ rx_data} };
+
+   assign debug  = debug_rx;
+   
+endmodule // simple_gemac_wrapper
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
new file mode 100755
index 000000000..4be0aac1f
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../control_lib/newfifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
new file mode 100644
index 000000000..6cdbd1a59
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
@@ -0,0 +1,170 @@
+
+module simple_gemac_wrapper19
+  #(parameter RXFIFOSIZE=9,
+    parameter TXFIFOSIZE=6)
+   (input clk125, input reset,
+    // GMII
+    output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+    input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+    
+    // Client FIFO Interfaces
+    input sys_clk,
+    output [18:0] rx_f19_data, output rx_f19_src_rdy, input rx_f19_dst_rdy,
+    input [18:0] tx_f19_data, input tx_f19_src_rdy, output tx_f19_dst_rdy,
+    
+    // Wishbone Interface
+    input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
+    input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
+    
+    // MIIM
+    inout mdio, output mdc,
+    output [31:0] debug);
+
+   wire 	  clear = 0;
+   wire [7:0] 	  rx_data, tx_data;
+   wire 	  tx_clk, tx_valid, tx_error, tx_ack;
+   wire 	  rx_clk, rx_valid, rx_error, rx_ack;
+   
+   wire [47:0] 	  ucast_addr, mcast_addr;
+   wire 	  pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
+   wire 	  pause_req;
+   wire 	  pause_request_en, pause_respect_en;
+   wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
+
+   wire [31:0] 	  debug_state;
+      
+   wire 	  tx_reset, rx_reset;
+   reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
+   reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
+   
+   simple_gemac simple_gemac
+     (.clk125(clk125),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time_req(pause_time_req), 
+      .pause_respect_en(pause_respect_en),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all),
+      .rx_clk(rx_clk), .rx_data(rx_data),
+      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .tx_clk(tx_clk), .tx_data(tx_data), 
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .debug(debug_state)
+      );
+   
+   simple_gemac_wb simple_gemac_wb
+     (.wb_clk(wb_clk), .wb_rst(wb_rst),
+      .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+      .mdio(mdio), .mdc(mdc),
+      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
+      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
+      .pass_pause(pass_pause), .pass_all(pass_all), 
+      .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
+      .pause_time(pause_time), .pause_thresh(pause_thresh) );
+
+   // RX FIFO Chain
+   wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   
+   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
+   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
+   
+   wire [7:0] 	  rx_ll_data, rx_ll_data2;
+   
+   wire [18:0] 	  rx_f19_data_int1;
+   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1;
+   
+   rxmac_to_ll8 rx_adapt
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
+
+   ll8_shortfifo rx_sfifo
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
+   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
+   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
+   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
+   
+   ll8_to_fifo19 ll8_to_fifo19
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
+      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
+
+   //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
+     (.wclk(rx_clk), .datain(rx_f19_data_int1), 
+      .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .space(rx_fifo_space),
+      .rclk(sys_clk), .dataout(rx_f19_data), 
+      .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), .arst(reset));
+   
+   // TX FIFO Chain
+   wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
+   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
+   wire [7:0] 	  tx_ll_data, tx_ll_data2;
+   wire [18:0] 	  tx_f19_data_int1;
+   wire 	  tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1;
+
+   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) tx_2clk_fifo
+     (.wclk(sys_clk), .datain(tx_f19_data), 
+      .src_rdy_i(tx_f19_src_rdy), .dst_rdy_o(tx_f19_dst_rdy), .space(),
+      .rclk(tx_clk), .dataout(tx_f19_data_int1), 
+      .src_rdy_o(tx_f19_src_rdy_int1), .dst_rdy_i(tx_f19_dst_rdy_int1), .occupied(), .arst(rx_reset));
+   
+   fifo19_to_ll8 fifo19_to_ll8
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .f19_data(tx_f19_data_int1), .f19_src_rdy_i(tx_f19_src_rdy_int1), .f19_dst_rdy_o(tx_f19_dst_rdy_int1),
+      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
+      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+
+   assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
+   assign tx_ll_eof2 	    = ~tx_ll_eof2_n;
+   assign tx_ll_src_rdy2    = ~tx_ll_src_rdy2_n;
+   assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
+   
+   ll8_shortfifo tx_sfifo
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
+      .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+   
+   ll8_to_txmac ll8_to_txmac
+     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
+      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
+
+   // Flow Control
+   flow_ctrl_rx flow_ctrl_rx
+     (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
+      .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
+      .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
+   
+   wire [31:0] 	  debug_tx, debug_rx;
+
+   assign debug_tx  = { { tx_ll_data },
+			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
+			  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
+			{ tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]},
+			{ tx_data} };
+   assign debug_rx  = { { rx_f19_src_rdy, rx_f19_dst_rdy, debug_state[5:0] },
+			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
+			  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
+			{ rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]},
+			{ rx_data} };
+
+   assign debug  = debug_rx;
+   
+endmodule // simple_gemac_wrapper19
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
new file mode 100644
index 000000000..7d57542dc
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
@@ -0,0 +1,209 @@
+
+
+module simple_gemac_wrapper19_tb;
+`include "eth_tasks_f19.v"
+     
+   reg reset   = 1;
+   initial #1000 reset = 0;
+   wire wb_rst 	= reset;
+
+   reg eth_clk     = 0;
+   always #50 eth_clk = ~eth_clk;
+
+   reg wb_clk 	= 0;
+   always #173 wb_clk = ~wb_clk;
+
+   reg sys_clk 	= 0;
+   always #77 sys_clk = ~ sys_clk;
+   
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+   wire [31:0] wb_dat_o;
+   reg [31:0]  wb_dat_i;
+   reg [7:0]   wb_adr;
+   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
+   wire        wb_ack;
+
+   reg [18:0]  tx_f19_data=0;
+   reg 	       tx_f19_src_rdy = 0;
+   wire        tx_f19_dst_rdy;
+   wire [35:0] rx_f36_data;
+   wire        rx_f36_src_rdy;
+   wire        rx_f36_dst_rdy = 1;
+   
+   simple_gemac_wrapper19 simple_gemac_wrapper19
+     (.clk125(eth_clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      //.pause_req(pause_req), .pause_time(pause_time),
+
+      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+
+      .mdio(), .mdc(),
+      .debug() );
+   
+   initial $dumpfile("simple_gemac_wrapper19_tb.vcd");
+   initial $dumpvars(0,simple_gemac_wrapper19_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge wb_clk);
+	WishboneWR(0,6'b111101); 
+	WishboneWR(4,16'hA0B0);
+	WishboneWR(8,32'hC0D0_A1B1);
+	WishboneWR(12,16'h0000);
+	WishboneWR(16,32'h0000_0000);
+	
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge eth_clk);
+	#30000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
+	#10000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge eth_clk); 
+
+	repeat (1000)
+	  @(posedge sys_clk);
+	SendPacket_to_fifo19(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
+	repeat (1000)
+	  @(posedge sys_clk);
+
+	SendPacket_to_fifo19(32'hAABBCCDD,100);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge sys_clk);
+/*
+ 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_f36(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,30);
+ */
+	#100000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge eth_clk);
+	FORCE_ERR <= 1;
+	@(posedge eth_clk);
+	FORCE_ERR <= 0;
+     end
+/*
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+  */
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+   task WishboneWR;
+      input [7:0] adr;
+      input [31:0] value;
+      begin
+	 wb_adr   <= adr;
+	 wb_dat_i <= value;
+	 wb_stb   <= 1;
+	 wb_cyc   <= 1;
+	 wb_we 	  <= 1;
+	 while (~wb_ack)
+	   @(posedge wb_clk);
+	 @(posedge wb_clk);
+	 wb_stb <= 0;
+	 wb_cyc <= 0;
+	 wb_we 	<= 0;
+      end
+   endtask // WishboneWR
+   /*
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   */
+endmodule // simple_gemac_wrapper19_tb
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v
new file mode 100644
index 000000000..804fa8748
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v
@@ -0,0 +1,243 @@
+
+
+module simple_gemac_wrapper_f36_tb;
+`include "eth_tasks_f36.v"
+     
+   reg clk     = 0;
+   reg reset   = 1;
+
+   initial #1000 reset = 0;
+   always #50 clk = ~clk;
+
+   reg wb_clk 	= 0;
+   wire wb_rst 	= reset;
+   always #173 wb_clk = ~wb_clk;
+       
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
+   wire 	rx_ll_dst_rdy2;
+   wire [7:0] rx_ll_data, rx_ll_data2;
+   wire rx_ll_error, rx_ll_error2;
+
+   wire [31:0] wb_dat_o;
+   reg [31:0]  wb_dat_i;
+   reg [7:0]   wb_adr;
+   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
+   wire        wb_ack;
+
+   reg [35:0]  tx_f36_dat;
+   reg 	       tx_f36_src_rdy;
+   wire        tx_f36_dst_rdy;
+
+   wire [35:0] rx_f36_dat;
+   wire        rx_f36_src_rdy;
+   reg 	       rx_f36_dst_rdy  = 1;
+   
+   simple_gemac_wrapper simple_gemac_wrapper
+     (.clk125(clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time(pause_time),
+      .rx_clk(rx_clk), .rx_ll_data(rx_ll_data), .rx_ll_sof(rx_ll_sof),
+      .rx_ll_eof(rx_ll_eof), .rx_ll_src_rdy(rx_ll_src_rdy), .rx_ll_dst_rdy(rx_ll_dst_rdy),
+      .tx_clk(tx_clk), .tx_ll_data(tx_ll_data), .tx_ll_sof(tx_ll_sof),
+      .tx_ll_eof(tx_ll_eof), .tx_ll_src_rdy(tx_ll_src_rdy), .tx_ll_dst_rdy(tx_ll_dst_rdy),
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack),
+      .wb_we(wb_we), .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+      .mdio(mdio), .mdc(mdc) );
+
+   wire        rx_ll_dst_rdy2_n;
+   assign        rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
+      
+   ll8_shortfifo rx_sfifo
+     (.clk(clk), .reset(reset), .clear(0),
+      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
+      .error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
+      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
+      .error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+
+   ll8_to_fifo36 ll8_to_fifo36
+     (.clk(clk), .reset(reset), .clear(0),
+      .ll_data(rx_ll_data2), .ll_sof_n(~rx_ll_sof2), .ll_eof_n(~rx_ll_eof2),
+      .ll_src_rdy_n(~rx_ll_src_rdy2), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .f36_data(rx_f36_dat), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy));
+   
+   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   wire tx_ll_sof2_n, tx_ll_eof2_n;
+   wire tx_ll_src_rdy2_n, tx_ll_dst_rdy2;
+   wire [7:0] tx_ll_data, tx_ll_data2;
+   wire tx_ll_error;
+   wire tx_ll_error2 = 0;
+
+   fifo36_to_ll8 fifo36_to_ll8
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_data(tx_f36_dat), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
+      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
+      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(~tx_ll_dst_rdy2));
+   
+   ll8_shortfifo tx_sfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_ll_data2), .sof_i(~tx_ll_sof2_n), .eof_i(~tx_ll_eof2_n),
+      .error_i(tx_ll_error2), .src_rdy_i(~tx_ll_src_rdy2_n), .dst_rdy_o(tx_ll_dst_rdy2),
+      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
+      .error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
+   
+   initial $dumpfile("simple_gemac_wrapper_f36_tb.vcd");
+   initial $dumpvars(0,simple_gemac_wrapper_f36_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge clk);
+	WishboneWR(0,6'b111001);
+	WishboneWR(4,16'hF1F2);
+	WishboneWR(8,32'hF3F4_F5F6);
+	WishboneWR(12,16'h0000);
+	WishboneWR(16,32'h0000_0000);
+	
+	@(posedge clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge clk);
+	#30000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
+	#10000;
+	@(posedge clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge clk); 
+
+	SendPacket_to_fifo36(8'hAA,10);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_fifo36(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_fifo36(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_fifo36(100,0,30);
+	#10000 $finish;
+     end
+/*
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge clk);
+	FORCE_ERR <= 1;
+	@(posedge clk);
+	FORCE_ERR <= 0;
+     end
+
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_f36_dst_rdy <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_f36_dst_rdy <= 1;
+     end
+  */ 
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+   task WishboneWR;
+      input [7:0] adr;
+      input [31:0] value;
+      begin
+	 wb_adr   <= adr;
+	 wb_dat_i <= value;
+	 wb_stb   <= 1;
+	 wb_cyc   <= 1;
+	 wb_we 	  <= 1;
+	 while (~wb_ack)
+	   @(posedge wb_clk);
+	 @(posedge wb_clk);
+	 wb_stb <= 0;
+	 wb_cyc <= 0;
+	 wb_we 	<= 0;
+      end
+   endtask // WishboneWR
+   
+   always @(posedge clk)
+     if(rx_f36_src_rdy & rx_f36_dst_rdy)
+       begin
+	  if(rx_f36_dat[32] & ~rx_f36_dat[33])
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR %d OCC %d DAT %x",rx_f36_dat[32],rx_f36_dat[33],
+		   &rx_f36_dat[33:32],rx_f36_dat[35:34],rx_f36_dat[31:0]);
+	  if(rx_f36_dat[33] & ~rx_f36_dat[32])
+	    $display("RX-PKT-END %d",$time);
+	  if(rx_f36_dat[33] & rx_f36_dat[32])
+	    $display("RX-PKT-ERROR %d",$time);
+       end
+   
+endmodule // simple_gemac_wrapper_tb
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
new file mode 100644
index 000000000..26a471a49
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v
@@ -0,0 +1,209 @@
+
+
+module simple_gemac_wrapper_tb;
+`include "eth_tasks_f36.v"
+     
+   reg reset   = 1;
+   initial #1000 reset = 0;
+   wire wb_rst 	= reset;
+
+   reg eth_clk     = 0;
+   always #50 eth_clk = ~eth_clk;
+
+   reg wb_clk 	= 0;
+   always #173 wb_clk = ~wb_clk;
+
+   reg sys_clk 	= 0;
+   always #77 sys_clk = ~ sys_clk;
+   
+   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
+   wire [7:0] GMII_RXD, GMII_TXD;
+
+   wire rx_valid, rx_error, rx_ack;
+   wire tx_ack, tx_valid, tx_error;
+   
+   wire [7:0] rx_data, tx_data;
+   
+   reg [15:0] pause_time;
+   reg pause_req      = 0;
+
+   wire GMII_RX_CLK   = GMII_GTX_CLK;
+
+   reg [7:0] FORCE_DAT_ERR = 0;
+   reg FORCE_ERR = 0;
+   
+   // Loopback
+   assign GMII_RX_DV  = GMII_TX_EN;
+   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
+   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
+
+
+   wire [31:0] wb_dat_o;
+   reg [31:0]  wb_dat_i;
+   reg [7:0]   wb_adr;
+   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
+   wire        wb_ack;
+
+   reg [35:0]  tx_f36_data=0;
+   reg 	       tx_f36_src_rdy = 0;
+   wire        tx_f36_dst_rdy;
+   wire        rx_f36_data;
+   wire        rx_f36_src_rdy;
+   wire        rx_f36_dst_rdy = 1;
+   
+   simple_gemac_wrapper simple_gemac_wrapper
+     (.clk125(eth_clk),  .reset(reset),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .pause_req(pause_req), .pause_time(pause_time),
+
+      .sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
+      .tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
+
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
+      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
+
+      .mdio(), .mdc(),
+      .debug() );
+   
+   initial $dumpfile("simple_gemac_wrapper_tb.vcd");
+   initial $dumpvars(0,simple_gemac_wrapper_tb);
+
+   integer i; 
+   reg [7:0] pkt_rom[0:65535];
+   reg [1023:0] ROMFile;
+   
+   initial
+     for (i=0;i<65536;i=i+1)
+       pkt_rom[i] <= 8'h0;
+
+   initial
+     begin
+	@(negedge reset);
+	repeat (10)
+	  @(posedge wb_clk);
+	WishboneWR(0,6'b111101); 
+	WishboneWR(4,16'hA0B0);
+	WishboneWR(8,32'hC0D0_A1B1);
+	WishboneWR(12,16'h0000);
+	WishboneWR(16,32'h0000_0000);
+	
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0007);  // Send flow control
+	@(posedge eth_clk);
+	#30000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
+	#10000;
+	@(posedge eth_clk);
+	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
+	@(posedge eth_clk); 
+
+	repeat (1000)
+	  @(posedge sys_clk);
+	SendPacket_to_fifo36(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
+	repeat (1000)
+	  @(posedge sys_clk);
+
+	SendPacket_to_fifo36(32'hAABBCCDD,100);    // This packet gets dropped by the filters
+	repeat (10)
+	  @(posedge sys_clk);
+/*
+ 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets
+	repeat (10)
+	  @(posedge clk);
+
+ 	SendPacketFromFile_f36(61,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(62,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(63,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(64,0,0);
+	repeat (10)
+	  @(posedge clk);
+	SendPacketFromFile_f36(59,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(58,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,0);
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
+	repeat (1)
+	  @(posedge clk);
+	SendPacketFromFile_f36(100,0,30);
+ */
+	#100000 $finish;
+     end
+
+   // Force a CRC error
+    initial
+     begin
+	#90000;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h10;
+	@(posedge eth_clk);
+	FORCE_DAT_ERR <= 8'h00;
+     end
+
+   // Force an RX_ER error (i.e. link loss)
+   initial
+     begin
+	#116000;
+	@(posedge eth_clk);
+	FORCE_ERR <= 1;
+	@(posedge eth_clk);
+	FORCE_ERR <= 0;
+     end
+/*
+   // Cause receive fifo to fill, causing an RX overrun
+   initial
+     begin
+	#126000;
+	@(posedge clk);
+	rx_ll_dst_rdy2 <= 0;
+	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
+	  @(posedge clk);
+	rx_ll_dst_rdy2 <= 1;
+     end
+  */
+   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
+   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
+
+   task WishboneWR;
+      input [7:0] adr;
+      input [31:0] value;
+      begin
+	 wb_adr   <= adr;
+	 wb_dat_i <= value;
+	 wb_stb   <= 1;
+	 wb_cyc   <= 1;
+	 wb_we 	  <= 1;
+	 while (~wb_ack)
+	   @(posedge wb_clk);
+	 @(posedge wb_clk);
+	 wb_stb <= 0;
+	 wb_cyc <= 0;
+	 wb_we 	<= 0;
+      end
+   endtask // WishboneWR
+   /*
+   always @(posedge clk)
+     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
+       begin
+	  if(rx_ll_sof2 & ~rx_ll_eof2)
+	    $display("RX-PKT-START %d",$time);
+	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
+	  if(rx_ll_eof2 & ~rx_ll_sof2)
+	    $display("RX-PKT-END %d",$time);
+       end
+   */
+endmodule // simple_gemac_wrapper_tb
diff --git a/fpga/usrp2/simple_gemac/test_packet.mem b/fpga/usrp2/simple_gemac/test_packet.mem
new file mode 100644
index 000000000..7f41d3e42
--- /dev/null
+++ b/fpga/usrp2/simple_gemac/test_packet.mem
@@ -0,0 +1,66 @@
+ff
+ff
+ff
+ff
+ff
+ff
+08
+00
+07
+5c
+2e
+e4
+08
+06
+00
+01
+08
+04
+06
+02
+00
+01
+08
+00
+07
+5c
+2e
+e4
+03
+64
+00
+00
+00
+00
+00
+00
+02
+64
+00
+3a
+f3
+5c
+4f
+12
+01
+10
+00
+01
+00
+00
+00
+00
+00
+00
+20
+41
+42
+41
+08
+00
+AA
+BB
+CC
+DD
+EE
+FF
diff --git a/fpga/usrp2/testbench/.gitignore b/fpga/usrp2/testbench/.gitignore
new file mode 100644
index 000000000..eedcf9652
--- /dev/null
+++ b/fpga/usrp2/testbench/.gitignore
@@ -0,0 +1,5 @@
+/single_u2_sim
+/dual_u2_sim
+/*.lxt
+/*.vcd
+/*.sav
diff --git a/fpga/usrp2/testbench/Makefile b/fpga/usrp2/testbench/Makefile
new file mode 100644
index 000000000..6032a0123
--- /dev/null
+++ b/fpga/usrp2/testbench/Makefile
@@ -0,0 +1,10 @@
+all: single dual
+
+single:	
+	iverilog -Wimplicit -Wportbind -c cmdfile ../top/single_u2_sim/single_u2_sim.v -o single_u2_sim
+
+dual:	
+	iverilog -Wimplicit -Wportbind -c cmdfile ../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim
+
+clean:
+	rm -f single_u2_sim dual_u2_sim *.vcd *.lxt
diff --git a/fpga/usrp2/testbench/README b/fpga/usrp2/testbench/README
new file mode 100644
index 000000000..14bbb68bb
--- /dev/null
+++ b/fpga/usrp2/testbench/README
@@ -0,0 +1,5 @@
+The path to happiness:
+
+make clean
+make
+./u2_sim +rom=../../firmware/eth_test.rom -lxt2
diff --git a/fpga/usrp2/testbench/cmdfile b/fpga/usrp2/testbench/cmdfile
new file mode 100644
index 000000000..8083eb92a
--- /dev/null
+++ b/fpga/usrp2/testbench/cmdfile
@@ -0,0 +1,27 @@
+
+# My stuff
+-y .
+-y ../top/u2_core
+-y ../control_lib
+-y ../control_lib/newfifo
+-y ../serdes
+-y ../sdr_lib
+-y ../timing
+-y ../coregen
+-y ../extram
+-y ../simple_gemac
+-y ../simple_gemac/miim
+
+# Models
+-y ../models
+-y ../models/CY7C1356C
+
+# Open Cores
+-y ../opencores/8b10b
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+-y ../opencores/aemb/rtl/verilog
+-y ../opencores/simple_pic/rtl
+
diff --git a/fpga/usrp2/timing/.gitignore b/fpga/usrp2/timing/.gitignore
new file mode 100644
index 000000000..515552fdb
--- /dev/null
+++ b/fpga/usrp2/timing/.gitignore
@@ -0,0 +1,2 @@
+/a.out
+/*.vcd
diff --git a/fpga/usrp2/timing/simple_timer.v b/fpga/usrp2/timing/simple_timer.v
new file mode 100644
index 000000000..17c7f1c36
--- /dev/null
+++ b/fpga/usrp2/timing/simple_timer.v
@@ -0,0 +1,60 @@
+
+
+module simple_timer
+  #(parameter BASE=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    output reg onetime_int, output reg periodic_int);
+
+   reg [31:0]  onetime_ctr;
+   always @(posedge clk)
+     if(reset)
+       begin
+	  onetime_int 	  <= 0;
+	  onetime_ctr 	  <= 0;
+       end
+     else
+       if(set_stb & (set_addr == BASE))
+	 begin
+	    onetime_int   <= 0;
+	    onetime_ctr   <= set_data;
+	 end
+       else 
+	 begin
+	    if(onetime_ctr == 1)
+	      onetime_int <= 1;
+	    if(onetime_ctr != 0)
+	      onetime_ctr <= onetime_ctr - 1;
+	    else
+	      onetime_int <= 0;
+	 end // else: !if(set_stb & (set_addr == BASE))
+   
+   reg [31:0]  periodic_ctr, period;
+   always @(posedge clk)
+     if(reset)
+       begin
+	  periodic_int 	     <= 0;
+	  periodic_ctr 	     <= 0;
+	  period 	     <= 0;
+       end
+     else
+       if(set_stb & (set_addr == (BASE+1)))
+	 begin
+	    periodic_int     <= 0;
+	    periodic_ctr     <= set_data;
+	    period 	     <= set_data;
+	 end
+       else 
+	 if(periodic_ctr == 1)
+	   begin
+	      periodic_int   <= 1;
+	      periodic_ctr   <= period;
+	   end
+	 else
+	   if(periodic_ctr != 0)
+	     begin
+		periodic_int <= 0;
+		periodic_ctr <= periodic_ctr - 1;
+	     end
+   
+endmodule // simple_timer
diff --git a/fpga/usrp2/timing/time_64bit.v b/fpga/usrp2/timing/time_64bit.v
new file mode 100644
index 000000000..8ccde3f54
--- /dev/null
+++ b/fpga/usrp2/timing/time_64bit.v
@@ -0,0 +1,93 @@
+
+
+module time_64bit
+  #(parameter TICKS_PER_SEC = 32'd100000000,
+    parameter BASE = 0)
+    (input clk, input rst,
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
+     input pps,
+     output [63:0] vita_time, output pps_int
+     );
+
+   localparam 	   NEXT_SECS = 0;   
+   localparam 	   NEXT_TICKS = 1;
+   localparam      PPS_POLSRC = 2;
+   localparam      PPS_IMM = 3;
+   
+   localparam 	   ROLLOVER = TICKS_PER_SEC - 1;	   
+   
+   reg [31:0] 	   seconds;
+   reg [31:0] 	   ticks;
+   wire 	   end_of_second;
+   assign 	   vita_time = {seconds,ticks};
+   
+   wire [31:0] 	   next_ticks_preset;
+   wire [31:0] 	   next_seconds_preset;
+   wire 	   set_on_pps_trig;
+   reg 		   set_on_next_pps;
+   wire 	   pps_polarity;
+   wire            set_imm;
+   wire 	   pps_source;
+   
+   setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(next_ticks_preset),.changed());
+   
+   setting_reg #(.my_addr(BASE+NEXT_SECS)) sr_next_secs
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(next_seconds_preset),.changed(set_on_pps_trig));
+
+   setting_reg #(.my_addr(BASE+PPS_POLSRC)) sr_pps_polsrc
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({pps_source,pps_polarity}),.changed());
+
+   setting_reg #(.my_addr(BASE+PPS_IMM)) sr_pps_imm
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(set_imm),.changed());
+
+   reg [1:0] 	   pps_del;
+   reg 		   pps_reg_p, pps_reg_n, pps_reg;
+   wire 	   pps_edge;
+   
+   always @(posedge clk)  pps_reg_p <= pps;   
+   always @(negedge clk)  pps_reg_n <= pps;
+   always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
+   
+   always @(posedge clk)
+     if(rst)
+       pps_del <= 2'b00;
+     else
+       pps_del <= {pps_del[0],pps_reg};
+
+   assign pps_edge = pps_del[0] & ~pps_del[1];
+   
+   always @(posedge clk)
+     if(rst)
+       set_on_next_pps <= 0;
+     else if(set_on_pps_trig)
+       set_on_next_pps <= 1;
+     else if(set_imm | pps_edge)
+       set_on_next_pps <= 0;
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  seconds <= 32'd0;
+	  ticks <= 32'd0;
+       end
+     else if((set_imm | pps_edge) & set_on_next_pps)
+       begin
+	  seconds <= next_seconds_preset;
+	  ticks <= next_ticks_preset;
+       end
+     else if(ticks == ROLLOVER)
+       begin
+	  seconds <= seconds + 1;
+	  ticks <= 0;
+       end
+     else
+       ticks <= ticks + 1;
+
+   assign pps_int = pps_edge;
+   
+endmodule // time_64bit
diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v
new file mode 100644
index 000000000..a21c9f8e0
--- /dev/null
+++ b/fpga/usrp2/timing/time_compare.v
@@ -0,0 +1,23 @@
+
+// Top 32 bits are integer seconds, bottom 32 are clock ticks within a second
+
+module time_compare
+  (input [63:0] time_now,
+   input [63:0] trigger_time,
+   output now,
+   output early,
+   output late, 
+   output too_early);
+   
+   wire    sec_match   = (time_now[63:32] == trigger_time[63:32]);
+   wire    sec_late    = (time_now[63:32] > trigger_time[63:32]);
+
+   wire    tick_match  = (time_now[31:0] == trigger_time[31:0]);
+   wire    tick_late   = (time_now[31:0] > trigger_time[31:0]);
+   
+   assign now 	       = sec_match & tick_match;
+   assign late 	       = sec_late | (sec_match & tick_late);
+   assign early        = ~now & ~late;
+   assign too_early    = (trigger_time[63:32] > (time_now[63:32] + 4));  // Don't wait too long
+   
+endmodule // time_compare
diff --git a/fpga/usrp2/timing/time_receiver.v b/fpga/usrp2/timing/time_receiver.v
new file mode 100644
index 000000000..8e7d3f1ea
--- /dev/null
+++ b/fpga/usrp2/timing/time_receiver.v
@@ -0,0 +1,94 @@
+
+module time_receiver
+  (input clk, input rst,
+   output [31:0] master_time,
+   output sync_rcvd,
+   input exp_pps_in);
+
+   wire       code_err, disp_err, dispout, complete_word;
+   reg 	      disp_reg;
+   reg [9:0]  shiftreg;
+   reg [3:0]  bit_count;
+   wire [8:0] dataout;
+   reg [8:0]  dataout_reg;
+ 	      
+   always @(posedge clk)
+     shiftreg <= {exp_pps_in, shiftreg[9:1]};
+
+   localparam COMMA_0 = 10'h283;
+   localparam COMMA_1 = 10'h17c;
+   
+   wire       found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1);
+   wire       set_disp = (shiftreg == COMMA_1);
+
+   always @(posedge clk)
+     if(rst)
+       bit_count <= 0;
+     else if(found_comma | complete_word)
+       bit_count <= 0;
+     else 
+       bit_count <= bit_count + 1;
+   assign     complete_word = (bit_count == 9);
+
+   always @(posedge clk)
+     if(set_disp)
+       disp_reg <= 1;
+     else if(complete_word)
+       disp_reg <= dispout;
+
+   always @(posedge clk)
+     if(complete_word)
+       dataout_reg <= dataout;
+     
+   decode_8b10b decode_8b10b 
+     (.datain(shiftreg),.dispin(disp_reg),
+      .dataout(dataout),.dispout(dispout),
+      .code_err(code_err),.disp_err(disp_err) );
+
+   reg 	      error;
+   always @(posedge clk)
+     if(complete_word)
+       error <= code_err | disp_err;
+   
+   localparam STATE_IDLE = 0;
+   localparam STATE_T0 = 1;
+   localparam STATE_T1 = 2;
+   localparam STATE_T2 = 3;
+   localparam STATE_T3 = 4;
+   
+   localparam HEAD = 9'h13c;   
+
+   reg [7:0]  clock_a, clock_b, clock_c;
+   reg [2:0]  state;
+   
+   always @(posedge clk)
+     if(rst)
+       state <= STATE_IDLE;
+     else if(complete_word)
+       case(state)
+	 STATE_IDLE :
+	   if(dataout_reg == HEAD)
+	     state <= STATE_T0;
+	 STATE_T0 :
+	   begin
+	      clock_a <= dataout_reg[7:0];
+	      state <= STATE_T1;
+	   end
+	 STATE_T1 :
+	   begin
+	      clock_b <= dataout_reg[7:0];
+	      state <= STATE_T2;
+	   end
+	 STATE_T2 :
+	   begin
+	      clock_c <= dataout_reg[7:0];
+	      state <= STATE_T3;
+	   end
+	 STATE_T3 :
+	   state <= STATE_IDLE;
+       endcase // case(state)
+
+   assign master_time =  {clock_a, clock_b, clock_c, dataout_reg[7:0]};
+   assign sync_rcvd = (complete_word & (state == STATE_T3));
+
+endmodule // time_sender
diff --git a/fpga/usrp2/timing/time_sender.v b/fpga/usrp2/timing/time_sender.v
new file mode 100644
index 000000000..aa2fcbbdb
--- /dev/null
+++ b/fpga/usrp2/timing/time_sender.v
@@ -0,0 +1,110 @@
+
+
+module time_sender
+  (input clk, input rst,
+   input [31:0] master_time,
+   input send_sync,
+   output exp_pps_out);
+
+   reg [7:0] datain;
+   reg 	     k;
+   wire [9:0] dataout;
+   reg [9:0] dataout_reg;
+   reg 	     disp_reg;
+   wire      disp, new_word;
+   
+   encode_8b10b encode_8b10b 
+     (.datain({k,datain}),.dispin(disp_reg),
+      .dataout(dataout),.dispout(disp));
+
+   assign    exp_pps_out = dataout_reg[0];
+
+   always @(posedge clk)
+     if(rst)
+       disp_reg <= 0;
+     else if(new_word)
+       disp_reg <= disp;
+   
+   always @(posedge clk)
+     if(rst)
+       dataout_reg <= 0;
+     else if(new_word)
+       dataout_reg <= dataout;
+     else
+       dataout_reg <= {1'b0,dataout_reg[9:1]};
+   
+   reg [4:0] state;
+   reg [3:0] bit_count;
+
+   assign    new_word = (bit_count == 9);
+   
+   always @(posedge clk)
+     if(rst)
+       bit_count <= 0;
+     else if(new_word | send_sync)
+       bit_count <= 0;
+     else
+       bit_count <= bit_count + 1;
+
+   localparam SEND_IDLE = 0;
+   localparam SEND_HEAD = 1;
+   localparam SEND_T0 = 2;
+   localparam SEND_T1 = 3;
+   localparam SEND_T2 = 4;
+   localparam SEND_T3 = 5;
+
+   localparam COMMA = 8'hBC;
+   localparam HEAD = 8'h3C;
+
+   reg [31:0] master_time_reg;
+   
+   always @(posedge clk)
+     if(rst)
+       master_time_reg <= 0;
+     else if(send_sync)
+       master_time_reg <= master_time;
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+	  {k,datain} <= 0;
+	  state <= SEND_IDLE;
+       end
+     else
+       if(send_sync)
+	 state <= SEND_HEAD;
+       else if(new_word)
+	 case(state)
+	   SEND_IDLE :
+	     {k,datain} <= {1'b1,COMMA};
+	   SEND_HEAD :
+	     begin
+		{k,datain} <= {1'b1, HEAD};
+		state <= SEND_T0;
+	     end
+	   SEND_T0 :
+	     begin
+		{k,datain} <= {1'b0, master_time_reg[31:24] };
+		state <= SEND_T1;
+	     end
+	   SEND_T1 :
+	     begin
+		{k,datain} <= {1'b0, master_time_reg[23:16]};
+		state <= SEND_T2;
+	     end
+	   SEND_T2 :
+	     begin
+		{k,datain} <= {1'b0, master_time_reg[15:8]};
+		state <= SEND_T3;
+	     end
+	   SEND_T3 :
+	     begin
+		{k,datain} <= {1'b0, master_time_reg[7:0]};
+		state <= SEND_IDLE;
+	     end
+	   default :
+	     state <= SEND_IDLE;
+	 endcase // case(state)
+   
+   
+endmodule // time_sender
diff --git a/fpga/usrp2/timing/time_sync.v b/fpga/usrp2/timing/time_sync.v
new file mode 100644
index 000000000..c0c8e195f
--- /dev/null
+++ b/fpga/usrp2/timing/time_sync.v
@@ -0,0 +1,146 @@
+
+
+module time_sync
+  (input wb_clk_i, input rst_i,
+   input cyc_i, input stb_i, input [2:0] adr_i,
+   input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
+   input sys_clk_i, output [31:0] master_time_o,
+   input pps_posedge, input pps_negedge, 
+   input exp_pps_in, output exp_pps_out,
+   output reg int_o,
+   output reg epoch_o,
+   output reg pps_o );
+   
+   wire [31:0] master_time_rcvd;
+   reg [31:0]  master_time;
+   reg [31:0]  delta_time;
+
+   reg 	       internal_tick;
+   wire        sync_rcvd, pps_ext;
+   reg [31:0]  tick_time, tick_time_wb;
+   wire        tick_free_run;
+   reg 	       tick_int_enable, tick_source, external_sync;
+   reg [31:0]  tick_interval;
+   reg 	       sync_on_next_pps;
+   reg         sync_every_pps;
+   reg 	       pps_edge;
+   
+   // Generate master time
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       master_time <= 0;
+     else if(external_sync & sync_rcvd)
+       master_time <= master_time_rcvd + delta_time;
+     else if(pps_ext & (sync_on_next_pps|sync_every_pps))
+       master_time <= 0;
+     else
+       master_time <= master_time + 1;
+   assign      master_time_o = master_time;
+   
+   time_sender time_sender
+     (.clk(sys_clk_i),.rst(rst_i),
+      .master_time(master_time),
+      .send_sync(internal_tick),
+      .exp_pps_out(exp_pps_out) );
+
+   time_receiver time_receiver
+     (.clk(sys_clk_i),.rst(rst_i),
+      .master_time(master_time_rcvd),
+      .sync_rcvd(sync_rcvd),
+      .exp_pps_in(exp_pps_in) );
+
+   assign     ack_o = stb_i;
+   wire       wb_write = cyc_i & stb_i & we_i;
+   wire       wb_read = cyc_i & stb_i & ~we_i;
+   wire       wb_acc = cyc_i & stb_i;
+   
+   always @(posedge wb_clk_i)
+     if(rst_i)
+       begin
+	  tick_source <= 0;
+	  tick_int_enable <= 0;
+	  external_sync <= 0;
+	  tick_interval <= 100000-1;  // default to 1K times per second
+	  delta_time <= 0;
+	  pps_edge <= 0;
+	  sync_every_pps <= 0;
+       end
+     else if(wb_write)
+       case(adr_i[2:0])
+	 3'd0 :
+	   begin
+	      tick_source <= dat_i[0];
+	      tick_int_enable <= dat_i[1];
+	      external_sync <= dat_i[2];
+	      pps_edge <= dat_i[3];
+	      sync_every_pps <= dat_i[4];
+	   end
+	 3'd1 :
+	   tick_interval <= dat_i;
+	 3'd2 :
+	   delta_time <= dat_i;
+	 3'd3 :
+	   ;
+	 // Do nothing here, this is to arm the sync_on_next
+       endcase // case(adr_i[2:0])
+
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       sync_on_next_pps <= 0;
+     else if(pps_ext)
+       sync_on_next_pps <= 0;
+     else if(wb_write & (adr_i[2:0] == 3))
+       sync_on_next_pps <= 1;
+   
+   always @(posedge sys_clk_i)
+     if(internal_tick)
+       tick_time <= master_time;
+
+   always @(posedge wb_clk_i)
+     tick_time_wb <= tick_time;
+   
+   assign dat_o = tick_time_wb;
+
+   always @(posedge sys_clk_i)
+     internal_tick <= (tick_source == 0) ? tick_free_run : pps_ext;
+
+   reg [31:0] counter;
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       counter <= 0;
+     else if(tick_free_run)
+       counter <= 0;
+     else
+       counter <= counter + 1;
+   assign     tick_free_run = (counter >= tick_interval);
+   
+   // Properly Latch and edge detect External PPS input
+   reg 	      pps_in_d1, pps_in_d2;
+   always @(posedge sys_clk_i)
+     begin
+	pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge;
+	pps_in_d2 <= pps_in_d1;
+     end
+   assign pps_ext = pps_in_d1 & ~pps_in_d2;
+
+   always @(posedge sys_clk_i)
+     pps_o <= pps_ext;
+   
+   // Need to register this?
+   reg 	  internal_tick_d1;
+   always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick;
+   
+   always @(posedge wb_clk_i)
+     if(rst_i)
+       int_o <= 0;
+     else if(tick_int_enable & (internal_tick | internal_tick_d1))
+       int_o <= 1;
+     else
+       int_o <= 0;
+
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       epoch_o <= 0;
+     else
+       epoch_o <= (master_time_o[27:0] == 0);
+endmodule // time_sync
diff --git a/fpga/usrp2/timing/time_transfer_tb.v b/fpga/usrp2/timing/time_transfer_tb.v
new file mode 100644
index 000000000..2b75c60bd
--- /dev/null
+++ b/fpga/usrp2/timing/time_transfer_tb.v
@@ -0,0 +1,50 @@
+
+`timescale 1ns / 1ps
+
+module time_transfer_tb();
+
+   reg clk = 0, rst = 1;
+   always #5 clk = ~clk;
+   
+   initial 
+     begin
+	@(negedge clk);
+	@(negedge clk);
+	rst <= 0;
+     end
+
+   initial $dumpfile("time_transfer_tb.vcd");
+   initial $dumpvars(0,time_transfer_tb);
+   
+   initial #100000000 $finish;
+
+   wire exp_pps, pps, pps_rcv;
+   wire [31:0] master_clock_rcv;
+   reg [31:0]  master_clock = 0;
+   reg [31:0]  counter = 0;
+
+   localparam  PPS_PERIOD = 109;
+   always @(posedge clk)
+     if(counter == PPS_PERIOD)
+       counter <= 0;
+     else
+       counter <= counter + 1;
+   assign      pps = (counter == (PPS_PERIOD-1));
+   
+   always @(posedge clk)
+     master_clock <= master_clock + 1;
+   
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .master_clock(master_clock),
+      .pps(pps),
+      .exp_pps_out(exp_pps) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .master_clock(master_clock_rcv),
+      .pps(pps_rcv),
+      .exp_pps_in(exp_pps) );
+
+   wire [31:0] delta = master_clock - master_clock_rcv;
+endmodule // time_transfer_tb
diff --git a/fpga/usrp2/timing/timer.v b/fpga/usrp2/timing/timer.v
new file mode 100644
index 000000000..70c9746be
--- /dev/null
+++ b/fpga/usrp2/timing/timer.v
@@ -0,0 +1,40 @@
+
+
+module timer
+  (input wb_clk_i, input rst_i,
+   input cyc_i, input stb_i, input [2:0] adr_i,
+   input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
+   input sys_clk_i, input [31:0] master_time_i,
+   output int_o );
+
+   reg [31:0] time_wb;
+   always @(posedge wb_clk_i)
+     time_wb <= master_time_i;
+
+   assign     ack_o = stb_i;
+
+   reg [31:0] int_time;
+   reg 	      int_reg;
+   
+   always @(posedge sys_clk_i)
+     if(rst_i)
+       begin
+	  int_time <= 0;
+	  int_reg <= 0;
+       end
+     else if(|int_time && (master_time_i == int_time))
+       begin
+	  int_time <= 0;
+	  int_reg <= 1;
+       end
+     else if(stb_i & we_i)
+       begin
+	  int_time <= dat_i;
+	  int_reg <= 0;
+       end
+
+   assign dat_o = time_wb;
+   assign int_o = int_reg;
+   
+endmodule // timer
+
diff --git a/fpga/usrp2/top/.gitignore b/fpga/usrp2/top/.gitignore
new file mode 100644
index 000000000..bf1b77066
--- /dev/null
+++ b/fpga/usrp2/top/.gitignore
@@ -0,0 +1 @@
+/*.sav
diff --git a/fpga/usrp2/top/eth_test/.gitignore b/fpga/usrp2/top/eth_test/.gitignore
new file mode 100644
index 000000000..b30397081
--- /dev/null
+++ b/fpga/usrp2/top/eth_test/.gitignore
@@ -0,0 +1,43 @@
+/xst
+/_ngo
+/_xmsgs
+/*.stx
+/*.tspec
+/*.xml
+/*.gyd
+/*.ngr
+/*.tim
+/*.err
+/*.lso
+/*.bld
+/*.cmd_log
+/*.ise_ISE_Backup
+/*.mfd
+/*.vm6
+/*.syr
+/*.xst
+/*.csv
+/*.html
+/*.jed
+/*.pad
+/*.ng*
+/*.pnx
+/*.rpt
+/*.prj
+/*_html
+/*_log
+/*.lfp
+/*.bit
+/*.bin
+/*.vcd
+/*.unroutes
+/*.drc
+/*_map.*
+/*_guide.*
+/*.twr
+/*.twx
+/a.out
+/*.xpi
+/*_pad.txt
+/*.bgn
+/*.par
diff --git a/fpga/usrp2/top/eth_test/eth_sim_top.v b/fpga/usrp2/top/eth_test/eth_sim_top.v
new file mode 100644
index 000000000..640a4e60f
--- /dev/null
+++ b/fpga/usrp2/top/eth_test/eth_sim_top.v
@@ -0,0 +1,437 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_basic
+//////////////////////////////////////////////////////////////////////////////////
+
+module eth_sim_top
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output led1,
+   output led2,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in,
+   output exp_pps_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   input PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx
+   );
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+   
+   wire 	ram_loader_done;
+   wire 	ram_loader_rst, wb_rst, dsp_rst;
+
+   wire [31:0] 	ser_debug;
+   
+   //////////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   parameter 	dw = 32;  // Data bus width
+   parameter 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   parameter 	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+      
+   wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i;
+   wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+   wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel;
+   wire 	 m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack;
+   wire 	 m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb;
+   wire 	 m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc;
+   wire 	 m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err;
+   wire 	 m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty;
+   wire 	 m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we;
+   
+   wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
+		.s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010),
+		.s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101),
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
+      );
+   
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   system_control sysctrl (.wb_clk_i(wb_clk),
+			   .ram_loader_rst_o(ram_loader_rst),
+			   .wb_rst_o(wb_rst),
+			   .ram_loader_done_i(ram_loader_done));
+   
+   // ///////////////////////////////////////////////////////////////////
+   // RAM Loader
+   wire 	 iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we;
+   wire [3:0] 	 iram_wr_sel;
+   wire [aw-1:0] iram_wr_adr, iram_rd_adr;
+   wire [dw-1:0] iram_wr_dat, iram_rd_dat;
+
+   wire 	 bus_error, proc_int;
+
+   assign 	 iram_rd_ack = ram_loader_done ? iram_ack : 1'b0;
+   assign 	 iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack;
+   
+   ram_loader #(.AWIDTH(16))
+     ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+		 // CPLD Interface
+		 .cfg_clk_i(cpld_clk),
+		 .cfg_data_i(cpld_din),
+		 .start_o(cpld_start),
+		 .mode_o(cpld_mode),
+		 .done_o(cpld_done),
+		 .detached_i(cpld_detached),
+		 // Wishbone Interface
+		 .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr),
+		 .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel),
+		 .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack),
+		 .ram_loader_done_o(ram_loader_done));
+
+   // Processor
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+	   // Instruction Wishbone bus to I-RAM
+	   .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr),
+	   .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack),
+	   // Data Wishbone bus to system bus fabric
+	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+
+   assign 	 bus_error = m0_err | m0_rty;
+   assign	 proc_int = 1'b0;
+   
+   // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+   // I-port connects directly to processor and ram loader
+   
+   ram_wb_harvard #(.AWIDTH(14))
+     ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+	     
+	     .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat),
+	     .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb),
+	     .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel),
+	     
+	     .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
+	     .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
+
+   assign 	 s0_err = 1'b0;
+   assign 	 s0_rty = 1'b0;
+
+   // Buffer Pool, slave #1
+   wire 	 rd0_read, rd0_ready, rd0_done, rd0_empty;
+   wire 	 rd1_read, rd1_ready, rd1_done, rd1_empty;
+   wire 	 rd2_read, rd2_ready, rd2_done, rd2_empty;
+   wire 	 rd3_read, rd3_ready, rd3_done, rd3_empty;
+   wire [31:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_write, wr0_done, wr0_ready, wr0_full;
+   wire 	 wr1_write, wr1_done, wr1_ready, wr1_full;
+   wire 	 wr2_write, wr2_done, wr2_ready, wr2_full;
+   wire 	 wr3_write, wr3_done, wr3_ready, wr3_full;
+   wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+
+/*   
+   buffer_pool buffer_pool
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+   
+      .stream_clk(dsp_clk),.stream_rst(dsp_rst),
+      // Write Interfaces
+      .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(),
+      .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(),
+      .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(),
+      .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(),
+      // Read Interfaces
+      .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty),
+      .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty),
+      .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty),
+      .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty)
+      );
+*/
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
+      .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),
+
+      .wb_err_o(s2_err),.wb_int_o(s2_int),
+      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   assign 	 s2_rty = 1'b0;
+   
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(st_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+   
+   assign 	 s3_err = 1'b0;
+   assign 	 s3_rty = 1'b0;
+
+   // GPIOs -- Slave #4
+   wire 	 s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d;
+   assign 	 s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d;
+
+   simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a),
+		      .gpio(/* io_tx[7:0]*/) );
+   
+   simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b),
+		      .gpio(/* io_tx[15:8] */) );
+   
+   simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c),
+		      .gpio(/* io_rx[7:0] */) );
+   
+   simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst),
+		      .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we),
+		      .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d),
+		      .gpio(/* io_rx[15:8]*/) );
+
+   assign 	 s4_err = 1'b0;
+   assign 	 s4_rty = 1'b0;
+   
+   // Output control lines, SLAVE #5
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs, misc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
+   assign 	 {led2, led1} = misc_outs[1:0];
+   
+   wb_output_pins32 control_lines
+     (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i),
+      .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc),
+      .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} )  );
+
+   assign 	 s5_err = 1'b0;
+   assign 	 s5_rty = 1'b0;
+
+   // Ethernet slave, #6
+   eth_wrapper eth_wrapper
+     (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(),
+      .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode
+      .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER),
+      .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL),
+      .Mdio(MDIO),.Mdc(MDC),
+      // FIFO Interfaces
+      .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(),
+      .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(),
+      // Wishbone
+      .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack)
+      );
+   
+   assign 	 s6_err = 1'b0;
+   assign 	 s6_rty = 1'b0;
+   
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_err = 1'b0;
+   assign 	 s7_rty = 1'b0;
+   assign 	 s7_dat_i = 32'd0;
+
+   ///////////////////////////////////////////////////////////////////////////
+   // DSP
+   reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+   reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+   
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg1 <= adc_a;
+	adc_a_reg2 <= adc_a_reg1;
+	adc_b_reg1 <= adc_b;
+	adc_b_reg2 <= adc_b_reg1;
+	adc_ovf_a_reg1 <= adc_ovf_a;
+	adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+	adc_ovf_b_reg1 <= adc_ovf_b;
+	adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+     end // always @ (posedge dsp_clk)
+   
+   dsp_core_rx dsp_core_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done),
+      .rx_ready_i(wr1_ready),.rx_full_i(wr1_full),
+      .overrun() );
+   
+   dsp_core_tx dsp_core_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done),
+      .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty),
+      .underrun() );
+   
+   assign dsp_rst = wb_rst;
+
+   /////////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+   serdes_tx serdes_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done),
+      .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty)
+      );
+
+   serdes_rx serdes_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done)
+      );
+   
+   // Debug Pins
+   wire [31:0]	debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst},
+   			{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+   			{8'hAF},
+   			{2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}};
+
+   wire [31:0]	debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst},
+   			  {iram_rd_adr[15:8]},
+   			  {iram_rd_adr[7:0]},
+   			  {serdes_outs}};
+
+   assign 	io_rx = ser_debug[31:16];
+   assign 	io_tx = ser_debug[15:0];
+ 
+   assign 	debug = debug_wb;
+   
+   assign 	debug_clk[0] = wb_clk;
+   assign 	debug_clk[1] = dsp_clk;	
+   
+endmodule // eth_test
+
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
diff --git a/fpga/usrp2/top/eth_test/eth_tb.v b/fpga/usrp2/top/eth_test/eth_tb.v
new file mode 100644
index 000000000..451ce1e7e
--- /dev/null
+++ b/fpga/usrp2/top/eth_test/eth_tb.v
@@ -0,0 +1,257 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module eth_tb();
+   // Misc, debug
+   wire led1;
+   wire led2;
+   wire [31:0] debug;
+   wire [1:0]  debug_clk;
+   
+   // Expansion
+   wire        exp_pps_in;
+   wire        exp_pps_out;
+   
+   // GMII
+   //   GMII-CTRL
+   wire        GMII_COL;
+   wire        GMII_CRS;
+   
+   //   GMII-TX
+   wire [7:0]  GMII_TXD;
+   wire        GMII_TX_EN;
+   wire        GMII_TX_ER;
+   wire        GMII_GTX_CLK;
+   wire        GMII_TX_CLK;  // 100mbps clk
+   
+   //   GMII-RX
+   wire [7:0]  GMII_RXD;
+   wire        GMII_RX_CLK;
+   wire        GMII_RX_DV;
+   wire        GMII_RX_ER;
+   
+   //   GMII-Management
+   wire        MDIO;
+   wire        MDC;
+   wire        PHY_INTn;   // open drain
+   wire        PHY_RESETn;
+   wire        PHY_CLK;   // possibly use on-board osc
+   
+   // RAM
+   wire [17:0] RAM_D;
+   wire [18:0] RAM_A;
+   wire        RAM_CE1n;
+   wire        RAM_CENn;
+   wire        RAM_CLK;
+   wire        RAM_WEn;
+   wire        RAM_OEn;
+   wire        RAM_LDn;
+   
+   // SERDES
+   wire        ser_enable;
+   wire        ser_prbsen;
+   wire        ser_loopen;
+   wire        ser_rx_en;
+   
+   wire        ser_tx_clk;
+   wire [15:0] ser_t;
+   wire        ser_tklsb;
+   wire        ser_tkmsb;
+   
+   wire        ser_rx_clk;
+   wire [15:0] ser_r;
+   wire        ser_rklsb;
+   wire        ser_rkmsb;
+   
+   // CPLD interface
+   wire        cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done;
+      
+   // ADC
+   wire [13:0] adc_a;
+   wire        adc_ovf_a;
+   wire        adc_oen_a;
+   wire        adc_pdn_a;
+   
+   wire [13:0] adc_b;
+   wire        adc_ovf_b;
+   wire        adc_oen_b;
+   wire        adc_pdn_b;
+   
+   // DAC
+   wire [15:0] dac_a;
+   wire [15:0] dac_b;
+   
+   // I2C
+   wire        SCL;
+   wire        SDA;
+   
+   // Clock Gen Control
+   wire [1:0]  clk_en;
+   wire [1:0]  clk_sel;
+   wire        clk_func;        // FIXME is an input to control the 9510
+   wire        clk_status;
+   
+   // Clocks
+   reg        clk_fpga;
+   wire        clk_to_mac;
+   wire        pps_in;
+   
+   // Generic SPI
+   wire        sclk, mosi, miso;   
+   wire        sen_clk;
+   wire        sen_dac;
+   wire        sen_tx_db;
+   wire        sen_tx_adc;
+   wire        sen_tx_dac;
+   wire        sen_rx_db;
+   wire        sen_rx_adc;
+   wire        sen_rx_dac;
+   
+   // GPIO to DBoards
+   wire [15:0] io_tx;
+   wire [15:0] io_rx;
+   
+   wire        wb_clk, wb_rst;
+   wire        start, clock_ready;
+   
+   reg 	       aux_clk;
+
+   initial aux_clk= 1'b0;
+   always #25 aux_clk = ~aux_clk;
+   
+   initial clk_fpga = 1'bx;
+   initial #3007 clk_fpga = 1'b0;
+   always #7 clk_fpga = ~clk_fpga;
+
+
+   wire        div_clk;
+   reg [2:0]   div_ctr = 0;
+   
+   always @(posedge clk_fpga or negedge clk_fpga)
+     if(div_ctr==5)
+       div_ctr = 0;
+     else
+       div_ctr = div_ctr + 1;
+   assign      div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2);
+   
+   assign      dsp_clk = clk_fpga;
+   assign      wb_clk = clock_ready ? div_clk : aux_clk;
+
+   initial
+     $monitor($time, ,clock_ready);
+   
+   initial begin
+      $dumpfile("eth_tb.vcd");
+      $dumpvars(0,eth_tb);
+   end
+
+   initial #10000000 $finish;
+
+   cpld_model 
+     cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
+		 .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
+   
+   eth_sim_top eth_sim_top(.dsp_clk		(dsp_clk),
+			   .wb_clk            (wb_clk),
+			   .clock_ready	(clock_ready),
+			   .clk_to_mac	(clk_to_mac),
+			   .pps_in		(pps_in),
+			   .led1		(led1),
+			   .led2		(led2),
+			   .debug		(debug[31:0]),
+			   .debug_clk		(debug_clk[1:0]),
+			   .exp_pps_in	(exp_pps_in),
+			   .exp_pps_out	(exp_pps_out),
+			   .GMII_COL		(GMII_COL),
+			   .GMII_CRS		(GMII_CRS),
+			   .GMII_TXD		(GMII_TXD[7:0]),
+			   .GMII_TX_EN	(GMII_TX_EN),
+			   .GMII_TX_ER	(GMII_TX_ER),
+			   .GMII_GTX_CLK	(GMII_GTX_CLK),
+			   .GMII_TX_CLK	(GMII_TX_CLK),
+			   .GMII_RXD		(GMII_RXD[7:0]),
+			   .GMII_RX_CLK	(GMII_RX_CLK),
+			   .GMII_RX_DV	(GMII_RX_DV),
+			   .GMII_RX_ER	(GMII_RX_ER),
+			   .MDIO		(MDIO),
+			   .MDC		(MDC),
+			   .PHY_INTn		(PHY_INTn),
+			   .PHY_RESETn	(PHY_RESETn),
+			   .PHY_CLK		(PHY_CLK),
+			   .ser_enable	(ser_enable),
+			   .ser_prbsen	(ser_prbsen),
+			   .ser_loopen	(ser_loopen),
+			   .ser_rx_en		(ser_rx_en),
+			   .ser_tx_clk	(ser_tx_clk),
+			   .ser_t		(ser_t[15:0]),
+			   .ser_tklsb		(ser_tklsb),
+			   .ser_tkmsb		(ser_tkmsb),
+			   .ser_rx_clk	(ser_rx_clk),
+			   .ser_r		(ser_r[15:0]),
+			   .ser_rklsb		(ser_rklsb),
+			   .ser_rkmsb		(ser_rkmsb),
+			   .cpld_start	(cpld_start),
+			   .cpld_mode		(cpld_mode),
+			   .cpld_done		(cpld_done),
+			   .cpld_din		(cpld_din),
+			   .cpld_clk		(cpld_clk),
+			   .cpld_detached	(cpld_detached),
+			   .adc_a		(adc_a[13:0]),
+			   .adc_ovf_a		(adc_ovf_a),
+			   .adc_oen_a		(adc_oen_a),
+			   .adc_pdn_a		(adc_pdn_a),
+			   .adc_b		(adc_b[13:0]),
+			   .adc_ovf_b		(adc_ovf_b),
+			   .adc_oen_b		(adc_oen_b),
+			   .adc_pdn_b		(adc_pdn_b),
+			   .dac_a		(dac_a[15:0]),
+			   .dac_b		(dac_b[15:0]),
+			   .scl_pad_i		(scl_pad_i),
+			   .scl_pad_o		(scl_pad_o),
+			   .scl_pad_oen_o	(scl_pad_oen_o),
+			   .sda_pad_i		(sda_pad_i),
+			   .sda_pad_o		(sda_pad_o),
+			   .sda_pad_oen_o	(sda_pad_oen_o),
+			   .clk_en		(clk_en[1:0]),
+			   .clk_sel		(clk_sel[1:0]),
+			   .clk_func		(clk_func),
+			   .clk_status	(clk_status),
+			   .sclk		(sclk),
+			   .mosi		(mosi),
+			   .miso		(miso),
+			   .sen_clk		(sen_clk),
+			   .sen_dac		(sen_dac),
+			   .sen_tx_db		(sen_tx_db),
+			   .sen_tx_adc	(sen_tx_adc),
+			   .sen_tx_dac	(sen_tx_dac),
+			   .sen_rx_db		(sen_rx_db),
+			   .sen_rx_adc	(sen_rx_adc),
+			   .sen_rx_dac	(sen_rx_dac),
+			   .io_tx		(io_tx[15:0]),
+			   .io_rx		(io_rx[15:0]));
+   
+   // Experimental printf-like function
+   always @(posedge wb_clk)
+     begin
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000))
+	  $write("%x",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100))
+	  $display("%x",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004))
+	  $write("%c",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104))
+	  $display("%c",eth_sim_top.m0_dat_i);
+	if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008))
+	  $display("");
+     end
+	
+
+endmodule // u2_sim_top
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
diff --git a/fpga/usrp2/top/single_u2_sim/single_u2_sim.v b/fpga/usrp2/top/single_u2_sim/single_u2_sim.v
new file mode 100644
index 000000000..2a7b24849
--- /dev/null
+++ b/fpga/usrp2/top/single_u2_sim/single_u2_sim.v
@@ -0,0 +1,324 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module single_u2_sim();
+   // Misc, debug
+   wire [7:0] leds;
+   wire [31:0] debug;
+   wire [1:0]  debug_clk;
+   
+   // Expansion
+   wire        exp_pps_in;
+   wire        exp_pps_out;
+   
+   // GMII
+   //   GMII-CTRL
+   wire        GMII_COL;
+   wire        GMII_CRS;
+   
+   //   GMII-TX
+   wire [7:0]  GMII_TXD;
+   wire        GMII_TX_EN;
+   wire        GMII_TX_ER;
+   wire        GMII_GTX_CLK;
+   wire        GMII_TX_CLK;  // 100mbps clk
+   
+   //   GMII-RX
+   wire [7:0]  GMII_RXD;
+   wire        GMII_RX_CLK;
+   wire        GMII_RX_DV;
+   wire        GMII_RX_ER;
+   
+   //   GMII-Management
+   wire        MDIO;
+   wire        MDC;
+   wire        PHY_INTn;   // open drain
+   wire        PHY_RESETn;
+   wire        PHY_CLK;   // possibly use on-board osc
+   
+   // RAM
+   wire [17:0] RAM_D;
+   wire [18:0] RAM_A;
+   wire        RAM_CE1n;
+   wire        RAM_CENn;
+   wire        RAM_CLK;
+   wire        RAM_WEn;
+   wire        RAM_OEn;
+   wire        RAM_LDn;
+   
+   // SERDES
+   wire        ser_enable;
+   wire        ser_prbsen;
+   wire        ser_loopen;
+   wire        ser_rx_en;
+   
+   wire        ser_tx_clk;
+   wire [15:0] ser_t;
+   wire        ser_tklsb;
+   wire        ser_tkmsb;
+   
+   wire        ser_rx_clk;
+   wire [15:0] ser_r;
+   wire        ser_rklsb;
+   wire        ser_rkmsb;
+   
+   // CPLD interface
+   wire        cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done;
+      
+   // ADC
+   wire [13:0] adc_a;
+   wire        adc_ovf_a;
+   wire        adc_on_a,  adc_oe_a;
+   
+   wire [13:0] adc_b;
+   wire        adc_ovf_b;
+   wire        adc_on_b, adc_oe_b;
+   
+   // DAC
+   wire [15:0] dac_a;
+   wire [15:0] dac_b;
+   
+   // I2C
+   wire        SCL;
+   wire        SDA;
+   
+   // Clock Gen Control
+   wire [1:0]  clk_en;
+   wire [1:0]  clk_sel;
+   wire        clk_func;        // FIXME is an input to control the 9510
+   wire        clk_status;
+   
+   // Clocks
+   reg 	       clk_fpga;
+   reg 	       clk_to_mac;
+   wire        pps_in;
+   
+   // Generic SPI
+   wire        sclk, mosi, miso;   
+   wire        sen_clk;
+   wire        sen_dac;
+   wire        sen_tx_db;
+   wire        sen_tx_adc;
+   wire        sen_tx_dac;
+   wire        sen_rx_db;
+   wire        sen_rx_adc;
+   wire        sen_rx_dac;
+   
+   // GPIO to DBoards
+   wire [15:0] io_tx;
+   wire [15:0] io_rx;
+   
+   wire        wb_clk;
+   wire        start, clock_ready;
+   
+   reg 	       aux_clk;
+
+   initial aux_clk= 1'b0;
+   always #6 aux_clk = ~aux_clk;
+   
+   initial clk_fpga = 1'bx;
+   initial #3007 clk_fpga = 1'b0;
+   always #5 clk_fpga = ~clk_fpga;
+   
+   initial clk_to_mac = 0;
+   always #4 clk_to_mac = ~clk_to_mac;
+   
+   wire        div_clk, dsp_clk;
+   reg [7:0]   div_ctr = 0;
+   
+   assign      dsp_clk = clock_ready ? clk_fpga : aux_clk;
+   assign      wb_clk = div_clk;
+
+`define CLK_DIV_2 1
+//`define CLK_DIV_3
+
+`ifdef CLK_DIV_2
+   localparam  clock_divider = 4'd2;
+   always @(posedge dsp_clk)
+     div_ctr <= div_ctr + 1;
+   assign      div_clk = div_ctr[0];
+`endif
+
+`ifdef CLK_DIV_3
+   localparam  clock_divider = 2;
+   always @(posedge dsp_clk or negedge dsp_clk)
+     if(div_ctr == 5)
+       div_ctr <= 0;
+     else
+       div_ctr <= div_ctr + 1;
+   assign      div_clk = ((div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2));
+`endif
+   
+   initial
+     $monitor($time, ,clock_ready);
+
+   always #1000000 $monitor("Time in ns ",$time);
+   
+   initial begin
+      @(negedge cpld_done);
+      @(posedge cpld_done);
+      $dumpfile("single_u2_sim.lxt");
+      $dumpvars(0,single_u2_sim);
+   end
+
+   initial #10000000 $finish;
+
+   cpld_model 
+     cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done),
+		 .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached));
+     
+   serdes_model serdes_model
+     (.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb), .ser_t(ser_t),
+      .ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb), .ser_r(ser_r),
+      .even(0),.error(0) );
+
+   adc_model adc_model
+     (.clk(dsp_clk),.rst(0),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_on_a(adc_on_a),.adc_oe_a(adc_oe_a),
+      .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) );
+
+   wire [2:0] speed;
+   phy_sim phy_model
+     (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK),
+      .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD),
+      .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD),
+      .Crs(GMII_CRS), .Col(GMII_COL),
+      .Speed(speed), .Done(0) );
+   pullup p3(MDIO);
+   
+   miim_model miim_model
+     (.mdc_i(MDC),.mdio(MDIO),.phy_resetn_i(PHY_RESETn),.phy_clk_i(PHY_CLK),
+      .phy_intn_o(PHY_INTn),.speed_o(speed) );
+   
+   xlnx_glbl glbl (.GSR(),.GTS());
+
+   wire       RAM_MODE = 1'b0;
+   cy1356 ram_model(.d(RAM_D),.clk(RAM_CLK),.a(RAM_A),
+		    .bws(2'b00),.we_b(RAM_WEn),.adv_lb(RAM_LDn),
+		    .ce1b(RAM_CE1n),.ce2(1'b1),.ce3b(1'b0),
+		    .oeb(RAM_OEn),.cenb(RAM_CENn),.mode(RAM_MODE) );
+   
+   M24LC024B eeprom_model(.A0(0),.A1(0),.A2(0),.WP(0),
+			  .SDA(SDA),.SCL(SCL),.RESET(0));
+
+   wire       scl_pad_i, scl_pad_o, scl_pad_oen_o;
+   wire       sda_pad_i, sda_pad_o, sda_pad_oen_o;
+   
+   pullup p1(SCL);
+   pullup p2(SDA);
+
+   assign     scl_pad_i = SCL;
+   assign     sda_pad_i = SDA;
+
+   assign     SCL = scl_pad_oen_o ? 1'bz : scl_pad_o;
+   assign     SDA = sda_pad_oen_o ? 1'bz : sda_pad_o;
+
+   // printf output
+   wire       uart_baud_o, uart_tx_o, uart_rx_i;
+   assign     uart_rx_i = 1'b1;
+   
+   uart_rx uart_rx(.baudclk(uart_baud_o),.rxd(uart_tx_o));
+   
+   // End the simulation
+   always @(posedge wb_clk)
+     if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0))
+       begin
+	  $display($time, "Finish called.",);
+	  $finish;
+       end
+   
+   u2_core #(.RAM_SIZE(32768))
+            u2_core(.dsp_clk		(dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready	(clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN),
+		     .GMII_TX_ER	(GMII_TX_ER),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk),
+		     .ser_t		(ser_t[15:0]),
+		     .ser_tklsb		(ser_tklsb),
+		     .ser_tkmsb		(ser_tkmsb),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r[15:0]),
+		     .ser_rklsb		(ser_rklsb),
+		     .ser_rkmsb		(ser_rkmsb),
+		     .cpld_start	(cpld_start),
+		     .cpld_mode		(cpld_mode),
+		     .cpld_done		(cpld_done),
+		     .cpld_din		(cpld_din),
+		     .cpld_clk		(cpld_clk),
+		     .cpld_detached	(cpld_detached),
+		     .cpld_init_b       (1),
+		     .por               (0),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(adc_ovf_a),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(adc_ovf_b),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a[15:0]),
+		     .dac_b		(dac_b[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn),
+		     .uart_tx_o         (uart_tx_o),
+		     .uart_rx_i         (uart_rx_i),
+		     .uart_baud_o       (uart_baud_o),
+		     .sim_mode          (1'b1),
+		     .clock_divider     (clock_divider)
+		     );
+
+endmodule // single_u2_sim
diff --git a/fpga/usrp2/top/tcl/ise_helper.tcl b/fpga/usrp2/top/tcl/ise_helper.tcl
new file mode 100644
index 000000000..fe9db87af
--- /dev/null
+++ b/fpga/usrp2/top/tcl/ise_helper.tcl
@@ -0,0 +1,89 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+proc set_props {process options} {
+	if ![string compare $options ""] {
+		return
+	}
+	set state 1
+	foreach opt $options {
+		if $state {
+			set key $opt
+			set state 0
+		} else {
+			puts ">>> Setting: $process\[$key\] = $opt" 
+			if ![string compare $process "Project"] {
+				project set $key $opt
+			} else {
+				project set $key $opt -process $process
+			}
+			set state 1	
+		}
+	}
+}
+
+if [file isfile $env(PROJ_FILE)] {
+	puts ">>> Opening project: $env(PROJ_FILE)"
+	project open $env(PROJ_FILE)
+} else {	
+	puts ">>> Creating project: $env(PROJ_FILE)"
+	project new $env(PROJ_FILE)
+	
+	##################################################
+	# Set the project properties
+	##################################################
+	set_props "Project" $env(PROJECT_PROPERTIES)
+	
+	##################################################
+	# Add the sources
+	##################################################
+	foreach source $env(SOURCES) {
+		set source $env(SOURCE_ROOT)$source
+		puts ">>> Adding source to project: $source"
+		xfile add $source
+	}
+	
+	##################################################
+	# Set the top level module
+	##################################################
+	project set top $env(TOP_MODULE)
+	
+	##################################################
+	# Set the process properties
+	##################################################
+	set_props "Synthesize - XST" $env(SYNTHESIZE_PROPERTIES)
+	set_props "Translate" $env(TRANSLATE_PROPERTIES)
+	set_props "Map" $env(MAP_PROPERTIES)
+	set_props "Place & Route" $env(PLACE_ROUTE_PROPERTIES)
+	set_props "Generate Post-Place & Route Static Timing" $env(STATIC_TIMING_PROPERTIES)
+	set_props "Generate Programming File" $env(GEN_PROG_FILE_PROPERTIES)
+	set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES)
+}
+
+if [string compare $env(PROCESS_RUN) ""] {
+	puts ">>> Running Process: $env(PROCESS_RUN)"
+	process run $env(PROCESS_RUN)
+}
+
+project close
+exit
+
+
diff --git a/fpga/usrp2/top/u2_core/.gitignore b/fpga/usrp2/top/u2_core/.gitignore
new file mode 100644
index 000000000..9728395c1
--- /dev/null
+++ b/fpga/usrp2/top/u2_core/.gitignore
@@ -0,0 +1,44 @@
+*~
+/xst
+/_ngo
+/_xmsgs
+/*.stx
+/*.tspec
+/*.xml
+/*.gyd
+/*.ngr
+/*.tim
+/*.err
+/*.lso
+/*.bld
+/*.cmd_log
+/*.ise_ISE_Backup
+/*.mfd
+/*.vm6
+/*.syr
+/*.xst
+/*.csv
+/*.html
+/*.jed
+/*.pad
+/*.ng*
+/*.pnx
+/*.rpt
+/*.prj
+/*_html
+/*_log
+/*.lfp
+/*.bit
+/*.bin
+/*.vcd
+/*.unroutes
+/*.drc
+/*_map.*
+/*_guide.*
+/*.twr
+/*.twx
+/a.out
+/*.xpi
+/*_pad.txt
+/*.bgn
+/*.par
diff --git a/fpga/usrp2/top/u2_core/u2_core.v b/fpga/usrp2/top/u2_core/u2_core.v
new file mode 100644
index 000000000..cd0199005
--- /dev/null
+++ b/fpga/usrp2/top/u2_core/u2_core.v
@@ -0,0 +1,867 @@
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2_core
+  #(parameter RAM_SIZE=32768)
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output [7:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in,
+   output exp_pps_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
+   output cpld_misc,
+   input cpld_init_b,
+   input por,
+   output config_success,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_on_a,
+   output adc_oe_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_on_b,
+   output adc_oe_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // External RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // Debug stuff
+   output uart_tx_o, 
+   input uart_rx_i,
+   output uart_baud_o,
+   input sim_mode,
+   input [3:0] clock_divider
+   );
+
+   localparam SR_BUF_POOL = 64;   // Uses 1 reg
+   localparam SR_UDP_SM   = 96;   // 64 regs
+   localparam SR_RX_DSP   = 160;  // 16
+   localparam SR_RX_CTRL  = 176;  // 16
+   localparam SR_TIME64   = 192;  //  3
+   localparam SR_SIMTIMER = 198;  //  2
+   localparam SR_TX_DSP   = 208;  // 16
+   localparam SR_TX_CTRL  = 224;  // 16
+
+   // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
+   // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
+   localparam DSP_TX_FIFOSIZE = 10;
+   localparam DSP_RX_FIFOSIZE = 10;
+   localparam ETH_TX_FIFOSIZE = 10;
+   localparam ETH_RX_FIFOSIZE = 11;
+   localparam SERDES_TX_FIFOSIZE = 9;
+   localparam SERDES_RX_FIFOSIZE = 9;  // RX currently doesn't use a fifo?
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+   
+   wire 	ram_loader_done;
+   wire 	ram_loader_rst, wb_rst, dsp_rst;
+
+   wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+   wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
+   wire 	proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   wire [31:0] 	atr_lines;
+
+   wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+
+   wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire 	ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+	
+   wire 	serdes_link_up;
+   wire 	epoch;
+   wire [31:0] 	irq;
+   wire [63:0] 	vita_time;
+   
+   // ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   localparam 	dw = 32;  // Data bus width
+   localparam 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   localparam	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+   
+   wire [dw-1:0] m0_dat_o, m0_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc;
+   wire 	 m0_err, m0_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we;
+   
+   wb_1master #(.decode_w(6),
+		.s0_addr(6'b0000_00),.s0_mask(6'b100000),
+		.s1_addr(6'b1000_00),.s1_mask(6'b110000),
+ 		.s2_addr(6'b1100_00),.s2_mask(6'b111111),
+		.s3_addr(6'b1100_01),.s3_mask(6'b111111),
+		.s4_addr(6'b1100_10),.s4_mask(6'b111111),
+		.s5_addr(6'b1100_11),.s5_mask(6'b111111),
+		.s6_addr(6'b1101_00),.s6_mask(6'b111111),
+		.s7_addr(6'b1101_01),.s7_mask(6'b111111),
+		.s8_addr(6'b1101_10),.s8_mask(6'b111111),
+		.s9_addr(6'b1101_11),.s9_mask(6'b111111),
+		.sa_addr(6'b1110_00),.sa_mask(6'b111111),
+		.sb_addr(6'b1110_01),.sb_mask(6'b111111),
+		.sc_addr(6'b1110_10),.sc_mask(6'b111111),
+		.sd_addr(6'b1110_11),.sd_mask(6'b111111),
+		.se_addr(6'b1111_00),.se_mask(6'b111111),
+		.sf_addr(6'b1111_01),.sf_mask(6'b111111),
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_i(0),.sf_ack_i(0),.sf_err_i(0),.sf_rty_i(0)  );
+   
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
+			   .ram_loader_rst_o(ram_loader_rst),
+			   .wb_rst_o(wb_rst),
+			   .ram_loader_done_i(ram_loader_done));
+
+   assign 	 config_success = ram_loader_done;
+   reg 		 takeover = 0;
+
+   wire 	 cpld_start_int, cpld_mode_int, cpld_done_int;
+   
+   always @(posedge wb_clk)
+     if(ram_loader_done)
+       takeover = 1;
+   assign 	 cpld_misc = ~takeover;
+
+   wire 	 sd_clk, sd_csn, sd_mosi, sd_miso;
+   
+   assign 	 sd_miso = cpld_din;
+   assign 	 cpld_start = takeover ? sd_clk	: cpld_start_int;
+   assign 	 cpld_mode = takeover ? sd_csn : cpld_mode_int;
+   assign 	 cpld_done = takeover ? sd_mosi : cpld_done_int;
+   
+   // ///////////////////////////////////////////////////////////////////
+   // RAM Loader
+
+   wire [31:0] 	 ram_loader_dat, iwb_dat;
+   wire [15:0] 	 ram_loader_adr, iwb_adr;
+   wire [3:0] 	 ram_loader_sel;
+   wire 	 ram_loader_stb, ram_loader_we, ram_loader_ack;
+   wire 	 iwb_ack, iwb_stb;
+   ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
+     ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+		 // CPLD Interface
+		 .cfg_clk_i(cpld_clk),
+		 .cfg_data_i(cpld_din),
+		 .start_o(cpld_start_int),
+		 .mode_o(cpld_mode_int),
+		 .done_o(cpld_done_int),
+		 .detached_i(cpld_detached),
+		 // Wishbone Interface
+		 .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
+		 .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
+		 .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
+		 .ram_loader_done_o(ram_loader_done));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Processor
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+	   // Instruction Wishbone bus to I-RAM
+	   .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+	   .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+	   // Data Wishbone bus to system bus fabric
+	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+   
+   assign 	 bus_error = m0_err | m0_rty;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+   // I-port connects directly to processor and ram loader
+
+   wire 	 flush_icache;
+   ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+     sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+	     
+	     .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
+	     .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
+	     .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+	     .ram_loader_done_i(ram_loader_done),
+	     
+	     .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
+	     .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+	     
+	     .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
+	     .flush_icache(flush_icache));
+   
+   setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					 .in(set_data),.out(),.changed(flush_icache));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool, slave #1
+   wire 	 rd0_ready_i, rd0_ready_o;
+   wire 	 rd1_ready_i, rd1_ready_o;
+   wire 	 rd2_ready_i, rd2_ready_o;
+   wire 	 rd3_ready_i, rd3_ready_o;
+   wire [3:0] 	 rd0_flags, rd1_flags, rd2_flags, rd3_flags;
+   wire [31:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_ready_i, wr0_ready_o;
+   wire 	 wr1_ready_i, wr1_ready_o;
+   wire 	 wr2_ready_i, wr2_ready_o;
+   wire 	 wr3_ready_i, wr3_ready_o;
+   wire [3:0] 	 wr0_flags, wr1_flags, wr2_flags, wr3_flags;
+   wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+   
+   buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
+   
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .status(status),.sys_int_o(buffer_int),
+
+      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+
+      // Write Interfaces
+      .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o),
+      .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o),
+      .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o),
+      .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o),
+      // Read Interfaces
+      .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o),
+      .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o),
+      .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o),
+      .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o)
+      );
+
+   wire [31:0] 	 status_enc;
+   priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+      .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
+      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_i[31:8] = 24'd0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs -- Slave #4
+   nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		 .gpio( {io_tx,io_rx} ) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool Status -- Slave #5   
+   
+   reg [31:0] 	 cycle_count;
+   always @(posedge wb_clk)
+     if(wb_rst)
+       cycle_count <= 0;
+     else
+       cycle_count <= cycle_count + 1;
+   
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
+      
+      .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+      .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
+      .word11(vita_time[31:0]),.word12(32'b0),.word13(irq),.word14(status_enc),.word15(cycle_count)
+      );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC  Slave #6
+
+   wire [18:0] 	 rx_f19_data, tx_f19_data;
+   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy;
+   
+   simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+     (.clk125(clk_to_mac),  .reset(wb_rst),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .sys_clk(dsp_clk),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
+      .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
+      .mdio(MDIO), .mdc(MDC),
+      .debug(debug_mac));
+
+   wire [35:0] 	 udp_tx_data, udp_rx_data;
+   wire 	 udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy;
+   
+   udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy),
+      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy),
+      .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy),
+      .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy),
+      .debug(debug_udp) );
+
+   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
+      .dataout(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy));
+
+   fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy),
+      .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_dat_i = 32'd0;
+
+   // Output control lines
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+   wire 	 phy_reset;
+   assign 	 PHY_RESETn = ~phy_reset;
+   
+   setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+				      .in(set_data),.out(clock_outs),.changed());
+   setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(serdes_outs),.changed());
+   setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(adc_outs),.changed());
+   setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(phy_reset),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
+   //  LEDS
+   //    register 8 determines whether leds are controlled by SW or not
+   //    1 = controlled by HW, 0 = by SW
+   //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+   
+   wire [7:0] 	 led_src, led_sw;
+   wire [7:0] 	 led_hw = {clk_status,serdes_link_up};
+   
+   setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(led_sw),.changed());
+   setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					  .in(set_data),.out(led_src),.changed());
+
+   assign 	 leds = (led_src & led_hw) | (~led_src & led_sw);
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+
+   assign irq= {{8'b0},
+		{8'b0},
+		{3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+		{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
+   
+   pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
+	   .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+	   .irq(irq) );
+ 	 
+   // /////////////////////////////////////////////////////////////////////////
+   // Master Timer, Slave #9
+
+   // No longer used, replaced with simple_timer below
+   /*
+   wire [31:0] 	 master_time;
+   timer timer
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
+      .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
+      .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
+    */
+   assign s9_ack = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   //  Simple Timer interrupts
+   
+   simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
+     (.clk(wb_clk), .reset(wb_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .onetime_int(onetime_int), .periodic_int(periodic_int));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+      .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller, Slave #11
+
+   wire 	 run_rx, run_tx;
+   reg 		 run_rx_d1;
+   always @(posedge dsp_clk)
+     run_rx_d1 <= run_rx;
+   
+   atr_controller atr_controller
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
+      .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
+      .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   
+   // //////////////////////////////////////////////////////////////////////////
+   // Time Sync, Slave #12 
+
+   // No longer used, see time_64bit.  Still need to handle mimo time, though
+   assign sc_ack = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SD Card Reader / Writer, Slave #13
+
+   sd_spi_wb sd_spi_wb
+     (.clk(wb_clk),.rst(wb_rst),
+      .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+      .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
+      .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]),
+      .wb_ack_o(sd_ack) );
+
+   assign sd_dat_i[31:8] = 0;
+
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+   wire 	 rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy;
+   wire [99:0] 	 rx_data;
+   wire [35:0] 	 rx1_data;
+   
+   dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   wire [31:0] 	 vrc_debug;
+   
+   vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time), .overrun(overrun),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy),
+      .debug_rx(vrc_debug));
+
+   wire [3:0] 	 vita_state;
+   
+   vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
+      .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty(),
+      .debug_rx(vita_state) );
+
+   fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
+      .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [35:0] 	 tx_data;
+   wire [99:0] 	 tx1_data;
+   wire 	 tx_src_rdy, tx_dst_rdy, tx1_src_rdy, tx1_dst_rdy;
+
+   wire [31:0] 	 debug_vtc, debug_vtd, debug_vt;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
+      .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
+
+   vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .data_i(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+      .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
+      .debug(debug_vtd) );
+
+   vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .vita_time(vita_time),.underrun(underrun),
+      .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug(debug_vtc) );
+   
+   assign debug_vt = debug_vtc | debug_vtd;
+   
+   dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .debug(debug_tx_dsp) );
+
+   assign dsp_rst = wb_rst;
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+
+   serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // External RAM Interface
+
+   localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
+
+   wire [15:0] bus2ram, ram2bus;
+   wire [15:0] bridge_adr;
+   wire [1:0]  bridge_sel;
+   wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
+   
+   wire [19:0] page;
+   wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
+   setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				       .in(set_data),.out(page),.changed());
+
+   wb_bridge_16_32 bridge
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),
+      .A_cyc_i(se_cyc),.A_stb_i(se_stb),.A_we_i(se_we),.A_sel_i(se_sel),
+      .A_adr_i(se_adr),.A_dat_i(se_dat_o),.A_dat_o(se_dat_i),.A_ack_o(se_ack),
+      .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
+      .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
+
+   wb_zbt16_b wb_zbt16_b
+     (.clk(wb_clk),.rst(wb_rst),
+      .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
+      .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
+      .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
+      .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
+      .sram_mode(),.sram_zz() );
+
+   assign      RAM_CE1n = 0;
+   assign      RAM_D[17:16] = 2'bzz;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+   
+   // /////////////////////////////////////////////////////////////////////////////////////////
+   // Debug Pins
+   
+   // FIFO Level Debugging
+   reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
+   
+   always @(posedge dsp_clk)
+     serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
+			     {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+
+   always @(posedge dsp_clk)
+     dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
+			     {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
+			   {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
+			   {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
+			{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+   
+   assign  debug_clk[0]  = GMII_RX_CLK; // wb_clk;
+   assign  debug_clk[1]  = dsp_clk;
+
+/*
+ 
+   wire        mdio_cpy  = MDIO;
+   assign  debug 	 = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] },
+			     { s6_adr[15:8] },
+			     { s6_adr[7:0] },
+			     { 6'd0, mdio_cpy, MDC } };
+*/
+/*
+   assign debug 	 = { { GMII_TXD },
+			     { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
+			     { wr2_flags, rd2_flags },
+			     { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
+   assign debug 	 = { { GMII_RXD },
+			     { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
+			     { wr2_flags, rd2_flags },
+			     { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
+ */
+
+//   assign debug = debug_udp;
+   assign debug = vrc_debug;
+   assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state},
+			   {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]},
+			   {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , 
+			   {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}};
+
+   assign debug_gpio_1 = {vita_time[63:32] };
+   
+/*
+    assign debug_gpio_1 = { { tx_f19_data[15:8] },
+			   { tx_f19_data[7:0] },
+			   { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] },
+			   { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } };
+ */  
+   
+endmodule // u2_core
+
+//   wire        debug_mux;
+//   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+//					.in(set_data),.out(debug_mux),.changed());
+
+//assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+//assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
+   
+//assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+//		{run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+//assign      debug = debug_tx_dsp;
+//assign      debug = debug_serdes0;
+
+//assign      debug_gpio_0 = 0; //debug_serdes0;
+//assign      debug_gpio_1 = 0; //debug_serdes1;
+
+//   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
+//	      {8'b0},
+//      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
+//    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
+
+//assign      debug = {dac_a,dac_b};
+
+/*
+ assign      debug = {{ram_loader_done, takeover, 6'd0},
+ {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
+ {8'd0},
+ {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
+
+/*assign      debug = host_to_dsp_fifo;
+ assign      debug_gpio_0 = eth_mac_debug;
+ assign      debug_gpio_1 = 0;
+ */
+// Assign various commonly used debug buses.
+/*
+ wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+ irq[7:0],
+ GMII_RXD,
+ GMII_TXD};
+ 
+ wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+   
+   wire [31:0] debug_time =  {uart_tx_o, 7'b0,
+			      irq[7:0],
+			      6'b0, GMII_RX_DV, GMII_TX_EN,
+			      4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
+
+   wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
+			     irq[7:0],
+			     proc_int,  7'b0 };
+
+   wire [31:0] debug_eth = 
+	       {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+		{8'd0},
+		{8'd0},
+		{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
+
+   assign      debug_serdes0 = { { rd0_dat[7:0] },
+				 { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
+				 { ser_t[15:8] },
+				 { ser_t[7:0] } };
+
+   assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
+				 { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
+				 { ser_r[15:8] },
+				 { ser_r[7:0] } };
+       
+   assign      debug_gpio_1 = {uart_tx_o,7'd0,
+			       3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
+			       debug_txc[15:0]};
+   assign      debug_gpio_1 = debug_rx;
+   assign      debug_gpio_1 = debug_serdes1;
+   assign      debug_gpio_1 = debug_eth;
+      
+    */
+      
diff --git a/fpga/usrp2/top/u2_rev1/.gitignore b/fpga/usrp2/top/u2_rev1/.gitignore
new file mode 100644
index 000000000..de5b50277
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev1/.gitignore
@@ -0,0 +1,52 @@
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
diff --git a/fpga/usrp2/top/u2_rev1/Makefile b/fpga/usrp2/top/u2_rev1/Makefile
new file mode 100644
index 000000000..b3245d883
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev1/Makefile
@@ -0,0 +1,129 @@
+FILENAME=u2_fpga_top
+PARTNUM=xc3s1500-5fg456
+
+all: project command xst ngd ncd ncd2 bit 
+
+xst: 
+	xst -ifn ${FILENAME}.cmd -ofn xst.log
+
+ngd: 
+	ngdbuild -nt timestamp -p ${PARTNUM} ${FILENAME}
+
+ncd: 
+	rm -rf ${FILENAME}.ncd
+	map -detail -cm speed -k 8 -retiming on -equivalent_register_removal on -timing -ol high -pr b -p ${PARTNUM} ${FILENAME}.ngd -o ${FILENAME}.ncd ${FILENAME}.pcf
+
+# Place and route ncd file into new ncd file
+ncd2:	
+	par -ol high -xe n -w ${FILENAME}.ncd ${FILENAME} ${FILENAME}.pcf
+
+bit:	
+	bitgen -w ${FILENAME}.ncd -b ${FILENAME}.bit
+
+clean:
+	@rm -rf ${FILENAME}.ngc *.lst *.bit *.lso *.xst *.stx *.syr \
+	*.ngr *.cmd_log _ngc _xmsgs xst *.html *.srp \
+	*.blc *.bld *.ise_ISE_Backup *~ \
+	*.pad *.ngm *.ngd *.par *.pcf *.unroutes     \
+	*.xpi *.bgn *.drc *.bin *.mrp *.csv *.txt    \
+	*.rbt *.ncd ${FILENAME} *_cg templates/ tmp/ \
+        output.dat coregen.log *.ngo *.log ${FILENAME}.map \
+	${FILENAME}_summary.xml ${FILENAME}_usage.xml ${FILENAME}.twr
+
+command:
+	rm -rf ${FILENAME}.cmd
+	@echo "identification"       >> ${FILENAME}.cmd
+	@echo "status"               >> ${FILENAME}.cmd
+	@echo "time short"           >> ${FILENAME}.cmd
+	@echo "memory on"            >> ${FILENAME}.cmd
+	@echo "run "	             >> ${FILENAME}.cmd
+	@echo "-top ${FILENAME}"     >> ${FILENAME}.cmd
+	@echo "-ifn ${FILENAME}.prj" >> ${FILENAME}.cmd
+	@echo "-ifmt Verilog "       >> ${FILENAME}.cmd
+	@echo "-ofn ${FILENAME} "    >> ${FILENAME}.cmd
+	@echo "-p ${PARTNUM}"        >> ${FILENAME}.cmd
+	@echo "-bufg 6"              >> ${FILENAME}.cmd
+	@echo "-vlgincdir { ../../opencores/i2c/rtl/verilog ../../eth/rtl/verilog/ ../../opencores/spi/rtl/verilog}"  >> ${FILENAME}.cmd
+
+project:
+	rm -f ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/TECH/duram.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/sign_extend.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cordic_stage.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_int_shifter.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_dec_shifter.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v" '   	>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_regfile.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_fetch.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_decode.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_control.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_aslu.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/miim/eth_shiftreg.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/miim/eth_outputcontrol.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/miim/eth_clockgen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/TECH/eth_clk_switch.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/TECH/eth_clk_div2.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/Reg_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON/RMON_dpram.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON/RMON_ctrl.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON/RMON_addr_gen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx/CRC_gen.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/CRC_chk.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ram_2port.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cordic.v" '   					>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_interp.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/cic_decim.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../opencores/spi/rtl/verilog/spi_shift.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/spi/rtl/verilog/spi_clgen.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v" '   	>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/eth_miim.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/RMON.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/Phy_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_tx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_rx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/Clk_ctrl.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/strobe_gen.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ss_rcvr.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/shortfifo.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/setting_reg.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/mux8.v" '   					>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/mux4.v" '   					>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/longfifo.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/decoder_3_8.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/buffer_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/CRC16_D16.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/tx_control.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/rx_control.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/dsp_core_tx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../sdr_lib/dsp_core_rx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../opencores/spi/rtl/verilog/spi_top.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/simple_pic/rtl/simple_pic.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/i2c/rtl/verilog/i2c_master_top.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v" '   		>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/MAC_top.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/mac_txfifo_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../eth/mac_rxfifo_int.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/wb_readback_mux.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/wb_1master.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/timer.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/system_control.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/settings_bus.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/serdes_tx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/serdes_rx.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ram_wb_harvard.v" '   			>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/ram_loader.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/nsgpio.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../../control_lib/buffer_pool.v" '   				>> ${FILENAME}.prj
+	@echo '`include "../u2_basic/u2_basic.v" '   					>> ${FILENAME}.prj
+	@echo '`include "u2_fpga_top.v" '   						>> ${FILENAME}.prj
+	@echo '`include "../../eth/rtl/verilog/elastic_buffer.v" '   			>> ${FILENAME}.prj
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga.ise b/fpga/usrp2/top/u2_rev1/u2_fpga.ise
new file mode 100644
index 000000000..f90caf024
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev1/u2_fpga.ise
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga.ucf b/fpga/usrp2/top/u2_rev1/u2_fpga.ucf
new file mode 100755
index 000000000..5d2124819
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev1/u2_fpga.ucf
@@ -0,0 +1,341 @@
+NET "adc_a[0]"  LOC = "A14"  ;
+NET "adc_a[10]"  LOC = "D20"  ;
+NET "adc_a[11]"  LOC = "D19"  ;
+NET "adc_a[12]"  LOC = "D21"  ;
+NET "adc_a[13]"  LOC = "E18"  ;
+NET "adc_a[1]"  LOC = "B14"  ;
+NET "adc_a[2]"  LOC = "C13"  ;
+NET "adc_a[3]"  LOC = "D13"  ;
+NET "adc_a[4]"  LOC = "A13"  ;
+NET "adc_a[5]"  LOC = "B13"  ;
+NET "adc_a[6]"  LOC = "E12"  ;
+NET "adc_a[7]"  LOC = "C22"  ;
+NET "adc_a[8]"  LOC = "C20"  ;
+NET "adc_a[9]"  LOC = "C21"  ;
+NET "adc_b[0]"  LOC = "A12"  ;
+NET "adc_b[10]"  LOC = "D18"  ;
+NET "adc_b[11]"  LOC = "B18"  ;
+NET "adc_b[12]"  LOC = "D17"  ;
+NET "adc_b[13]"  LOC = "E17"  ;
+NET "adc_b[1]"  LOC = "E16"  ;
+NET "adc_b[2]"  LOC = "F12"  ;
+NET "adc_b[3]"  LOC = "F13"  ;
+NET "adc_b[4]"  LOC = "F16"  ;
+NET "adc_b[5]"  LOC = "F17"  ;
+NET "adc_b[6]"  LOC = "C19"  ;
+NET "adc_b[7]"  LOC = "B20"  ;
+NET "adc_b[8]"  LOC = "B19"  ;
+NET "adc_b[9]"  LOC = "C18"  ;
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_TXD[0]"  LOC = "W14"  ;
+NET "GMII_TXD[1]"  LOC = "AA20"  ;
+NET "GMII_TXD[2]"  LOC = "AB20"  ;
+NET "GMII_TXD[3]"  LOC = "Y18"  ;
+NET "GMII_TXD[4]"  LOC = "AA18"  ;
+NET "GMII_TXD[5]"  LOC = "AB18"  ;
+NET "GMII_TXD[6]"  LOC = "V17"  ;
+NET "GMII_TXD[7]"  LOC = "W17"  ;
+NET "io_rx[0]"  LOC = "L21"  ;
+NET "io_rx[10]"  LOC = "F21"  ;
+NET "io_rx[11]"  LOC = "F20"  ;
+NET "io_rx[12]"  LOC = "G19"  ;
+NET "io_rx[13]"  LOC = "G18"  ;
+NET "io_rx[14]"  LOC = "G17"  ;
+NET "io_rx[15]"  LOC = "E22"  ;
+NET "io_rx[1]"  LOC = "L20"  ;
+NET "io_rx[2]"  LOC = "L19"  ;
+NET "io_rx[3]"  LOC = "L18"  ;
+NET "io_rx[4]"  LOC = "L17"  ;
+NET "io_rx[5]"  LOC = "K22"  ;
+NET "io_rx[6]"  LOC = "K21"  ;
+NET "io_rx[7]"  LOC = "K20"  ;
+NET "io_rx[8]"  LOC = "G22"  ;
+NET "io_rx[9]"  LOC = "G21"  ;
+NET "io_tx[0]"  LOC = "K4"  ;
+NET "io_tx[10]"  LOC = "E1"  ;
+NET "io_tx[11]"  LOC = "E3"  ;
+NET "io_tx[12]"  LOC = "F4"  ;
+NET "io_tx[13]"  LOC = "D2"  ;
+NET "io_tx[14]"  LOC = "D4"  ;
+NET "io_tx[15]"  LOC = "E4"  ;
+NET "io_tx[1]"  LOC = "K3"  ;
+NET "io_tx[2]"  LOC = "G1"  ;
+NET "io_tx[3]"  LOC = "G5"  ;
+NET "io_tx[4]"  LOC = "H5"  ;
+NET "io_tx[5]"  LOC = "F3"  ;
+NET "io_tx[6]"  LOC = "F2"  ;
+NET "io_tx[7]"  LOC = "F5"  ;
+NET "io_tx[8]"  LOC = "G6"  ;
+NET "io_tx[9]"  LOC = "E2"  ;
+NET "RAM_A[0]"  LOC = "N22"  ;
+NET "RAM_A[10]"  LOC = "P18"  ;
+NET "RAM_A[11]"  LOC = "R19"  ;
+NET "RAM_A[12]"  LOC = "P19"  ;
+NET "RAM_A[13]"  LOC = "R21"  ;
+NET "RAM_A[14]"  LOC = "R22"  ;
+NET "RAM_A[15]"  LOC = "T19"  ;
+NET "RAM_A[16]"  LOC = "T20"  ;
+NET "RAM_A[17]"  LOC = "U20"  ;
+NET "RAM_A[18]"  LOC = "W19"  ;
+NET "RAM_A[1]"  LOC = "N20"  ;
+NET "RAM_A[2]"  LOC = "T21"  ;
+NET "RAM_A[3]"  LOC = "M22"  ;
+NET "RAM_A[4]"  LOC = "N19"  ;
+NET "RAM_A[5]"  LOC = "N17"  ;
+NET "RAM_A[6]"  LOC = "N18"  ;
+NET "RAM_A[7]"  LOC = "P21"  ;
+NET "RAM_A[8]"  LOC = "P22"  ;
+NET "RAM_A[9]"  LOC = "P17"  ;
+NET "RAM_D[0]"  LOC = "Y21"  ;
+NET "RAM_D[10]"  LOC = "V22"  ;
+NET "RAM_D[11]"  LOC = "V21"  ;
+NET "RAM_D[12]"  LOC = "T17"  ;
+NET "RAM_D[13]"  LOC = "U18"  ;
+NET "RAM_D[14]"  LOC = "U21"  ;
+NET "RAM_D[15]"  LOC = "R18"  ;
+NET "RAM_D[16]"  LOC = "T18"  ;
+NET "RAM_D[17]"  LOC = "T22"  ;
+NET "RAM_D[1]"  LOC = "Y20"  ;
+NET "RAM_D[2]"  LOC = "Y19"  ;
+NET "RAM_D[3]"  LOC = "W22"  ;
+NET "RAM_D[4]"  LOC = "Y22"  ;
+NET "RAM_D[5]"  LOC = "V19"  ;
+NET "RAM_D[6]"  LOC = "W21"  ;
+NET "RAM_D[7]"  LOC = "W20"  ;
+NET "RAM_D[8]"  LOC = "U19"  ;
+NET "RAM_D[9]"  LOC = "V20"  ;
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_t[0]"  LOC = "V7"  ;
+NET "ser_t[10]"  LOC = "AA6"  ;
+NET "ser_t[11]"  LOC = "Y6"  ;
+NET "ser_t[12]"  LOC = "W8"  ;
+NET "ser_t[13]"  LOC = "V8"  ;
+NET "ser_t[14]"  LOC = "AB8"  ;
+NET "ser_t[15]"  LOC = "AA8"  ;
+NET "ser_t[1]"  LOC = "V10"  ;
+NET "ser_t[2]"  LOC = "AB4"  ;
+NET "ser_t[3]"  LOC = "AA4"  ;
+NET "ser_t[4]"  LOC = "Y5"  ;
+NET "ser_t[5]"  LOC = "W5"  ;
+NET "ser_t[6]"  LOC = "AB5"  ;
+NET "ser_t[7]"  LOC = "AA5"  ;
+NET "ser_t[8]"  LOC = "W6"  ;
+NET "ser_t[9]"  LOC = "V6"  ;
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "exp_pps_in_n"  LOC = "V4"  ; 
+NET "exp_pps_in_p"  LOC = "V3"  ; 
+NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "exp_pps_out_p"  LOC = "V1"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_RX_CLK"  LOC = "W16"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_TX_EN"  LOC = "Y17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "led1"  LOC = "V11"  ; 
+NET "led2"  LOC = "Y12"  ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "MDIO"  LOC = "Y16" | PULLUP ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "pps_in"  LOC = "Y11"  ; 
+NET "RAM_CE1n"  LOC = "N21"  ; 
+NET "RAM_CENn"  LOC = "M18"  ; 
+NET "RAM_CLK"  LOC = "M17"  ; 
+NET "RAM_LDn"  LOC = "M21"  ; 
+NET "RAM_OEn"  LOC = "M19"  ; 
+NET "RAM_WEn"  LOC = "M20"  ; 
+NET "SCL"  LOC = "A7"  ; 
+NET "SCL_force"  LOC = "E8"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "SDA_force"  LOC = "C11"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_rklsb"  LOC = "V9"  ; 
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tklsb"  LOC = "U10" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_tx_clk"  LOC = "U7" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ; 
+NET "ser_t<0>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<1>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<2>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<3>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<4>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<5>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<6>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<7>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<8>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<9>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<10>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<11>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<12>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<13>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<14>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "ser_t<15>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj b/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj
new file mode 100644
index 000000000..544415f4d
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev1/u2_fpga_top.prj
@@ -0,0 +1,102 @@
+verilog work "../../opencores/uart16550/rtl/verilog/raminfr.v"
+verilog work "../../control_lib/ram_2port.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
+verilog work "../../coregen/fifo_generator_v4_1.v"
+verilog work "../../control_lib/shortfifo.v"
+verilog work "../../control_lib/longfifo.v"
+verilog work "../../sdr_lib/sign_extend.v"
+verilog work "../../sdr_lib/cordic_stage.v"
+verilog work "../../sdr_lib/cic_int_shifter.v"
+verilog work "../../sdr_lib/cic_dec_shifter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_transmitter.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_sync_flops.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_receiver.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_xecu.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_regf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
+verilog work "../../opencores/8b10b/encode_8b10b.v"
+verilog work "../../opencores/8b10b/decode_8b10b.v"
+verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
+verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
+verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
+verilog work "../../eth/rtl/verilog/Reg_int.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
+verilog work "../../control_lib/ss_rcvr.v"
+verilog work "../../control_lib/cascadefifo2.v"
+verilog work "../../control_lib/CRC16_D16.v"
+verilog work "../../timing/time_sender.v"
+verilog work "../../timing/time_receiver.v"
+verilog work "../../serdes/serdes_tx.v"
+verilog work "../../serdes/serdes_rx.v"
+verilog work "../../serdes/serdes_fc_tx.v"
+verilog work "../../serdes/serdes_fc_rx.v"
+verilog work "../../sdr_lib/round.v"
+verilog work "../../sdr_lib/cordic.v"
+verilog work "../../sdr_lib/cic_interp.v"
+verilog work "../../sdr_lib/cic_decim.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_wb.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_regs.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_debug_if.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_shift.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
+verilog work "../../eth/rtl/verilog/eth_miim.v"
+verilog work "../../eth/rtl/verilog/RMON.v"
+verilog work "../../eth/rtl/verilog/Phy_int.v"
+verilog work "../../eth/rtl/verilog/MAC_tx.v"
+verilog work "../../eth/rtl/verilog/MAC_rx.v"
+verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
+verilog work "../../control_lib/strobe_gen.v"
+verilog work "../../control_lib/setting_reg.v"
+verilog work "../../control_lib/mux8.v"
+verilog work "../../control_lib/mux4.v"
+verilog work "../../control_lib/icache.v"
+verilog work "../../control_lib/dpram32.v"
+verilog work "../../control_lib/decoder_3_8.v"
+verilog work "../../control_lib/dcache.v"
+verilog work "../../control_lib/buffer_int.v"
+verilog work "../../timing/timer.v"
+verilog work "../../timing/time_sync.v"
+verilog work "../../serdes/serdes.v"
+verilog work "../../sdr_lib/tx_control.v"
+verilog work "../../sdr_lib/rx_control.v"
+verilog work "../../sdr_lib/dsp_core_tx.v"
+verilog work "../../sdr_lib/dsp_core_rx.v"
+verilog work "../../opencores/uart16550/rtl/verilog/uart_top.v"
+verilog work "../../opencores/spi/rtl/verilog/spi_top.v"
+verilog work "../../opencores/simple_pic/rtl/simple_pic.v"
+verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
+verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
+verilog work "../../eth/rtl/verilog/MAC_top.v"
+verilog work "../../eth/mac_txfifo_int.v"
+verilog work "../../eth/mac_rxfifo_int.v"
+verilog work "../../control_lib/wb_readback_mux.v"
+verilog work "../../control_lib/wb_1master.v"
+verilog work "../../control_lib/system_control.v"
+verilog work "../../control_lib/settings_bus.v"
+verilog work "../../control_lib/ram_loader.v"
+verilog work "../../control_lib/ram_harv_cache.v"
+verilog work "../../control_lib/nsgpio.v"
+verilog work "../../control_lib/extram_interface.v"
+verilog work "../../control_lib/buffer_pool.v"
+verilog work "../../control_lib/atr_controller.v"
+verilog work "../u2_basic/u2_basic.v"
+verilog work "u2_fpga_top.v"
diff --git a/fpga/usrp2/top/u2_rev1/u2_fpga_top.v b/fpga/usrp2/top/u2_rev1/u2_fpga_top.v
new file mode 100644
index 000000000..63798a0c8
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev1/u2_fpga_top.v
@@ -0,0 +1,393 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_fpga_top
+  (
+   // Misc, debug
+   output led1,
+   output led2,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,  // AA9
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
+   input cpld_din,     // AA14 Now shared with CFG_Din
+   input cpld_clk,     // AB14 serial clock
+
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   inout SCL,
+   inout SDA,
+   input SCL_force,
+   input SDA_force,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   input sdo_tx_db,
+   output sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   input sdo_tx_adc,
+   output sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout [15:0] io_tx,
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+   
+   inout [15:0] io_rx
+   );
+
+   // FPGA-specific pins connections
+   wire 	aux_clk = PHY_CLK;
+   //wire 	cpld_detached = RAM_A[14]; // FIXME  Hacked on with Blue Wire
+   wire 	cpld_detached = SDA_force; // FIXME  Hacked on with Blue Wire
+
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge aux_clk)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   wire 	clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_muxed), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(), 
+                 .CLK180(), 
+                 .CLK270(), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire 	led1_int, led2_int;
+   assign 	led1 = ~led1_int;
+   assign 	led2 = ~led2_int;
+
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+   
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_basic u2_basic(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .led1		(led1_int),
+		     .led2		(led2_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .PHY_CLK		(PHY_CLK),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(adc_ovf_a),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(adc_ovf_b),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a[15:0]),
+		     .dac_b		(dac_b[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (),
+		     .uart_rx_i         (),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2_fpga_top
diff --git a/fpga/usrp2/top/u2_rev2/.gitignore b/fpga/usrp2/top/u2_rev2/.gitignore
new file mode 100644
index 000000000..432f8fd58
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev2/.gitignore
@@ -0,0 +1,57 @@
+/*.ptwx
+/*.xrpt
+/*.zip
+/*_xdb
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
+/build
diff --git a/fpga/usrp2/top/u2_rev2/Makefile b/fpga/usrp2/top/u2_rev2/Makefile
new file mode 100644
index 000000000..275c24b02
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev2/Makefile
@@ -0,0 +1,248 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev2
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev2/u2_rev2.ucf \
+top/u2_rev2/u2_rev2.v 
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+
diff --git a/fpga/usrp2/top/u2_rev2/u2_rev2.ucf b/fpga/usrp2/top/u2_rev2/u2_rev2.ucf
new file mode 100644
index 000000000..e18dc6f17
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev2/u2_rev2.ucf
@@ -0,0 +1,337 @@
+NET "leds[0]"  LOC = "F7"  ; 
+NET "leds[1]"  LOC = "E5"  ; 
+NET "leds[2]"  LOC = "B7"  ; 
+NET "leds[3]"  LOC = "C11"  ; 
+NET "leds[4]"  LOC = "AB19"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "uart_tx_o"  LOC = "C7"  ;
+NET "uart_rx_i"  LOC = "A3"  ;
+NET "exp_pps_in_p"  LOC = "V3"  ; 
+NET "exp_pps_in_n"  LOC = "V4"  ; 
+NET "exp_pps_out_p"  LOC = "V1"  ; 
+NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[1]"  LOC = "AA20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[2]"  LOC = "AB20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[3]"  LOC = "Y18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[4]"  LOC = "AA18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[5]"  LOC = "AB18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[6]"  LOC = "V17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[7]"  LOC = "W17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TX_EN"  LOC = "Y17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_RX_CLK"  LOC = "W16"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "MDIO"  LOC = "Y16" |PULLUP ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "RAM_D[0]"  LOC = "N20"  ;
+NET "RAM_D[1]"  LOC = "N21"  ;
+NET "RAM_D[2]"  LOC = "N22"  ;
+NET "RAM_D[3]"  LOC = "M17"  ;
+NET "RAM_D[4]"  LOC = "M18"  ;
+NET "RAM_D[5]"  LOC = "M19"  ;
+NET "RAM_D[6]"  LOC = "M20"  ;
+NET "RAM_D[7]"  LOC = "M21"  ;
+NET "RAM_D[8]"  LOC = "M22"  ;
+NET "RAM_D[9]"  LOC = "Y22"  ;
+NET "RAM_D[10]"  LOC = "Y21"  ;
+NET "RAM_D[11]"  LOC = "Y20"  ;
+NET "RAM_D[12]"  LOC = "Y19"  ;
+NET "RAM_D[13]"  LOC = "W22"  ;
+NET "RAM_D[14]"  LOC = "W21"  ;
+NET "RAM_D[15]"  LOC = "W20"  ;
+NET "RAM_D[16]"  LOC = "W19"  ;
+NET "RAM_D[17]"  LOC = "V22"  ;
+NET "RAM_A[0]"  LOC = "U21"  ;
+NET "RAM_A[1]"  LOC = "T19"  ;
+NET "RAM_A[2]"  LOC = "V21"  ;
+NET "RAM_A[3]"  LOC = "V20"  ;
+NET "RAM_A[4]"  LOC = "T20"  ;
+NET "RAM_A[5]"  LOC = "T21"  ;
+NET "RAM_A[6]"  LOC = "T22"  ;
+NET "RAM_A[7]"  LOC = "T18"  ;
+NET "RAM_A[8]"  LOC = "R18"  ;
+NET "RAM_A[9]"  LOC = "P19"  ;
+NET "RAM_A[10]"  LOC = "P21"  ;
+NET "RAM_A[11]"  LOC = "P22"  ;
+NET "RAM_A[12]"  LOC = "N19"  ;
+NET "RAM_A[13]"  LOC = "N17"  ;
+NET "RAM_A[14]"  LOC = "N18"  ;
+NET "RAM_A[15]"  LOC = "T17"  ;
+NET "RAM_A[16]"  LOC = "U19"  ;
+NET "RAM_A[17]"  LOC = "U18"  ;
+NET "RAM_A[18]"  LOC = "V19"  ;
+NET "RAM_CE1n"  LOC = "U20"  ; 
+NET "RAM_CENn"  LOC = "P18"  ; 
+NET "RAM_CLK"  LOC = "P17"  ; 
+NET "RAM_WEn"  LOC = "R22"  ; 
+NET "RAM_OEn"  LOC = "R21"  ; 
+NET "RAM_LDn"  LOC = "R19"  ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tx_clk"  LOC = "U7" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_t[0]"  LOC = "V7"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[1]"  LOC = "V10"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[2]"  LOC = "AB4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[3]"  LOC = "AA4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[4]"  LOC = "Y5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[5]"  LOC = "W5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[6]"  LOC = "AB5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[7]"  LOC = "AA5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[8]"  LOC = "W6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[9]"  LOC = "V6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[10]"  LOC = "AA6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[11]"  LOC = "Y6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[12]"  LOC = "W8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[13]"  LOC = "V8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[14]"  LOC = "AB8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[15]"  LOC = "AA8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_tklsb"  LOC = "U10" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_rklsb"  LOC = "V9"  ;
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_detached"  LOC = "V11"  ;
+NET "cpld_init_b"  LOC = "W12"  ;
+NET "cpld_misc"  LOC = "Y12"  ;
+NET "adc_a[0]"  LOC = "A14" | IOBDELAY= "NONE" ;
+NET "adc_a[1]"  LOC = "B14" | IOBDELAY= "NONE" ;
+NET "adc_a[2]"  LOC = "C13" | IOBDELAY= "NONE" ;
+NET "adc_a[3]"  LOC = "D13" | IOBDELAY= "NONE" ;
+NET "adc_a[4]"  LOC = "A13" | IOBDELAY= "NONE" ;
+NET "adc_a[5]"  LOC = "B13" | IOBDELAY= "NONE" ;
+NET "adc_a[6]"  LOC = "E12" | IOBDELAY= "NONE" ;
+NET "adc_a[7]"  LOC = "C22" | IOBDELAY= "NONE" ;
+NET "adc_a[8]"  LOC = "C20" | IOBDELAY= "NONE" ;
+NET "adc_a[9]"  LOC = "C21" | IOBDELAY= "NONE" ;
+NET "adc_a[10]"  LOC = "D20" | IOBDELAY= "NONE" ;
+NET "adc_a[11]"  LOC = "D19" | IOBDELAY= "NONE" ;
+NET "adc_a[12]"  LOC = "D21" | IOBDELAY= "NONE" ;
+NET "adc_a[13]"  LOC = "E18" | IOBDELAY= "NONE" ;
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_b[0]"  LOC = "A12" | IOBDELAY= "NONE";
+NET "adc_b[1]"  LOC = "E16" | IOBDELAY= "NONE" ;
+NET "adc_b[2]"  LOC = "F12" | IOBDELAY= "NONE" ;
+NET "adc_b[3]"  LOC = "F13" | IOBDELAY= "NONE" ;
+NET "adc_b[4]"  LOC = "F16" | IOBDELAY= "NONE" ;
+NET "adc_b[5]"  LOC = "F17" | IOBDELAY= "NONE" ;
+NET "adc_b[6]"  LOC = "C19" | IOBDELAY= "NONE" ;
+NET "adc_b[7]"  LOC = "B20" | IOBDELAY= "NONE" ;
+NET "adc_b[8]"  LOC = "B19" | IOBDELAY= "NONE" ;
+NET "adc_b[9]"  LOC = "C18" | IOBDELAY= "NONE" ;
+NET "adc_b[10]"  LOC = "D18" | IOBDELAY= "NONE" ;
+NET "adc_b[11]"  LOC = "B18" | IOBDELAY= "NONE" ;
+NET "adc_b[12]"  LOC = "D17" | IOBDELAY= "NONE" ;
+NET "adc_b[13]"  LOC = "E17" | IOBDELAY= "NONE" ;
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_lock"  LOC = "D6"  ;
+NET "SCL"  LOC = "A7"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "pps_in"  LOC = "Y11"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "io_tx[0]"  LOC = "K4"  ;
+NET "io_tx[1]"  LOC = "K3"  ;
+NET "io_tx[2]"  LOC = "G1"  ;
+NET "io_tx[3]"  LOC = "G5"  ;
+NET "io_tx[4]"  LOC = "H5"  ;
+NET "io_tx[5]"  LOC = "F3"  ;
+NET "io_tx[6]"  LOC = "F2"  ;
+NET "io_tx[7]"  LOC = "F5"  ;
+NET "io_tx[8]"  LOC = "G6"  ;
+NET "io_tx[9]"  LOC = "E2"  ;
+NET "io_tx[10]"  LOC = "E1"  ;
+NET "io_tx[11]"  LOC = "E3"  ;
+NET "io_tx[12]"  LOC = "F4"  ;
+NET "io_tx[13]"  LOC = "D2"  ;
+NET "io_tx[14]"  LOC = "D4"  ;
+NET "io_tx[15]"  LOC = "E4"  ;
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "io_rx[0]"  LOC = "L21"  ;
+NET "io_rx[1]"  LOC = "L20"  ;
+NET "io_rx[2]"  LOC = "L19"  ;
+NET "io_rx[3]"  LOC = "L18"  ;
+NET "io_rx[4]"  LOC = "L17"  ;
+NET "io_rx[5]"  LOC = "K22"  ;
+NET "io_rx[6]"  LOC = "K21"  ;
+NET "io_rx[7]"  LOC = "K20"  ;
+NET "io_rx[8]"  LOC = "G22"  ;
+NET "io_rx[9]"  LOC = "G21"  ;
+NET "io_rx[10]"  LOC = "F21"  ;
+NET "io_rx[11]"  LOC = "F20"  ;
+NET "io_rx[12]"  LOC = "G19"  ;
+NET "io_rx[13]"  LOC = "G18"  ;
+NET "io_rx[14]"  LOC = "G17"  ;
+NET "io_rx[15]"  LOC = "E22"  ;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+#NET "dsp_clk" TNM_NET = "dsp_clk";
+#TIMESPEC "TS_dsp_clk" = PERIOD "dsp_clk" 10 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+#NET "wb_clk" TNM_NET = "wb_clk";
+#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" 20 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/fpga/usrp2/top/u2_rev2/u2_rev2.v b/fpga/usrp2/top/u2_rev2/u2_rev2.v
new file mode 100644
index 000000000..517285e52
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev2/u2_rev2.v
@@ -0,0 +1,417 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_rev2
+  (
+   // Misc, debug
+   output [4:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+   output uart_tx_o,
+   input uart_rx_i,
+   
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,  // AA9
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
+   input cpld_din,     // AA14 Now shared with CFG_Din
+   input cpld_clk,     // AB14 serial clock
+   input cpld_detached,// V11 unused
+   output cpld_init_b,  // W12 unused dual purpose
+   output cpld_misc,  // Y12 
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b,
+   input dac_lock,     // unused for now
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   input sdo_tx_db,
+   output sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   input sdo_tx_adc,
+   output sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout [15:0] io_tx,
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+   
+   inout [15:0] io_rx   
+   );
+
+   assign 	cpld_init_b = 0;
+   // FPGA-specific pins connections
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+   wire 	clk90, clk180, clk270;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge clk_fpga)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+   reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg1 <= adc_a;
+	adc_b_reg1 <= adc_b;
+	adc_ovf_a_reg1 <= adc_ovf_a;
+	adc_ovf_b_reg1 <= adc_ovf_b;
+     end
+   
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg2 <= adc_a_reg1;
+	adc_b_reg2 <= adc_b_reg1;
+	adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+	adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+     end // always @ (posedge dsp_clk)
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_fpga), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(clk90), 
+                 .CLK180(clk180), 
+                 .CLK270(clk270), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [4:0] leds_int;
+   assign     leds = 5'b01111 ^ leds_int;  // all except eth are active-low
+   
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+
+   wire [15:0] dac_a_int, dac_b_int;
+   always @(negedge dsp_clk) dac_a <= dac_a_int;
+   always @(negedge dsp_clk) dac_b <= dac_b_int;
+
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_core #(.RAM_SIZE(32768))
+	u2_core(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .cpld_misc         (cpld_misc),
+		     .cpld_init_b       (cpld_init_b),
+		     .por               (~POR),
+		     .config_success    (config_success),
+		     .adc_a		(adc_a_reg2),
+		     .adc_ovf_a		(adc_ovf_a_reg2),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b_reg2),
+		     .adc_ovf_b		(adc_ovf_b_reg2),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a_int),
+		     .dac_b		(dac_b_int),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (uart_tx_o),
+		     .uart_rx_i         (uart_rx_i),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2_rev2
diff --git a/fpga/usrp2/top/u2_rev3/.gitignore b/fpga/usrp2/top/u2_rev3/.gitignore
new file mode 100644
index 000000000..432f8fd58
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3/.gitignore
@@ -0,0 +1,57 @@
+/*.ptwx
+/*.xrpt
+/*.zip
+/*_xdb
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
+/build
diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/u2_rev3/Makefile
new file mode 100644
index 000000000..1fd8638d9
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3/Makefile
@@ -0,0 +1,262 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+control_lib/priority_enc.v \
+control_lib/pic.v \
+vrt/vita_rx_control.v \
+vrt/vita_rx_framer.v \
+vrt/vita_tx_control.v \
+vrt/vita_tx_deframer.v \
+udp/udp_wrapper.v \
+udp/fifo19_rxrealign.v \
+udp/prot_eng_tx.v \
+udp/add_onescomp.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac_wrapper19.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo19_to_ll8.v \
+control_lib/newfifo/ll8_to_fifo19.v \
+control_lib/newfifo/fifo36_to_fifo19.v \
+control_lib/newfifo/fifo19_to_fifo36.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+coregen/fifo_xlnx_16x19_2clk.v \
+coregen/fifo_xlnx_16x19_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_64bit.v \
+timing/time_compare.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/simple_timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v 
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
new file mode 100644
index 000000000..255a298ac
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -0,0 +1,333 @@
+NET "leds[0]"  LOC = "E8"  ; 
+NET "leds[1]"  LOC = "F7"  ; 
+NET "leds[2]"  LOC = "E5"  ; 
+NET "leds[3]"  LOC = "B7"  ; 
+NET "leds[4]"  LOC = "C11"  ;
+NET "leds[5]"  LOC = "AB19"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "uart_tx_o"  LOC = "C7"  ;
+NET "uart_rx_i"  LOC = "A3"  ;
+NET "exp_pps_in_p"  LOC = "V3"  ; 
+NET "exp_pps_in_n"  LOC = "V4"  ; 
+NET "exp_pps_out_p"  LOC = "V1"  ; 
+NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[1]"  LOC = "AA20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[2]"  LOC = "AB20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[3]"  LOC = "Y18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[4]"  LOC = "AA18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[5]"  LOC = "AB18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[6]"  LOC = "V17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[7]"  LOC = "W17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TX_EN"  LOC = "Y17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_RX_CLK"  LOC = "AA12"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "MDIO"  LOC = "Y16" |PULLUP ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "RAM_D[0]"  LOC = "N20"  ;
+NET "RAM_D[1]"  LOC = "N21"  ;
+NET "RAM_D[2]"  LOC = "N22"  ;
+NET "RAM_D[3]"  LOC = "M17"  ;
+NET "RAM_D[4]"  LOC = "M18"  ;
+NET "RAM_D[5]"  LOC = "M19"  ;
+NET "RAM_D[6]"  LOC = "M20"  ;
+NET "RAM_D[7]"  LOC = "M21"  ;
+NET "RAM_D[8]"  LOC = "M22"  ;
+NET "RAM_D[9]"  LOC = "Y22"  ;
+NET "RAM_D[10]"  LOC = "Y21"  ;
+NET "RAM_D[11]"  LOC = "Y20"  ;
+NET "RAM_D[12]"  LOC = "Y19"  ;
+NET "RAM_D[13]"  LOC = "W22"  ;
+NET "RAM_D[14]"  LOC = "W21"  ;
+NET "RAM_D[15]"  LOC = "W20"  ;
+NET "RAM_D[16]"  LOC = "W19"  ;
+NET "RAM_D[17]"  LOC = "V22"  ;
+NET "RAM_A[0]"  LOC = "U21"  ;
+NET "RAM_A[1]"  LOC = "T19"  ;
+NET "RAM_A[2]"  LOC = "V21"  ;
+NET "RAM_A[3]"  LOC = "V20"  ;
+NET "RAM_A[4]"  LOC = "T20"  ;
+NET "RAM_A[5]"  LOC = "T21"  ;
+NET "RAM_A[6]"  LOC = "T22"  ;
+NET "RAM_A[7]"  LOC = "T18"  ;
+NET "RAM_A[8]"  LOC = "R18"  ;
+NET "RAM_A[9]"  LOC = "P19"  ;
+NET "RAM_A[10]"  LOC = "P21"  ;
+NET "RAM_A[11]"  LOC = "P22"  ;
+NET "RAM_A[12]"  LOC = "N19"  ;
+NET "RAM_A[13]"  LOC = "N17"  ;
+NET "RAM_A[14]"  LOC = "N18"  ;
+NET "RAM_A[15]"  LOC = "T17"  ;
+NET "RAM_A[16]"  LOC = "U19"  ;
+NET "RAM_A[17]"  LOC = "U18"  ;
+NET "RAM_A[18]"  LOC = "V19"  ;
+NET "RAM_CE1n"  LOC = "U20"  ; 
+NET "RAM_CENn"  LOC = "P18"  ; 
+NET "RAM_CLK"  LOC = "P17"  ; 
+NET "RAM_WEn"  LOC = "R22"  ; 
+NET "RAM_OEn"  LOC = "R21"  ; 
+NET "RAM_LDn"  LOC = "R19"  ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tx_clk"  LOC = "U7" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_t[0]"  LOC = "V7"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[1]"  LOC = "V10"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[2]"  LOC = "AB4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[3]"  LOC = "AA4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[4]"  LOC = "Y5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[5]"  LOC = "W5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[6]"  LOC = "AB5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[7]"  LOC = "AA5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[8]"  LOC = "W6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[9]"  LOC = "V6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[10]"  LOC = "AA6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[11]"  LOC = "Y6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[12]"  LOC = "W8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[13]"  LOC = "V8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[14]"  LOC = "AB8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[15]"  LOC = "AA8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_tklsb"  LOC = "U10" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_rklsb"  LOC = "V9"  ;
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_detached"  LOC = "V11"  ;
+NET "cpld_init_b"  LOC = "W12"  ;
+NET "cpld_misc"  LOC = "Y12"  ;
+NET "POR"  LOC = "W18"  ;
+NET "WDI"  LOC = "W15"  ;
+NET "adc_a[0]"  LOC = "A14" | IOBDELAY= "NONE" ;
+NET "adc_a[1]"  LOC = "B14" | IOBDELAY= "NONE" ;
+NET "adc_a[2]"  LOC = "C13" | IOBDELAY= "NONE" ;
+NET "adc_a[3]"  LOC = "D13" | IOBDELAY= "NONE" ;
+NET "adc_a[4]"  LOC = "A13" | IOBDELAY= "NONE" ;
+NET "adc_a[5]"  LOC = "B13" | IOBDELAY= "NONE" ;
+NET "adc_a[6]"  LOC = "E12" | IOBDELAY= "NONE" ;
+NET "adc_a[7]"  LOC = "C22" | IOBDELAY= "NONE" ;
+NET "adc_a[8]"  LOC = "C20" | IOBDELAY= "NONE" ;
+NET "adc_a[9]"  LOC = "C21" | IOBDELAY= "NONE" ;
+NET "adc_a[10]"  LOC = "D20" | IOBDELAY= "NONE" ;
+NET "adc_a[11]"  LOC = "D19" | IOBDELAY= "NONE" ;
+NET "adc_a[12]"  LOC = "D21" | IOBDELAY= "NONE" ;
+NET "adc_a[13]"  LOC = "E18" | IOBDELAY= "NONE" ;
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_b[0]"  LOC = "A12" | IOBDELAY= "NONE";
+NET "adc_b[1]"  LOC = "E16" | IOBDELAY= "NONE" ;
+NET "adc_b[2]"  LOC = "F12" | IOBDELAY= "NONE" ;
+NET "adc_b[3]"  LOC = "F13" | IOBDELAY= "NONE" ;
+NET "adc_b[4]"  LOC = "F16" | IOBDELAY= "NONE" ;
+NET "adc_b[5]"  LOC = "F17" | IOBDELAY= "NONE" ;
+NET "adc_b[6]"  LOC = "C19" | IOBDELAY= "NONE" ;
+NET "adc_b[7]"  LOC = "B20" | IOBDELAY= "NONE" ;
+NET "adc_b[8]"  LOC = "B19" | IOBDELAY= "NONE" ;
+NET "adc_b[9]"  LOC = "C18" | IOBDELAY= "NONE" ;
+NET "adc_b[10]"  LOC = "D18" | IOBDELAY= "NONE" ;
+NET "adc_b[11]"  LOC = "B18" | IOBDELAY= "NONE" ;
+NET "adc_b[12]"  LOC = "D17" | IOBDELAY= "NONE" ;
+NET "adc_b[13]"  LOC = "E17" | IOBDELAY= "NONE" ;
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_lock"  LOC = "D6"  ;
+NET "SCL"  LOC = "A7"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "pps_in"  LOC = "K1"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "io_tx[0]"  LOC = "K4"  ;
+NET "io_tx[1]"  LOC = "K3"  ;
+NET "io_tx[2]"  LOC = "G1"  ;
+NET "io_tx[3]"  LOC = "G5"  ;
+NET "io_tx[4]"  LOC = "H5"  ;
+NET "io_tx[5]"  LOC = "F3"  ;
+NET "io_tx[6]"  LOC = "F2"  ;
+NET "io_tx[7]"  LOC = "F5"  ;
+NET "io_tx[8]"  LOC = "G6"  ;
+NET "io_tx[9]"  LOC = "E2"  ;
+NET "io_tx[10]"  LOC = "E1"  ;
+NET "io_tx[11]"  LOC = "E3"  ;
+NET "io_tx[12]"  LOC = "F4"  ;
+NET "io_tx[13]"  LOC = "D2"  ;
+NET "io_tx[14]"  LOC = "D4"  ;
+NET "io_tx[15]"  LOC = "E4"  ;
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "io_rx[0]"  LOC = "L21"  ;
+NET "io_rx[1]"  LOC = "L20"  ;
+NET "io_rx[2]"  LOC = "L19"  ;
+NET "io_rx[3]"  LOC = "L18"  ;
+NET "io_rx[4]"  LOC = "L17"  ;
+NET "io_rx[5]"  LOC = "K22"  ;
+NET "io_rx[6]"  LOC = "K21"  ;
+NET "io_rx[7]"  LOC = "K20"  ;
+NET "io_rx[8]"  LOC = "G22"  ;
+NET "io_rx[9]"  LOC = "G21"  ;
+NET "io_rx[10]"  LOC = "F21"  ;
+NET "io_rx[11]"  LOC = "F20"  ;
+NET "io_rx[12]"  LOC = "G19"  ;
+NET "io_rx[13]"  LOC = "G18"  ;
+NET "io_rx[14]"  LOC = "G17"  ;
+NET "io_rx[15]"  LOC = "E22"  ;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v
new file mode 100644
index 000000000..23a825007
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v
@@ -0,0 +1,432 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_rev3
+  (
+   // Misc, debug
+   output [5:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+   output uart_tx_o,
+   input uart_rx_i,
+   
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,  // AA9
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
+   input cpld_din,     // AA14 Now shared with CFG_Din
+   input cpld_clk,     // AB14 serial clock
+   input cpld_detached,// V11 unused
+   output cpld_init_b,  // W12 unused dual purpose
+   output cpld_misc,  // Y12 
+
+   // Watchdog interface
+   input POR,
+   output WDI,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b,
+   input dac_lock,     // unused for now
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   input sdo_tx_db,
+   output sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   input sdo_tx_adc,
+   output sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout [15:0] io_tx,
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+   
+   inout [15:0] io_rx   
+   );
+
+   assign 	cpld_init_b = 0;
+   // FPGA-specific pins connections
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+   wire 	clk90, clk180, clk270;
+
+   // reset the watchdog continuously
+   reg [15:0] 	wd;
+   wire 	config_success;
+   
+   always @(posedge wb_clk)
+     if(~config_success)
+       wd <= 0;
+     else
+       wd <= wd + 1;
+   assign 	WDI = wd[15];
+   
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge clk_fpga)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+   reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg1 <= adc_a;
+	adc_b_reg1 <= adc_b;
+	adc_ovf_a_reg1 <= adc_ovf_a;
+	adc_ovf_b_reg1 <= adc_ovf_b;
+     end
+   
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg2 <= adc_a_reg1;
+	adc_b_reg2 <= adc_b_reg1;
+	adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+	adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+     end // always @ (posedge dsp_clk)
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_fpga), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(clk90), 
+                 .CLK180(clk180), 
+                 .CLK270(clk270), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [5:0] leds_int;
+   assign     leds = 6'b011111 ^ leds_int;  // all except eth are active-low
+   
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+
+   wire [15:0] dac_a_int, dac_b_int;
+   always @(negedge dsp_clk) dac_a <= dac_a_int;
+   always @(negedge dsp_clk) dac_b <= dac_b_int;
+
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_core #(.RAM_SIZE(32768))
+	u2_core(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .cpld_misc         (cpld_misc),
+		     .cpld_init_b       (cpld_init_b),
+		     .por               (~POR),
+		     .config_success    (config_success),
+		     .adc_a		(adc_a_reg2),
+		     .adc_ovf_a		(adc_ovf_a_reg2),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b_reg2),
+		     .adc_ovf_b		(adc_ovf_b_reg2),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a_int),
+		     .dac_b		(dac_b_int),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (uart_tx_o),
+		     .uart_rx_i         (uart_rx_i),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2_rev2
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
new file mode 100644
index 000000000..5b7ed5a8e
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
@@ -0,0 +1,254 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/integrate.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v \
+top/u2_rev3_2rx_iad/u2_core.v \
+top/u2_rev3_2rx_iad/dsp_core_rx.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, testbench, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+testbench:
+	iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v
+
+clean:
+	rm -rf $(BUILD_DIR)
+	rm -f dsp_core_tb
+	rm -f *.lx2
+	rm -f *.dat
+	rm -f *.vcd
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/README b/fpga/usrp2/top/u2_rev3_2rx_iad/README
new file mode 100644
index 000000000..3efc5305b
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/README
@@ -0,0 +1,32 @@
+This is a custom build for USRP2 FPGA.  It allows using a BasicRX or
+LFRX board and feed two independent, real signals.  In addition, instead
+of the CIC/HB decimator, which optimizes frequency response, it uses an
+integrate and dump decimator, which optimizes for time-domain impulse
+response.
+
+These changes have been made in dsp_core_rx.v:
+
+* A second DDC has been added, sharing a frequency register with
+  the existing DDC.
+
+* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ...
+  into the receive FIFO.  This limits the host configured decimation
+  to 8 intead of 4.  Use gr.deinterleave to recover the streams.
+
+* The ADCs are hardcoded:
+ 
+  RX_A ==>  DDC #1 I-input
+     0 ==>  DDC #1 Q-input
+  RX_B ==>  DDC #2 I-input
+     0 ==>  DDC #2 Q-input
+
+  Thus, the input mux has been disabled.
+
+* The CIC/HB decimator has been replaced by an integrate and dump at
+  the decimation rate.
+
+* To assist with meeting timing, the external RAM has been disabled.
+
+The basic application is to coherently sample two real IF streams and
+downconvert to baseband, while minimizing the impulse response duration
+of the resampling filters.
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile b/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile
new file mode 100644
index 000000000..34373a676
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile
@@ -0,0 +1,4 @@
+-y .
+-y ../../sdr_lib
+-y ../../control_lib
+-y ../../models
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v
new file mode 100644
index 000000000..4a945bd1a
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v
@@ -0,0 +1,212 @@
+`define DSP_CORE_RX_BASE 160
+module dsp_core_rx
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   input [15:0] io_rx,
+
+   output reg [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg  [13:0] adc_i, adc_q;
+   wire [31:0] phase_inc;
+   reg  [31:0] phase;
+
+   wire [35:0] prod_i, prod_q;
+   wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b;
+   wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b;
+   wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b;
+   
+   wire        enable_hb1, enable_hb2; // Correspond to std firmware settings
+   wire [7:0]  cic_decim;              // for combined CIC/HB decimator
+   wire [9:0]  decim_rate;             // Reconstructed original decimation setting
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed());
+
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+
+`ifdef MUXCTRL
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+`endif
+   
+   wire [1:0] gpio_ena;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(gpio_ena),.changed());
+
+   // The TVRX connects to what is called adc_b, thus A and B are
+   // swapped throughout the design.
+   //
+   // In the interest of expediency and keeping the s/w sane, we just remap them here.
+   // The I & Q fields are mapped the same:
+   // 0 -> "the real A" (as determined by the TVRX)
+   // 1 -> "the real B"
+   // 2 -> const zero
+
+`ifdef MUXCTRL   
+   always @(posedge clk)
+     case(muxctrl[1:0])		// The I mapping
+       0: adc_i <= adc_b_ofs;	// "the real A"
+       1: adc_i <= adc_a_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])		// The Q mapping
+       0: adc_q <= adc_b_ofs;	// "the real A"
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+`else // !`ifdef MUXCTRL
+   always @(posedge clk)
+     begin
+	adc_i <= adc_a_ofs;
+	adc_q <= adc_b_ofs;
+     end
+`endif // !`ifdef MUXCTRL
+   
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
+   
+   // Route I,0 to first CORDIC
+   cordic_z24 #(.bitwidth(24))
+     cordic_a(.clock(clk), .reset(rst), .enable(run),
+	      .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]),
+	      .xo(i_cordic_a),.yo(q_cordic_a),.zo() );
+
+   // Route Q,0 to second CORDIC
+   cordic_z24 #(.bitwidth(24))
+     cordic_b(.clock(clk), .reset(rst), .enable(run),
+	      .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]),
+	      .xo(i_cordic_b),.yo(q_cordic_b),.zo() );
+
+   // Reconstruct original decimation rate from standard firmware settings
+   assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : 
+                                                  {1'b0,cic_decim,1'b0 }) :
+				    cic_decim;
+
+   cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator
+   cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
+	       .strobe_fast(1),.strobe_slow(strobe_iad) );
+
+   wire       strobe_iad_o;
+   
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(i_cordic_a),
+      .stb_o(strobe_iad_o),.integ_o(i_iad_a) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(q_cordic_a),
+      .stb_o(),.integ_o(q_iad_a) );
+   
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(i_cordic_b),
+      .stb_o(),.integ_o(i_iad_b) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(q_cordic_b),
+      .stb_o(),.integ_o(q_iad_b) );
+   
+   round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a));
+   round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a));
+   round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b));
+   round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b));
+
+   reg [31:0]  sample_out_a, sample_out_b, sample_out;
+   reg 	       stb_d1, stb_d2, stb_d3, stb_d4, stb_d5;
+   reg         strobe_out;
+   
+   // Register samples on strobe_iad
+   // Output A on d1
+   // Output B on d5
+   always @(posedge clk)
+     begin
+	stb_d1 <= strobe_iad_o;
+	stb_d2 <= stb_d1;
+	stb_d3 <= stb_d2;
+	stb_d4 <= stb_d3;
+	stb_d5 <= stb_d4;
+     end
+   
+   always @(posedge clk)
+     if (strobe_iad_o)
+       begin	
+	  // Streaming GPIO
+	  // io_rx[15] => I channel LSB if gpio_ena[0] high
+	  // io_rx[14] => Q channel LSB if gpio_ena[1] high
+	  sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0],
+			   q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] };
+	  sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0],
+			   q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] };
+       end
+
+   always @(posedge clk)
+     begin
+	if (stb_d1)
+	  sample <= sample_out_a;
+	else if (stb_d5)
+	  sample <= sample_out_b;
+	strobe_out <= stb_d1|stb_d5;
+     end
+
+   assign strobe = strobe_out;
+   assign debug = 0;
+      
+endmodule // dsp_core_rx
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav
new file mode 100644
index 000000000..12f746860
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav
@@ -0,0 +1,106 @@
+[size] 1680 975
+[pos] -1 -1
+*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] dsp_core_tb.
+@200
+-SYSCON
+@28
+dsp_core_tb.clk
+dsp_core_tb.rst
+dsp_core_tb.run
+@200
+-
+-Settings Bus
+@22
+dsp_core_tb.set_addr[7:0]
+@24
+dsp_core_tb.set_data[31:0]
+@28
+dsp_core_tb.set_stb
+@200
+-
+-RX DSP CORE
+@22
+dsp_core_tb.rx_path.adc_a[13:0]
+dsp_core_tb.rx_path.adc_b[13:0]
+@28
+dsp_core_tb.rx_path.adc_ovf_a
+dsp_core_tb.rx_path.adc_ovf_b
+@22
+dsp_core_tb.rx_path.io_rx[15:0]
+@200
+-
+@22
+dsp_core_tb.rx_path.sample[31:0]
+@28
+dsp_core_tb.rx_path.strobe
+@200
+-
+@22
+dsp_core_tb.rx_path.phase_inc[31:0]
+dsp_core_tb.rx_path.scale_i[15:0]
+dsp_core_tb.rx_path.scale_q[15:0]
+@28
+dsp_core_tb.rx_path.enable_hb1
+dsp_core_tb.rx_path.enable_hb2
+@22
+dsp_core_tb.rx_path.cic_decim[7:0]
+dsp_core_tb.rx_path.adc_a_ofs[13:0]
+dsp_core_tb.rx_path.adc_b_ofs[13:0]
+dsp_core_tb.rx_path.muxctrl[3:0]
+@200
+-
+@22
+dsp_core_tb.rx_path.adc_i[13:0]
+dsp_core_tb.rx_path.adc_q[13:0]
+dsp_core_tb.rx_path.phase[31:0]
+dsp_core_tb.rx_path.prod_i[35:0]
+dsp_core_tb.rx_path.prod_q[35:0]
+@8420
+dsp_core_tb.rx_path.i_cordic_a[23:0]
+dsp_core_tb.rx_path.q_cordic_a[23:0]
+dsp_core_tb.rx_path.i_cordic_b[23:0]
+dsp_core_tb.rx_path.q_cordic_b[23:0]
+@22
+dsp_core_tb.rx_path.decim_rate[9:0]
+@28
+dsp_core_tb.rx_path.strobe_iad
+@22
+dsp_core_tb.rx_path.i_iad_a[31:0]
+dsp_core_tb.rx_path.q_iad_a[31:0]
+@23
+dsp_core_tb.rx_path.i_iad_b[31:0]
+@22
+dsp_core_tb.rx_path.q_iad_b[31:0]
+@28
+dsp_core_tb.rx_path.strobe_iad_o
+@8420
+dsp_core_tb.rx_path.i_out_a[15:0]
+dsp_core_tb.rx_path.q_out_a[15:0]
+dsp_core_tb.rx_path.i_out_b[15:0]
+dsp_core_tb.rx_path.q_out_b[15:0]
+@28
+dsp_core_tb.rx_path.gpio_ena[1:0]
+@22
+dsp_core_tb.rx_path.sample_out_a[31:0]
+dsp_core_tb.rx_path.sample_out_b[31:0]
+dsp_core_tb.rx_path.sample[31:0]
+@28
+dsp_core_tb.rx_path.strobe_out
+dsp_core_tb.rx_path.stb_d1
+dsp_core_tb.rx_path.stb_d2
+dsp_core_tb.rx_path.stb_d3
+dsp_core_tb.rx_path.stb_d4
+dsp_core_tb.rx_path.stb_d5
+@200
+-
+-FIFO Bus
+@22
+dsp_core_tb.master_time[31:0]
+dsp_core_tb.wr_dat[31:0]
+@28
+dsp_core_tb.wr_done
+dsp_core_tb.wr_error
+dsp_core_tb.wr_full
+dsp_core_tb.wr_ready
+dsp_core_tb.wr_write
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v
new file mode 100644
index 000000000..d947df40a
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v
@@ -0,0 +1,233 @@
+`timescale 1ns / 100ps
+
+module dsp_core_tb;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Sim-wide wires/busses                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // System control bus
+   reg                clk = 0;
+   reg                rst = 1;
+   
+   // Configuration bus
+   reg                set_stb = 0;  
+   reg          [7:0] set_addr = 0; 
+   reg         [31:0] set_data = 0; 
+
+   // ADC input bus
+   wire signed [13:0] adc_a;
+   wire signed [13:0] adc_b;
+   wire               adc_ovf_a;
+   wire               adc_ovf_b;
+   
+   // RX sample bus
+   reg                run = 1;
+   wire        [31:0] sample;
+   wire               stb;
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation control                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // Set up output files
+   initial begin
+      $dumpfile("dsp_core_tb.vcd");
+      $dumpvars(0,dsp_core_tb);
+   end
+
+   // Update display every 10 us
+   always #1000 $monitor("Time in us ",$time/1000);
+
+   // Generate master clock 50% @ 100 MHz
+   always
+     #5 clk = ~clk;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Unit(s) under test                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   reg [13:0] amplitude = 13'h1fff;
+   reg [15:0] impulse_len = 0;
+   reg [15:0] zero_len = 0;
+   reg 	      adc_ena = 0;
+
+   initial #500 @(posedge clk) adc_ena = 1;
+
+   impulse adc
+     (.clk(clk),.rst(rst),.ena(adc_ena),
+      .dc_offset_a(0),.dc_offset_b(0),
+      .amplitude(amplitude),
+      .impulse_len(impulse_len),.zero_len(zero_len),
+      .adc_a(adc_a),.adc_b(adc_b),
+      .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) );
+
+   initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's
+   initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset
+   dsp_core_rx rx_path
+     (.clk(clk),.rst(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),
+      .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .io_rx(16'b0),
+      .run(adc_ena),.sample(sample),.strobe(stb),
+      .debug() );
+
+   reg  [31:0] master_time = 0;
+   always @(posedge clk)
+     master_time <= master_time + 1;
+
+   reg         wr_ready    = 1;
+   reg         wr_full     = 0;
+
+   wire [31:0] wr_dat;
+   wire        wr_write;
+   wire        wr_done;
+   wire        wr_error;
+   wire [15:0] fifo_occupied;
+   wire        fifo_full;
+   wire        fifo_empty;
+   
+   rx_control rx_buffer
+    (.clk(clk),.rst(rst),
+     .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+     .master_time(master_time),
+     .overrun(), // unconnected output
+     .wr_dat_o(wr_dat),
+     .wr_write_o(wr_write),
+     .wr_done_o(wr_done),
+     .wr_error_o(wr_error),
+     .wr_ready_i(wr_ready),
+     .wr_full_i(wr_full),
+     .sample(sample),
+     .run(), // unconnected output, supposed to drive 'run'
+     .strobe(stb),
+     .fifo_occupied(fifo_occupied),
+     .fifo_full(fifo_full),
+     .fifo_empty(fifo_empty),
+     .debug_rx() // unconnected output
+     );
+
+
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation output/checking                                                    //
+///////////////////////////////////////////////////////////////////////////////////
+
+   integer rx_file;
+   
+   initial
+     rx_file = $fopen("rx.dat", "wb");
+   
+   always @(posedge clk)
+     begin
+	// Write RX sample I&Q in format Octave can load
+	if (stb)
+	  begin
+	     $fwrite(rx_file, sample[31:16]);
+	     $fputc(32, rx_file);
+	     $fwrite(rx_file, sample[15:0]);
+	     $fputc(13, rx_file);
+	  end
+     end
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Tasks                                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task power_on;
+     begin
+	@(posedge clk)
+	  rst = #1 1'b1;
+	@(posedge clk)
+	  rst = #1 1'b0;
+     end
+   endtask // power_on
+   
+   task set_impulse_len;
+      input [15:0] len;
+      @(posedge clk) impulse_len = len-1;
+   endtask
+ 
+   task set_zero_len;
+      input [15:0] len;
+      @(posedge clk) zero_len = len-1;
+   endtask
+
+   // Strobe configuration bus with addr, data
+   task write_cfg_register;
+      input [7:0]  regno;
+      input [31:0] value;
+      
+      begin
+	 @(posedge clk);
+	 set_addr <= regno;
+	 set_data <= value;
+	 set_stb  <= 1'b1;
+	 @(posedge clk);
+	 set_stb  <= 1'b0;
+      end
+   endtask // write_cfg_register
+
+   // Set RX DDC frequency
+   task set_ddc_freq;
+      input [31:0] freq;
+
+      write_cfg_register(160, freq);
+   endtask // set_ddc_freq
+
+   // Set RX IQ scaling registers
+   task set_rx_scale_iq;
+      input [15:0] scale_i;
+      input [15:0] scale_q;
+
+      write_cfg_register(161, {scale_i,scale_q});
+   endtask // set_rx_scale_iq
+   
+   // Set RX MUX control
+   task set_rx_muxctrl;
+      input [3:0] muxctrl;
+
+      write_cfg_register(168, muxctrl);
+   endtask // set_rx_muxctrl
+   
+   // Set RX CIC decim and halfband enables
+   task set_decim;
+      input hb1_ena;
+      input hb2_ena;
+      input [7:0] decim;
+
+      write_cfg_register(162, {hb1_ena,hb2_ena,decim});
+   endtask // set_decim
+      
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Individual tests                                                              //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task test_rx;
+      begin
+	 set_impulse_len(10);
+	 set_zero_len(990);
+	 set_rx_muxctrl(1);
+	 set_ddc_freq(32'h10000000);
+	 set_rx_scale_iq(1243, 1243);
+	 set_decim(1, 1, 1);
+
+	 #100000 $finish;
+      end
+   endtask // test_rx
+   
+      
+///////////////////////////////////////////////////////////////////////////////////
+// Top-level test                                                                //
+///////////////////////////////////////////////////////////////////////////////////
+
+   // Execute tests
+   initial
+     begin
+	power_on();
+	test_rx();
+     end
+
+endmodule // dsp_core_tb
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v b/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v
new file mode 100644
index 000000000..fc5e3c1ed
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v
@@ -0,0 +1,68 @@
+module impulse
+  (input clk,
+   input rst,
+   input ena,
+   
+   input [13:0] dc_offset_a,
+   input [13:0] dc_offset_b,
+   input [13:0] amplitude,
+   input [15:0] impulse_len,
+   input [15:0] zero_len,
+
+   output [13:0] adc_a,
+   output [13:0] adc_b,
+   output        adc_ovf_a,
+   output        adc_ovf_b
+   );
+
+   reg [13:0] adc_a_int = 0;
+   reg [13:0] adc_b_int = 0;
+   
+   reg [15:0] count;
+
+   localparam ST_ZERO = 0;
+   localparam ST_HIGH = 1;
+   reg 	      state;
+   
+   always @(posedge clk)
+     if (rst | ~ena)
+       begin
+	  adc_a_int <= 0;
+	  adc_b_int <= 0;
+	  count <= 0;
+	  state <= ST_ZERO;
+       end
+     else
+       case(state)
+	 ST_ZERO:
+	   if (count == zero_len)
+	     begin
+		adc_a_int <= amplitude;
+		adc_b_int <= amplitude >> 2;
+		state <= ST_HIGH;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+	 ST_HIGH:
+	   if (count == impulse_len)
+	     begin
+		adc_a_int <= 0;
+		adc_b_int <= 0;
+		state <= ST_ZERO;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+       endcase // case (state)
+
+   assign adc_a = adc_a_int + dc_offset_a;
+   assign adc_b = adc_b_int + dc_offset_b;
+
+   // Ignore for now
+   assign adc_ovf_a = 0;
+   assign adc_ovf_b = 0;
+
+endmodule // impulse
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v b/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v
new file mode 100755
index 000000000..3d96a4e0e
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v
@@ -0,0 +1,789 @@
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2_core
+  #(parameter RAM_SIZE=32768)
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output [7:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in,
+   output exp_pps_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
+   output cpld_misc,
+   input cpld_init_b,
+   input por,
+   output config_success,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_on_a,
+   output adc_oe_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_on_b,
+   output adc_oe_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // External RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // Debug stuff
+   output uart_tx_o, 
+   input uart_rx_i,
+   output uart_baud_o,
+   input sim_mode,
+   input [3:0] clock_divider
+   );
+   
+   wire [7:0] 	set_addr;
+   wire [31:0] 	set_data;
+   wire 	set_stb;
+   
+   wire 	ram_loader_done;
+   wire 	ram_loader_rst, wb_rst, dsp_rst;
+
+   wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
+   wire 	bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   wire [31:0] 	atr_lines;
+
+   wire [31:0] 	debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, 
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp;
+
+   wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire 	ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+	
+   wire 	serdes_link_up;
+   wire 	epoch;
+   
+   // ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   localparam 	dw = 32;  // Data bus width
+   localparam 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   localparam	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+   
+   wire [dw-1:0] m0_dat_o, m0_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o,
+		 s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc;
+   wire 	 m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err;
+   wire 	 m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we;
+   
+   wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10),
+		.s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10),
+		.s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10),
+		.s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10),
+		.s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01),
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty),
+      .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb),
+      .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
+      .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
+      .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
+      .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
+      .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
+      .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb),
+      .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty),
+      .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb),
+      .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty),
+      .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  );
+   
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
+			   .ram_loader_rst_o(ram_loader_rst),
+			   .wb_rst_o(wb_rst),
+			   .ram_loader_done_i(ram_loader_done));
+
+   assign 	 config_success = ram_loader_done;
+   reg 		 takeover = 0;
+
+   wire 	 cpld_start_int, cpld_mode_int, cpld_done_int;
+   
+   always @(posedge wb_clk)
+     if(ram_loader_done)
+       takeover = 1;
+   assign 	 cpld_misc = ~takeover;
+
+   wire 	 sd_clk, sd_csn, sd_mosi, sd_miso;
+   
+   assign 	 sd_miso = cpld_din;
+   assign 	 cpld_start = takeover ? sd_clk	: cpld_start_int;
+   assign 	 cpld_mode = takeover ? sd_csn : cpld_mode_int;
+   assign 	 cpld_done = takeover ? sd_mosi : cpld_done_int;
+   
+   // ///////////////////////////////////////////////////////////////////
+   // RAM Loader
+
+   wire [31:0] 	 ram_loader_dat, iwb_dat;
+   wire [15:0] 	 ram_loader_adr, iwb_adr;
+   wire [3:0] 	 ram_loader_sel;
+   wire 	 ram_loader_stb, ram_loader_we, ram_loader_ack;
+   wire 	 iwb_ack, iwb_stb;
+   ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
+     ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
+		 // CPLD Interface
+		 .cfg_clk_i(cpld_clk),
+		 .cfg_data_i(cpld_din),
+		 .start_o(cpld_start_int),
+		 .mode_o(cpld_mode_int),
+		 .done_o(cpld_done_int),
+		 .detached_i(cpld_detached),
+		 // Wishbone Interface
+		 .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
+		 .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
+		 .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
+		 .ram_loader_done_o(ram_loader_done));
+
+   // Processor
+   aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
+     aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+	   // Instruction Wishbone bus to I-RAM
+	   .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+	   .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
+	   // Data Wishbone bus to system bus fabric
+	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
+	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .sys_int_i(proc_int),.sys_exc_i(bus_error) );
+   
+   assign 	 bus_error = m0_err | m0_rty;
+   
+   // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+   // I-port connects directly to processor and ram loader
+
+   wire 	 flush_icache;
+   ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+     sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+	     
+	     .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
+	     .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
+	     .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
+	     .ram_loader_done_i(ram_loader_done),
+	     
+	     .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
+	     .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
+	     
+	     .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
+	     .flush_icache(flush_icache));
+   
+   assign 	 s0_err = 1'b0;
+   assign 	 s0_rty = 1'b0;
+
+   setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					 .in(set_data),.out(),.changed(flush_icache));
+
+   // Buffer Pool, slave #1
+   wire 	 rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop;
+   wire 	 rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop;
+   wire 	 rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop;
+   wire 	 rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
+   wire [31:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
+   wire 	 wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
+   wire 	 wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
+   wire 	 wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
+   wire [31:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+   
+   buffer_pool buffer_pool
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),   
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty),
+   
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .status(status),.sys_int_o(buffer_int),
+
+      .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3),
+      .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7),
+      
+      // Write Interfaces
+      .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
+      .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
+      .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done),
+      .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
+      .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done),
+      .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
+      .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done),
+      .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
+      // Read Interfaces
+      .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
+      .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop),
+      .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done),
+      .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop),
+      .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done),
+      .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop),
+      .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done),
+      .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop)
+      );
+
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+      .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int),
+      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   assign 	 s2_rty = 1'b0;
+   
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_i[31:8] = 24'd0;
+   assign 	 s3_err = 1'b0;
+   assign 	 s3_rty = 1'b0;
+   
+   // GPIOs -- Slave #4
+   nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		 .gpio( {io_tx,io_rx} ) );
+   assign 	 s4_err = 1'b0;
+   assign 	 s4_rty = 1'b0;
+
+   // Buffer Pool Status -- Slave #5
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk),
+      .wb_rst_i(wb_rst),
+      .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr),
+      .wb_dat_o(s5_dat_i),
+      .wb_ack_o(s5_ack),
+      
+      .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3),
+      .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7),
+      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0),
+      .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0)
+      );
+
+   assign 	 s5_err = 1'b0;
+   assign 	 s5_rty = 1'b0;
+
+   // Slave, #6 Ethernet MAC, see below
+   
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_err = 1'b0;
+   assign 	 s7_rty = 1'b0;
+   assign 	 s7_dat_i = 32'd0;
+
+   // Output control lines
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+   wire 	 phy_reset;
+   assign 	 PHY_RESETn = ~phy_reset;
+   
+   setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+				      .in(set_data),.out(clock_outs),.changed());
+   setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(serdes_outs),.changed());
+   setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(adc_outs),.changed());
+   setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(phy_reset),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
+   //  LEDS
+   //    register 8 determines whether leds are controlled by SW or not
+   //    1 = controlled by HW, 0 = by SW
+   //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+   
+   wire [7:0] 	 led_src, led_sw;
+   wire [7:0] 	 led_hw = {clk_status,serdes_link_up};
+   
+   setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(led_sw),.changed());
+   setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+					  .in(set_data),.out(led_src),.changed());
+
+   assign 	 leds = (led_src & led_hw) | (~led_src & led_sw);
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC  Slave #6
+   
+   wire 	 Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
+   wire 	 Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err;
+   wire [31:0] 	 Tx_mac_data, Rx_mac_data;
+   wire [1:0] 	 Tx_mac_BE, Rx_mac_BE;
+   wire 	 rst_mac;
+  
+   oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac));
+   
+   MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
+     MAC_top
+       (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),
+	.rst_mac(rst_mac),.rst_user(dsp_rst),
+	.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
+	.WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack),
+	.Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
+	.Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
+	.Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+	.Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+	.Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
+	.Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
+	.Crs(GMII_CRS),.Col(GMII_COL),
+	.Mdio(MDIO),.Mdc(MDC),
+	.rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2),
+	.tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(),
+	.debug0(debug_mac0),.debug1(debug_mac1) );
+
+   assign 	 s6_err = 1'b0;
+   assign 	 s6_rty = 1'b0;
+
+   mac_rxfifo_int mac_rxfifo_int
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
+      .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop),
+      .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
+      .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
+      .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full),
+      .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) );
+
+   mac_txfifo_int mac_txfifo_int
+     (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac),
+      .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+      .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+      .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
+      .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop),
+      .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) );
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+
+   wire [15:0] 	 irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+		      {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}};
+   
+   simple_pic #(.is(16),.dwidth(32)) simple_pic
+     (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
+      .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+      .irq(irq) );
+   assign 	 s8_err = 0;
+   assign 	 s8_rty = 0;
+ 	 
+   // /////////////////////////////////////////////////////////////////////////
+   // Master Timer, Slave #9
+
+   wire [31:0] 	 master_time;
+   timer timer
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
+      .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
+      .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
+   assign 	 s9_err = 0;
+   assign 	 s9_rty = 0;
+
+   // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack),
+      .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   
+   assign 	 s10_err = 0;
+   assign 	 s10_rty = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller, Slave #11
+
+   wire 	 run_rx, run_tx;
+   reg 		 run_rx_d1;
+   always @(posedge dsp_clk)
+     run_rx_d1 <= run_rx;
+   
+   atr_controller atr_controller
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
+      .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
+      .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   assign 	 s11_err = 0;
+   assign 	 s11_rty = 0;
+   
+   // //////////////////////////////////////////////////////////////////////////
+   // Time Sync, Slave #12 
+
+   reg 		 pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1;
+   always @(negedge dsp_clk) pps_negedge <= pps_in;
+   always @(posedge dsp_clk) pps_posedge <= pps_in;
+   always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge;
+   always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge;   
+   
+   wire 	 pps_o;
+   time_sync time_sync
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
+      .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
+      .sys_clk_i(dsp_clk),.master_time_o(master_time),
+      .pps_posedge(pps_posedge),.pps_negedge(pps_negedge),
+      .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
+      .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) );
+   assign 	 s12_err = 0;
+   assign 	 s12_rty = 0;
+
+   // /////////////////////////////////////////////////////////////////////////
+   // SD Card Reader / Writer, Slave #13
+
+   sd_spi_wb sd_spi_wb
+     (.clk(wb_clk),.rst(wb_rst),
+      .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+      .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we),
+      .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i),
+      .wb_ack_o(s13_ack) );
+   assign 	 s13_err = 0;
+   assign 	 s13_rty = 0;
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP
+   wire [31:0] 	 sample_rx, sample_tx;
+   wire 	 strobe_rx, strobe_tx;
+
+   rx_control #(.FIFOSIZE(10)) rx_control
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .master_time(master_time),.overrun(overrun),
+      .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error),
+      .wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
+      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
+      .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
+      .debug_rx(debug_rx) );
+   
+   // dummy_rx dsp_core_rx
+   dsp_core_rx dsp_core_rx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx),
+      .debug(debug_rx_dsp) );
+
+   tx_control #(.FIFOSIZE(10)) tx_control
+     (.clk(dsp_clk), .rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .master_time(master_time),.underrun(underrun),
+      .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
+      .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty),
+      .debug(debug_txc) );
+   
+   dsp_core_tx dsp_core_tx
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) );
+
+   assign dsp_rst = wb_rst;
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+
+   serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error),
+      .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
+      .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+`ifdef EXTRAM
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // External RAM Interface
+
+   localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
+
+   wire [15:0] bus2ram, ram2bus;
+   wire [15:0] bridge_adr;
+   wire [1:0]  bridge_sel;
+   wire        bridge_stb, bridge_cyc, bridge_we, bridge_ack;
+   
+   wire [19:0] page;
+   wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]};
+   setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				       .in(set_data),.out(page),.changed());
+
+   wb_bridge_16_32 bridge
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),
+      .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel),
+      .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack),
+      .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel),
+      .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack));
+
+   wb_zbt16_b wb_zbt16_b
+     (.clk(wb_clk),.rst(wb_rst),
+      .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel),
+      .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we),
+      .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn),
+      .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn),
+      .sram_mode(),.sram_zz() );
+
+   assign      s14_err = 0; assign s14_rty = 0;
+   assign      RAM_CE1n = 0;
+   assign      RAM_D[17:16] = 2'bzz;
+`endif
+
+`ifdef DEBUG   
+   // /////////////////////////////////////////////////////////////////////////////////////////
+   // Debug Pins
+   
+   // FIFO Level Debugging
+   reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
+   
+   always @(posedge dsp_clk)
+     serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]},
+			     {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+
+   always @(posedge dsp_clk)
+     dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]},
+			     {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]},
+			   {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]},
+			   {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} };
+   
+   always @(posedge dsp_clk)
+     eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]},
+			{eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} };
+   
+   assign      debug_clk[0] = 0;
+   assign      debug_clk[1] = dsp_clk;	
+   
+   assign     debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+   assign      debug_gpio_0 = eth_mac_debug;
+   assign      debug_gpio_1 = 0;
+`endif
+   
+endmodule // u2_core
+
+//   wire        debug_mux;
+//   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+//					.in(set_data),.out(debug_mux),.changed());
+
+//assign     debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo;
+//assign     debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo;
+   
+//assign      debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a},
+//		{run_rx,/*adc_ovf_b*/ 1'b0,adc_b}};
+
+//assign      debug = debug_tx_dsp;
+//assign      debug = debug_serdes0;
+
+//assign      debug_gpio_0 = 0; //debug_serdes0;
+//assign      debug_gpio_1 = 0; //debug_serdes1;
+
+//   assign      debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success},
+//	      {8'b0},
+//      {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done },
+//    {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} };
+
+//assign      debug = {dac_a,dac_b};
+
+/*
+ assign      debug = {{ram_loader_done, takeover, 6'd0},
+ {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi},
+ {8'd0},
+ {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */
+
+/*assign      debug = host_to_dsp_fifo;
+ assign      debug_gpio_0 = eth_mac_debug;
+ assign      debug_gpio_1 = 0;
+ */
+// Assign various commonly used debug buses.
+/*
+ wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
+ irq[7:0],
+ GMII_RXD,
+ GMII_TXD};
+ 
+ wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
+   
+   wire [31:0] debug_time =  {uart_tx_o, 7'b0,
+			      irq[7:0],
+			      6'b0, GMII_RX_DV, GMII_TX_EN,
+			      4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
+
+   wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
+			     irq[7:0],
+			     proc_int,  7'b0 };
+
+   wire [31:0] debug_eth = 
+	       {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+		{8'd0},
+		{8'd0},
+		{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} };
+
+   assign      debug_serdes0 = { { rd0_dat[7:0] },
+				 { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done },
+				 { ser_t[15:8] },
+				 { ser_t[7:0] } };
+
+   assign      debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
+				 { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
+				 { ser_r[15:8] },
+				 { ser_r[7:0] } };
+       
+   assign      debug_gpio_1 = {uart_tx_o,7'd0,
+			       3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
+			       debug_txc[15:0]};
+   assign      debug_gpio_1 = debug_rx;
+   assign      debug_gpio_1 = debug_serdes1;
+   assign      debug_gpio_1 = debug_eth;
+      
+    */
+      
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh b/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh
new file mode 100755
index 000000000..626f224e5
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+gtkwave dsp_core_tb.vcd dsp_core_tb.sav &
diff --git a/fpga/usrp2/top/u2_rev3_iad/.gitignore b/fpga/usrp2/top/u2_rev3_iad/.gitignore
new file mode 100644
index 000000000..e4daaf1ea
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/.gitignore
@@ -0,0 +1,4 @@
+/build
+/*.vcd
+/dsp_core_tb
+/*.dat
diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile
new file mode 100644
index 000000000..5ae8846dd
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/Makefile
@@ -0,0 +1,254 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2_rev3
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/buffer_int.v \
+control_lib/buffer_pool.v \
+control_lib/cascadefifo2.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/fifo_2clock.v \
+control_lib/fifo_2clock_casc.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/longfifo.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+eth/mac_rxfifo_int.v \
+eth/mac_txfifo_int.v \
+eth/rtl/verilog/Clk_ctrl.v \
+eth/rtl/verilog/MAC_rx.v \
+eth/rtl/verilog/MAC_rx/Broadcast_filter.v \
+eth/rtl/verilog/MAC_rx/CRC_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \
+eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \
+eth/rtl/verilog/MAC_top.v \
+eth/rtl/verilog/MAC_tx.v \
+eth/rtl/verilog/MAC_tx/CRC_gen.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \
+eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \
+eth/rtl/verilog/MAC_tx/Random_gen.v \
+eth/rtl/verilog/Phy_int.v \
+eth/rtl/verilog/RMON.v \
+eth/rtl/verilog/RMON/RMON_addr_gen.v \
+eth/rtl/verilog/RMON/RMON_ctrl.v \
+eth/rtl/verilog/Reg_int.v \
+eth/rtl/verilog/eth_miim.v \
+eth/rtl/verilog/flow_ctrl_rx.v \
+eth/rtl/verilog/flow_ctrl_tx.v \
+eth/rtl/verilog/miim/eth_clockgen.v \
+eth/rtl/verilog/miim/eth_outputcontrol.v \
+eth/rtl/verilog/miim/eth_shiftreg.v \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/integrate.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2_rev3/u2_rev3.ucf \
+top/u2_rev3/u2_rev3.v \
+top/u2_rev3_iad/dsp_core_rx.v
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, testbench, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+testbench:
+	iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v
+
+clean:
+	rm -rf $(BUILD_DIR)
+	rm -f dsp_core_tb
+	rm -f *.lx2
+	rm -f *.dat
+	rm -f *.vcd
diff --git a/fpga/usrp2/top/u2_rev3_iad/cmdfile b/fpga/usrp2/top/u2_rev3_iad/cmdfile
new file mode 100644
index 000000000..34373a676
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/cmdfile
@@ -0,0 +1,4 @@
+-y .
+-y ../../sdr_lib
+-y ../../control_lib
+-y ../../models
diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v
new file mode 100644
index 000000000..2882464ba
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v
@@ -0,0 +1,158 @@
+`define DSP_CORE_RX_BASE 160
+module dsp_core_rx
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   input [15:0] io_rx,
+
+   output [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg [13:0] adc_i, adc_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [35:0] prod_i, prod_q;
+   wire [23:0] i_cordic, q_cordic;
+   wire [31:0] i_iad, q_iad;
+   wire [15:0] i_out, q_out;
+   
+   wire        enable_hb1, enable_hb2; // Correspond to std firmware settings
+   wire [7:0]  cic_decim;              // for combined CIC/HB decimator
+   wire [9:0]  decim_rate;             // Reconstructed original decimation setting
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed());
+
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(muxctrl),.changed());
+
+   wire [1:0] gpio_ena;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(gpio_ena),.changed());
+
+   // The TVRX connects to what is called adc_b, thus A and B are
+   // swapped throughout the design.
+   //
+   // In the interest of expediency and keeping the s/w sane, we just remap them here.
+   // The I & Q fields are mapped the same:
+   // 0 -> "the real A" (as determined by the TVRX)
+   // 1 -> "the real B"
+   // 2 -> const zero
+   
+   always @(posedge clk)
+     case(muxctrl[1:0])		// The I mapping
+       0: adc_i <= adc_b_ofs;	// "the real A"
+       1: adc_i <= adc_a_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])		// The Q mapping
+       0: adc_q <= adc_b_ofs;	// "the real A"
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+       
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
+   
+   cordic_z24 #(.bitwidth(24))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]),
+	    .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   // Reconstruct original decimation rate from standard firmware settings
+   assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : 
+                                                  {1'b0,cic_decim,1'b0 }) :
+				    cic_decim;
+
+   cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator
+   cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate),
+	       .strobe_fast(1),.strobe_slow(strobe_iad) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(i_cordic),
+      .stb_o(strobe),.integ_o(i_iad) );
+
+   integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q
+     (.clk_i(clk),.rst_i(rst),.ena_i(run),
+      .dump_i(strobe_iad),.data_i(q_cordic),
+      .stb_o(),.integ_o(q_iad) );
+   
+   round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out));
+   round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out));
+  
+   // Streaming GPIO
+   //
+   // io_rx[15] => I channel LSB if gpio_ena[0] high
+   // io_rx[14] => Q channel LSB if gpio_ena[1] high
+
+   reg [31:0] sample_reg;
+   always @(posedge clk)
+     begin
+	sample_reg[31:17] <= i_out[15:1];
+	sample_reg[15:1]  <= q_out[15:1];
+	sample_reg[16]    <= gpio_ena[0] ? io_rx[15] : i_out[0]; 
+	sample_reg[0]     <= gpio_ena[1] ? io_rx[14] : q_out[0];
+     end
+   
+   assign      sample = sample_reg;
+   assign      debug = {clk, rst, run, strobe};
+   
+endmodule // dsp_core_rx
diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav
new file mode 100644
index 000000000..17c90cdd7
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav
@@ -0,0 +1,61 @@
+[size] 1680 975
+[pos] -1 -1
+*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] dsp_core_tb.
+@200
+-SYSCON
+@28
+dsp_core_tb.clk
+dsp_core_tb.rst
+dsp_core_tb.run
+@200
+-
+-Settings Bus
+@22
+dsp_core_tb.set_addr[7:0]
+@24
+dsp_core_tb.set_data[31:0]
+@28
+dsp_core_tb.set_stb
+@200
+-
+-RX DSP CORE
+-
+@24
+dsp_core_tb.rx_path.decim_rate[9:0]
+@200
+-
+@8420
+dsp_core_tb.adc_a[13:0]
+@20000
+-
+@200
+-
+@8420
+dsp_core_tb.rx_path.adc_a_ofs[13:0]
+@20000
+-
+@200
+-
+@8022
+dsp_core_tb.rx_path.i_cordic[23:0]
+@20000
+-
+@200
+-
+@8022
+dsp_core_tb.rx_path.i_iad[31:0]
+@20000
+-
+@200
+-
+@8420
+dsp_core_tb.rx_path.i_out[15:0]
+@20000
+-
+@200
+-
+@28
+dsp_core_tb.stb
+@200
+-
diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v
new file mode 100644
index 000000000..4d5a5b537
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v
@@ -0,0 +1,196 @@
+`timescale 1ns / 100ps
+
+module dsp_core_tb;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Sim-wide wires/busses                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // System control bus
+   reg                clk = 0;
+   reg                rst = 1;
+   
+   // Configuration bus
+   reg                set_stb = 0;  
+   reg          [7:0] set_addr = 0; 
+   reg         [31:0] set_data = 0; 
+
+   // ADC input bus
+   wire signed [13:0] adc_a;
+   wire signed [13:0] adc_b;
+   wire               adc_ovf_a;
+   wire               adc_ovf_b;
+   
+   // RX sample bus
+   reg                run = 1;
+   wire        [31:0] sample;
+   wire               stb;
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation control                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   // Set up output files
+   initial begin
+      $dumpfile("dsp_core_tb.vcd");
+      $dumpvars(0,dsp_core_tb);
+   end
+
+   // Update display every 10 us
+   always #1000 $monitor("Time in us ",$time/1000);
+
+   // Generate master clock 50% @ 100 MHz
+   always
+     #5 clk = ~clk;
+
+///////////////////////////////////////////////////////////////////////////////////
+// Unit(s) under test                                                            //
+///////////////////////////////////////////////////////////////////////////////////
+   
+   reg [13:0] amplitude = 13'h1fff;
+   reg [15:0] impulse_len = 0;
+   reg [15:0] zero_len = 0;
+   reg 	      adc_ena = 0;
+
+   initial #500 @(posedge clk) adc_ena = 1;
+
+   impulse adc
+     (.clk(clk),.rst(rst),.ena(adc_ena),
+      .dc_offset_a(0),.dc_offset_b(0),
+      .amplitude(amplitude),
+      .impulse_len(impulse_len),.zero_len(zero_len),
+      .adc_a(adc_a),.adc_b(adc_b),
+      .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) );
+
+   initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's
+   initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset
+   dsp_core_rx rx_path
+     (.clk(clk),.rst(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),
+      .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .io_rx(16'b0),
+      .run(adc_ena),.sample(sample),.strobe(stb),
+      .debug() );
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Simulation output/checking                                                    //
+///////////////////////////////////////////////////////////////////////////////////
+
+   integer rx_file;
+   
+   initial
+     rx_file = $fopen("rx.dat", "wb");
+   
+   always @(posedge clk)
+     begin
+	// Write RX sample I&Q in format Octave can load
+	if (stb)
+	  begin
+	     $fwrite(rx_file, sample[31:16]);
+	     $fputc(32, rx_file);
+	     $fwrite(rx_file, sample[15:0]);
+	     $fputc(13, rx_file);
+	  end
+     end
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Tasks                                                                         //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task power_on;
+     begin
+	@(posedge clk)
+	  rst = #1 1'b1;
+	@(posedge clk)
+	  rst = #1 1'b0;
+     end
+   endtask // power_on
+   
+   task set_impulse_len;
+      input [15:0] len;
+      @(posedge clk) impulse_len = len-1;
+   endtask
+ 
+   task set_zero_len;
+      input [15:0] len;
+      @(posedge clk) zero_len = len-1;
+   endtask
+
+   // Strobe configuration bus with addr, data
+   task write_cfg_register;
+      input [7:0]  regno;
+      input [31:0] value;
+      
+      begin
+	 @(posedge clk);
+	 set_addr <= regno;
+	 set_data <= value;
+	 set_stb  <= 1'b1;
+	 @(posedge clk);
+	 set_stb  <= 1'b0;
+      end
+   endtask // write_cfg_register
+
+   // Set RX DDC frequency
+   task set_ddc_freq;
+      input [31:0] freq;
+
+      write_cfg_register(160, freq);
+   endtask // set_ddc_freq
+
+   // Set RX IQ scaling registers
+   task set_rx_scale_iq;
+      input [15:0] scale_i;
+      input [15:0] scale_q;
+
+      write_cfg_register(161, {scale_i,scale_q});
+   endtask // set_rx_scale_iq
+   
+   // Set RX MUX control
+   task set_rx_muxctrl;
+      input [3:0] muxctrl;
+
+      write_cfg_register(168, muxctrl);
+   endtask // set_rx_muxctrl
+   
+   // Set RX CIC decim and halfband enables
+   task set_decim;
+      input hb1_ena;
+      input hb2_ena;
+      input [7:0] decim;
+
+      write_cfg_register(162, {hb1_ena,hb2_ena,decim});
+   endtask // set_decim
+      
+   
+///////////////////////////////////////////////////////////////////////////////////
+// Individual tests                                                              //
+///////////////////////////////////////////////////////////////////////////////////
+
+   task test_rx;
+      begin
+	 set_impulse_len(1);
+	 set_zero_len(999);
+	 set_rx_muxctrl(1);
+	 set_ddc_freq(0);
+	 set_rx_scale_iq(1243, 1243);
+	 set_decim(0, 1, 3);
+
+	 #100000 $finish;
+      end
+   endtask // test_rx
+   
+      
+///////////////////////////////////////////////////////////////////////////////////
+// Top-level test                                                                //
+///////////////////////////////////////////////////////////////////////////////////
+
+   // Execute tests
+   initial
+     begin
+	power_on();
+	test_rx();
+     end
+
+endmodule // dsp_core_tb
diff --git a/fpga/usrp2/top/u2_rev3_iad/impulse.v b/fpga/usrp2/top/u2_rev3_iad/impulse.v
new file mode 100644
index 000000000..7f0cdc9be
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/impulse.v
@@ -0,0 +1,63 @@
+module impulse
+  (input clk,
+   input rst,
+   input ena,
+   
+   input [13:0] dc_offset_a,
+   input [13:0] dc_offset_b,
+   input [13:0] amplitude,
+   input [15:0] impulse_len,
+   input [15:0] zero_len,
+
+   output [13:0] adc_a,
+   output [13:0] adc_b,
+   output        adc_ovf_a,
+   output        adc_ovf_b
+   );
+
+   reg [13:0] adc_a_int = 0;
+   reg [15:0] count;
+
+   localparam ST_ZERO = 0;
+   localparam ST_HIGH = 1;
+   reg 	      state;
+   
+   always @(posedge clk)
+     if (rst | ~ena)
+       begin
+	  adc_a_int <= 0;
+	  count <= 0;
+	  state <= ST_ZERO;
+       end
+     else
+       case(state)
+	 ST_ZERO:
+	   if (count == zero_len)
+	     begin
+		adc_a_int <= amplitude;
+		state <= ST_HIGH;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+	 ST_HIGH:
+	   if (count == impulse_len)
+	     begin
+		adc_a_int <= 0;
+		state <= ST_ZERO;
+		count <= 0;
+	     end
+	   else
+	     count <= count + 1;
+
+       endcase // case (state)
+
+   assign adc_a = adc_a_int + dc_offset_a;
+
+   // Ignore for now
+   assign adc_b = dc_offset_b;
+   assign adc_ovf_a = 0;
+   assign adc_ovf_b = 0;
+
+endmodule // impulse
diff --git a/fpga/usrp2/top/u2_rev3_iad/wave.sh b/fpga/usrp2/top/u2_rev3_iad/wave.sh
new file mode 100755
index 000000000..626f224e5
--- /dev/null
+++ b/fpga/usrp2/top/u2_rev3_iad/wave.sh
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+gtkwave dsp_core_tb.vcd dsp_core_tb.sav &
diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/u2plus/u2plus.ucf
new file mode 100755
index 000000000..091eb2005
--- /dev/null
+++ b/fpga/usrp2/top/u2plus/u2plus.ucf
@@ -0,0 +1,354 @@
+NET "DAC_LOCK"  LOC = "P4"  ;
+NET "ADC_clkout_p"  LOC = "P1"  ;
+NET "ADC_clkout_n"  LOC = "P2"  ;
+NET "io_rx<15>"  LOC = "AD1"  ;
+NET "io_rx<14>"  LOC = "AD2"  ;
+NET "io_rx<13>"  LOC = "AC2"  ;
+NET "io_rx<12>"  LOC = "AC3"  ;
+NET "io_rx<11>"  LOC = "W7"  ;
+NET "io_rx<10>"  LOC = "W6"  ;
+NET "io_rx<09>"  LOC = "U9"  ;
+NET "io_rx<08>"  LOC = "V8"  ;
+NET "io_rx<07>"  LOC = "AB1"  ;
+NET "io_rx<06>"  LOC = "AC1"  ;
+NET "io_rx<05>"  LOC = "V7"  ;
+NET "io_rx<04>"  LOC = "V6"  ;
+NET "io_rx<03>"  LOC = "Y5"  ;
+NET "ADCB_2_3_p"  LOC = "U7"  ;
+NET "ADCB_2_3_n"  LOC = "U8"  ;
+NET "ADCB_0_1_p"  LOC = "AA2"  ;
+NET "ADCB_0_1_n"  LOC = "AA3"  ;
+NET "ADCA_12_13_p"  LOC = "Y1"  ;
+NET "ADCA_12_13_n"  LOC = "Y2"  ;
+NET "ADCA_10_11_p"  LOC = "W3"  ;
+NET "ADCA_10_11_n"  LOC = "W4"  ;
+NET "ADCA_8_9_p"  LOC = "T7"  ;
+NET "ADCA_8_9_n"  LOC = "U6"  ;
+NET "ADCA_6_7_p"  LOC = "U5"  ;
+NET "ADCA_6_7_n"  LOC = "V5"  ;
+NET "ADCA_4_5_p"  LOC = "T10"  ;
+NET "ADCA_4_5_n"  LOC = "T9"  ;
+NET "ADCA_2_3_p"  LOC = "V1"  ;
+NET "ADCA_2_3_n"  LOC = "V2"  ;
+NET "ADCA_0_1_p"  LOC = "R8"  ;
+NET "ADCA_0_1_n"  LOC = "R7"  ;
+NET "TX00_A"  LOC = "P8"  ;
+NET "TX01_A"  LOC = "P9"  ;
+NET "TX02_A"  LOC = "R5"  ;
+NET "TX03_A"  LOC = "R6"  ;
+NET "TX04_A"  LOC = "P7"  ;
+NET "TX05_A"  LOC = "P6"  ;
+NET "TX06_A"  LOC = "T3"  ;
+NET "TX07_A"  LOC = "T4"  ;
+NET "TX08_A"  LOC = "R3"  ;
+NET "TX09_A"  LOC = "R4"  ;
+NET "TX10_A"  LOC = "R2"  ;
+NET "TX11_A"  LOC = "N1"  ;
+NET "TX12_A"  LOC = "N2"  ;
+NET "TX13_A"  LOC = "N5"  ;
+NET "TX14_A"  LOC = "N4"  ;
+NET "TX15_A"  LOC = "M2"  ;
+NET "TX00_B"  LOC = "M5"  ;
+NET "TX01_B"  LOC = "M6"  ;
+NET "TX02_B"  LOC = "M4"  ;
+NET "TX03_B"  LOC = "M3"  ;
+NET "TX04_B"  LOC = "M8"  ;
+NET "TX05_B"  LOC = "M7"  ;
+NET "TX06_B"  LOC = "L4"  ;
+NET "TX07_B"  LOC = "L3"  ;
+NET "TX08_B"  LOC = "K3"  ;
+NET "TX09_B"  LOC = "K2"  ;
+NET "TX10_B"  LOC = "K5"  ;
+NET "TX11_B"  LOC = "K4"  ;
+NET "TX12_B"  LOC = "M10"  ;
+NET "TX13_B"  LOC = "M9"  ;
+NET "TX14_B"  LOC = "J5"  ;
+NET "TX15_B"  LOC = "J4"  ;
+NET "io_tx<15>"  LOC = "K6"  ;
+NET "io_tx<14>"  LOC = "L7"  ;
+NET "io_tx<13>"  LOC = "H2"  ;
+NET "io_tx<12>"  LOC = "H1"  ;
+NET "io_tx<11>"  LOC = "L10"  ;
+NET "io_tx<10>"  LOC = "L9"  ;
+NET "io_tx<09>"  LOC = "G3"  ;
+NET "io_tx<08>"  LOC = "F3"  ;
+NET "io_tx<07>"  LOC = "K7"  ;
+NET "io_tx<06>"  LOC = "J6"  ;
+NET "io_tx<05>"  LOC = "E1"  ;
+NET "io_tx<04>"  LOC = "F2"  ;
+NET "io_tx<03>"  LOC = "J7"  ;
+NET "io_tx<02>"  LOC = "H6"  ;
+NET "io_tx<01>"  LOC = "F5"  ;
+NET "io_tx<00>"  LOC = "G4"  ;
+NET "MOSI_RX_ADC"  LOC = "E3"  ;
+NET "SCLK_RX_ADC"  LOC = "F4"  ;
+NET "SEN_RX_ADC"  LOC = "D3"  ;
+NET "SCLK_RX_DAC"  LOC = "E4"  ;
+NET "SEN_RX_DAC"  LOC = "K9"  ;
+NET "MOSI_RX_DAC"  LOC = "K8"  ;
+NET "SCLK_RX_DB"  LOC = "G6"  ;
+NET "MOSI_RX_DB"  LOC = "H7"  ;
+NET "SEN_RX_DB"  LOC = "B2"  ;
+NET "SCLK_ADC"  LOC = "B1"  ;
+NET "MOSI_ADC"  LOC = "J8"  ;
+NET "SEN_ADC"  LOC = "J9"  ;
+NET "ADCB_4_5_p"  LOC = "AE1"  ;
+NET "ADCB_4_5_n"  LOC = "AE2"  ;
+NET "ADCB_6_7_p"  LOC = "W1"  ;
+NET "ADCB_6_7_n"  LOC = "W2"  ;
+NET "ADCB_8_9_p"  LOC = "U3"  ;
+NET "ADCB_8_9_n"  LOC = "V4"  ;
+NET "ADCB_10_11_p"  LOC = "J1"  ;
+NET "ADCB_10_11_n"  LOC = "K1"  ;
+NET "ADCB_12_13_p"  LOC = "J3"  ;
+NET "ADCB_12_13_n"  LOC = "J2"  ;
+NET "MISO_RX_DB"  LOC = "H4"  ;
+NET "MISO_RX_ADC"  LOC = "C1"  ;
+NET "MISO_TX_DB"  LOC = "AA5"  ;
+NET "MISO_DAC"  LOC = "Y3"  ;
+NET "MISO_TX_ADC"  LOC = "G1"  ;
+NET "io_rx<02>"  LOC = "R10"  ;
+NET "io_rx<01>"  LOC = "R1"  ;
+NET "io_rx<00>"  LOC = "M1"  ;
+NET "exp_user_out_p"  LOC = "AF14"  ;
+NET "exp_user_out_n"  LOC = "AE14"  ;
+NET "exp_time_out_p"  LOC = "Y14"  ;
+NET "exp_time_out_n"  LOC = "AA14"  ;
+NET "CLK_FPGA_P"  LOC = "AA13"  ;
+NET "CLK_FPGA_N"  LOC = "Y13"  ;
+NET "leds<5>"  LOC = "AF25"  ;
+NET "leds<4>"  LOC = "AE25"  ;
+NET "leds<3>"  LOC = "AF23"  ;
+NET "leds<2>"  LOC = "AE23"  ;
+NET "leds<1>"  LOC = "AB18"  ;
+NET "SEN_CLK"  LOC = "AA18"  ;
+NET "MOSI_CLK"  LOC = "W17"  ;
+NET "SCLK_CLK"  LOC = "V17"  ;
+NET "CLK_STATUS"  LOC = "AD22"  ;
+NET "CLK_FUNC"  LOC = "AC21"  ;
+NET "clk_sel<0>"  LOC = "AE21"  ;
+NET "clk_sel<1>"  LOC = "AD21"  ;
+NET "clk_en<1>"  LOC = "AA17"  ;
+NET "clk_en<0>"  LOC = "Y17"  ;
+NET "SDA"  LOC = "V16"  ;
+NET "SCL"  LOC = "U16"  ;
+NET "TXD3"  LOC = "AD20"  ;
+NET "TXD2"  LOC = "AC20"  ;
+NET "TXD1"  LOC = "AD19"  ;
+NET "debug<00>"  LOC = "AC19"  ;
+NET "debug<01>"  LOC = "AF20"  ;
+NET "debug<02>"  LOC = "AE20"  ;
+NET "debug<03>"  LOC = "AC16"  ;
+NET "debug<04>"  LOC = "AB16"  ;
+NET "debug<05>"  LOC = "AF19"  ;
+NET "debug<06>"  LOC = "AE19"  ;
+NET "debug<07>"  LOC = "V15"  ;
+NET "debug<08>"  LOC = "U15"  ;
+NET "debug<09>"  LOC = "AE17"  ;
+NET "debug<10>"  LOC = "AD17"  ;
+NET "debug<11>"  LOC = "V14"  ;
+NET "debug<12>"  LOC = "W15"  ;
+NET "debug<13>"  LOC = "AC15"  ;
+NET "debug<14>"  LOC = "AD14"  ;
+NET "debug<15>"  LOC = "AC14"  ;
+NET "debug_clk<1>"  LOC = "AD11"  ;
+NET "debug<16>"  LOC = "AC11"  ;
+NET "debug<17>"  LOC = "AB12"  ;
+NET "debug<18>"  LOC = "AC12"  ;
+NET "debug<19>"  LOC = "V13"  ;
+NET "debug<20>"  LOC = "W13"  ;
+NET "debug<21>"  LOC = "AE8"  ;
+NET "debug<22>"  LOC = "AF8"  ;
+NET "debug<23>"  LOC = "V12"  ;
+NET "debug<24>"  LOC = "W12"  ;
+NET "debug<25>"  LOC = "AB9"  ;
+NET "debug<26>"  LOC = "AC9"  ;
+NET "debug<27>"  LOC = "AC8"  ;
+NET "debug<28>"  LOC = "AB7"  ;
+NET "debug<29>"  LOC = "V11"  ;
+NET "debug<30>"  LOC = "U11"  ;
+NET "debug<31>"  LOC = "Y10"  ;
+NET "debug_clk<0>"  LOC = "AA10"  ;
+NET "SEN_DAC"  LOC = "AE7"  ;
+NET "SCLK_DAC"  LOC = "AF5"  ;
+NET "MOSI_DAC"  LOC = "AE6"  ;
+NET "MOSI_TX_ADC"  LOC = "V10"  ;
+NET "SEN_TX_ADC"  LOC = "W10"  ;
+NET "SCLK_TX_ADC"  LOC = "AC6"  ;
+NET "MOSI_TX_DAC"  LOC = "AD6"  ;
+NET "SEN_TX_DAC"  LOC = "AE4"  ;
+NET "SCLK_TX_DAC"  LOC = "AF4"  ;
+NET "SCLK_TX_DB"  LOC = "AE3"  ;
+NET "MOSI_TX_DB"  LOC = "AF3"  ;
+NET "SEN_TX_DB"  LOC = "W9"  ;
+NET "RXD3"  LOC = "AF17"  ;
+NET "RXD2"  LOC = "AF15"  ;
+NET "RXD1"  LOC = "AD12"  ;
+NET "MISO_CLK"  LOC = "AC10"  ;
+NET "PPS_IN"  LOC = "AB6"  ;
+NET "PPS2_IN"  LOC = "AA20"  ;
+NET "ser_rx_clk"  LOC = "P18"  ;
+NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
+NET "CLK_TO_MAC"  LOC = "P26"  ;
+NET "GMII_TX_CLK"  LOC = "P25"  ;
+NET "GMII_RX_CLK"  LOC = "P21"  ;
+NET "ETH_LED"  LOC = "H20"  ;
+NET "GMII_TXD7"  LOC = "G21"  ;
+NET "GMII_TXD6"  LOC = "C26"  ;
+NET "GMII_TXD5"  LOC = "C25"  ;
+NET "GMII_TXD4"  LOC = "J21"  ;
+NET "GMII_TXD3"  LOC = "H21"  ;
+NET "GMII_TXD2"  LOC = "D25"  ;
+NET "GMII_TXD1"  LOC = "D24"  ;
+NET "GMII_TXD0"  LOC = "E26"  ;
+NET "GMII_TX_EN"  LOC = "D26"  ;
+NET "GMII_TX_ER"  LOC = "J19"  ;
+NET "GMII_GTX_CLK"  LOC = "J20"  ;
+NET "GMII_RXD7"  LOC = "G22"  ;
+NET "GMII_RXD6"  LOC = "K19"  ;
+NET "GMII_RXD5"  LOC = "K18"  ;
+NET "GMII_RXD4"  LOC = "E24"  ;
+NET "GMII_RXD3"  LOC = "F23"  ;
+NET "GMII_RXD2"  LOC = "L18"  ;
+NET "GMII_RXD1"  LOC = "L17"  ;
+NET "GMII_RXD0"  LOC = "F25"  ;
+NET "GMII_RX_DV"  LOC = "F24"  ;
+NET "GMII_RX_ER"  LOC = "L20"  ;
+NET "GMII_CRS"  LOC = "K20"  ;
+NET "GMII_COL"  LOC = "G23"  ;
+NET "PHY_INTn"  LOC = "L22"  ;
+NET "MDIO"  LOC = "K21"  ;
+NET "MDC"  LOC = "J23"  ;
+NET "PHY_RESET"  LOC = "J22"  ;
+NET "exp_time_in_p"  LOC = "N18"  ;
+NET "exp_time_in_n"  LOC = "N17"  ;
+NET "exp_user_in_p"  LOC = "L24"  ;
+NET "exp_user_in_n"  LOC = "M23"  ;
+NET "ser_prbsen"  LOC = "U23"  ;
+NET "ser_loopen"  LOC = "R19"  ;
+NET "ser_enable"  LOC = "R20"  ;
+NET "ser_t<15>"  LOC = "V23"  ;
+NET "ser_t<14>"  LOC = "U22"  ;
+NET "ser_t<13>"  LOC = "V24"  ;
+NET "ser_t<12>"  LOC = "V25"  ;
+NET "ser_t<11>"  LOC = "W23"  ;
+NET "ser_t<10>"  LOC = "V22"  ;
+NET "ser_t<09>"  LOC = "T18"  ;
+NET "ser_t<08>"  LOC = "T17"  ;
+NET "ser_t<07>"  LOC = "Y24"  ;
+NET "ser_t<06>"  LOC = "Y25"  ;
+NET "ser_t<05>"  LOC = "U21"  ;
+NET "ser_t<04>"  LOC = "T20"  ;
+NET "ser_t<03>"  LOC = "Y22"  ;
+NET "ser_t<02>"  LOC = "Y23"  ;
+NET "ser_t<01>"  LOC = "U19"  ;
+NET "ser_t<00>"  LOC = "U18"  ;
+NET "ser_tkmsb"  LOC = "AA24"  ;
+NET "ser_tklsb"  LOC = "AA25"  ;
+NET "ser_r<15>"  LOC = "V21"  ;
+NET "ser_r<14>"  LOC = "U20"  ;
+NET "ser_r<13>"  LOC = "AA22"  ;
+NET "ser_r<12>"  LOC = "AA23"  ;
+NET "ser_r<11>"  LOC = "V18"  ;
+NET "ser_r<10>"  LOC = "V19"  ;
+NET "ser_r<09>"  LOC = "AB23"  ;
+NET "ser_r<08>"  LOC = "AC26"  ;
+NET "ser_r<07>"  LOC = "AB26"  ;
+NET "ser_r<06>"  LOC = "AD26"  ;
+NET "ser_r<05>"  LOC = "AC25"  ;
+NET "ser_r<04>"  LOC = "W20"  ;
+NET "ser_r<03>"  LOC = "W21"  ;
+NET "ser_r<02>"  LOC = "AC23"  ;
+NET "ser_r<01>"  LOC = "AC24"  ;
+NET "ser_r<00>"  LOC = "AE26"  ;
+NET "ser_rkmsb"  LOC = "AD25"  ;
+NET "ser_rklsb"  LOC = "Y20"  ;
+NET "ser_rx_en"  LOC = "Y21"  ;
+NET "FPGA_RESET"  LOC = "K24"  ;
+NET "RAM_D<17>"  LOC = "F7"  ;
+NET "RAM_D<16>"  LOC = "E7"  ;
+NET "RAM_D<15>"  LOC = "G9"  ;
+NET "RAM_D<14>"  LOC = "H9"  ;
+NET "RAM_D<13>"  LOC = "G10"  ;
+NET "RAM_D<12>"  LOC = "H10"  ;
+NET "RAM_D<11>"  LOC = "A4"  ;
+NET "RAM_D<10>"  LOC = "B4"  ;
+NET "RAM_D<09>"  LOC = "C5"  ;
+NET "RAM_D<08>"  LOC = "D6"  ;
+NET "RAM_D<07>"  LOC = "J11"  ;
+NET "RAM_D<06>"  LOC = "K11"  ;
+NET "RAM_D<05>"  LOC = "B7"  ;
+NET "RAM_D<04>"  LOC = "C7"  ;
+NET "RAM_D<03>"  LOC = "B6"  ;
+NET "RAM_D<02>"  LOC = "C6"  ;
+NET "RAM_D<01>"  LOC = "C8"  ;
+NET "RAM_D<00>"  LOC = "D8"  ;
+NET "RAM_ZZ"  LOC = "J12"  ;
+NET "RAM_BWn<3>"  LOC = "D9"  ;
+NET "RAM_BWn<2>"  LOC = "A9"  ;
+NET "RAM_BWn<1>"  LOC = "B9"  ;
+NET "RAM_BWn<0>"  LOC = "G12"  ;
+NET "RAM_LDn"  LOC = "H12"  ;
+NET "RAM_OEn"  LOC = "C10"  ;
+NET "RAM_WEn"  LOC = "D10"  ;
+NET "RAM_CLK"  LOC = "A10"  ;
+NET "RAM_CENn"  LOC = "B10"  ;
+NET "RAM_A<00>"  LOC = "C11"  ;
+NET "RAM_A<01>"  LOC = "E12"  ;
+NET "RAM_A<02>"  LOC = "F12"  ;
+NET "RAM_A<03>"  LOC = "D13"  ;
+NET "RAM_A<04>"  LOC = "C12"  ;
+NET "RAM_A<05>"  LOC = "A12"  ;
+NET "RAM_A<06>"  LOC = "B12"  ;
+NET "RAM_A<07>"  LOC = "E14"  ;
+NET "RAM_A<08>"  LOC = "F14"  ;
+NET "RAM_A<09>"  LOC = "B15"  ;
+NET "RAM_A<10>"  LOC = "A15"  ;
+NET "RAM_A<11>"  LOC = "D16"  ;
+NET "RAM_A<12>"  LOC = "C15"  ;
+NET "RAM_A<13>"  LOC = "D17"  ;
+NET "RAM_A<14>"  LOC = "C16"  ;
+NET "RAM_A<15>"  LOC = "F15"  ;
+NET "RAM_A<16>"  LOC = "C17"  ;
+NET "RAM_A<17>"  LOC = "B17"  ;
+NET "RAM_A<18>"  LOC = "B18"  ;
+NET "RAM_A<19>"  LOC = "A18"  ;
+NET "RAM_A<20>"  LOC = "D18"  ;
+NET "RAM_D<35>"  LOC = "K16"  ;
+NET "RAM_D<34>"  LOC = "D20"  ;
+NET "RAM_D<33>"  LOC = "C20"  ;
+NET "RAM_D<32>"  LOC = "E21"  ;
+NET "RAM_D<31>"  LOC = "D21"  ;
+NET "RAM_D<30>"  LOC = "C21"  ;
+NET "RAM_D<29>"  LOC = "B21"  ;
+NET "RAM_D<28>"  LOC = "H17"  ;
+NET "RAM_D<27>"  LOC = "G17"  ;
+NET "RAM_D<26>"  LOC = "B23"  ;
+NET "RAM_D<25>"  LOC = "A22"  ;
+NET "RAM_D<24>"  LOC = "D23"  ;
+NET "RAM_D<23>"  LOC = "C23"  ;
+NET "RAM_D<22>"  LOC = "D22"  ;
+NET "RAM_D<21>"  LOC = "C22"  ;
+NET "RAM_D<20>"  LOC = "F19"  ;
+NET "RAM_D<19>"  LOC = "G20"  ;
+NET "RAM_D<18>"  LOC = "F20"  ;
+#NET "unnamed_net20"  LOC = "V20"  ;  # SUSPEND
+NET "PROG_B"  LOC = "A2"  ;
+NET "PUDC_B"  LOC = "G8"  ;
+NET "DONE"  LOC = "AB21"  ;
+NET "flash_miso"  LOC = "AF24"  ;
+NET "flash_clk"  LOC = "AE24"  ;
+NET "INIT_B"  LOC = "AA15"  ;
+NET "flash_mosi"  LOC = "AB15"  ;
+#NET "unnamed_net19"  LOC = "AE9"  ;    # VS1
+#NET "unnamed_net18"  LOC = "AF9"  ;    # VS0
+#NET "unnamed_net17"  LOC = "AA12"  ;   # VS2
+#NET "unnamed_net16"  LOC = "Y7"  ;     # M2
+NET "flash_cs"  LOC = "AA7"  ;
+#NET "unnamed_net15"  LOC = "AC4"  ;    # M1
+#NET "unnamed_net14"  LOC = "AD4"  ;    # M0
+#NET "unnamed_net13"  LOC = "D4"  ;     # TMS
+#NET "unnamed_net12"  LOC = "E23"  ;    # TDO
+#NET "unnamed_net11"  LOC = "G7"  ;     # TDI
+#NET "unnamed_net10"  LOC = "A25"  ;    # TCK
+
diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v
new file mode 100644
index 000000000..e95445867
--- /dev/null
+++ b/fpga/usrp2/top/u2plus/u2plus.v
@@ -0,0 +1,377 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2plus
+  (
+   // Misc, debug
+   output [4:0] leds,  // LED4 is shared w/INIT_B
+   input [3:0] dipsw,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+   output uart_tx_o,
+   input uart_rx_i,
+   
+   // Expansion
+   input exp_pps_in_p, // Diff
+   input exp_pps_in_n, // Diff
+   output exp_pps_out_p, // Diff 
+   output exp_pps_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+   input clk_to_mac,
+   output eth_led,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+   input dac_lock,     // unused for now
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input pps_in,
+   input POR,
+   
+   // AD9510 SPI
+   output sclk,
+   output sen_clk,
+   output sdi,
+   input sdo,
+
+   // TX side SPI -- tx_db, tx_adc, tx_dac, 9777
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output mosi_tx,
+   input miso_dac,
+   input miso_tx_db,
+   input miso_tx_adc,
+   output sclk_tx,
+
+   // RX side SPI
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+
+   // DB IO Pins
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // SPI Flash
+   output flash_cs,
+   output flash_clk,
+   output flash_mosi,
+   input flash_miso
+   );
+
+   // FPGA-specific pins connections
+   wire 	aux_clk = PHY_CLK;
+
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+   
+   wire 	exp_pps_in;
+   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_pps_out;
+   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge aux_clk)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   wire 	clk_muxed = clock_ready ? clk_fpga : aux_clk;
+
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_muxed), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(), 
+                 .CLK180(), 
+                 .CLK270(), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [4:0] leds_int;
+   assign     leds = ~leds_int;  // drive low to turn on leds
+   
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+   
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+   u2_core u2_core(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_pps_in),
+		     .exp_pps_out	(exp_pps_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .PHY_CLK		(PHY_CLK),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(adc_ovf_a),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(adc_ovf_b),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(dac_a[15:0]),
+		     .dac_b		(dac_b[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (uart_tx_o),
+		     //.uart_rx_i         (uart_rx_i),
+		     .uart_rx_i         (),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+   
+endmodule // u2plus
diff --git a/fpga/usrp2/udp/add_onescomp.v b/fpga/usrp2/udp/add_onescomp.v
new file mode 100644
index 000000000..048842a86
--- /dev/null
+++ b/fpga/usrp2/udp/add_onescomp.v
@@ -0,0 +1,12 @@
+
+
+module add_onescomp
+  #(parameter WIDTH = 16)
+   (input [WIDTH-1:0] A,
+    input [WIDTH-1:0] B,
+    output [WIDTH-1:0] SUM);
+
+   wire [WIDTH:0] SUM_INT = {1'b0,A} + {1'b0,B};
+   assign SUM  = SUM_INT[WIDTH-1:0] + {{WIDTH-1{1'b0}},SUM_INT[WIDTH]};
+   
+endmodule // add_onescomp
diff --git a/fpga/usrp2/udp/fifo19_rxrealign.v b/fpga/usrp2/udp/fifo19_rxrealign.v
new file mode 100644
index 000000000..35ad90951
--- /dev/null
+++ b/fpga/usrp2/udp/fifo19_rxrealign.v
@@ -0,0 +1,42 @@
+
+
+//  Adds a junk line at the beginning of every packet, which the
+//   following stages should ignore.  This gives us proper alignment due
+//   to the 14 byte ethernet header
+
+// Bit 18 -- odd length
+// Bit 17 -- eof
+// Bit 16 -- sof
+// Bit 15:0 -- data
+
+module fifo19_rxrealign
+  (input clk, input reset, input clear,
+   input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+   output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+   
+   reg 	rxre_state;
+   localparam RXRE_DUMMY  = 0;
+   localparam RXRE_PKT 	  = 1;
+   
+   assign dataout[18] 	  = datain[18];
+   assign dataout[17] 	  = datain[17];
+   assign dataout[16] 	  = (rxre_state==RXRE_DUMMY) | (datain[17] & datain[16]);  // allows for passing error signal
+   assign dataout[15:0] = datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       rxre_state <= RXRE_DUMMY;
+     else if(src_rdy_i & dst_rdy_i)
+       case(rxre_state)
+	 RXRE_DUMMY :
+	   rxre_state <= RXRE_PKT;
+	 RXRE_PKT :
+	   if(datain[17])   // if eof or error
+	     rxre_state <= RXRE_DUMMY;
+       endcase // case (rxre_state)
+
+   assign src_rdy_o 	 = src_rdy_i & dst_rdy_i;   // Send anytime both sides are ready
+   assign dst_rdy_o = src_rdy_i & dst_rdy_i & (rxre_state == RXRE_PKT);  // Only consume after the dummy
+   
+endmodule // fifo19_rxrealign
+
diff --git a/fpga/usrp2/udp/prot_eng_rx.v b/fpga/usrp2/udp/prot_eng_rx.v
new file mode 100644
index 000000000..5df158b2b
--- /dev/null
+++ b/fpga/usrp2/udp/prot_eng_rx.v
@@ -0,0 +1,121 @@
+
+
+
+// Protocol Engine Receiver
+//  Checks each line (16 bits) against values in setting regs
+//  3 options for each line -- 
+//      Error if mismatch, Slowpath if mismatch, or ignore line
+//  The engine increases the length of each packet by 32 or 48 bits,
+//   bringing the total length to a multiple of 32 bits.  The last line
+//   is entirely new, and contains the results of the matching operation:
+//      16 bits of flags, 16 bits of data.  Flags indicate error or slowpath
+//      Data indicates line that caused mismatch if any.
+
+
+//   Flags[2:0] is {occ, eop, sop}
+//   Protocol word format is:
+//             22   Last Header Line
+//             21   SLOWPATH if mismatch
+//             20   ERROR if mismatch
+//             19   This is the IP checksum
+//             18   This is the UDP checksum
+//             17   Compute IP checksum on this word
+//             16   Compute UDP checksum on this word
+//           15:0   data word to be matched
+
+module prot_eng_rx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   localparam HDR_WIDTH  = 16 + 7;  // 16 bits plus flags
+   localparam HDR_LEN 	 = 32;      // Up to 64 bytes of protocol
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
+   wire [HDR_WIDTH-1:0] header_word;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hE0) == BASE))
+       header_ram[set_addr[4:0]] <= set_data;
+
+   assign header_word 	= header_ram[state];
+
+   wire consume_input 	= src_rdy_i & dst_rdy_o;
+   wire produce_output 	= src_rdy_o & dst_rdy_i;
+   
+   // Main State Machine
+   reg [15:0] pkt_length, fail_word, dataout_int;
+   
+   reg slowpath, error, sof_o, eof_o, occ_o, odd;
+
+   assign dataout    = {occ_o, eof_o, sof_o, dataout_int};
+
+   wire [15:0] calc_ip_checksum, calc_udp_checksum;
+   reg [15:0] rx_ip_checksum, rx_udp_checksum;
+
+   always @(posedge clk) 
+     if(header_word[19]) 
+       rx_ip_checksum  <= datain[15:0];
+   always @(posedge clk) 
+     if(header_word[18]) 
+       rx_udp_checksum <= datain[15:0];
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  slowpath     <= 0;
+	  error        <= 0;
+	  state        <= 0;
+	  fail_word    <= 0;
+	  eof_o        <= 0;
+	  occ_o        <= 0;
+       end
+     else if(src_rdy_i & dst_rdy_i)
+       case (state)
+	 0 :
+	   begin
+	      slowpath 	   <= 0;
+	      error 	   <= 0;
+	      eof_o 	   <= 0;
+	      occ_o 	   <= 0;
+	      state 	   <= 1;
+	   end
+
+	 ST_SLOWPATH :
+	   ;
+	 ST_ERROR :
+	   ;
+	 ST_PAYLOAD :
+	   ;
+	 ST_FILLER :
+	   ;
+	 ST_END1 :
+	   ;
+	 ST_END2 :
+	   ;
+	 default :
+	   if(header_word[21] && mismatch)
+	     state <= ST_SLOWPATH;
+	   else if(header_word[20] && mismatch)
+	     state <= ST_ERROR;
+	   else if(header_word[22])
+	     state <= ST_PAYLOAD;
+	   else
+	     state <= state + 1;
+       endcase // case (state)
+   
+
+
+   // IP + UDP checksum state machines
+   checksum_sm ip_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[17]), .clear(state==0), .checksum(ip_checksum));
+   
+   checksum_sm udp_chk
+     (.clk(clk), .reset(reset), .in(datain), 
+      .calc(consume_input & header_word[16]), .clear(state==0), .checksum(udp_checksum));
+   
+endmodule // prot_eng_rx
diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v
new file mode 100644
index 000000000..9031011f7
--- /dev/null
+++ b/fpga/usrp2/udp/prot_eng_tx.v
@@ -0,0 +1,119 @@
+
+// The input FIFO contents should be 16 bits wide
+//   The first word is 1 for fast path (accelerated protocol)
+//                     0 for software implemented protocol
+//   The second word is the number of bytes in the packet, 
+//         and must be valid even if we are in slow path mode
+//            Odd means the last word is half full
+//   Flags[1:0] is {eop, sop}
+//   Protocol word format is:
+//             19   Last Header Line
+//             18   IP Header Checksum XOR
+//             17   IP Length Here
+//             16   UDP Length Here
+//           15:0   data word to be sent
+
+module prot_eng_tx
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] datain, input src_rdy_i, output dst_rdy_o,
+    output [18:0] dataout, output src_rdy_o, input dst_rdy_i);
+
+   wire [2:0] flags_i = datain[18:16];
+   reg [15:0] dataout_int;
+   reg fast_path, sof_o;
+   
+   wire [2:0] flags_o 	 = {flags_i[2], flags_i[1], sof_o};  // OCC, EOF, SOF
+
+   assign dataout 	 = {flags_o[2:0], dataout_int[15:0]};
+
+   reg [4:0] state;
+   wire do_payload 	 = (state == 31);
+   
+   assign dst_rdy_o 	 = dst_rdy_i & (do_payload | (state==0) | (state==1) | (state==30));
+   assign src_rdy_o 	 = src_rdy_i & ~((state==0) | (state==1) | (state==30));
+   
+   localparam HDR_WIDTH  = 16 + 4;  // 16 bits plus flags
+   localparam HDR_LEN 	 = 32;      // Up to 64 bytes of protocol
+   
+   // Store header values in a small dual-port (distributed) ram
+   reg [HDR_WIDTH-1:0] header_ram[0:HDR_LEN-1];
+   wire [HDR_WIDTH-1:0] header_word;
+   
+   always @(posedge clk)
+     if(set_stb & ((set_addr & 8'hE0) == BASE))
+       header_ram[set_addr[4:0]] <= set_data;
+
+   assign header_word = header_ram[state];
+
+   wire last_hdr_line  = header_word[19];
+   wire ip_chk 	       = header_word[18];
+   wire ip_len 	       = header_word[17];
+   wire udp_len        = header_word[16];
+   
+   // Protocol State Machine
+   reg [15:0] length;
+   wire [15:0] ip_length = length + 28;  // IP HDR + UDP HDR
+   wire [15:0] udp_length = length + 8;  //  UDP HDR
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  state     <= 0;
+	  fast_path <= 0;
+	  sof_o   <= 0;
+       end
+     else
+       if(src_rdy_i & dst_rdy_i)
+	 case(state)
+	   0 :
+	     begin
+		fast_path <= datain[0];
+		state <= 1;
+	     end
+	   1 :
+	     begin
+		length 	<= datain[15:0];
+		sof_o <= 1;
+		if(fast_path)
+		  state <= 2;
+		else
+		  state <= 30;  // Skip 1 word for alignment
+	     end
+	   30 :
+	     state <= 31;
+	   31 :
+	     begin
+		sof_o <= 0;
+		if(flags_i[1]) // eop
+		  state <= 0;
+	     end
+	   default :
+	     begin
+		sof_o 	<= 0;
+		if(~last_hdr_line)
+		  state <= state + 1;
+		else
+		  state <= 31;
+	     end
+	 endcase // case (state)
+
+   wire [15:0] checksum;
+   add_onescomp #(.WIDTH(16)) add_onescomp 
+     (.A(header_word[15:0]),.B(ip_length),.SUM(checksum));
+
+   always @*
+     if(ip_chk)
+       //dataout_int 	<= header_word[15:0] ^ ip_length;
+       dataout_int 	<= 16'hFFFF ^ checksum;
+     else if(ip_len)
+       dataout_int 	<= ip_length;
+     else if(udp_len)
+       dataout_int 	<= udp_length;
+     else if(do_payload)
+       dataout_int 	<= datain[15:0];
+     else
+       dataout_int 	<= header_word[15:0];
+   
+endmodule // prot_eng_tx
diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v
new file mode 100644
index 000000000..e7ffeb5e1
--- /dev/null
+++ b/fpga/usrp2/udp/prot_eng_tx_tb.v
@@ -0,0 +1,167 @@
+module prot_eng_tx_tb();
+
+   localparam BASE = 128;
+   reg clk    = 0;
+   reg rst    = 1;
+   reg clear  = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data;
+   reg [1:0] f36_occ;
+   reg f36_sof, f36_eof;
+   
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg src_rdy_f36i  = 0;
+   reg [15:0] count;
+
+   wire [35:0] casc_do;
+   wire [18:0] final_out, prot_out;
+
+   wire src_rdy_final, dst_rdy_final, src_rdy_prot;
+   reg dst_rdy_prot =0;
+   
+   wire dst_rdy_f36o ;
+   fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(casc_do),.src_rdy_o(src_rdy_f36o),.dst_rdy_i(dst_rdy_f36o));
+
+   fifo36_to_fifo19 fifo_converter
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f36_datain(casc_do),.f36_src_rdy_i(src_rdy_f36o),.f36_dst_rdy_o(dst_rdy_f36o),
+      .f19_dataout(final_out),.f19_src_rdy_o(src_rdy_final),.f19_dst_rdy_i(dst_rdy_final));
+
+   reg set_stb;
+   reg [7:0] set_addr;
+   reg [31:0] set_data;
+	
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(rst),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .datain(final_out[18:0]),.src_rdy_i(src_rdy_final),.dst_rdy_o(dst_rdy_final),
+      .dataout(prot_out[18:0]),.src_rdy_o(src_rdy_prot),.dst_rdy_i(dst_rdy_prot));
+   
+   reg [35:0] printer;
+
+   task WriteSREG;
+      input [7:0] addr;
+      input [31:0] data;
+
+      begin
+	 @(posedge clk);
+	 set_addr <= addr;
+	 set_data <= data;
+	 set_stb  <= 1;
+	 @(posedge clk);
+	 set_stb <= 0;
+      end
+   endtask // WriteSREG
+   	
+   task ReadFromFIFO36;
+      begin
+	 $display("Read from FIFO36");
+	 #1 dst_rdy_prot <= 1;
+	 while(~src_rdy_prot)
+	   @(posedge clk);
+	 while(1)
+	   begin
+	      while(~src_rdy_prot)
+		@(posedge clk);
+	      $display("Read: %h",prot_out);
+	      @(posedge clk);
+	   end
+      end
+   endtask // ReadFromFIFO36
+   
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+	 count 	      <= 4;
+	 src_rdy_f36i <= 1;
+	 f36_data     <= 32'h0001_000c;
+	 f36_sof      <= 1;
+	 f36_eof      <= 0;
+	 f36_occ      <= 0;
+	
+	 $display("Put Packet in FIFO36");
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 $display("PPI_FIFO36: Entered First Line");
+	 f36_sof  <= 0;
+	 f36_data <= data_start;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 while(count+4 < data_len)
+	   begin
+	      f36_data <= f36_data + 32'h01010101;
+	      count    <= count + 4;
+	      while(~dst_rdy_f36i)
+		@(posedge clk);
+	      @(posedge clk);
+	      $display("PPI_FIFO36: Entered New Line");
+	   end
+	 f36_data  <= f36_data + 32'h01010101;
+	 f36_eof   <= 1;
+	 if(count + 4 == data_len)
+	   f36_occ <= 0;
+	 else if(count + 3 == data_len)
+	   f36_occ <= 3;
+	 else if(count + 2 == data_len)
+	   f36_occ <= 2;
+	 else
+	   f36_occ <= 1;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 f36_occ      <= 0;
+	 f36_eof      <= 0;
+	 f36_data     <= 0;
+	 src_rdy_f36i <= 0;
+	 $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("prot_eng_tx_tb.vcd");
+   initial $dumpvars(0,prot_eng_tx_tb);
+
+   initial
+     begin
+	#10000;
+	@(posedge clk);
+	ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	WriteSREG(BASE, {12'b0, 4'h0, 16'h0000});
+	WriteSREG(BASE+1, {12'b0, 4'h0, 16'h0000});
+	WriteSREG(BASE+2, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+3, {12'b0, 4'h0, 16'h1234});
+	WriteSREG(BASE+4, {12'b0, 4'h8, 16'h5678});
+	WriteSREG(BASE+5, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+6, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+7, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+8, {12'b0, 4'h0, 16'hABCD});
+	WriteSREG(BASE+9, {12'b0, 4'h0, 16'hABCD});
+	@(posedge clk);
+	PutPacketInFIFO36(32'hA0B0C0D0,16);
+	@(posedge clk);
+	@(posedge clk);
+	#10000;
+	@(posedge clk);
+	PutPacketInFIFO36(32'hE0F0A0B0,36);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // prot_eng_tx_tb
diff --git a/fpga/usrp2/udp/udp_wrapper.v b/fpga/usrp2/udp/udp_wrapper.v
new file mode 100644
index 000000000..f4c642615
--- /dev/null
+++ b/fpga/usrp2/udp/udp_wrapper.v
@@ -0,0 +1,92 @@
+
+module udp_wrapper
+  #(parameter BASE=0)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input [18:0] rx_f19_data, input rx_f19_src_rdy_i, output rx_f19_dst_rdy_o,
+    output [18:0] tx_f19_data, output tx_f19_src_rdy_o, input tx_f19_dst_rdy_i,
+    
+    output [35:0] rx_f36_data, output rx_f36_src_rdy_o, input rx_f36_dst_rdy_i,
+    input [35:0] tx_f36_data, input tx_f36_src_rdy_i, output tx_f36_dst_rdy_o,
+    output [31:0] debug
+    );
+
+   wire 	 tx_int1_src_rdy, tx_int1_dst_rdy;
+   wire [18:0] 	 tx_int1_data;
+   
+   wire 	 tx_int2_src_rdy, tx_int2_dst_rdy;
+   wire [18:0] 	 tx_int2_data;
+   wire [31:0] 	 debug_state;
+   
+   // TX side
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy_i), .f36_dst_rdy_o(tx_f36_dst_rdy_o),
+      .f19_dataout(tx_int1_data), .f19_src_rdy_o(tx_int1_src_rdy), .f19_dst_rdy_i(tx_int1_dst_rdy) );
+
+   fifo_short #(.WIDTH(19)) shortfifo19_a
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(tx_int1_data), .src_rdy_i(tx_int1_src_rdy), .dst_rdy_o(tx_int1_dst_rdy),
+      .dataout(tx_int2_data), .src_rdy_o(tx_int2_src_rdy), .dst_rdy_i(tx_int2_dst_rdy),
+      .space(), .occupied() );
+     
+   prot_eng_tx #(.BASE(BASE)) prot_eng_tx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .datain(tx_int2_data), .src_rdy_i(tx_int2_src_rdy), .dst_rdy_o(tx_int2_dst_rdy),
+      .dataout(tx_f19_data), .src_rdy_o(tx_f19_src_rdy_o), .dst_rdy_i(tx_f19_dst_rdy_i) );
+
+   // RX side
+   wire rx_int1_src_rdy, rx_int1_dst_rdy;
+   wire [18:0] rx_int1_data;
+      
+   wire rx_int2_src_rdy, rx_int2_dst_rdy;
+   wire [18:0] rx_int2_data;
+      
+   //wire        rx_int3_src_rdy, rx_int3_dst_rdy;
+   //wire [35:0] rx_int3_data;
+   
+`ifdef USE_PROT_ENG
+   prot_eng_rx #(.BASE(BASE+32)) prot_eng_rx
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`else
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy_i), .dst_rdy_o(rx_f19_dst_rdy_o),
+      .dataout(rx_int1_data), .src_rdy_o(rx_int1_src_rdy), .dst_rdy_i(rx_int1_dst_rdy) );
+`endif // !`ifdef USE_PROT_ENG
+   
+   fifo_short #(.WIDTH(19)) shortfifo19_b
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int1_data), .src_rdy_i(rx_int1_src_rdy), .dst_rdy_o(rx_int1_dst_rdy),
+      .dataout(rx_int2_data), .src_rdy_o(rx_int2_src_rdy), .dst_rdy_i(rx_int2_dst_rdy),
+      .space(), .occupied() );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy),
+      .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy_o), .f36_dst_rdy_i(rx_f36_dst_rdy_i),
+      .debug(debug_state));
+
+   /*
+   fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
+      .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy_o), .dst_rdy_i(rx_f36_dst_rdy_i),
+      .space(), .occupied() );
+*/
+   /*
+   assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i },
+		    { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy},
+		    { rx_int3_data[35:32], rx_f36_data[35:32] },
+		    { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } };
+    */
+
+   assign debug = { { 3'd0, tx_int1_src_rdy, tx_int1_dst_rdy, tx_int1_data[18:16] },
+		    { 3'd0, tx_int2_src_rdy, tx_int2_dst_rdy, tx_int2_data[18:16] },
+		    { tx_int2_data[15:8] },
+		    { tx_int2_data[7:0] } };
+   
+endmodule // udp_wrapper
diff --git a/fpga/usrp2/vrt/.gitignore b/fpga/usrp2/vrt/.gitignore
new file mode 100644
index 000000000..446b2daae
--- /dev/null
+++ b/fpga/usrp2/vrt/.gitignore
@@ -0,0 +1,4 @@
+vita_rx_tb
+vita_tx_tb
+*.vcd
+*.sav
diff --git a/fpga/usrp2/vrt/vita_rx.build b/fpga/usrp2/vrt/vita_rx.build
new file mode 100755
index 000000000..f6d2d75a3
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_rx.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v
new file mode 100644
index 000000000..669b8299d
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_rx_control.v
@@ -0,0 +1,180 @@
+
+module vita_rx_control
+  #(parameter BASE=0,
+    parameter WIDTH=32)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input [63:0] vita_time,
+    output overrun,
+
+    // To vita_rx_framer
+    output [4+64+WIDTH-1:0] sample_fifo_o,
+    output sample_fifo_src_rdy_o,
+    input sample_fifo_dst_rdy_i,
+    
+    // From DSP Core
+    input [WIDTH-1:0] sample,
+    output run,
+    input strobe,
+    
+    output [31:0] debug_rx
+    );
+
+   // FIXME add TX Interruption (halt, pause, continue) functionality
+   
+   wire [63:0] 	  new_time;
+   wire [31:0] 	  new_command;
+   wire 	  sc_pre1, clear_int, clear_reg;
+
+   assign clear_int  = clear | clear_reg;
+   
+   wire [63:0] 	  rcvtime_pre;
+   reg [63:0] 	  rcvtime;
+   wire [29:0] 	  numlines_pre;
+   wire 	  send_imm_pre, chain_pre;
+   reg 		  send_imm, chain;
+   wire 	  full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+   reg 		  sc_pre2;
+   wire [33:0] 	  fifo_line;
+   reg [29:0] 	  lines_left;
+   reg [2:0] 	  ibs_state;
+   wire 	  now, early, late;
+   wire 	  sample_fifo_in_rdy;
+   
+   setting_reg #(.my_addr(BASE)) sr_cmd
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(new_command),.changed());
+
+   setting_reg #(.my_addr(BASE+1)) sr_time_h
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(new_time[63:32]),.changed());
+   
+   setting_reg #(.my_addr(BASE+2)) sr_time_l
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(new_time[31:0]),.changed(sc_pre1));
+   
+   setting_reg #(.my_addr(BASE+3)) sr_clear
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_reg));
+
+   // FIFO to store commands sent from the settings bus
+   always @(posedge clk)
+     sc_pre2 		  <= sc_pre1;
+   assign      write_ctrl  = sc_pre1 & ~sc_pre2;
+
+   wire [4:0]  command_queue_len;
+   shortfifo #(.WIDTH(96)) commandfifo
+     (.clk(clk),.rst(reset),.clear(clear_int),
+      .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl),
+      .dataout({send_imm_pre,chain_pre,numlines_pre,rcvtime_pre}), 
+      .read(read_ctrl), .empty(empty_ctrl),
+      .occupied(command_queue_len), .space() );
+   
+   reg [33:0]  pkt_fifo_line;
+
+   localparam IBS_IDLE = 0;
+   localparam IBS_WAITING = 1;
+   localparam IBS_RUNNING = 2;
+   localparam IBS_OVERRUN = 4;
+   localparam IBS_BROKENCHAIN = 5;
+   localparam IBS_LATECMD = 6;
+
+   wire signal_cmd_done     = (lines_left == 1) & (~chain | (~empty_ctrl & (numlines_pre==0)));
+   wire signal_overrun 	    = (ibs_state == IBS_OVERRUN);
+   wire signal_brokenchain  = (ibs_state == IBS_BROKENCHAIN);
+   wire signal_latecmd 	    = (ibs_state == IBS_LATECMD);
+
+   // Buffer of samples for while we're writing the packet headers
+   wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+
+   wire       attempt_sample_write    = ((run & strobe) | (ibs_state==IBS_OVERRUN) |
+				       (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD));
+   
+   fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo
+     (.clk(clk),.reset(reset),.clear(clear_int),
+      .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy),
+      .dataout(sample_fifo_o), 
+      .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
+      .space(), .occupied() );
+   
+   // Inband Signalling State Machine
+   time_compare 
+     time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late));
+   
+   wire too_late 	    = late & ~send_imm;
+   wire go_now 		    = now | send_imm;
+   wire full 		    = ~sample_fifo_in_rdy;
+   
+   always @(posedge clk)
+     if(reset | clear_int)
+       begin
+	  ibs_state 	   <= IBS_IDLE;
+	  lines_left 	   <= 0;
+	  rcvtime 	   <= 0;
+	  send_imm 	   <= 0;
+	  chain 	   <= 0;
+       end
+     else
+       case(ibs_state)
+	 IBS_IDLE :
+	   if(~empty_ctrl)
+	     begin
+		lines_left <= numlines_pre;
+		rcvtime <= rcvtime_pre;
+		ibs_state <= IBS_WAITING;
+		send_imm <= send_imm_pre;
+		chain <= chain_pre;
+	     end
+	 IBS_WAITING :
+	   if(go_now)
+	     ibs_state <= IBS_RUNNING;
+	   else if(too_late)
+	     ibs_state <= IBS_LATECMD;
+	 IBS_RUNNING :
+	   if(strobe)
+	     if(full)
+	       ibs_state 	     <= IBS_OVERRUN;
+	     else
+	       begin
+		  lines_left 	     <= lines_left - 1;
+		  if(lines_left == 1)
+		    if(~chain)
+		      ibs_state      <= IBS_IDLE;
+		    else if(empty_ctrl)
+		      ibs_state      <= IBS_BROKENCHAIN;
+		    else
+		      begin
+			 lines_left  <= numlines_pre;
+			 rcvtime     <= rcvtime_pre;
+			 send_imm    <= send_imm_pre;
+			 chain 	     <= chain_pre;
+			 if(numlines_pre == 0)  // If we are told to stop here
+			   ibs_state <= IBS_IDLE;
+			 else
+			   ibs_state <= IBS_RUNNING;
+		      end
+	       end // else: !if(full)
+	 IBS_OVERRUN :
+	   if(sample_fifo_in_rdy)
+	     ibs_state <= IBS_IDLE;
+	 IBS_LATECMD :
+	   if(sample_fifo_in_rdy)
+	     ibs_state <= IBS_IDLE;
+	 IBS_BROKENCHAIN :
+	   if(sample_fifo_in_rdy)
+	     ibs_state <= IBS_IDLE;
+       endcase // case(ibs_state)
+   
+   assign overrun = (ibs_state == IBS_OVERRUN);
+   assign run = (ibs_state == IBS_RUNNING);
+
+   assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) )
+     & ~empty_ctrl;
+   
+   assign debug_rx = { { ibs_state[2:0], command_queue_len },
+		       { 8'd0 },
+		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, full_ctrl, empty_ctrl },
+		       { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
+   
+endmodule // rx_control
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
new file mode 100644
index 000000000..f3a81664a
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -0,0 +1,199 @@
+
+module vita_rx_framer
+  #(parameter BASE=0,
+    parameter MAXCHAN=1)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    // To FIFO interface of Buffer Pool
+    output [35:0] data_o,
+    input dst_rdy_i,
+    output src_rdy_o,
+    
+    // From vita_rx_control
+    input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i,
+    input sample_fifo_src_rdy_i,
+    output sample_fifo_dst_rdy_o,
+    
+    // FIFO Levels
+    output [15:0] fifo_occupied,
+    output fifo_full,
+    output fifo_empty,
+    
+    output [31:0] debug_rx
+    );
+
+   localparam SAMP_WIDTH  = 4+64+(32*MAXCHAN);
+   reg [3:0] 	  sample_phase;
+   wire [3:0] 	  numchan;
+   wire [3:0] 	  flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4];
+   wire [63:0] 	  vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68];
+
+   reg [31:0] 	  data_fifo_o;
+
+   // The tools won't synthesize properly without this kludge because of the variable
+   // parameter length
+   
+   wire [127:0]   FIXED_WIDTH_KLUDGE = sample_fifo_i;
+   always @*
+     case(sample_phase)
+       4'd0 : data_fifo_o = FIXED_WIDTH_KLUDGE[31:0];
+       4'd1 : data_fifo_o = FIXED_WIDTH_KLUDGE[63:32];
+       4'd2 : data_fifo_o = FIXED_WIDTH_KLUDGE[95:64];
+       4'd3 : data_fifo_o = FIXED_WIDTH_KLUDGE[127:96];
+       default : data_fifo_o = 32'hDEADBEEF;
+     endcase // case (sample_phase)
+   
+   wire 	  clear_pkt_count, pkt_fifo_rdy, sample_fifo_in_rdy;
+   
+   wire [31:0] 	  vita_header, vita_streamid, vita_trailer;
+   wire [15:0] 	  samples_per_packet;
+   
+   reg [33:0] 	  pkt_fifo_line;
+   reg [3:0] 	  vita_state;
+   reg [15:0] 	  sample_ctr;
+   reg [3:0] 	  pkt_count;
+   
+   wire [15:0] 	  vita_pkt_len = samples_per_packet + 6;
+   //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+
+   wire 	  clear_reg;
+   wire 	  clear_int  = clear | clear_reg;
+
+   setting_reg #(.my_addr(BASE+3)) sr_clear
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_reg));
+
+   setting_reg #(.my_addr(BASE+4)) sr_header
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(vita_header),.changed());
+
+   setting_reg #(.my_addr(BASE+5)) sr_streamid
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(vita_streamid),.changed(clear_pkt_count));
+
+   setting_reg #(.my_addr(BASE+6)) sr_trailer
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(vita_trailer),.changed());
+
+   setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(samples_per_packet),.changed());
+
+   setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(numchan),.changed());
+
+   // Output FIFO for packetized data
+   localparam VITA_IDLE 	 = 0;
+   localparam VITA_HEADER 	 = 1;
+   localparam VITA_STREAMID 	 = 2;
+   localparam VITA_SECS 	 = 3;
+   localparam VITA_TICS 	 = 4;
+   localparam VITA_TICS2 	 = 5;
+   localparam VITA_PAYLOAD 	 = 6;
+   localparam VITA_TRAILER 	 = 7;
+   localparam VITA_ERR_HEADER 	 = 9;  // All ERR at 4'b1000 or'ed with base
+   localparam VITA_ERR_STREAMID  = 10;
+   localparam VITA_ERR_SECS 	 = 11;
+   localparam VITA_ERR_TICS 	 = 12;
+   localparam VITA_ERR_TICS2 	 = 13;
+   localparam VITA_ERR_PAYLOAD 	 = 14;
+   localparam VITA_ERR_TRAILER 	 = 15;
+      
+   always @(posedge clk)
+     if(reset | clear_pkt_count)
+       pkt_count <= 0;
+     else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
+       pkt_count <= pkt_count + 1;
+
+   always @*
+     case(vita_state)
+       VITA_HEADER, VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,vita_header[31:20],pkt_count,vita_pkt_len};
+       VITA_STREAMID, VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
+       VITA_SECS, VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
+       VITA_TICS, VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
+       VITA_TICS2, VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
+       VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o};
+       VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b00,28'd0,flags_fifo_o};
+       VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer};
+       VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+       default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
+       endcase // case (vita_state)
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  vita_state   <= VITA_IDLE;
+	  sample_ctr   <= 0;
+	  sample_phase <= 0;
+       end
+     else
+       if(vita_state==VITA_IDLE)
+	 begin
+	    sample_ctr <= 1;
+	    sample_phase <= 0;
+	    if(sample_fifo_src_rdy_i)
+	      if(|flags_fifo_o[3:1])
+		vita_state <= VITA_ERR_HEADER;
+	      else
+		vita_state <= VITA_HEADER;
+	 end
+       else if(pkt_fifo_rdy)
+	 case(vita_state)
+	   VITA_PAYLOAD :
+	     if(sample_fifo_src_rdy_i)
+	       begin
+		  if(sample_phase == (numchan-4'd1))
+		    begin
+		       sample_phase <= 0;
+		       sample_ctr   <= sample_ctr + 1;
+		       if(sample_ctr == samples_per_packet)
+			 vita_state <= VITA_TRAILER;
+		       if(|flags_fifo_o)   // end early if any flag is set
+			 vita_state <= VITA_TRAILER;
+		    end
+		  else
+		    sample_phase <= sample_phase + 1;
+	       end
+	   VITA_TRAILER, VITA_ERR_TRAILER :
+	     vita_state <= VITA_IDLE;
+	   default :
+	     vita_state 	   <= vita_state + 1;
+	 endcase // case (vita_state)
+
+   reg req_write_pkt_fifo;
+   always @*
+     case(vita_state)
+       VITA_IDLE :
+	 req_write_pkt_fifo <= 0;
+       VITA_HEADER, VITA_STREAMID, VITA_SECS, VITA_TICS, VITA_TICS2, VITA_TRAILER :
+	 req_write_pkt_fifo <= 1;
+       VITA_PAYLOAD :
+	 // Write if sample ready and no error flags
+     	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
+       VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER :
+	 req_write_pkt_fifo <= 1;
+       default :
+	 req_write_pkt_fifo <= 0;
+     endcase // case (vita_state)
+   
+   //wire req_write_pkt_fifo  = (vita_state != VITA_IDLE) & (sample_fifo_src_rdy_i | (vita_state != VITA_PAYLOAD));
+   
+   // Short FIFO to buffer between us and the FIFOs outside
+   fifo_short #(.WIDTH(34)) rx_pkt_fifo 
+     (.clk(clk), .reset(reset), .clear(clear_int),
+      .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy),
+      .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+      .space(),.occupied(fifo_occupied[4:0]) );
+   assign fifo_occupied[15:5] = 0;
+   assign data_o[35:34] = 2'b00;  // Always write full lines
+   assign sample_fifo_dst_rdy_o  = pkt_fifo_rdy & 
+				   ( ((vita_state==VITA_PAYLOAD) & 
+				      (sample_phase == (numchan-4'd1)) & 
+				      ~|flags_fifo_o[3:1]) |
+				     (vita_state==VITA_ERR_TRAILER));
+   
+   assign debug_rx  = vita_state;
+   
+endmodule // rx_control
diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v
new file mode 100644
index 000000000..b4fda9622
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_rx_tb.v
@@ -0,0 +1,213 @@
+
+
+module vita_rx_tb;
+
+   localparam DECIM  = 8'd4;
+   localparam MAXCHAN=4;
+   localparam NUMCHAN=4;
+   
+   reg clk 	     = 0;
+   reg reset 	     = 1;
+
+   initial #1000 reset = 0;
+   always #50 clk = ~clk;
+
+   initial $dumpfile("vita_rx_tb.vcd");
+   initial $dumpvars(0,vita_rx_tb);
+
+   wire [(MAXCHAN*32)-1:0] sample;
+   wire        strobe, run;
+   wire [35:0] data_o;
+   wire        src_rdy;
+   reg 	       dst_rdy = 1;
+   wire [63:0] vita_time;
+
+   reg 	       set_stb = 0;
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   wire        set_stb_dsp;
+   wire [7:0]  set_addr_dsp;
+   wire [31:0] set_data_dsp;
+
+   /*
+   settings_bus_crossclock settings_bus_xclk_dsp
+     (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
+      .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+    */
+   
+   wire        sample_dst_rdy, sample_src_rdy;
+   //wire [99:0] sample_data_o;
+   wire [64+4+(MAXCHAN*32)-1:0] sample_data_o;
+
+   vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
+     (.clk(clk), .reset(reset), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time), .overrun(overrun),
+      .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy),
+      .sample(sample), .run(run), .strobe(strobe));
+
+   vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer
+     (.clk(clk), .reset(reset), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy),
+      .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty() );
+   
+   rx_dsp_model rx_dsp_model
+     (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0]));
+
+   generate
+      if(MAXCHAN>1)
+	assign sample[(MAXCHAN*32)-1:32] = 0;
+   endgenerate
+   
+   time_64bit #(.TICKS_PER_SEC(120000000), .BASE(0)) time_64bit
+     (.clk(clk), .rst(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(0), .vita_time(vita_time));
+   
+   always @(posedge clk)
+     if(src_rdy & dst_rdy)
+       begin
+	  if(data_o[32] & ~data_o[33])
+	    begin
+	       $display("RX-PKT-START %d",$time);
+	       $display("       RX-PKT-DAT %x",data_o[31:0]);
+	    end
+	  else if(data_o[32] & data_o[33])
+	    begin
+	       $display("       RX-PKT-DAT %x -- With ERR",data_o[31:0]);
+	       $display("RX-PKT-ERR %d",$time);
+	    end
+	  else if(~data_o[32] & data_o[33])
+	    begin
+	       $display("       RX-PKT-DAT %x",data_o[31:0]);
+	       $display("RX-PKT-END %d",$time);
+	    end
+	  else
+	    $display("       RX-PKT DAT %x",data_o[31:0]);
+       end
+
+   initial 
+     begin
+	@(negedge reset);
+	@(posedge clk);
+	write_setting(4,32'hDEADBEEF);  // VITA header
+	write_setting(5,32'hF00D1234);  // VITA streamid
+	write_setting(6,32'h98765432);  // VITA trailer
+	write_setting(7,8);  // Samples per VITA packet
+	write_setting(8,NUMCHAN);  // Samples per VITA packet
+	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
+	queue_rx_cmd(1,0,16,32'h0,32'h0);  // send imm, 2 packets worth
+	queue_rx_cmd(1,0,7,32'h0,32'h0);  // send imm, 1 short packet worth
+	queue_rx_cmd(1,0,9,32'h0,32'h0);  // send imm, just longer than 1 packet
+	
+	queue_rx_cmd(1,1,16,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,8,32'h0,32'h0);  // 2nd in chain
+	
+	queue_rx_cmd(1,1,17,32'h0,32'h0);  // chained, odd length
+	queue_rx_cmd(0,0,9,32'h0,32'h0);  // 2nd in chain, also odd length
+	
+	queue_rx_cmd(0,0,8,32'h0,32'h340);  // send at, on time
+	queue_rx_cmd(0,0,8,32'h0,32'h100);  // send at, but late
+
+	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained, but break chain
+	#100000;
+	$display("\nEnd chain with zero samples, shouldn't error\n");
+	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	#100000;
+
+	$display("\nEnd chain with zero samples on odd-length, shouldn't error\n");
+	queue_rx_cmd(1,1,14,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	#100000;
+	$display("Should have gotten 14 samples and EOF by now\n");
+	
+	queue_rx_cmd(1,1,9,32'h0,32'h0);  // chained, but break chain, odd length
+	#100000;
+	dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
+	queue_rx_cmd(1,0,100,32'h0,32'h0);  // long enough to fill the fifos
+	queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	#100000;
+	dst_rdy <= 1;  // restart the reads so we can see what we got
+	#100000;
+	dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
+	queue_rx_cmd(1,1,100,32'h0,32'h0);  // long enough to fill the fifos
+	//queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	#100000;
+	@(posedge clk);
+	dst_rdy <= 1;
+	  
+	#100000 $finish;
+     end
+
+   task write_setting;
+      input [7:0] addr;
+      input [31:0] data;
+      begin
+	 set_stb <= 0;
+	 @(posedge clk);
+	 set_addr <= addr;
+	 set_data <= data;
+	 set_stb  <= 1;
+	 @(posedge clk);
+	 set_stb <= 0;
+      end
+   endtask // write_setting
+   
+   task queue_rx_cmd;
+      input send_imm;
+      input chain;
+      input [29:0] lines;
+      input [31:0] secs;
+      input [31:0] tics;
+      begin
+	 write_setting(0,{send_imm,chain,lines});
+	 write_setting(1,secs);
+	 write_setting(2,tics);
+      end
+   endtask // queue_rx_cmd
+   
+endmodule // rx_control_tb
+
+module rx_dsp_model
+  (input clk, input reset,
+   input run,
+   input [7:0] decim,
+   output strobe,
+   output [31:0] sample);
+   
+   reg [15:0] 	  pktnum = 0;
+   reg [15:0] 	 counter = 0;
+
+   reg 		 run_d1;
+   always @(posedge clk) run_d1 <= run;
+   
+   always @(posedge clk)
+     if(run & ~run_d1)
+       begin
+	  counter 		<= 0;
+	  pktnum 		<= pktnum + 1;
+       end
+     else if(run & strobe)
+       counter 			<= counter + 1;
+       
+   assign sample 		 = {pktnum,counter};
+
+   reg [7:0] stb_ctr = 0;
+   
+   always @(posedge clk)
+     if(reset)
+       stb_ctr 	 <= 0;
+     else if(run & ~run_d1)
+       stb_ctr 	 <= 1;
+     else if(run)
+       if(stb_ctr == decim-1)
+	 stb_ctr <= 0;
+       else
+	 stb_ctr <= stb_ctr + 1;
+
+   assign strobe  = stb_ctr == decim-1;
+   
+endmodule // rx_dsp_model
diff --git a/fpga/usrp2/vrt/vita_tx.build b/fpga/usrp2/vrt/vita_tx.build
new file mode 100755
index 000000000..902929c08
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_tx.build
@@ -0,0 +1 @@
+iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v
diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v
new file mode 100644
index 000000000..bffc64e52
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_tx_control.v
@@ -0,0 +1,98 @@
+
+module vita_tx_control
+  #(parameter BASE=0,
+    parameter WIDTH=32)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    input [63:0] vita_time,
+    output underrun,
+
+    // From vita_tx_deframer
+    input [4+64+WIDTH-1:0] sample_fifo_i,
+    input sample_fifo_src_rdy_i,
+    output sample_fifo_dst_rdy_o,
+    
+    // To DSP Core
+    output [WIDTH-1:0] sample,
+    output run,
+    input strobe,
+
+    output [31:0] debug
+    );
+   
+   assign sample = sample_fifo_i[4+64+WIDTH-1:4+64];
+
+   wire [63:0] send_time = sample_fifo_i[63:0];
+   wire        eop = sample_fifo_i[64];
+   wire        eob = sample_fifo_i[65];
+   wire        sob = sample_fifo_i[66];
+   wire        send_at = sample_fifo_i[67];
+   wire        now, early, late, too_early;
+
+   // FIXME ignore too_early for now for timing reasons
+   assign too_early = 0;
+   time_compare 
+     time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), 
+		   .late(late), .too_early());
+//		   .late(late), .too_early(too_early));
+   
+   localparam IBS_IDLE = 0;
+   localparam IBS_RUN = 1;  // FIXME do we need this?
+   localparam IBS_CONT_BURST = 2;
+   localparam IBS_UNDERRUN = 3;
+   localparam IBS_UNDERRUN_DONE = 4;
+   
+   reg [2:0] ibs_state;
+
+   wire      clear_state;
+   setting_reg #(.my_addr(BASE+1)) sr
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_state));
+   
+   always @(posedge clk)
+     if(reset | clear_state)
+       ibs_state <= 0;
+     else
+       case(ibs_state)
+	 IBS_IDLE :
+	   if(sample_fifo_src_rdy_i)
+	     if(~send_at | now)
+	       ibs_state <= IBS_RUN;
+	     else if(late | too_early)
+	       ibs_state <= IBS_UNDERRUN;
+	 
+	 IBS_RUN :
+	   if(strobe)
+	     if(~sample_fifo_src_rdy_i)
+	       ibs_state <= IBS_UNDERRUN;
+	     else if(eop)
+	       if(eob)
+		 ibs_state <= IBS_IDLE;
+	       else
+		 ibs_state <= IBS_CONT_BURST;
+
+	 IBS_CONT_BURST :
+	   if(strobe)
+	     ibs_state <= IBS_UNDERRUN_DONE;
+	   else if(sample_fifo_src_rdy_i)
+	     ibs_state <= IBS_RUN;
+	 
+	 IBS_UNDERRUN :
+	   if(sample_fifo_src_rdy_i & eop)
+	     ibs_state <= IBS_UNDERRUN_DONE;
+
+	 IBS_UNDERRUN_DONE :
+	   ;
+       endcase // case (ibs_state)
+
+   assign sample_fifo_dst_rdy_o = (ibs_state == IBS_UNDERRUN) | (strobe & (ibs_state == IBS_RUN));  // FIXME also cleanout
+   assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
+   assign underrun = (ibs_state == IBS_UNDERRUN_DONE);
+
+   assign debug = { { now,early,late,too_early,eop,eob,sob,send_at },
+		    { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, underrun, ibs_state[2:0] },
+		    { 8'b0 },
+		    { 8'b0 } };
+   
+endmodule // vita_tx_control
diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v
new file mode 100644
index 000000000..49428ead5
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_tx_deframer.v
@@ -0,0 +1,187 @@
+
+module vita_tx_deframer
+  #(parameter BASE=0,
+    parameter MAXCHAN=1)
+   (input clk, input reset, input clear,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    
+    // To FIFO interface of Buffer Pool
+    input [35:0] data_i,
+    input src_rdy_i,
+    output dst_rdy_o,
+    
+    output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o,
+    output sample_fifo_src_rdy_o,
+    input sample_fifo_dst_rdy_i,
+    
+    // FIFO Levels
+    output [15:0] fifo_occupied,
+    output fifo_full,
+    output fifo_empty,
+    output [31:0] debug
+    );
+
+   wire [1:0] numchan;
+   setting_reg #(.my_addr(BASE), .at_reset(0)) sr_numchan
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(numchan),.changed());
+
+   reg [3:0] vita_state;
+   wire      has_streamid, has_classid, has_secs, has_tics, has_trailer;
+   assign has_streamid 	= (data_i[31:28]==4'b001);
+   assign has_classid 	= data_i[27];
+   assign has_secs 	= ~(data_i[23:22]==2'b00);
+   assign has_tics 	= ~(data_i[21:20]==2'b00);
+   assign has_trailer 	= data_i[26];
+   assign is_sob = data_i[25];
+   assign is_eob = data_i[24];
+   wire      eof = data_i[33];
+   
+   reg 	     has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg;
+   reg 	     has_trailer_reg, is_sob_reg, is_eob_reg;
+
+   reg [15:0] pkt_len;
+   reg [1:0]  vector_phase;
+   wire       line_done;
+   
+   // Output FIFO for packetized data
+   localparam VITA_HEADER 	 = 0;
+   localparam VITA_STREAMID 	 = 1;
+   localparam VITA_CLASSID 	 = 2;
+   localparam VITA_CLASSID2 	 = 3;
+   localparam VITA_SECS 	 = 4;
+   localparam VITA_TICS 	 = 5;
+   localparam VITA_TICS2 	 = 6;
+   localparam VITA_PAYLOAD 	 = 7;
+   localparam VITA_STORE         = 8;
+   localparam VITA_TRAILER 	 = 9;
+
+   wire [15:0] hdr_len = 2 + has_streamid_reg + has_classid_reg + has_classid_reg + has_secs_reg + 
+	       has_tics_reg + has_tics_reg + has_trailer_reg;
+
+   wire        eop = eof | (pkt_len==hdr_len);  // FIXME would ignoring eof allow larger VITA packets?
+   wire        fifo_space;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  vita_state 		<= VITA_HEADER;
+	  {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} 
+	    <= 0;
+       end
+     else 
+       if((vita_state == VITA_STORE) & fifo_space)
+	 if(eop)  
+	   if(has_trailer_reg)
+	     vita_state <= VITA_TRAILER;
+	   else
+	     vita_state <= VITA_HEADER;
+	 else
+	   begin
+	      vita_state <= VITA_PAYLOAD;
+	      pkt_len <= pkt_len - 1;
+	   end
+       else if(src_rdy_i)
+	 case(vita_state)
+	   VITA_HEADER :
+	     begin
+		{has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} 
+ 		  <= {has_streamid, has_classid, has_secs, has_tics, has_trailer, is_sob, is_eob};
+		pkt_len <= data_i[15:0];
+		vector_phase <= 0;
+		if(has_streamid)
+		  vita_state <= VITA_STREAMID;
+		else if(has_classid)
+		  vita_state <= VITA_CLASSID;
+		else if(has_secs)
+		  vita_state <= VITA_SECS;
+		else if(has_tics)
+		  vita_state <= VITA_TICS;
+		else
+		  vita_state <= VITA_PAYLOAD;
+	     end // case: VITA_HEADER
+	   VITA_STREAMID :
+	     if(has_classid_reg)
+	       vita_state <= VITA_CLASSID;
+	     else if(has_secs_reg)
+	       vita_state <= VITA_SECS;
+	     else if(has_tics_reg)
+	       vita_state <= VITA_TICS;
+	     else
+	       vita_state <= VITA_PAYLOAD;
+	   VITA_CLASSID :
+	     vita_state <= VITA_CLASSID2;
+	   VITA_CLASSID2 :
+	     if(has_secs_reg)
+	       vita_state <= VITA_SECS;
+	     else if(has_tics_reg)
+	       vita_state <= VITA_TICS;
+	     else
+	       vita_state <= VITA_PAYLOAD;
+	   VITA_SECS :
+	     if(has_tics_reg)
+	       vita_state <= VITA_TICS;
+	     else
+	       vita_state <= VITA_PAYLOAD;
+	   VITA_TICS :
+	     vita_state <= VITA_TICS2;
+	   VITA_TICS2 :
+	     vita_state <= VITA_PAYLOAD;
+	   VITA_PAYLOAD :
+	     if(line_done)
+	       begin
+		  vector_phase <= 0;
+		  vita_state <= VITA_STORE;
+	       end
+	     else
+	       vector_phase <= vector_phase + 1;
+	   VITA_TRAILER :
+	     vita_state <= VITA_HEADER;
+	   VITA_STORE :
+	     ;
+	   default :
+	     vita_state <= VITA_HEADER;
+	 endcase // case (vita_state)
+
+   assign line_done = (vector_phase == numchan);
+   
+   wire [4+64+32*MAXCHAN-1:0] fifo_i;
+   reg [63:0] 		      send_time;
+   reg [31:0] 		      sample_a, sample_b, sample_c, sample_d;
+   
+   always @(posedge clk)
+     case(vita_state)
+       VITA_SECS :
+	 send_time[63:32] <= data_i[31:0];
+       VITA_TICS2 :
+	 send_time[31:0] <= data_i[31:0];
+       VITA_STORE, VITA_HEADER :
+	 send_time[63:0] <= 64'd0;
+     endcase // case (vita_state)
+   
+   always @(posedge clk)
+     if(vita_state == VITA_PAYLOAD)
+       case(vector_phase)
+	 0: sample_a <= data_i[31:0];
+	 1: sample_b <= data_i[31:0];
+	 2: sample_c <= data_i[31:0];
+	 3: sample_d <= data_i[31:0];
+       endcase // case (vector_phase)
+   
+   wire 		      store = (vita_state == VITA_STORE);
+   fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space),
+      .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) );
+
+   // sob, eob, has_secs (send_at) ignored on all lines except first
+   assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time};
+
+   assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ;
+
+   assign debug = { { 8'b0 },
+		    { 8'b0 },
+		    { eof, line_done, store, fifo_space, src_rdy_i, dst_rdy_o, vector_phase[1:0] },
+		    { has_secs_reg, is_sob_reg, is_eob_reg, eop, vita_state[3:0] } };
+   
+endmodule // vita_tx_deframer
diff --git a/fpga/usrp2/vrt/vita_tx_tb.v b/fpga/usrp2/vrt/vita_tx_tb.v
new file mode 100644
index 000000000..90986a35f
--- /dev/null
+++ b/fpga/usrp2/vrt/vita_tx_tb.v
@@ -0,0 +1,264 @@
+
+
+module vita_tx_tb;
+
+   localparam DECIM  = 8'd4;
+   localparam INTERP = 8'd4;
+   
+   localparam MAXCHAN=4;
+   localparam NUMCHAN=1;
+   
+   reg clk 	     = 0;
+   reg reset 	     = 1;
+
+   initial #1000 reset = 0;
+   always #50 clk = ~clk;
+
+   initial $dumpfile("vita_tx_tb.vcd");
+   initial $dumpvars(0,vita_tx_tb);
+
+   wire [(MAXCHAN*32)-1:0] sample, sample_tx;
+   wire        strobe, run;
+   wire [35:0] data_o;
+   wire        src_rdy;
+   wire        dst_rdy;
+   
+   wire [63:0] vita_time;
+
+   reg 	       set_stb = 0;
+   reg [7:0]   set_addr;
+   reg [31:0]  set_data;
+   wire        set_stb_dsp;
+   wire [7:0]  set_addr_dsp;
+   wire [31:0] set_data_dsp;
+
+   /*
+   settings_bus_crossclock settings_bus_xclk_dsp
+     (.clk_i(clk), .rst_i(reset), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
+      .clk_o(clk), .rst_o(reset), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+     */
+ 
+   wire        sample_dst_rdy, sample_src_rdy;
+   //wire [99:0] sample_data_o;
+   wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx;
+
+   time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit
+     (.clk(clk), .rst(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(0), .vita_time(vita_time));
+   
+   rx_dsp_model rx_dsp_model
+     (.clk(clk), .reset(reset), .run(run), .decim(DECIM), .strobe(strobe), .sample(sample[31:0]));
+
+   generate
+      if(MAXCHAN>1)
+	assign sample[(MAXCHAN*32)-1:32] = 0;
+   endgenerate
+   
+   vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
+     (.clk(clk), .reset(reset), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time), .overrun(overrun),
+      .sample_fifo_o(sample_data_o), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy),
+      .sample(sample), .run(run), .strobe(strobe));
+
+   vita_rx_framer #(.BASE(0), .MAXCHAN(MAXCHAN)) vita_rx_framer
+     (.clk(clk), .reset(reset), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .data_o(data_o), .dst_rdy_i(dst_rdy), .src_rdy_o(src_rdy),
+      .sample_fifo_i(sample_data_o), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy),
+      .fifo_occupied(), .fifo_full(), .fifo_empty() );
+
+   wire [35:0] 			data_tx;
+   wire 			src_rdy_tx, dst_rdy_tx;
+   wire 			sample_dst_rdy_tx, sample_src_rdy_tx;
+   
+   fifo_long #(.WIDTH(36)) fifo_short
+     (.clk(clk), .reset(reset), .clear(0),
+      .datain(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+      .dataout(data_tx), .src_rdy_o(src_rdy_tx), .dst_rdy_i(dst_rdy_tx));
+   
+   vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN)) vita_tx_deframer
+     (.clk(clk), .reset(reset), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .data_i(data_tx), .dst_rdy_o(dst_rdy_tx), .src_rdy_i(src_rdy_tx),
+      .sample_fifo_o(sample_data_tx), 
+      .sample_fifo_dst_rdy_i(sample_dst_rdy_tx), .sample_fifo_src_rdy_o(sample_src_rdy_tx),
+      .fifo_occupied(), .fifo_full(), .fifo_empty() );
+
+   vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control
+     (.clk(clk), .reset(reset), .clear(0),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .vita_time(vita_time-100), .underrun(underrun),
+      .sample_fifo_i(sample_data_tx), 
+      .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx),
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx));
+   
+   tx_dsp_model tx_dsp_model
+     (.clk(clk), .reset(reset), .run(run_tx), .interp(INTERP), .strobe(strobe_tx), .sample(sample_tx[31:0] ));
+
+   always @(posedge clk)
+     if(src_rdy & dst_rdy)
+       begin
+	  if(data_o[32] & ~data_o[33])
+	    begin
+	       $display("RX-PKT-START %d",$time);
+	       $display("       RX-PKT-DAT %x",data_o[31:0]);
+	    end
+	  else if(data_o[32] & data_o[33])
+	    begin
+	       $display("       RX-PKT-DAT %x -- With ERR",data_o[31:0]);
+	       $display("RX-PKT-ERR %d",$time);
+	    end
+	  else if(~data_o[32] & data_o[33])
+	    begin
+	       $display("       RX-PKT-DAT %x",data_o[31:0]);
+	       $display("RX-PKT-END %d",$time);
+	    end
+	  else
+	    $display("       RX-PKT DAT %x",data_o[31:0]);
+       end
+
+   initial 
+     begin
+	@(negedge reset);
+	@(posedge clk);
+	write_setting(4,32'h14900008);  // VITA header
+	write_setting(5,32'hF00D1234);  // VITA streamid
+	write_setting(6,32'h98765432);  // VITA trailer
+	write_setting(7,8);  // Samples per VITA packet
+	write_setting(8,NUMCHAN);  // Samples per VITA packet
+	#10000;
+	
+	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
+/*
+ 	queue_rx_cmd(1,0,16,32'h0,32'h0);  // send imm, 2 packets worth
+	queue_rx_cmd(1,0,7,32'h0,32'h0);  // send imm, 1 short packet worth
+	queue_rx_cmd(1,0,9,32'h0,32'h0);  // send imm, just longer than 1 packet
+	
+	queue_rx_cmd(1,1,16,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,8,32'h0,32'h0);  // 2nd in chain
+	
+	queue_rx_cmd(1,1,17,32'h0,32'h0);  // chained, odd length
+	queue_rx_cmd(0,0,9,32'h0,32'h0);  // 2nd in chain, also odd length
+	
+	queue_rx_cmd(0,0,8,32'h0,32'h340);  // send at, on time
+	queue_rx_cmd(0,0,8,32'h0,32'h100);  // send at, but late
+
+	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained, but break chain
+	#100000;
+	$display("\nEnd chain with zero samples, shouldn't error\n");
+	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	#100000;
+
+	$display("\nEnd chain with zero samples on odd-length, shouldn't error\n");
+	queue_rx_cmd(1,1,14,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	#100000;
+	$display("Should have gotten 14 samples and EOF by now\n");
+	
+	queue_rx_cmd(1,1,9,32'h0,32'h0);  // chained, but break chain, odd length
+	#100000;
+	//dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
+	queue_rx_cmd(1,0,100,32'h0,32'h0);  // long enough to fill the fifos
+	queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	#100000;
+	//dst_rdy <= 1;  // restart the reads so we can see what we got
+	#100000;
+	//dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
+	queue_rx_cmd(1,1,100,32'h0,32'h0);  // long enough to fill the fifos
+	//queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	#100000;
+	@(posedge clk);
+	//dst_rdy <= 1;
+	*/
+	#100000 $finish;
+     end
+
+   task write_setting;
+      input [7:0] addr;
+      input [31:0] data;
+      begin
+	 set_stb <= 0;
+	 @(posedge clk);
+	 set_addr <= addr;
+	 set_data <= data;
+	 set_stb  <= 1;
+	 @(posedge clk);
+	 set_stb <= 0;
+      end
+   endtask // write_setting
+   
+   task queue_rx_cmd;
+      input send_imm;
+      input chain;
+      input [29:0] lines;
+      input [31:0] secs;
+      input [31:0] tics;
+      begin
+	 write_setting(0,{send_imm,chain,lines});
+	 write_setting(1,secs);
+	 write_setting(2,tics);
+      end
+   endtask // queue_rx_cmd
+   
+endmodule // vita_tx_tb
+
+
+module rx_dsp_model
+  (input clk, input reset,
+   input run,
+   input [7:0] decim,
+   output strobe,
+   output [31:0] sample);
+   
+   reg [15:0] 	  pktnum = 0;
+   reg [15:0] 	 counter = 0;
+
+   reg 		 run_d1;
+   always @(posedge clk) run_d1 <= run;
+   
+   always @(posedge clk)
+     if(run & ~run_d1)
+       begin
+	  counter 		<= 0;
+	  pktnum 		<= pktnum + 1;
+       end
+     else if(run & strobe)
+       counter 			<= counter + 1;
+       
+   assign sample 		 = {pktnum,counter};
+
+   reg [7:0] stb_ctr = 0;
+   
+   always @(posedge clk)
+     if(reset)
+       stb_ctr 	 <= 0;
+     else if(run & ~run_d1)
+       stb_ctr 	 <= 1;
+     else if(run)
+       if(stb_ctr == decim-1)
+	 stb_ctr <= 0;
+       else
+	 stb_ctr <= stb_ctr + 1;
+
+   assign strobe  = stb_ctr == decim-1;
+   
+endmodule // rx_dsp_model
+
+module tx_dsp_model
+  (input clk, input reset,
+   input run,
+   input [7:0] interp,
+   output strobe,
+   input [31:0] sample);
+
+   cic_strober strober(.clock(clk), .reset(reset), .enable(run), .rate(interp), .strobe_fast(1), .strobe_slow(strobe));
+
+   always @(posedge clk)
+     if(strobe)
+       $display("Time %d, Sent Sample %x",$time,sample);
+   
+   
+endmodule // tx_dsp_model