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authorJosh Blum <josh@joshknows.com>2011-01-14 15:22:02 -0800
committerJosh Blum <josh@joshknows.com>2011-01-14 15:22:02 -0800
commit1254656ef914482cc111ffa3aca48be5c1e8caaf (patch)
tree0833ee4271c99efce01ac8944a8ea5c3c241e94b /fpga/usrp2
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usrp-e100: added readback mux 32 as slave 7 for time readback
created new component wb_readback_mux_16LE.v for 16 wide bus connected vita time pps to vita time controller and readbacks
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