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| author | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-06-14 17:29:21 -0700 |
| commit | dd157937466f3ee18b08712625eba84582a913f3 (patch) | |
| tree | 6a4eadb148a2c8141032b78d3c521d56c1f34910 /fpga/usrp2 | |
| parent | a1f36ebf436fccbb6cc81bb5f32a790d444772c2 (diff) | |
| parent | c0fadece89314f3a00892122c28caf187ce1a717 (diff) | |
| download | uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.gz uhd-dd157937466f3ee18b08712625eba84582a913f3.tar.bz2 uhd-dd157937466f3ee18b08712625eba84582a913f3.zip | |
Merge branch 'fpga_next' into uhd_next
Diffstat (limited to 'fpga/usrp2')
301 files changed, 11113 insertions, 4201 deletions
diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs index 751b40828..a1c11c026 100644 --- a/fpga/usrp2/control_lib/Makefile.srcs +++ b/fpga/usrp2/control_lib/Makefile.srcs @@ -50,4 +50,5 @@ bootram.v \ nsgpio16LE.v \ settings_bus_16LE.v \ atr_controller16.v \ +fifo_to_wb.v \ )) diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v index a161b5e00..2cef8ba2b 100644 --- a/fpga/usrp2/control_lib/atr_controller.v +++ b/fpga/usrp2/control_lib/atr_controller.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Automatic transmit/receive switching of control pins to daughterboards // Store everything in registers for now, but could use a RAM for more diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v index 74ce30a54..ff4f634c7 100644 --- a/fpga/usrp2/control_lib/atr_controller16.v +++ b/fpga/usrp2/control_lib/atr_controller16.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Automatic transmit/receive switching of control pins to daughterboards // Store everything in registers for now, but could use a RAM for more diff --git a/fpga/usrp2/control_lib/bin2gray.v b/fpga/usrp2/control_lib/bin2gray.v index 513402163..8336a5afc 100644 --- a/fpga/usrp2/control_lib/bin2gray.v +++ b/fpga/usrp2/control_lib/bin2gray.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module bin2gray diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v index 29d21ab5a..249a09814 100644 --- a/fpga/usrp2/control_lib/bootram.v +++ b/fpga/usrp2/control_lib/bootram.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Boot RAM for S3A, 8KB, dual port diff --git a/fpga/usrp2/control_lib/clock_bootstrap_rom.v b/fpga/usrp2/control_lib/clock_bootstrap_rom.v index 46563db65..542f49380 100644 --- a/fpga/usrp2/control_lib/clock_bootstrap_rom.v +++ b/fpga/usrp2/control_lib/clock_bootstrap_rom.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module clock_bootstrap_rom(input [15:0] addr, output [47:0] data); diff --git a/fpga/usrp2/control_lib/clock_control.v b/fpga/usrp2/control_lib/clock_control.v index 1bbe6bd75..000eaf1fb 100644 --- a/fpga/usrp2/control_lib/clock_control.v +++ b/fpga/usrp2/control_lib/clock_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // AD9510 Register Map (from datasheet Rev. A) diff --git a/fpga/usrp2/control_lib/clock_control_tb.v b/fpga/usrp2/control_lib/clock_control_tb.v index 4e705cf23..9760efbe3 100644 --- a/fpga/usrp2/control_lib/clock_control_tb.v +++ b/fpga/usrp2/control_lib/clock_control_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module clock_control_tb(); diff --git a/fpga/usrp2/control_lib/dcache.v b/fpga/usrp2/control_lib/dcache.v index 9063bf02a..384c5a149 100644 --- a/fpga/usrp2/control_lib/dcache.v +++ b/fpga/usrp2/control_lib/dcache.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module dcache #(parameter AWIDTH=14, diff --git a/fpga/usrp2/control_lib/decoder_3_8.v b/fpga/usrp2/control_lib/decoder_3_8.v index 729b45d18..8f91d8263 100644 --- a/fpga/usrp2/control_lib/decoder_3_8.v +++ b/fpga/usrp2/control_lib/decoder_3_8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module decoder_3_8 (input [2:0] sel, diff --git a/fpga/usrp2/control_lib/dpram32.v b/fpga/usrp2/control_lib/dpram32.v index 4da621823..386435e70 100644 --- a/fpga/usrp2/control_lib/dpram32.v +++ b/fpga/usrp2/control_lib/dpram32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Dual ported RAM // Addresses are byte-oriented, so botton 2 address bits are ignored. diff --git a/fpga/usrp2/control_lib/fifo_tb.v b/fpga/usrp2/control_lib/fifo_tb.v deleted file mode 100644 index 616fe4ee7..000000000 --- a/fpga/usrp2/control_lib/fifo_tb.v +++ /dev/null @@ -1,151 +0,0 @@ -module fifo_tb(); - - reg clk, rst; - wire short_full, short_empty, long_full, long_empty; - wire casc2_full, casc2_empty; - reg read, write; - - wire [7:0] short_do, long_do; - wire [7:0] casc2_do; - reg [7:0] di; - - reg clear = 0; - - shortfifo #(.WIDTH(8)) shortfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear), - .read(read),.write(write),.full(short_full),.empty(short_empty)); - - longfifo #(.WIDTH(8), .SIZE(4)) longfifo - (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear), - .read(read),.write(write),.full(long_full),.empty(long_empty)); - - cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2 - (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear), - .read(read),.write(write),.full(casc2_full),.empty(casc2_empty)); - - initial rst = 1; - initial #1000 rst = 0; - initial clk = 0; - always #50 clk = ~clk; - - initial di = 8'hAE; - initial read = 0; - initial write = 0; - - always @(posedge clk) - if(write) - di <= di + 1; - - always @(posedge clk) - begin - if(short_full != long_full) - $display("Error: FULL mismatch"); - if(short_empty != long_empty) - $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)"); - if(read & (short_do != long_do)) - $display("Error: DATA mismatch"); - end - - initial $dumpfile("fifo_tb.vcd"); - initial $dumpvars(0,fifo_tb); - - initial - begin - @(negedge rst); - @(posedge clk); - repeat (10) - @(posedge clk); - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - - repeat(10) - begin - write <= 1; - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - end // repeat (10) - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - read <= 1; - repeat (4) - @(posedge clk); - read <= 0; - @(posedge clk); - - - write <= 1; - repeat (4) - @(posedge clk); - write <= 0; - @(posedge clk); - repeat (4) - begin - read <= 1; - @(posedge clk); - read <= 0; - @(posedge clk); - end - - write <= 1; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); - read <= 1; - repeat (5) - @(posedge clk); - write <= 0; - @(posedge clk); - @(posedge clk); - read <= 0; - @(posedge clk); - - write <= 1; - repeat (16) - @(posedge clk); - write <= 0; - @(posedge clk); - - read <= 1; - repeat (16) - @(posedge clk); - read <= 0; - @(posedge clk); - - repeat (10) - @(posedge clk); - $finish; - end -endmodule // longfifo_tb diff --git a/fpga/usrp2/control_lib/fifo_to_wb.v b/fpga/usrp2/control_lib/fifo_to_wb.v new file mode 100644 index 000000000..9b6b5e804 --- /dev/null +++ b/fpga/usrp2/control_lib/fifo_to_wb.v @@ -0,0 +1,183 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module fifo_to_wb + #(parameter PKT_LEN = 16) + (input clk, input reset, input clear, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, + output reg [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + input [7:0] triggers, + output [31:0] debug0, output [31:0] debug1); + + wire [18:0] ctrl_data; + reg [18:0] resp_data; + wire ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy; + + fifo_short #(.WIDTH(19)) ctrl_sfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), + .dataout(ctrl_data), .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy)); + + fifo_short #(.WIDTH(19)) resp_sfifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(resp_data), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); + + // Need a programmable state machine here. The program is the fifo contents. + // All words are 16 bits wide + // Word 0 Command { Read, Write, Triggers[5:0], Seqno [7:0] } + // Word 1 Length + // Word 2 Address LSW + // Word 3 Address MSW (should all be 0) + + localparam RESP_IDLE = 0; + localparam RESP_LEN = 1; + localparam RESP_ADDR_LSW = 2; + localparam RESP_ADDR_MSW = 3; + localparam RESP_WRITE = 4; + localparam RESP_DUMP = 5; + localparam RESP_WAIT_READ = 6; + localparam RESP_RCMD = 7; + localparam RESP_RLEN = 8; + localparam RESP_RADDR_LSW = 9; + localparam RESP_RADDR_MSW = 10; + localparam RESP_READ = 11; + + reg [3:0] resp_state; + reg rd, wr; + reg [15:0] base_addr; + reg [15:0] length; + reg [15:0] count; + reg [7:0] seqnum; + reg [5:0] which_trig; + + always @(posedge clk) + if(reset | clear) + resp_state <= RESP_IDLE; + else + case(resp_state) + RESP_IDLE : + if(ctrl_src_rdy) + begin + { rd, wr, which_trig[5:0], seqnum[7:0] } <= ctrl_data[15:0]; + if(ctrl_data[16]) // WAIT for start of packet, clean out otherwise + resp_state <= RESP_LEN; + end + RESP_LEN : + if(ctrl_src_rdy) + begin + length <= ctrl_data[15:0]; + count <= ctrl_data[15:0]; + resp_state <= RESP_ADDR_LSW; + end + RESP_ADDR_LSW : + if(ctrl_src_rdy) + begin + base_addr <= ctrl_data[15:0]; + wb_adr_o <= ctrl_data[15:0]; + resp_state <= RESP_ADDR_MSW; + end + RESP_ADDR_MSW : + if(ctrl_src_rdy) + if(wr) + resp_state <= RESP_WRITE; + else + resp_state <= RESP_DUMP; + RESP_WRITE : + if(ctrl_src_rdy & wb_ack_i) + if(count==1) + if(ctrl_data[17]) //eof + resp_state <= RESP_IDLE; + else // clean out padding + resp_state <= RESP_DUMP; + else + begin + wb_adr_o <= wb_adr_o + 2; + count <= count - 1; + end + RESP_DUMP : + if(ctrl_src_rdy & ctrl_data[17]) + if(rd) + resp_state <= RESP_WAIT_READ; + else + resp_state <= RESP_IDLE; + RESP_WAIT_READ : + begin + wb_adr_o <= base_addr; + count <= length; + if( &(triggers | ~which_trig) ) + resp_state <= RESP_RCMD; + end + RESP_RCMD : + if(resp_dst_rdy) + resp_state <= RESP_RLEN; + RESP_RLEN : + if(resp_dst_rdy) + resp_state <= RESP_RADDR_LSW; + RESP_RADDR_LSW : + if(resp_dst_rdy) + resp_state <= RESP_RADDR_MSW; + RESP_RADDR_MSW : + if(resp_dst_rdy) + resp_state <= RESP_READ; + RESP_READ : + if(resp_dst_rdy & wb_ack_i) + if(count==1) + resp_state <= RESP_IDLE; + else + begin + wb_adr_o <= wb_adr_o + 2; + count <= count - 1; + end + endcase // case (resp_state) + + always @* + case(resp_state) + RESP_RCMD : resp_data <= { 3'b001, 8'hAA, seqnum }; + RESP_RLEN : resp_data <= { 3'b000, length }; + RESP_RADDR_LSW : resp_data <= { 3'b000, base_addr }; + RESP_RADDR_MSW : resp_data <= { 3'b000, 16'd0 }; + default : resp_data <= { 1'b0, (count==1), 1'b0, wb_dat_miso }; + endcase // case (resp_state) + + assign ctrl_dst_rdy = (resp_state == RESP_IDLE) | + (resp_state == RESP_LEN) | + (resp_state == RESP_ADDR_LSW) | + (resp_state == RESP_ADDR_MSW) | + ((resp_state == RESP_WRITE) & wb_ack_i) | + (resp_state == RESP_DUMP); + + assign resp_src_rdy = (resp_state == RESP_RCMD) | + (resp_state == RESP_RLEN) | + (resp_state == RESP_RADDR_LSW) | + (resp_state == RESP_RADDR_MSW) | + ((resp_state == RESP_READ) & wb_ack_i); + + assign wb_dat_mosi = ctrl_data[15:0]; + assign wb_we_o = (resp_state == RESP_WRITE); + assign wb_cyc_o = wb_stb_o; + assign wb_sel_o = 2'b11; + assign wb_stb_o = (ctrl_src_rdy & (resp_state == RESP_WRITE)) | (resp_dst_rdy & (resp_state == RESP_READ)); + + + assign debug0 = { 14'd0, ctrl_data[17:0] }; + assign debug1 = { ctrl_src_rdy, ctrl_dst_rdy, resp_src_rdy, resp_dst_rdy, 2'b00, ctrl_data[17:16] }; + +endmodule // fifo_to_wb diff --git a/fpga/usrp2/control_lib/fifo_to_wb_tb.v b/fpga/usrp2/control_lib/fifo_to_wb_tb.v new file mode 100644 index 000000000..37459e2c2 --- /dev/null +++ b/fpga/usrp2/control_lib/fifo_to_wb_tb.v @@ -0,0 +1,136 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +module fifo_to_wb_tb(); + + reg clk = 0; + reg rst = 1; + reg clear = 0; + initial #1000 rst = 0; + always #50 clk = ~clk; + + reg trigger = 0; + initial #10000 trigger = 1; + + wire wb_cyc, wb_stb, wb_we, wb_ack; + wire [15:0] wb_adr; + wire [15:0] wb_dat_miso, wb_dat_mosi; + + reg cmd_src_rdy; + wire cmd_dst_rdy, resp_src_rdy, resp_dst_rdy; + reg [17:0] cmd; + wire [17:0] resp; + + wire [17:0] resp_int; + wire resp_src_rdy_int, resp_dst_rdy_int; + + fifo_to_wb fifo_to_wb + (.clk(clk), .reset(rst), .clear(clear), + .data_i(cmd), .src_rdy_i(cmd_src_rdy), .dst_rdy_o(cmd_dst_rdy), + .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int), + + .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), + .wb_sel_o(), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), + .wb_we_o(wb_we), .wb_ack_i(wb_ack), + .triggers()); + + assign wb_dat_miso = {wb_adr[7:0],8'hBF}; + + fifo19_pad #(.LENGTH(16)) fifo19_pad + (.clk(clk), .reset(rst), .clear(clear), + .data_i(resp_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), + .data_o(resp), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); + + + // Set up monitors + always @(posedge clk) + if(wb_cyc & wb_stb & wb_ack) + if(wb_we) + $display("WB-WRITE ADDR:%h DATA:%h",wb_adr, wb_dat_mosi); + else + $display("WB-READ ADDR:%h DATA:%h",wb_adr, wb_dat_miso); + + always @(posedge clk) + if(cmd_src_rdy & cmd_dst_rdy) + $display("CMD-WRITE SOF:%b EOF:%b DATA:%h",cmd[16],cmd[17],cmd[15:0]); + + always @(posedge clk) + if(resp_src_rdy & resp_dst_rdy) + $display("RESP-READ SOF:%b EOF:%b DATA:%h",resp[16],resp[17],resp[15:0]); + + assign wb_ack = wb_stb; + assign resp_dst_rdy = 1; + + task InsertRW; + input [15:0] data_start; + input [5:0] triggers; + input [7:0] seqno; + input [15:0] len; + input [15:0] addr; + reg [15:0] data_val; + + begin + data_val <= data_start; + @(posedge clk); + cmd <= {2'b01,2'b11,triggers,seqno}; + cmd_src_rdy <= 1; + @(posedge clk); + cmd <= {2'b00,len}; + @(posedge clk); + cmd <= {2'b00,addr}; + @(posedge clk); + cmd <= {2'b00,16'd0}; + @(posedge clk); + repeat (len) + begin + cmd <= {2'b00,data_val}; + data_val <= data_val + 1; + @(posedge clk); + end + repeat (12-len-1) + begin + cmd <= {2'b00,16'hBEEF}; + @(posedge clk); + end + cmd <= {2'b10, 16'hDEAD}; + @(posedge clk); + cmd_src_rdy <= 0; + end + endtask // InsertRead + + initial $dumpfile("fifo_to_wb_tb.vcd"); + initial $dumpvars(0,fifo_to_wb_tb); + + initial + begin + @(negedge rst); + //#10000; + @(posedge clk); + @(posedge clk); + @(posedge clk); + @(posedge clk); + InsertRW(16'hF00D, 6'd0, 8'hB5, 16'd7, 16'h1234); + #20000; + InsertRW(16'h9876, 6'd0, 8'h43, 16'd8, 16'hBEEF); + #20000; + InsertRW(16'h1000, 6'd0, 8'h96, 16'd4, 16'hF00D); + #20000; + InsertRW(16'h3000, 6'd0, 8'h12, 16'd10,16'hDEAD); + #20000 $finish; + end + +endmodule // fifo_to_wb_tb diff --git a/fpga/usrp2/control_lib/gray2bin.v b/fpga/usrp2/control_lib/gray2bin.v index 5df40bd52..399d5bba0 100644 --- a/fpga/usrp2/control_lib/gray2bin.v +++ b/fpga/usrp2/control_lib/gray2bin.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module gray2bin diff --git a/fpga/usrp2/control_lib/gray_send.v b/fpga/usrp2/control_lib/gray_send.v index 7fc07d40c..62402f8d3 100644 --- a/fpga/usrp2/control_lib/gray_send.v +++ b/fpga/usrp2/control_lib/gray_send.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + diff --git a/fpga/usrp2/control_lib/icache.v b/fpga/usrp2/control_lib/icache.v index bd21f47cc..810b5fa64 100644 --- a/fpga/usrp2/control_lib/icache.v +++ b/fpga/usrp2/control_lib/icache.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module icache #(parameter AWIDTH=14, diff --git a/fpga/usrp2/control_lib/longfifo.v b/fpga/usrp2/control_lib/longfifo.v index bf3338e0b..c77f2dcb1 100644 --- a/fpga/usrp2/control_lib/longfifo.v +++ b/fpga/usrp2/control_lib/longfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // FIFO intended to be interchangeable with shortfifo, but // based on block ram instead of SRL16's diff --git a/fpga/usrp2/control_lib/medfifo.v b/fpga/usrp2/control_lib/medfifo.v index 5a77e8c16..0f66f6597 100644 --- a/fpga/usrp2/control_lib/medfifo.v +++ b/fpga/usrp2/control_lib/medfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module medfifo #(parameter WIDTH=32, diff --git a/fpga/usrp2/control_lib/mux4.v b/fpga/usrp2/control_lib/mux4.v index 31c85c832..b1878f011 100644 --- a/fpga/usrp2/control_lib/mux4.v +++ b/fpga/usrp2/control_lib/mux4.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module mux4 diff --git a/fpga/usrp2/control_lib/mux8.v b/fpga/usrp2/control_lib/mux8.v index 9db96a60f..bdb015dc3 100644 --- a/fpga/usrp2/control_lib/mux8.v +++ b/fpga/usrp2/control_lib/mux8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module mux8 diff --git a/fpga/usrp2/control_lib/mux_32_4.v b/fpga/usrp2/control_lib/mux_32_4.v index fef5812e9..4a1244933 100644 --- a/fpga/usrp2/control_lib/mux_32_4.v +++ b/fpga/usrp2/control_lib/mux_32_4.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module mux_32_4 diff --git a/fpga/usrp2/control_lib/oneshot_2clk.v b/fpga/usrp2/control_lib/oneshot_2clk.v index 72f16a4b3..7ed5bc8f6 100644 --- a/fpga/usrp2/control_lib/oneshot_2clk.v +++ b/fpga/usrp2/control_lib/oneshot_2clk.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Retime a single bit from one clock domain to another // Guarantees that no matter what the relative clock rates, if the in signal is high for at least diff --git a/fpga/usrp2/control_lib/priority_enc.v b/fpga/usrp2/control_lib/priority_enc.v index 916192445..d30870be9 100644 --- a/fpga/usrp2/control_lib/priority_enc.v +++ b/fpga/usrp2/control_lib/priority_enc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module priority_enc (input [31:0] in, diff --git a/fpga/usrp2/control_lib/quad_uart.v b/fpga/usrp2/control_lib/quad_uart.v index afa6fae1d..39998150d 100644 --- a/fpga/usrp2/control_lib/quad_uart.v +++ b/fpga/usrp2/control_lib/quad_uart.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module quad_uart #(parameter TXDEPTH = 1, diff --git a/fpga/usrp2/control_lib/ram_2port.v b/fpga/usrp2/control_lib/ram_2port.v index 3716a7c8a..86d7e4703 100644 --- a/fpga/usrp2/control_lib/ram_2port.v +++ b/fpga/usrp2/control_lib/ram_2port.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ram_2port diff --git a/fpga/usrp2/control_lib/ram_2port_mixed_width.v b/fpga/usrp2/control_lib/ram_2port_mixed_width.v index fae7d8de3..2910d4041 100644 --- a/fpga/usrp2/control_lib/ram_2port_mixed_width.v +++ b/fpga/usrp2/control_lib/ram_2port_mixed_width.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ram_2port_mixed_width (input clk16, diff --git a/fpga/usrp2/control_lib/ram_harv_cache.v b/fpga/usrp2/control_lib/ram_harv_cache.v index 29fdebf7a..e68ed7f68 100644 --- a/fpga/usrp2/control_lib/ram_harv_cache.v +++ b/fpga/usrp2/control_lib/ram_harv_cache.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Dual ported, Harvard architecture, cached ram diff --git a/fpga/usrp2/control_lib/ram_harvard.v b/fpga/usrp2/control_lib/ram_harvard.v index a190e20fd..00ffb1984 100644 --- a/fpga/usrp2/control_lib/ram_harvard.v +++ b/fpga/usrp2/control_lib/ram_harvard.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Dual ported, Harvard architecture, cached ram diff --git a/fpga/usrp2/control_lib/ram_harvard2.v b/fpga/usrp2/control_lib/ram_harvard2.v index 67777af2a..d8fe472f5 100644 --- a/fpga/usrp2/control_lib/ram_harvard2.v +++ b/fpga/usrp2/control_lib/ram_harvard2.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Dual ported, Harvard architecture diff --git a/fpga/usrp2/control_lib/ram_loader.v b/fpga/usrp2/control_lib/ram_loader.v index c53ea7aa7..85ccf91b4 100644 --- a/fpga/usrp2/control_lib/ram_loader.v +++ b/fpga/usrp2/control_lib/ram_loader.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ram_loader #(parameter AWIDTH=16, RAM_SIZE=16384) ( diff --git a/fpga/usrp2/control_lib/ram_wb_harvard.v b/fpga/usrp2/control_lib/ram_wb_harvard.v index c3efc12e0..8d5a45247 100644 --- a/fpga/usrp2/control_lib/ram_wb_harvard.v +++ b/fpga/usrp2/control_lib/ram_wb_harvard.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Dual ported RAM for Harvard architecture processors // Does no forwarding diff --git a/fpga/usrp2/control_lib/reset_sync.v b/fpga/usrp2/control_lib/reset_sync.v index 94d966840..304aba106 100644 --- a/fpga/usrp2/control_lib/reset_sync.v +++ b/fpga/usrp2/control_lib/reset_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module reset_sync diff --git a/fpga/usrp2/control_lib/s3a_icap_wb.v b/fpga/usrp2/control_lib/s3a_icap_wb.v index 83d9f775e..e49b56cff 100644 --- a/fpga/usrp2/control_lib/s3a_icap_wb.v +++ b/fpga/usrp2/control_lib/s3a_icap_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module s3a_icap_wb diff --git a/fpga/usrp2/control_lib/sd_spi.v b/fpga/usrp2/control_lib/sd_spi.v index 3f4d7f46a..fa998d19a 100644 --- a/fpga/usrp2/control_lib/sd_spi.v +++ b/fpga/usrp2/control_lib/sd_spi.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module sd_spi (input clk, input rst, diff --git a/fpga/usrp2/control_lib/sd_spi_tb.v b/fpga/usrp2/control_lib/sd_spi_tb.v index e30a5bdf6..2b5ae083f 100644 --- a/fpga/usrp2/control_lib/sd_spi_tb.v +++ b/fpga/usrp2/control_lib/sd_spi_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module sd_spi_tb; diff --git a/fpga/usrp2/control_lib/sd_spi_wb.v b/fpga/usrp2/control_lib/sd_spi_wb.v index 7a6258b56..b09debd70 100644 --- a/fpga/usrp2/control_lib/sd_spi_wb.v +++ b/fpga/usrp2/control_lib/sd_spi_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Wishbone module for spi communications with an SD Card // The programming interface is simple -- diff --git a/fpga/usrp2/control_lib/setting_reg.v b/fpga/usrp2/control_lib/setting_reg.v index 3d3bb65e5..e4c84d910 100644 --- a/fpga/usrp2/control_lib/setting_reg.v +++ b/fpga/usrp2/control_lib/setting_reg.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module setting_reg diff --git a/fpga/usrp2/control_lib/settings_bus.v b/fpga/usrp2/control_lib/settings_bus.v index aec179516..e2ea7e44b 100644 --- a/fpga/usrp2/control_lib/settings_bus.v +++ b/fpga/usrp2/control_lib/settings_bus.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock diff --git a/fpga/usrp2/control_lib/settings_bus_16LE.v b/fpga/usrp2/control_lib/settings_bus_16LE.v index 76061e9e0..7c42a0870 100644 --- a/fpga/usrp2/control_lib/settings_bus_16LE.v +++ b/fpga/usrp2/control_lib/settings_bus_16LE.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Grab settings off the wishbone bus, send them out to settings bus // 16 bits little endian, but all registers need to be written 32 bits at a time. diff --git a/fpga/usrp2/control_lib/settings_bus_crossclock.v b/fpga/usrp2/control_lib/settings_bus_crossclock.v index b043aa0ad..9c5912042 100644 --- a/fpga/usrp2/control_lib/settings_bus_crossclock.v +++ b/fpga/usrp2/control_lib/settings_bus_crossclock.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // This module takes the settings bus on one clock domain and crosses it over to another domain diff --git a/fpga/usrp2/control_lib/shortfifo.v b/fpga/usrp2/control_lib/shortfifo.v index d8ce1428e..c7c916375 100644 --- a/fpga/usrp2/control_lib/shortfifo.v +++ b/fpga/usrp2/control_lib/shortfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module shortfifo #(parameter WIDTH=32) diff --git a/fpga/usrp2/control_lib/simple_uart.v b/fpga/usrp2/control_lib/simple_uart.v index 0dd58b5f5..f44a719f4 100644 --- a/fpga/usrp2/control_lib/simple_uart.v +++ b/fpga/usrp2/control_lib/simple_uart.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_uart #(parameter TXDEPTH = 1, diff --git a/fpga/usrp2/control_lib/simple_uart_rx.v b/fpga/usrp2/control_lib/simple_uart_rx.v index debdd618b..5f7646e03 100644 --- a/fpga/usrp2/control_lib/simple_uart_rx.v +++ b/fpga/usrp2/control_lib/simple_uart_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_uart_rx diff --git a/fpga/usrp2/control_lib/simple_uart_tx.v b/fpga/usrp2/control_lib/simple_uart_tx.v index e11a347ed..f38460bd4 100644 --- a/fpga/usrp2/control_lib/simple_uart_tx.v +++ b/fpga/usrp2/control_lib/simple_uart_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_uart_tx #(parameter DEPTH=0) diff --git a/fpga/usrp2/control_lib/spi.v b/fpga/usrp2/control_lib/spi.v index a80c488e9..1abebee1c 100644 --- a/fpga/usrp2/control_lib/spi.v +++ b/fpga/usrp2/control_lib/spi.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // AD9510 Register Map (from datasheet Rev. A) diff --git a/fpga/usrp2/control_lib/srl.v b/fpga/usrp2/control_lib/srl.v index fa28c7669..bdef30058 100644 --- a/fpga/usrp2/control_lib/srl.v +++ b/fpga/usrp2/control_lib/srl.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module srl #(parameter WIDTH=18) diff --git a/fpga/usrp2/control_lib/ss_rcvr.v b/fpga/usrp2/control_lib/ss_rcvr.v index 8e650d21b..4fb732c23 100644 --- a/fpga/usrp2/control_lib/ss_rcvr.v +++ b/fpga/usrp2/control_lib/ss_rcvr.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Source-synchronous receiver diff --git a/fpga/usrp2/control_lib/system_control.v b/fpga/usrp2/control_lib/system_control.v index 5d89f13db..7e7b71f3c 100644 --- a/fpga/usrp2/control_lib/system_control.v +++ b/fpga/usrp2/control_lib/system_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // System bootup order: // 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? // 1 - Everything in reset diff --git a/fpga/usrp2/control_lib/system_control_tb.v b/fpga/usrp2/control_lib/system_control_tb.v index a8eff4811..8fecfd1f0 100644 --- a/fpga/usrp2/control_lib/system_control_tb.v +++ b/fpga/usrp2/control_lib/system_control_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module system_control_tb(); diff --git a/fpga/usrp2/control_lib/traffic_cop.v b/fpga/usrp2/control_lib/traffic_cop.v index e7579656a..874e4c2d9 100644 --- a/fpga/usrp2/control_lib/traffic_cop.v +++ b/fpga/usrp2/control_lib/traffic_cop.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module traffic_cop(); diff --git a/fpga/usrp2/control_lib/v5icap_wb.v b/fpga/usrp2/control_lib/v5icap_wb.v index c8800285a..92a6769e5 100644 --- a/fpga/usrp2/control_lib/v5icap_wb.v +++ b/fpga/usrp2/control_lib/v5icap_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module v5icap_wb diff --git a/fpga/usrp2/control_lib/wb_bridge_16_32.v b/fpga/usrp2/control_lib/wb_bridge_16_32.v index 405e25c3c..7c62c9cbd 100644 --- a/fpga/usrp2/control_lib/wb_bridge_16_32.v +++ b/fpga/usrp2/control_lib/wb_bridge_16_32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module wb_bridge_16_32 diff --git a/fpga/usrp2/control_lib/wb_bus_writer.v b/fpga/usrp2/control_lib/wb_bus_writer.v index fc148a0ff..08e641d37 100644 --- a/fpga/usrp2/control_lib/wb_bus_writer.v +++ b/fpga/usrp2/control_lib/wb_bus_writer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // wb_bus_writer // diff --git a/fpga/usrp2/control_lib/wb_output_pins32.v b/fpga/usrp2/control_lib/wb_output_pins32.v index 1517f2066..43e239797 100644 --- a/fpga/usrp2/control_lib/wb_output_pins32.v +++ b/fpga/usrp2/control_lib/wb_output_pins32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Simple 32-bit Wishbone compatible slave output port diff --git a/fpga/usrp2/control_lib/wb_ram_block.v b/fpga/usrp2/control_lib/wb_ram_block.v index 044d34ca4..da6c610d3 100644 --- a/fpga/usrp2/control_lib/wb_ram_block.v +++ b/fpga/usrp2/control_lib/wb_ram_block.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Since this is a block ram, there are no byte-selects and there is a 1-cycle read latency diff --git a/fpga/usrp2/control_lib/wb_ram_dist.v b/fpga/usrp2/control_lib/wb_ram_dist.v index cffc2f423..491a6ae11 100644 --- a/fpga/usrp2/control_lib/wb_ram_dist.v +++ b/fpga/usrp2/control_lib/wb_ram_dist.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module wb_ram_dist diff --git a/fpga/usrp2/control_lib/wb_readback_mux.v b/fpga/usrp2/control_lib/wb_readback_mux.v index 3922b03e3..a5bf224b8 100644 --- a/fpga/usrp2/control_lib/wb_readback_mux.v +++ b/fpga/usrp2/control_lib/wb_readback_mux.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Note -- clocks must be synchronous (derived from the same source) diff --git a/fpga/usrp2/control_lib/wb_readback_mux_16LE.v b/fpga/usrp2/control_lib/wb_readback_mux_16LE.v index 2b01898c1..aceec601b 100644 --- a/fpga/usrp2/control_lib/wb_readback_mux_16LE.v +++ b/fpga/usrp2/control_lib/wb_readback_mux_16LE.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Note -- clocks must be synchronous (derived from the same source) diff --git a/fpga/usrp2/control_lib/wb_regfile_2clock.v b/fpga/usrp2/control_lib/wb_regfile_2clock.v index e248e5161..ce93ab3f4 100644 --- a/fpga/usrp2/control_lib/wb_regfile_2clock.v +++ b/fpga/usrp2/control_lib/wb_regfile_2clock.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module wb_regfile_2clock (input wb_clk_i, diff --git a/fpga/usrp2/control_lib/wb_semaphore.v b/fpga/usrp2/control_lib/wb_semaphore.v index a9208e6a1..e90950509 100644 --- a/fpga/usrp2/control_lib/wb_semaphore.v +++ b/fpga/usrp2/control_lib/wb_semaphore.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // up to 8 semaphores diff --git a/fpga/usrp2/control_lib/wb_sim.v b/fpga/usrp2/control_lib/wb_sim.v index b324e1457..9f2fbea54 100644 --- a/fpga/usrp2/control_lib/wb_sim.v +++ b/fpga/usrp2/control_lib/wb_sim.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module wb_sim(); diff --git a/fpga/usrp2/extramfifo/ext_fifo.v b/fpga/usrp2/extramfifo/ext_fifo.v index 80f82fc63..620f4dddd 100644 --- a/fpga/usrp2/extramfifo/ext_fifo.v +++ b/fpga/usrp2/extramfifo/ext_fifo.v @@ -1,4 +1,21 @@ // +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +// // FIFO backed by an off chip ZBT/NoBL SRAM. // // This module and its sub-hierarchy implment a FIFO capable of sustaining diff --git a/fpga/usrp2/extramfifo/ext_fifo_tb.v b/fpga/usrp2/extramfifo/ext_fifo_tb.v index 395ad2884..f6fe47297 100644 --- a/fpga/usrp2/extramfifo/ext_fifo_tb.v +++ b/fpga/usrp2/extramfifo/ext_fifo_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps `define USRP2 //`define USRP2PLUS diff --git a/fpga/usrp2/extramfifo/nobl_fifo.v b/fpga/usrp2/extramfifo/nobl_fifo.v index 0b63768fc..469e3eab5 100644 --- a/fpga/usrp2/extramfifo/nobl_fifo.v +++ b/fpga/usrp2/extramfifo/nobl_fifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Since this FIFO uses a ZBT/NoBL SRAM for its storage which is a since port // device it can only sustain data throughput at half the RAM clock rate. // Fair arbitration to ensure this occurs is included in this logic and diff --git a/fpga/usrp2/extramfifo/nobl_if.v b/fpga/usrp2/extramfifo/nobl_if.v index b5ebe9c6b..0a64d3857 100644 --- a/fpga/usrp2/extramfifo/nobl_if.v +++ b/fpga/usrp2/extramfifo/nobl_if.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world. module nobl_if diff --git a/fpga/usrp2/extramfifo/refill_randomizer.v b/fpga/usrp2/extramfifo/refill_randomizer.v index 0b30f4049..09728b8c0 100644 --- a/fpga/usrp2/extramfifo/refill_randomizer.v +++ b/fpga/usrp2/extramfifo/refill_randomizer.v @@ -1,4 +1,21 @@ // +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +// // EMI mitigation. // Process FULL flag from FIFO so that de-assertion // (FIFO now not FULL) is delayed by a pseudo random diff --git a/fpga/usrp2/extramfifo/test_sram_if.v b/fpga/usrp2/extramfifo/test_sram_if.v index 0e74b49eb..dcb881a92 100644 --- a/fpga/usrp2/extramfifo/test_sram_if.v +++ b/fpga/usrp2/extramfifo/test_sram_if.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Instantiate this block at the core level to conduct closed // loop testing of the AC performance of the USRP2 SRAM interface diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs index 31b1f505a..02c567049 100644 --- a/fpga/usrp2/fifo/Makefile.srcs +++ b/fpga/usrp2/fifo/Makefile.srcs @@ -23,6 +23,7 @@ fifo19_to_ll8.v \ ll8_to_fifo19.v \ fifo36_to_fifo19.v \ fifo19_to_fifo36.v \ +fifo19_mux.v \ fifo36_mux.v \ fifo36_demux.v \ packet_router.v \ @@ -34,4 +35,5 @@ packet_generator32.v \ packet_generator.v \ packet_verifier32.v \ packet_verifier.v \ +fifo19_pad.v \ )) diff --git a/fpga/usrp2/fifo/buffer_int.v b/fpga/usrp2/fifo/buffer_int.v index 49ded8c8d..c068226ec 100644 --- a/fpga/usrp2/fifo/buffer_int.v +++ b/fpga/usrp2/fifo/buffer_int.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // FIFO Interface to the 2K buffer RAMs // Read port is read-acknowledge diff --git a/fpga/usrp2/fifo/buffer_int2.v b/fpga/usrp2/fifo/buffer_int2.v index 532980aa2..7dd528dd5 100644 --- a/fpga/usrp2/fifo/buffer_int2.v +++ b/fpga/usrp2/fifo/buffer_int2.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // FIFO Interface to the 2K buffer RAMs // Read port is read-acknowledge diff --git a/fpga/usrp2/fifo/buffer_int_tb.v b/fpga/usrp2/fifo/buffer_int_tb.v index df54dcc0b..44f8be0a0 100644 --- a/fpga/usrp2/fifo/buffer_int_tb.v +++ b/fpga/usrp2/fifo/buffer_int_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module buffer_int_tb (); diff --git a/fpga/usrp2/fifo/buffer_pool.v b/fpga/usrp2/fifo/buffer_pool.v index 41ac1deb3..48f5bd69c 100644 --- a/fpga/usrp2/fifo/buffer_pool.v +++ b/fpga/usrp2/fifo/buffer_pool.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer // is a dual-ported RAM. Port A on each of them is indirectly connected diff --git a/fpga/usrp2/fifo/buffer_pool_tb.v b/fpga/usrp2/fifo/buffer_pool_tb.v index 91a01d268..0ee76689e 100644 --- a/fpga/usrp2/fifo/buffer_pool_tb.v +++ b/fpga/usrp2/fifo/buffer_pool_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module buffer_pool_tb(); diff --git a/fpga/usrp2/fifo/crossbar36.v b/fpga/usrp2/fifo/crossbar36.v index 2a046d8bf..4e2aed7ce 100644 --- a/fpga/usrp2/fifo/crossbar36.v +++ b/fpga/usrp2/fifo/crossbar36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module crossbar36 diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v index 58455cee1..ef7395551 100644 --- a/fpga/usrp2/fifo/dsp_framer36.v +++ b/fpga/usrp2/fifo/dsp_framer36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // This has 3 functions: // Correct the VITA packet length diff --git a/fpga/usrp2/fifo/fifo19_mux.v b/fpga/usrp2/fifo/fifo19_mux.v new file mode 100644 index 000000000..a23ac2bb4 --- /dev/null +++ b/fpga/usrp2/fifo/fifo19_mux.v @@ -0,0 +1,94 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +// Mux packets from multiple FIFO interfaces onto a single one. +// Can alternate or give priority to one port (port 0) +// In prio mode, port 1 will never get access if port 0 is always busy + +module fifo19_mux + #(parameter prio = 0) + (input clk, input reset, input clear, + input [18:0] data0_i, input src0_rdy_i, output dst0_rdy_o, + input [18:0] data1_i, input src1_rdy_i, output dst1_rdy_o, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i); + + wire [18:0] data0_int, data1_int; + wire src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int; + + fifo_short #(.WIDTH(19)) mux_fifo_in0 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o), + .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int)); + + fifo_short #(.WIDTH(19)) mux_fifo_in1 + (.clk(clk), .reset(reset), .clear(clear), + .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o), + .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int)); + + localparam MUX_IDLE0 = 0; + localparam MUX_DATA0 = 1; + localparam MUX_IDLE1 = 2; + localparam MUX_DATA1 = 3; + + reg [1:0] state; + + wire eof0 = data0_int[17]; + wire eof1 = data1_int[17]; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + + always @(posedge clk) + if(reset | clear) + state <= MUX_IDLE0; + else + case(state) + MUX_IDLE0 : + if(src0_rdy_int) + state <= MUX_DATA0; + else if(src1_rdy_int) + state <= MUX_DATA1; + + MUX_DATA0 : + if(src0_rdy_int & dst_rdy_int & eof0) + state <= prio ? MUX_IDLE0 : MUX_IDLE1; + + MUX_IDLE1 : + if(src1_rdy_int) + state <= MUX_DATA1; + else if(src0_rdy_int) + state <= MUX_DATA0; + + MUX_DATA1 : + if(src1_rdy_int & dst_rdy_int & eof1) + state <= MUX_IDLE0; + + default : + state <= MUX_IDLE0; + endcase // case (state) + + assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0; + assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0; + assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0; + assign data_int = (state==MUX_DATA0) ? data0_int : data1_int; + + fifo_short #(.WIDTH(19)) mux_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i)); +endmodule // fifo19_mux diff --git a/fpga/usrp2/fifo/fifo19_pad.v b/fpga/usrp2/fifo/fifo19_pad.v new file mode 100644 index 000000000..bb6e1fa92 --- /dev/null +++ b/fpga/usrp2/fifo/fifo19_pad.v @@ -0,0 +1,83 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +// Pads a packet out to the minimum length +// Packets already longer than min length are unchanged + + +module fifo19_pad + #(parameter LENGTH=16, + parameter PAD_VALUE=0) + (input clk, input reset, input clear, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i); + + reg [15:0] count; + reg [1:0] pad_state; + localparam PAD_IDLE = 0; + localparam PAD_TOOSHORT = 1; + localparam PAD_LONGENOUGH = 2; + localparam PAD_PADDING = 3; + + always @(posedge clk) + if(reset | clear) + pad_state <= PAD_IDLE; + else + case(pad_state) + PAD_IDLE : + begin + count <= 1; + pad_state <= PAD_TOOSHORT; + end + PAD_TOOSHORT : + if(src_rdy_i & dst_rdy_i) + begin + count <= count + 1; + if(data_i[17]) + pad_state <= PAD_PADDING; + else if(count == (LENGTH-1)) + pad_state <= PAD_LONGENOUGH; + end + PAD_PADDING : + if(dst_rdy_i) + begin + count <= count + 1; + if(count == LENGTH) + pad_state <= PAD_IDLE; + end + PAD_LONGENOUGH : + if(src_rdy_i & dst_rdy_i & data_i[17]) + pad_state <= PAD_IDLE; + endcase // case (pad_state) + + wire passthru = (pad_state == PAD_TOOSHORT) | (pad_state == PAD_LONGENOUGH); + + assign dst_rdy_o = passthru ? dst_rdy_i : 1'b0; + assign src_rdy_o = passthru ? src_rdy_i : (pad_state == PAD_PADDING); + + assign data_o[15:0] = (pad_state == PAD_PADDING) ? PAD_VALUE : data_i[15:0]; + assign data_o[16] = (count == 1); + assign data_o[17] = (pad_state == PAD_LONGENOUGH) ? data_i[17] : (count == LENGTH); + assign data_o[18] = (pad_state == PAD_LONGENOUGH) ? data_i[18] : 1'b0; + + +endmodule // fifo19_pad diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v index 502821435..32734405a 100644 --- a/fpga/usrp2/fifo/fifo19_to_fifo36.v +++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/fpga/usrp2/fifo/fifo19_to_ll8.v b/fpga/usrp2/fifo/fifo19_to_ll8.v index 4707f7523..1ebb140c2 100644 --- a/fpga/usrp2/fifo/fifo19_to_ll8.v +++ b/fpga/usrp2/fifo/fifo19_to_ll8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo19_to_ll8 (input clk, input reset, input clear, diff --git a/fpga/usrp2/fifo/fifo36_demux.v b/fpga/usrp2/fifo/fifo36_demux.v index a54759d4d..6f516691a 100644 --- a/fpga/usrp2/fifo/fifo36_demux.v +++ b/fpga/usrp2/fifo/fifo36_demux.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Demux packets from a fifo based on the contents of the first line // If first line matches the parameter and mask, send to data1, otherwise send to data0 diff --git a/fpga/usrp2/fifo/fifo36_mux.v b/fpga/usrp2/fifo/fifo36_mux.v index 7f0f803ff..cf7b2b4d1 100644 --- a/fpga/usrp2/fifo/fifo36_mux.v +++ b/fpga/usrp2/fifo/fifo36_mux.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Mux packets from multiple FIFO interfaces onto a single one. // Can alternate or give priority to one port (port 0) diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v index 0e9b2d442..cb93e10ad 100644 --- a/fpga/usrp2/fifo/fifo36_to_fifo19.v +++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/fpga/usrp2/fifo/fifo36_to_fifo72.v b/fpga/usrp2/fifo/fifo36_to_fifo72.v index 038eda9e9..237149cc2 100644 --- a/fpga/usrp2/fifo/fifo36_to_fifo72.v +++ b/fpga/usrp2/fifo/fifo36_to_fifo72.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v index 390e49962..5c2da812f 100644 --- a/fpga/usrp2/fifo/fifo36_to_ll8.v +++ b/fpga/usrp2/fifo/fifo36_to_ll8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo36_to_ll8 (input clk, input reset, input clear, diff --git a/fpga/usrp2/fifo/fifo72_to_fifo36.v b/fpga/usrp2/fifo/fifo72_to_fifo36.v index 1b3bc3ab7..c365f0196 100644 --- a/fpga/usrp2/fifo/fifo72_to_fifo36.v +++ b/fpga/usrp2/fifo/fifo72_to_fifo36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Parameter LE tells us if we are little-endian. // Little-endian means send lower 16 bits first. diff --git a/fpga/usrp2/fifo/fifo_19to36_tb.v b/fpga/usrp2/fifo/fifo_19to36_tb.v index c585392c3..143b92b1b 100644 --- a/fpga/usrp2/fifo/fifo_19to36_tb.v +++ b/fpga/usrp2/fifo/fifo_19to36_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo_tb(); reg clk = 0; diff --git a/fpga/usrp2/fifo/fifo_2clock.v b/fpga/usrp2/fifo/fifo_2clock.v index 34c85ccb4..756ad508f 100644 --- a/fpga/usrp2/fifo/fifo_2clock.v +++ b/fpga/usrp2/fifo/fifo_2clock.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // FIXME ignores the AWIDTH (fifo size) parameter @@ -14,7 +31,8 @@ module fifo_2clock assign src_rdy_o = ~empty; assign write = src_rdy_i & dst_rdy_o; assign read = src_rdy_o & dst_rdy_i; - + wire dummy; + generate if(WIDTH==36) if(SIZE==9) @@ -37,12 +55,16 @@ module fifo_2clock (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if((WIDTH==19)|(WIDTH==18)) - if(SIZE==4) - fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(arst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==18) & (SIZE==4)) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(arst), + .wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; diff --git a/fpga/usrp2/fifo/fifo_2clock_cascade.v b/fpga/usrp2/fifo/fifo_2clock_cascade.v index 4e8c244c2..49cac7097 100644 --- a/fpga/usrp2/fifo/fifo_2clock_cascade.v +++ b/fpga/usrp2/fifo/fifo_2clock_cascade.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo_2clock_cascade #(parameter WIDTH=32, SIZE=9) diff --git a/fpga/usrp2/fifo/fifo_cascade.v b/fpga/usrp2/fifo/fifo_cascade.v index fdd8449bc..5a79c4090 100644 --- a/fpga/usrp2/fifo/fifo_cascade.v +++ b/fpga/usrp2/fifo/fifo_cascade.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // This FIFO exists to provide an intermediate point for the data on its diff --git a/fpga/usrp2/fifo/fifo_long.v b/fpga/usrp2/fifo/fifo_long.v index 0426779f6..e9739ad94 100644 --- a/fpga/usrp2/fifo/fifo_long.v +++ b/fpga/usrp2/fifo/fifo_long.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // FIFO intended to be interchangeable with shortfifo, but // based on block ram instead of SRL16's diff --git a/fpga/usrp2/fifo/fifo_pacer.v b/fpga/usrp2/fifo/fifo_pacer.v index 1bf03ab6e..3e3fbf8b8 100644 --- a/fpga/usrp2/fifo/fifo_pacer.v +++ b/fpga/usrp2/fifo/fifo_pacer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo_pacer diff --git a/fpga/usrp2/fifo/fifo_short.v b/fpga/usrp2/fifo/fifo_short.v index 53a7603c7..32f26beef 100644 --- a/fpga/usrp2/fifo/fifo_short.v +++ b/fpga/usrp2/fifo/fifo_short.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo_short #(parameter WIDTH=32) diff --git a/fpga/usrp2/fifo/fifo_tb.v b/fpga/usrp2/fifo/fifo_tb.v index 3e2862a70..c63c201d0 100644 --- a/fpga/usrp2/fifo/fifo_tb.v +++ b/fpga/usrp2/fifo/fifo_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo_tb(); reg clk = 0; diff --git a/fpga/usrp2/fifo/ll8_shortfifo.v b/fpga/usrp2/fifo/ll8_shortfifo.v index 39ada9a4f..49b3a3139 100644 --- a/fpga/usrp2/fifo/ll8_shortfifo.v +++ b/fpga/usrp2/fifo/ll8_shortfifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ll8_shortfifo diff --git a/fpga/usrp2/fifo/ll8_to_fifo19.v b/fpga/usrp2/fifo/ll8_to_fifo19.v index ac8ac19a6..4503d0c3d 100644 --- a/fpga/usrp2/fifo/ll8_to_fifo19.v +++ b/fpga/usrp2/fifo/ll8_to_fifo19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ll8_to_fifo19 (input clk, input reset, input clear, diff --git a/fpga/usrp2/fifo/ll8_to_fifo36.v b/fpga/usrp2/fifo/ll8_to_fifo36.v index 108daa903..b26f745d2 100644 --- a/fpga/usrp2/fifo/ll8_to_fifo36.v +++ b/fpga/usrp2/fifo/ll8_to_fifo36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ll8_to_fifo36 (input clk, input reset, input clear, diff --git a/fpga/usrp2/fifo/packet32_tb.v b/fpga/usrp2/fifo/packet32_tb.v index 82bb09c29..8a7cfcec5 100644 --- a/fpga/usrp2/fifo/packet32_tb.v +++ b/fpga/usrp2/fifo/packet32_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module packet32_tb(); diff --git a/fpga/usrp2/fifo/packet_generator.v b/fpga/usrp2/fifo/packet_generator.v index 2ae911e24..5e9d3c2ab 100644 --- a/fpga/usrp2/fifo/packet_generator.v +++ b/fpga/usrp2/fifo/packet_generator.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module packet_generator diff --git a/fpga/usrp2/fifo/packet_generator32.v b/fpga/usrp2/fifo/packet_generator32.v index 1dc57191d..7b4e3bd57 100644 --- a/fpga/usrp2/fifo/packet_generator32.v +++ b/fpga/usrp2/fifo/packet_generator32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module packet_generator32 diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v index 04c17b647..7bfa6893d 100644 --- a/fpga/usrp2/fifo/packet_router.v +++ b/fpga/usrp2/fifo/packet_router.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module packet_router #( parameter BUF_SIZE = 9, diff --git a/fpga/usrp2/fifo/packet_tb.v b/fpga/usrp2/fifo/packet_tb.v index 3c423d2ba..ec0665e0a 100644 --- a/fpga/usrp2/fifo/packet_tb.v +++ b/fpga/usrp2/fifo/packet_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module packet_tb(); diff --git a/fpga/usrp2/fifo/packet_verifier.v b/fpga/usrp2/fifo/packet_verifier.v index 21a4c136e..3cc7b0a04 100644 --- a/fpga/usrp2/fifo/packet_verifier.v +++ b/fpga/usrp2/fifo/packet_verifier.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Packet format -- diff --git a/fpga/usrp2/fifo/packet_verifier32.v b/fpga/usrp2/fifo/packet_verifier32.v index ec08e657d..3579a9bcf 100644 --- a/fpga/usrp2/fifo/packet_verifier32.v +++ b/fpga/usrp2/fifo/packet_verifier32.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module packet_verifier32 diff --git a/fpga/usrp2/fifo/splitter36.v b/fpga/usrp2/fifo/splitter36.v index ed998b4f5..d002d7afd 100644 --- a/fpga/usrp2/fifo/splitter36.v +++ b/fpga/usrp2/fifo/splitter36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Split packets from a fifo based interface so it goes out identically on two interfaces diff --git a/fpga/usrp2/fifo/valve36.v b/fpga/usrp2/fifo/valve36.v index d45eee497..795fe511e 100644 --- a/fpga/usrp2/fifo/valve36.v +++ b/fpga/usrp2/fifo/valve36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module valve36 diff --git a/fpga/usrp2/gpif/Makefile.srcs b/fpga/usrp2/gpif/Makefile.srcs new file mode 100644 index 000000000..bf2b7f74d --- /dev/null +++ b/fpga/usrp2/gpif/Makefile.srcs @@ -0,0 +1,14 @@ +# +# Copyright 2010 Ettus Research LLC +# + +################################################## +# SERDES Sources +################################################## +GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \ +gpif.v \ +gpif_wr.v \ +gpif_rd.v \ +packet_reframer.v \ +packet_splitter.v \ +)) diff --git a/fpga/usrp2/gpif/gpif.v b/fpga/usrp2/gpif/gpif.v new file mode 100644 index 000000000..51d6e8ba9 --- /dev/null +++ b/fpga/usrp2/gpif/gpif.v @@ -0,0 +1,257 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +////////////////////////////////////////////////////////////////////////////////// + +module gpif + #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11) + (// GPIF signals + input gpif_clk, input gpif_rst, + inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + output [2:0] gpif_misc, + + // Wishbone signals + input wb_clk, input wb_rst, + output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, + output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i, + input [7:0] triggers, + + // FIFO interface + input fifo_clk, input fifo_rst, input clear_tx, input clear_rx, + output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i, + input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o, + input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o, + + output tx_underrun, output rx_overrun, + input [7:0] frames_per_packet, input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl, + output [31:0] debug0, output [31:0] debug1 + ); + + wire WR = gpif_ctl[0]; + wire RD = gpif_ctl[1]; + wire OE = gpif_ctl[2]; + wire EP = gpif_ctl[3]; + + wire CF, CE, DF, DE; + + assign gpif_rdy = { CF, CE, DF, DE }; + + wire [15:0] gpif_d_out; + assign gpif_d = OE ? gpif_d_out : 16'bz; + + wire [15:0] gpif_d_copy = gpif_d; + + wire [31:0] debug_rd, debug_wr, debug_split0, debug_split1; + + // //////////////////////////////////////////////////////////////////// + // TX Data Path + + wire [18:0] tx19_data; + wire tx19_src_rdy, tx19_dst_rdy; + wire [35:0] tx36_data, tx_data; + wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy; + + wire [18:0] ctrl_data; + wire ctrl_src_rdy, ctrl_dst_rdy; + + gpif_wr gpif_wr + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_d), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(fifo_clk), .sys_rst(fifo_rst), + .data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx19_dst_rdy), + .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), + .debug(debug_wr) ); + + // join vita packets which are longer than one frame, drop frame padding + wire [18:0] refr_data; + wire refr_src_rdy, refr_dst_rdy; + + packet_reframer tx_packet_reframer + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy), + .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy)); + + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy), + .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); + + fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy)); + + // //////////////////////////////////////////// + // RX Data Path + + wire [35:0] rx36_data, rx_data; + wire rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy; + wire [18:0] rx19_data, splt_data; + wire rx19_src_rdy, rx19_dst_rdy, splt_src_rdy, splt_dst_rdy; + wire [18:0] resp_data, resp_int1, resp_int2; + wire resp_src_rdy, resp_dst_rdy; + wire resp_src_rdy_int1, resp_dst_rdy_int1, resp_src_rdy_int2, resp_dst_rdy_int2; + + fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy), + .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy), + .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) ); + + packet_splitter #(.FRAME_LEN(256)) packet_splitter + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .frames_per_packet(frames_per_packet), + .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), + .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy), + .debug0(debug_split0), .debug1(debug_split1)); + + gpif_rd gpif_rd + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP), + .gpif_empty_d(DE), .gpif_empty_c(CE), .gpif_flush(gpif_misc[0]), + + .sys_clk(fifo_clk), .sys_rst(fifo_rst), + .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy), + .resp_i(resp_data), .resp_src_rdy_i(resp_src_rdy), .resp_dst_rdy_o(resp_dst_rdy), + .debug(debug_rd) ); + + // //////////////////////////////////////////////////////////////////// + // FIFO to Wishbone interface + + fifo_to_wb fifo_to_wb + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), + .data_o(resp_int1), .src_rdy_o(resp_src_rdy_int1), .dst_rdy_i(resp_dst_rdy_int1), + .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), + .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i), + .triggers(triggers), + .debug0(), .debug1()); + + wire [18:0] tx_err19_data; + wire tx_err19_src_rdy, tx_err19_dst_rdy; + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o), + .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) ); + + fifo19_mux #(.prio(0)) mux_err_stream + (.clk(wb_clk), .reset(wb_rst), .clear(0), + .data0_i(resp_int1), .src0_rdy_i(resp_src_rdy_int1), .dst0_rdy_o(resp_dst_rdy_int1), + .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy), + .data_o(resp_int2), .src_rdy_o(resp_src_rdy_int2), .dst_rdy_i(resp_dst_rdy_int2)); + + fifo19_pad #(.LENGTH(16)) fifo19_pad + (.clk(fifo_clk), .reset(fifo_rst), .clear(0), + .data_i(resp_int2), .src_rdy_i(resp_src_rdy_int2), .dst_rdy_o(resp_dst_rdy_int2), + .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy)); + + // //////////////////////////////////////////////////////////////////// + // Debug support, timed and loopback + // RX side muxes test data into the same stream + wire [35:0] timedrx_data, loopbackrx_data, testrx_data; + wire [35:0] timedtx_data, loopbacktx_data, testtx_data; + wire timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy, + testrx_src_rdy, testrx_dst_rdy; + wire timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy, + testtx_src_rdy, testtx_dst_rdy; + wire timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int; + + wire [31:0] total, crc_err, seq_err, len_err; + wire sel_testtx = test_ctrl[0]; + wire sel_loopbacktx = test_ctrl[1]; + wire pkt_src_enable = test_ctrl[2]; + wire pkt_sink_enable = test_ctrl[3]; + + fifo36_mux rx_test_mux_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy), + .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy), + .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy)); + + fifo36_mux rx_test_mux_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy), + .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o), + .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy)); + + fifo_short #(.WIDTH(36)) loopback_fifo + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx), + .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy), + .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy)); + + // Crossbar used as a demux for switching TX stream to main DSP or to test logic + crossbar36 tx_crossbar_lvl_1 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_testtx), + .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy), + .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i), + .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) ); + + crossbar36 tx_crossbar_lvl_2 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .cross(sel_loopbacktx), + .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy), + .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(), // No 2nd input + .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy), + .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) ); + + // Fixed rate TX traffic consumer + fifo_pacer tx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable), + .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy), + .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int), + .underrun(tx_underrun), .overrun()); + + packet_verifier32 pktver32 + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int), + .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err)); + + // Fixed rate RX traffic generator + vita_pkt_gen pktgen + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), + .len(test_len), + .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int)); + + fifo_pacer rx_pacer + (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable), + .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int), + .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy), + .underrun(), .overrun(rx_overrun)); + + // //////////////////////////////////////////// + // DEBUG + + //assign debug0 = { rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy, gpif_ctl[3:0], gpif_rdy[3:0], + // gpif_d_copy[15:0] }; + + //assign debug1 = { { debug_rd[15:8] }, + // { debug_rd[7:0] }, + // { rx_src_rdy_i, rx_dst_rdy_o, rx36_src_rdy, rx36_dst_rdy, rx19_src_rdy, rx19_dst_rdy, resp_src_rdy, resp_dst_rdy}, + // { tx_src_rdy_o, tx_dst_rdy_i, tx19_src_rdy, tx19_dst_rdy, tx36_src_rdy, tx36_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy} }; + + assign debug0 = { gpif_ctl[3:0], gpif_rdy[3:0], debug_split0[23:0] }; + assign debug1 = { gpif_misc[0], debug_rd[14:0], debug_split1[15:8], debug_split1[7:0] }; +endmodule // gpif diff --git a/fpga/usrp2/gpif/gpif_rd.v b/fpga/usrp2/gpif/gpif_rd.v new file mode 100644 index 000000000..b05c3cfb6 --- /dev/null +++ b/fpga/usrp2/gpif/gpif_rd.v @@ -0,0 +1,111 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_rd + (input gpif_clk, input gpif_rst, + output [15:0] gpif_data, input gpif_rd, input gpif_ep, + output reg gpif_empty_d, output reg gpif_empty_c, + output reg gpif_flush, + + input sys_clk, input sys_rst, + input [18:0] data_i, input src_rdy_i, output dst_rdy_o, + input [18:0] resp_i, input resp_src_rdy_i, output resp_dst_rdy_o, + output [31:0] debug + ); + + wire [18:0] data_o; // occ bit indicates flush + wire [17:0] resp_o; // no occ bit + wire final_rdy_data, final_rdy_resp; + + // 33/257 Bug Fix + reg [8:0] read_count; + always @(negedge gpif_clk) + if(gpif_rst) + read_count <= 0; + else if(gpif_rd) + read_count <= read_count + 1; + else + read_count <= 0; + + // Data Path + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk + (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(), + .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(), + .arst(sys_rst)); + + reg [7:0] packet_count; + wire consume_data_line = gpif_rd & ~gpif_ep & ~read_count[8]; + wire produce_eop = src_rdy_int & dst_rdy_int & data_int[17]; + wire consume_sop = consume_data_line & final_rdy_data & data_o[16]; + wire consume_eop = consume_data_line & final_rdy_data & data_o[17]; + + fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo + (.clk(~gpif_clk), .reset(gpif_rst), .clear(0), + .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), + .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied()); + + always @(negedge gpif_clk) + if(gpif_rst) + packet_count <= 0; + else + if(produce_eop & ~consume_sop) + packet_count <= packet_count + 1; + else if(consume_sop & ~produce_eop) + packet_count <= packet_count - 1; + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_d <= 1; + else + gpif_empty_d <= ~|packet_count; + + // Use occ bit to signal a gpif flush + always @(negedge gpif_clk) + if(gpif_rst) + gpif_flush <= 0; + else if(consume_eop & data_o[18]) + gpif_flush <= ~gpif_flush; + + // Response Path + wire [15:0] resp_fifolevel; + wire consume_resp_line = gpif_rd & gpif_ep & ~read_count[4]; + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk + (.wclk(sys_clk), .datain(resp_i[17:0]), .src_rdy_i(resp_src_rdy_i), .dst_rdy_o(resp_dst_rdy_o), .space(), + .rclk(~gpif_clk), .dataout(resp_o), + .src_rdy_o(final_rdy_resp), .dst_rdy_i(consume_resp_line), .occupied(resp_fifolevel), + .arst(sys_rst)); + + // FIXME -- handle short packets + + always @(negedge gpif_clk) + if(gpif_rst) + gpif_empty_c <= 1; + else + gpif_empty_c <= resp_fifolevel < 16; + + // Output Mux + assign gpif_data = gpif_ep ? resp_o[15:0] : data_o[15:0]; + + assign debug = { { 16'd0 }, + { data_int[17:16], data_o[17:16], packet_count[3:0] }, + { consume_sop, consume_eop, final_rdy_data, data_o[18], consume_data_line, consume_resp_line, src_rdy_int, dst_rdy_int} }; + +endmodule // gpif_rd diff --git a/fpga/usrp2/gpif/gpif_tb.v b/fpga/usrp2/gpif/gpif_tb.v new file mode 100644 index 000000000..686284c2b --- /dev/null +++ b/fpga/usrp2/gpif/gpif_tb.v @@ -0,0 +1,142 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o, data_splt; + wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + + initial $dumpfile("gpif_tb.vcd"); + initial $dumpvars(0,gpif_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + + assign dst_rdy_splt = 1; + + gpif_wr gpif_write + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(sys_clk), .sys_rst(sys_rst), + .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), + .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + + packet_reframer tx_packet_reframer + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .frames_per_packet(2), + .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy_splt & dst_rdy_splt) + begin + if(data_splt[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_splt); + if(data_splt[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + @(posedge gpif_clk); + + WR <= 1; + gpif_data <= 256; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + + while(DF) + @(posedge gpif_clk); + repeat (16) + @(posedge gpif_clk); + + WR <= 1; + repeat(256) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + + +/* + while(DF) + @(posedge gpif_clk); + + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + */ + end + end // initial begin + + initial #200000 $finish; + + +endmodule // gpif_tb diff --git a/fpga/usrp2/gpif/gpif_wr.v b/fpga/usrp2/gpif/gpif_wr.v new file mode 100644 index 000000000..89fae282e --- /dev/null +++ b/fpga/usrp2/gpif/gpif_wr.v @@ -0,0 +1,95 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_wr + (input gpif_clk, input gpif_rst, + input [15:0] gpif_data, input gpif_wr, input gpif_ep, + output reg gpif_full_d, output reg gpif_full_c, + + input sys_clk, input sys_rst, + output [18:0] data_o, output src_rdy_o, input dst_rdy_i, + output [18:0] ctrl_o, output ctrl_src_rdy_o, input ctrl_dst_rdy_i, + output [31:0] debug ); + + reg wr_reg, ep_reg; + reg [15:0] gpif_data_reg; + + always @(posedge gpif_clk) + begin + ep_reg <= gpif_ep; + wr_reg <= gpif_wr; + gpif_data_reg <= gpif_data; + end + + reg [9:0] write_count; + + always @(posedge gpif_clk) + if(gpif_rst) + write_count <= 0; + else if(wr_reg) + write_count <= write_count + 1; + else + write_count <= 0; + + reg sop; + wire eop = (write_count == 255); + wire eop_ctrl = (write_count == 15); + + always @(posedge gpif_clk) + sop <= gpif_wr & ~wr_reg; + + // Data Path + wire [15:0] fifo_space; + always @(posedge gpif_clk) + if(gpif_rst) + gpif_full_d <= 1; + else + gpif_full_d <= fifo_space < 256; + + wire [17:0] data_int; + wire src_rdy_int, dst_rdy_int; + + fifo_cascade #(.WIDTH(18), .SIZE(10)) wr_fifo + (.clk(gpif_clk), .reset(gpif_rst), .clear(0), + .datain({eop,sop,gpif_data_reg}), .src_rdy_i(~ep_reg & wr_reg & ~write_count[8]), .dst_rdy_o(), .space(fifo_space), + .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied()); + + fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) wr_fifo_2clk + (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(), + .rclk(sys_clk), .dataout(data_o[17:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), + .arst(sys_rst)); + assign data_o[18] = 1'b0; + + // Control Path + wire [15:0] ctrl_fifo_space; + always @(posedge gpif_clk) + if(gpif_rst) + gpif_full_c <= 1; + else + gpif_full_c <= ctrl_fifo_space < 16; + + fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk + (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop,gpif_data_reg}), + .src_rdy_i(ep_reg & wr_reg & ~write_count[4]), .dst_rdy_o(), .space(ctrl_fifo_space), + .rclk(sys_clk), .dataout(ctrl_o[18:0]), + .src_rdy_o(ctrl_src_rdy_o), .dst_rdy_i(ctrl_dst_rdy_i), .occupied(), + .arst(sys_rst)); + + assign debug = { 16'd0, ep_reg, wr_reg, eop, sop, (~ep_reg & wr_reg & ~write_count[8]), src_rdy_int, dst_rdy_int, write_count[8:0]}; + +endmodule // gpif_wr diff --git a/fpga/usrp2/gpif/gpif_wr_tb.v b/fpga/usrp2/gpif/gpif_wr_tb.v new file mode 100644 index 000000000..171bb96a1 --- /dev/null +++ b/fpga/usrp2/gpif/gpif_wr_tb.v @@ -0,0 +1,110 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module gpif_wr_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o; + wire src_rdy, dst_rdy; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + assign dst_rdy = 1; + + initial $dumpfile("gpif_wr_tb.vcd"); + initial $dumpvars(0,gpif_wr_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; + + gpif_wr gpif_write + (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), + .gpif_data(gpif_data), .gpif_wr(WR), .gpif_ep(EP), + .gpif_full_d(DF), .gpif_full_c(CF), + + .sys_clk(sys_clk), .sys_rst(sys_rst), + .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), + .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + + packet_reframer tx_packet_reframer + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy & dst_rdy) + begin + if(data_o[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_o); + if(data_o[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + WR <= 1; + gpif_data <= 10; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + end + end // initial begin + + initial #100000 $finish; + + +endmodule // gpif_wr_tb diff --git a/fpga/usrp2/gpif/packet_reframer.v b/fpga/usrp2/gpif/packet_reframer.v new file mode 100644 index 000000000..923d499ae --- /dev/null +++ b/fpga/usrp2/gpif/packet_reframer.v @@ -0,0 +1,79 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +// Join vita packets longer than one GPIF frame, drop padding on short frames + +module packet_reframer + (input clk, input reset, input clear, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i); + + reg [1:0] state; + reg [15:0] length; + + localparam RF_IDLE = 0; + localparam RF_PKT = 1; + localparam RF_DUMP = 2; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_i & dst_rdy_i) + case(state) + RF_IDLE : + begin + length <= {data_i[14:0],1'b0}; + state <= RF_PKT; + end + RF_PKT : + begin + if(length == 2) + if(data_i[17]) + state <= RF_IDLE; + else + state <= RF_DUMP; + else + length <= length - 1; + end + RF_DUMP : + if(data_i[17]) + state <= RF_IDLE; + default : + state<= RF_IDLE; + endcase // case (state) + + assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok + assign src_rdy_o = src_rdy_i & (state != RF_DUMP); + + wire occ_out = 0; + wire eof_out = (state == RF_PKT) & (length == 2); + wire sof_out = (state == RF_IDLE); + wire [15:0] data_out = data_i[15:0]; + assign data_o = {occ_out, eof_out, sof_out, data_out}; + + +endmodule // packet_reframer + + + + diff --git a/fpga/usrp2/gpif/packet_splitter.v b/fpga/usrp2/gpif/packet_splitter.v new file mode 100644 index 000000000..ba4c8cded --- /dev/null +++ b/fpga/usrp2/gpif/packet_splitter.v @@ -0,0 +1,123 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +// Split vita packets longer than one GPIF frame, add padding on short frames + +module packet_splitter + #(parameter FRAME_LEN=256) + (input clk, input reset, input clear, + input [7:0] frames_per_packet, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i, + output [31:0] debug0, + output [31:0] debug1); + + reg [1:0] state; + reg [15:0] length; + reg [15:0] frame_len; + reg [7:0] frame_count; + + localparam PS_IDLE = 0; + localparam PS_FRAME = 1; + localparam PS_NEW_FRAME = 2; + localparam PS_PAD = 3; + + wire eof_i = data_i[17]; + + always @(posedge clk) + if(reset | clear) + begin + state <= PS_IDLE; + frame_count <= 0; + end + else + case(state) + PS_IDLE : + if(src_rdy_i & dst_rdy_i) + begin + length <= { data_i[14:0],1'b0}; + frame_len <= FRAME_LEN; + state <= PS_FRAME; + frame_count <= 1; + end + PS_FRAME : + if(src_rdy_i & dst_rdy_i) + if((frame_len == 2) & ((length == 2) | eof_i)) + state <= PS_IDLE; + else if(frame_len == 2) + begin + length <= length - 1; + state <= PS_NEW_FRAME; + frame_count <= frame_count + 1; + end + else if((length == 2)|eof_i) + begin + frame_len <= frame_len - 1; + state <= PS_PAD; + end + else + begin + frame_len <= frame_len - 1; + length <= length - 1; + end + PS_NEW_FRAME : + if(src_rdy_i & dst_rdy_i) + begin + frame_len <= FRAME_LEN; + if((length == 2)|eof_i) + state <= PS_PAD; + else + begin + state <= PS_FRAME; + length <= length - 1; + end // else: !if((length == 2)|eof_i) + end // if (src_rdy_i & dst_rdy_i) + + PS_PAD : + if(dst_rdy_i) + if(frame_len == 2) + state <= PS_IDLE; + else + frame_len <= frame_len - 1; + + endcase // case (state) + + wire next_state_is_idle = dst_rdy_i & (frame_len==2) & + ( (state==PS_PAD) | ( (state==PS_FRAME) & src_rdy_i & ((length==2)|eof_i) ) ); + + + + + assign dst_rdy_o = dst_rdy_i & (state != PS_PAD); + assign src_rdy_o = src_rdy_i | (state == PS_PAD); + + wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME); + wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME); + wire occ_out = eof_out & next_state_is_idle & (frames_per_packet != frame_count); + + wire [15:0] data_out = data_i[15:0]; + assign data_o = {occ_out, eof_out, sof_out, data_out}; + + assign debug0 = { 8'd0, dst_rdy_o, src_rdy_o, next_state_is_idle, eof_out, sof_out, occ_out, state[1:0], frame_count[7:0], frames_per_packet[7:0] }; + assign debug1 = { length[15:0], frame_len[15:0] }; + +endmodule // packet_splitter diff --git a/fpga/usrp2/gpif/packet_splitter_tb.v b/fpga/usrp2/gpif/packet_splitter_tb.v new file mode 100644 index 000000000..329b58e0d --- /dev/null +++ b/fpga/usrp2/gpif/packet_splitter_tb.v @@ -0,0 +1,137 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + +module packet_splitter_tb(); + + reg sys_clk = 0; + reg sys_rst = 1; + reg gpif_clk = 0; + reg gpif_rst = 1; + + reg [15:0] gpif_data; + reg WR = 0, EP = 0; + + wire CF, DF; + + wire gpif_full_d, gpif_full_c; + wire [18:0] data_o, ctrl_o, data_splt; + wire src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt; + wire ctrl_src_rdy, ctrl_dst_rdy; + + assign ctrl_dst_rdy = 1; + + initial $dumpfile("packet_splitter_tb.vcd"); + initial $dumpvars(0,packet_splitter_tb); + + initial #1000 gpif_rst = 0; + initial #1000 sys_rst = 0; + always #64 gpif_clk <= ~gpif_clk; + always #47.9 sys_clk <= ~sys_clk; + + wire [35:0] data_int; + wire src_rdy_int, dst_rdy_int; + + assign dst_rdy_splt = 1; + + vita_pkt_gen vita_pkt_gen + (.clk(sys_clk), .reset(sys_rst) , .clear(0), + .len(512),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int)); + + fifo36_to_fifo19 #(.LE(1)) f36_to_f19 + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int), + .f19_dataout(data_o), .f19_src_rdy_o(src_rdy), .f19_dst_rdy_i(dst_rdy)); + + packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .frames_per_packet(4), + .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy), + .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt)); + + always @(posedge sys_clk) + if(ctrl_src_rdy & ctrl_dst_rdy) + $display("CTRL: %x",ctrl_o); + + always @(posedge sys_clk) + if(src_rdy_splt & dst_rdy_splt) + begin + if(data_splt[16]) + $display("<-------- DATA SOF--------->"); + $display("DATA: %x",data_splt); + if(data_splt[17]) + $display("<-------- DATA EOF--------->"); + end + + initial + begin + #10000; + repeat (1) + begin + @(posedge gpif_clk); + + WR <= 1; + gpif_data <= 256; // Length + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data + 1; + @(posedge gpif_clk); + end + WR <= 0; + + while(DF) + @(posedge gpif_clk); + repeat (16) + @(posedge gpif_clk); + + WR <= 1; + repeat(256) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + + +/* + while(DF) + @(posedge gpif_clk); + + repeat (20) + @(posedge gpif_clk); + WR <= 1; + gpif_data <= 16'h5; + @(posedge gpif_clk); + gpif_data <= 16'h00; + @(posedge gpif_clk); + repeat(254) + begin + gpif_data <= gpif_data - 1; + @(posedge gpif_clk); + end + WR <= 0; + */ + end + end // initial begin + + initial #200000 $finish; + + +endmodule // packet_splitter_tb diff --git a/fpga/usrp2/gpmc/dbsm.v b/fpga/usrp2/gpmc/dbsm.v index 530af7205..1ee250738 100644 --- a/fpga/usrp2/gpmc/dbsm.v +++ b/fpga/usrp2/gpmc/dbsm.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module bsm (input clk, input reset, input clear, diff --git a/fpga/usrp2/gpmc/edge_sync.v b/fpga/usrp2/gpmc/edge_sync.v index 5d9417c08..74f1a2f1c 100644 --- a/fpga/usrp2/gpmc/edge_sync.v +++ b/fpga/usrp2/gpmc/edge_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module edge_sync diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v index 9a8e37ce9..bb4c58ec4 100644 --- a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v +++ b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo_to_gpmc_async (input clk, input reset, input clear, diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v index ef59d7137..9da9caf86 100644 --- a/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v +++ b/fpga/usrp2/gpmc/fifo_to_gpmc_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Assumes a GPMC cycle with GPMC clock, as in the timing diagrams // If a packet bigger or smaller than we are told is sent, behavior is undefined. diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v index fe4e35de3..b139f5143 100644 --- a/fpga/usrp2/gpmc/fifo_watcher.v +++ b/fpga/usrp2/gpmc/fifo_watcher.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module fifo_watcher diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v index 02bf45b8a..c0bec683a 100644 --- a/fpga/usrp2/gpmc/gpmc_async.v +++ b/fpga/usrp2/gpmc/gpmc_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + ////////////////////////////////////////////////////////////////////////////////// module gpmc_async diff --git a/fpga/usrp2/gpmc/gpmc_sync.v b/fpga/usrp2/gpmc/gpmc_sync.v index 61c54a793..ba7251c8d 100644 --- a/fpga/usrp2/gpmc/gpmc_sync.v +++ b/fpga/usrp2/gpmc/gpmc_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + ////////////////////////////////////////////////////////////////////////////////// module gpmc_sync diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_async.v b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v index 55c0cef50..aa93e52af 100644 --- a/fpga/usrp2/gpmc/gpmc_to_fifo_async.v +++ b/fpga/usrp2/gpmc/gpmc_to_fifo_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module gpmc_to_fifo_async (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE, diff --git a/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v index 688de0e17..7ff7afdc2 100644 --- a/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v +++ b/fpga/usrp2/gpmc/gpmc_to_fifo_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Assumes a GPMC cycle with GPMC clock, as in the timing diagrams // If a packet bigger or smaller than we are told is sent, behavior is undefined. diff --git a/fpga/usrp2/gpmc/gpmc_wb.v b/fpga/usrp2/gpmc/gpmc_wb.v index db6fbc6e9..645201ef7 100644 --- a/fpga/usrp2/gpmc/gpmc_wb.v +++ b/fpga/usrp2/gpmc/gpmc_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module gpmc_wb diff --git a/fpga/usrp2/gpmc/ram_to_fifo.v b/fpga/usrp2/gpmc/ram_to_fifo.v index 8549dcc35..958c88b0f 100644 --- a/fpga/usrp2/gpmc/ram_to_fifo.v +++ b/fpga/usrp2/gpmc/ram_to_fifo.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ram_to_fifo diff --git a/fpga/usrp2/models/CY7C1356C/cy1356.v b/fpga/usrp2/models/CY7C1356C/cy1356.v index 9197eea6d..ab7ace610 100644 --- a/fpga/usrp2/models/CY7C1356C/cy1356.v +++ b/fpga/usrp2/models/CY7C1356C/cy1356.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `define sb200
//************************************************************************
//************************************************************************
diff --git a/fpga/usrp2/models/CY7C1356C/testbench.v b/fpga/usrp2/models/CY7C1356C/testbench.v index 5dde89e6c..01e0cbe00 100644 --- a/fpga/usrp2/models/CY7C1356C/testbench.v +++ b/fpga/usrp2/models/CY7C1356C/testbench.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 10ps
diff --git a/fpga/usrp2/models/FIFO_GENERATOR_V6_1.v b/fpga/usrp2/models/FIFO_GENERATOR_V6_1.v new file mode 100644 index 000000000..65bbac447 --- /dev/null +++ b/fpga/usrp2/models/FIFO_GENERATOR_V6_1.v @@ -0,0 +1,4575 @@ +/* + ******************************************************************************* + * + * FIFO Generator - Verilog Behavioral Model + * + ******************************************************************************* + * + * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. + * + * This file contains confidential and proprietary information + * of Xilinx, Inc. and is protected under U.S. and + * international copyright and other intellectual property + * laws. + * + * DISCLAIMER + * This disclaimer is not a license and does not grant any + * rights to the materials distributed herewith. Except as + * otherwise provided in a valid license issued to you by + * Xilinx, and to the maximum extent permitted by applicable + * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND + * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES + * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING + * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- + * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and + * (2) Xilinx shall not be liable (whether in contract or tort, + * including negligence, or under any other theory of + * liability) for any loss or damage of any kind or nature + * related to, arising under or in connection with these + * materials, including for any direct, or any indirect, + * special, incidental, or consequential loss or damage + * (including loss of data, profits, goodwill, or any type of + * loss or damage suffered as a result of any action brought + * by a third party) even if such damage or loss was + * reasonably foreseeable or Xilinx had been advised of the + * possibility of the same. + * + * CRITICAL APPLICATIONS + * Xilinx products are not designed or intended to be fail- + * safe, or for use in any application requiring fail-safe + * performance, such as life-support or safety devices or + * systems, Class III medical devices, nuclear facilities, + * applications related to the deployment of airbags, or any + * other applications that could lead to death, personal + * injury, or severe property or environmental damage + * (individually and collectively, "Critical + * Applications"). Customer assumes the sole risk and + * liability of any use of Xilinx products in Critical + * Applications, subject only to applicable laws and + * regulations governing limitations on product liability. + * + * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS + * PART OF THIS FILE AT ALL TIMES. + * + ******************************************************************************* + ******************************************************************************* + * + * Filename: FIFO_GENERATOR_V6_1.v + * + * Author : Xilinx + * + ******************************************************************************* + * Structure: + * + * fifo_generator_v6_1.vhd + * | + * +-fifo_generator_v6_1_bhv_ver_as + * | + * +-fifo_generator_v6_1_bhv_ver_ss + * | + * +-fifo_generator_v6_1_bhv_ver_preload0 + * + ******************************************************************************* + * Description: + * + * The Verilog behavioral model for the FIFO Generator. + * + * The behavioral model has three parts: + * - The behavioral model for independent clocks FIFOs (_as) + * - The behavioral model for common clock FIFOs (_ss) + * - The "preload logic" block which implements First-word Fall-through + * + ******************************************************************************* + * Description: + * The verilog behavioral model for the FIFO generator core. + * + ******************************************************************************* + */ + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module FIFO_GENERATOR_V6_1 + #( + parameter C_COMMON_CLOCK = 0, + parameter C_COUNT_TYPE = 0, + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DEFAULT_VALUE = "", + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_ENABLE_RLOCS = 0, + parameter C_FAMILY = "virtex6", //Not allowed in Verilog model + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_BACKUP = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_INT_CLK = 0, + parameter C_HAS_MEMINIT_FILE = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RD_RST = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_HAS_WR_RST = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_INIT_WR_PNTR_VAL = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_MIF_FILE_NAME = "", + parameter C_OPTIMIZATION_MODE = 0, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PRIM_FIFO_TYPE = "", + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_FREQ = 1, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_ECC = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FIFO16_FLAGS = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_FREQ = 1, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_WR_RESPONSE_LATENCY = 1, + parameter C_MSGON_VAL = 1, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + ( + input BACKUP, + input BACKUP_MARKER, + input CLK, + input RST, + input SRST, + input WR_CLK, + input WR_RST, + input RD_CLK, + input RD_RST, + input [C_DIN_WIDTH-1:0] DIN, + input WR_EN, + input RD_EN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input INT_CLK, + input INJECTDBITERR, + input INJECTSBITERR, + + output [C_DOUT_WIDTH-1:0] DOUT, + output FULL, + output ALMOST_FULL, + output WR_ACK, + output OVERFLOW, + output EMPTY, + output ALMOST_EMPTY, + output VALID, + output UNDERFLOW, + output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output PROG_FULL, + output PROG_EMPTY, + output SBITERR, + output DBITERR + ); + +/* + ****************************************************************************** + * Definition of Parameters + ****************************************************************************** + * C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) + * C_COUNT_TYPE : *not used + * C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus + * C_DEFAULT_VALUE : *not used + * C_DIN_WIDTH : Width of DIN bus + * C_DOUT_RST_VAL : Reset value of DOUT + * C_DOUT_WIDTH : Width of DOUT bus + * C_ENABLE_RLOCS : *not used + * C_FAMILY : not used in bhv model + * C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) + * C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag + * C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag + * C_HAS_BACKUP : *not used + * C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus + * C_HAS_INT_CLK : not used in bhv model + * C_HAS_MEMINIT_FILE : *not used + * C_HAS_OVERFLOW : 1=Core has OVERFLOW flag + * C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus + * C_HAS_RD_RST : *not used + * C_HAS_RST : 1=Core has Async Rst + * C_HAS_SRST : 1=Core has Sync Rst + * C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag + * C_HAS_VALID : 1=Core has VALID flag + * C_HAS_WR_ACK : 1=Core has WR_ACK flag + * C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus + * C_HAS_WR_RST : *not used + * C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram + * 1=Common-Clock ShiftRam + * 2=Indep. Clocks Bram/Dram + * 3=Virtex-4 Built-in + * 4=Virtex-5 Built-in + * C_INIT_WR_PNTR_VAL : *not used + * C_MEMORY_TYPE : 1=Block RAM + * 2=Distributed RAM + * 3=Shift RAM + * 4=Built-in FIFO + * C_MIF_FILE_NAME : *not used + * C_OPTIMIZATION_MODE : *not used + * C_OVERFLOW_LOW : 1=OVERFLOW active low + * C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 + * C_PRELOAD_REGS : 1=Use output registers + * C_PRIM_FIFO_TYPE : not used in bhv model + * C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold + * C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold + * C_PROG_EMPTY_TYPE : 0=No programmable empty + * 1=Single prog empty thresh constant + * 2=Multiple prog empty thresh constants + * 3=Single prog empty thresh input + * 4=Multiple prog empty thresh inputs + * C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold + * C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold + * C_PROG_FULL_TYPE : 0=No prog full + * 1=Single prog full thresh constant + * 2=Multiple prog full thresh constants + * 3=Single prog full thresh input + * 4=Multiple prog full thresh inputs + * C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus + * C_RD_DEPTH : Depth of read interface (2^N) + * C_RD_FREQ : not used in bhv model + * C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) + * C_UNDERFLOW_LOW : 1=UNDERFLOW active low + * C_USE_DOUT_RST : 1=Resets DOUT on RST + * C_USE_ECC : Used for error injection purpose + * C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register + * C_USE_FIFO16_FLAGS : not used in bhv model + * C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count + * C_VALID_LOW : 1=VALID active low + * C_WR_ACK_LOW : 1=WR_ACK active low + * C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus + * C_WR_DEPTH : Depth of write interface (2^N) + * C_WR_FREQ : not used in bhv model + * C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) + * C_WR_RESPONSE_LATENCY : *not used + * C_MSGON_VAL : *not used by bhv model + * C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST + * 1 = Use RST + * C_ERROR_INJECTION_TYPE : 0 = No error injection + * 1 = Single bit error injection only + * 2 = Double bit error injection only + * 3 = Single and double bit error injection + ****************************************************************************** + * Definition of Ports + ****************************************************************************** + * BACKUP : Not used + * BACKUP_MARKER: Not used + * CLK : Clock + * DIN : Input data bus + * PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag + * PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag + * PROG_FULL_THRESH : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag + * PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag + * RD_CLK : Read Domain Clock + * RD_EN : Read enable + * RD_RST : Read Reset + * RST : Asynchronous Reset + * SRST : Synchronous Reset + * WR_CLK : Write Domain Clock + * WR_EN : Write enable + * WR_RST : Write Reset + * INT_CLK : Internal Clock + * INJECTSBITERR: Inject Signle bit error + * INJECTDBITERR: Inject Double bit error + * ALMOST_EMPTY : One word remaining in FIFO + * ALMOST_FULL : One empty space remaining in FIFO + * DATA_COUNT : Number of data words in fifo( synchronous to CLK) + * DOUT : Output data bus + * EMPTY : Empty flag + * FULL : Full flag + * OVERFLOW : Last write rejected + * PROG_EMPTY : Programmable Empty Flag + * PROG_FULL : Programmable Full Flag + * RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) + * UNDERFLOW : Last read rejected + * VALID : Last read acknowledged, DOUT bus VALID + * WR_ACK : Last write acknowledged + * WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) + * SBITERR : Single Bit ECC Error Detected + * DBITERR : Double Bit ECC Error Detected + ****************************************************************************** + */ + + + /***************************************************************************** + * Derived parameters + ****************************************************************************/ + //There are 2 Verilog behavioral models + // 0 = Common-Clock FIFO/ShiftRam FIFO + // 1 = Independent Clocks FIFO + parameter C_VERILOG_IMPL = (C_IMPLEMENTATION_TYPE == 2) ? 1 : 0; + + //Internal reset signals + reg rd_rst_asreg = 0; + reg rd_rst_asreg_d1 = 0; + reg rd_rst_asreg_d2 = 0; + reg rd_rst_reg = 0; + wire rd_rst_comb; + reg rd_rst_d1 = 0; + reg wr_rst_asreg = 0; + reg wr_rst_asreg_d1 = 0; + reg wr_rst_asreg_d2 = 0; + reg wr_rst_reg = 0; + wire wr_rst_comb; + wire wr_rst_i; + wire rd_rst_i; + wire rst_i; + + //Internal reset signals + reg rst_asreg = 0; + reg rst_asreg_d1 = 0; + reg rst_asreg_d2 = 0; + reg rst_reg = 0; + wire rst_comb; + wire rst_full_gen_i; + wire rst_full_ff_i; + + wire RD_CLK_P0_IN; + wire RST_P0_IN; + wire RD_EN_FIFO_IN; + wire RD_EN_P0_IN; + + wire ALMOST_EMPTY_FIFO_OUT; + wire ALMOST_FULL_FIFO_OUT; + wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT; + wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT; + wire EMPTY_FIFO_OUT; + wire FULL_FIFO_OUT; + wire OVERFLOW_FIFO_OUT; + wire PROG_EMPTY_FIFO_OUT; + wire PROG_FULL_FIFO_OUT; + wire VALID_FIFO_OUT; + wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT; + wire UNDERFLOW_FIFO_OUT; + wire WR_ACK_FIFO_OUT; + wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT; + + + //*************************************************************************** + // Internal Signals + // The core uses either the internal_ wires or the preload0_ wires depending + // on whether the core uses Preload0 or not. + // When using preload0, the internal signals connect the internal core to + // the preload logic, and the external core's interfaces are tied to the + // preload0 signals from the preload logic. + //*************************************************************************** + wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT; + wire VALID_P0_OUT; + wire EMPTY_P0_OUT; + wire ALMOSTEMPTY_P0_OUT; + reg EMPTY_P0_OUT_Q; + reg ALMOSTEMPTY_P0_OUT_Q; + wire UNDERFLOW_P0_OUT; + wire RDEN_P0_OUT; + wire [C_DOUT_WIDTH-1:0] DATA_P0_IN; + wire EMPTY_P0_IN; + reg [31:0] DATA_COUNT_FWFT; + reg SS_FWFT_WR ; + reg SS_FWFT_RD ; + + wire sbiterr_fifo_out; + wire dbiterr_fifo_out; + + // Assign 0 if not selected to avoid 'X' propogation to S/DBITERR. + assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTSBITERR : 0; + assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ? + INJECTDBITERR : 0; + + +// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL +// parameter (1=Independent Clocks, 0=Common Clock) + + localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL; +generate +case (C_VERILOG_IMPL) +0 : begin : block1 + //Common Clock Behavioral Model + fifo_generator_v6_1_bhv_ver_ss + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, +// C_FULL_FLAGS_RST_VAL, + FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_SRST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_ss + ( + .CLK (CLK), + .RST (rst_i), + .SRST (SRST), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .DATA_COUNT (DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end +1 : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +default : begin : block1 + //Independent Clocks Behavioral Model + fifo_generator_v6_1_bhv_ver_as + #( + C_DATA_COUNT_WIDTH, + C_DIN_WIDTH, + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_FULL_FLAGS_RST_VAL, + C_HAS_ALMOST_EMPTY, + C_HAS_ALMOST_FULL, + C_HAS_DATA_COUNT, + C_HAS_OVERFLOW, + C_HAS_RD_DATA_COUNT, + C_HAS_RST, + C_HAS_UNDERFLOW, + C_HAS_VALID, + C_HAS_WR_ACK, + C_HAS_WR_DATA_COUNT, + C_IMPLEMENTATION_TYPE, + C_MEMORY_TYPE, + C_OVERFLOW_LOW, + C_PRELOAD_LATENCY, + C_PRELOAD_REGS, + C_PROG_EMPTY_THRESH_ASSERT_VAL, + C_PROG_EMPTY_THRESH_NEGATE_VAL, + C_PROG_EMPTY_TYPE, + C_PROG_FULL_THRESH_ASSERT_VAL, + C_PROG_FULL_THRESH_NEGATE_VAL, + C_PROG_FULL_TYPE, + C_RD_DATA_COUNT_WIDTH, + C_RD_DEPTH, + C_RD_PNTR_WIDTH, + C_UNDERFLOW_LOW, + C_USE_DOUT_RST, + C_USE_EMBEDDED_REG, + C_USE_FWFT_DATA_COUNT, + C_VALID_LOW, + C_WR_ACK_LOW, + C_WR_DATA_COUNT_WIDTH, + C_WR_DEPTH, + C_WR_PNTR_WIDTH, + C_USE_ECC, + C_ENABLE_RST_SYNC, + C_ERROR_INJECTION_TYPE + ) + gen_as + ( + .WR_CLK (WR_CLK), + .RD_CLK (RD_CLK), + .RST (rst_i), + .RST_FULL_GEN (rst_full_gen_i), + .RST_FULL_FF (rst_full_ff_i), + .WR_RST (wr_rst_i), + .RD_RST (rd_rst_i), + .DIN (DIN), + .WR_EN (WR_EN), + .RD_EN (RD_EN_FIFO_IN), + .RD_EN_USER (RD_EN), + .PROG_EMPTY_THRESH (PROG_EMPTY_THRESH), + .PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT), + .PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE), + .PROG_FULL_THRESH (PROG_FULL_THRESH), + .PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT), + .PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE), + .INJECTSBITERR (inject_sbit_err), + .INJECTDBITERR (inject_dbit_err), + .USER_EMPTY_FB (EMPTY_P0_OUT), + .DOUT (DOUT_FIFO_OUT), + .FULL (FULL_FIFO_OUT), + .ALMOST_FULL (ALMOST_FULL_FIFO_OUT), + .WR_ACK (WR_ACK_FIFO_OUT), + .OVERFLOW (OVERFLOW_FIFO_OUT), + .EMPTY (EMPTY_FIFO_OUT), + .ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT), + .VALID (VALID_FIFO_OUT), + .UNDERFLOW (UNDERFLOW_FIFO_OUT), + .RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT), + .WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT), + .PROG_FULL (PROG_FULL_FIFO_OUT), + .PROG_EMPTY (PROG_EMPTY_FIFO_OUT), + .SBITERR (sbiterr_fifo_out), + .DBITERR (dbiterr_fifo_out) + ); +end + +endcase +endgenerate + + + //************************************************************************** + // Connect Internal Signals + // (Signals labeled internal_*) + // In the normal case, these signals tie directly to the FIFO's inputs and + // outputs. + // In the case of Preload Latency 0 or 1, there are intermediate + // signals between the internal FIFO and the preload logic. + //************************************************************************** + + + //*********************************************** + // If First-Word Fall-Through, instantiate + // the preload0 (FWFT) module + //*********************************************** + generate + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin : block2 + + + fifo_generator_v6_1_bhv_ver_preload0 + #( + C_DOUT_RST_VAL, + C_DOUT_WIDTH, + C_HAS_RST, + C_ENABLE_RST_SYNC, + C_HAS_SRST, + C_USE_DOUT_RST, + C_USE_ECC, + C_VALID_LOW, + C_UNDERFLOW_LOW, + C_MEMORY_TYPE + ) + fgpl0 + ( + .RD_CLK (RD_CLK_P0_IN), + .RD_RST (RST_P0_IN), + .SRST (SRST), + .RD_EN (RD_EN_P0_IN), + .FIFOEMPTY (EMPTY_P0_IN), + .FIFODATA (DATA_P0_IN), + .FIFOSBITERR (sbiterr_fifo_out), + .FIFODBITERR (dbiterr_fifo_out), + .USERDATA (DATA_P0_OUT), + .USERVALID (VALID_P0_OUT), + .USEREMPTY (EMPTY_P0_OUT), + .USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT), + .USERUNDERFLOW (UNDERFLOW_P0_OUT), + .RAMVALID (RAMVALID_P0_OUT), + .FIFORDEN (RDEN_P0_OUT), + .USERSBITERR (SBITERR), + .USERDBITERR (DBITERR) + ); + + + //*********************************************** + // Connect inputs to preload (FWFT) module + //*********************************************** + //Connect the RD_CLK of the Preload (FWFT) module to CLK if we + // have a common-clock FIFO, or RD_CLK if we have an + // independent clock FIFO + assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK); + assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0; + assign RD_EN_P0_IN = RD_EN; + assign EMPTY_P0_IN = EMPTY_FIFO_OUT; + assign DATA_P0_IN = DOUT_FIFO_OUT; + + //*********************************************** + // Connect outputs from preload (FWFT) module + //*********************************************** + assign DOUT = DATA_P0_OUT; + assign VALID = VALID_P0_OUT ; + assign EMPTY = EMPTY_P0_OUT; + assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT; + assign UNDERFLOW = UNDERFLOW_P0_OUT ; + + assign RD_EN_FIFO_IN = RDEN_P0_OUT; + + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT: + (C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] : + DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1]; + + //*********************************************** + // Create DATA_COUNT from First-Word Fall-Through + // data count + //*********************************************** + always @ (posedge RD_CLK or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + EMPTY_P0_OUT_Q <= #`TCQ 1; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1; + end else begin + EMPTY_P0_OUT_Q <= #`TCQ EMPTY_P0_OUT; + ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT; + end + end //always + + + //*********************************************** + // logic for common-clock data count when FWFT is selected + //*********************************************** + initial begin + SS_FWFT_RD = 1'b0; + DATA_COUNT_FWFT = 0 ; + SS_FWFT_WR = 1'b0 ; + end //initial + + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter. SS_FWFT_WR and SS_FWFT_RD + // are the up/down enables for the counter. + //*********************************************** + always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT) begin + if (C_VALID_LOW == 1) begin + SS_FWFT_RD = RD_EN && ~VALID_P0_OUT ; + end else begin + SS_FWFT_RD = RD_EN && VALID_P0_OUT ; + end + SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ; + end + + //*********************************************** + // common-clock data count is implemented as an + // up-down counter for FWFT. This always block + // calculates the counter. + //*********************************************** + always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin + if (RST_P0_IN) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + if (SRST && (C_HAS_SRST == 1) ) begin + DATA_COUNT_FWFT <= #`TCQ 0; + end else begin + case ( {SS_FWFT_WR, SS_FWFT_RD}) + 2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + 2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ; + 2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ; + 2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ; + endcase + end //if SRST + end //IF RST + end //always + + + end else begin : block2 //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + //*********************************************** + // If NOT First-Word Fall-Through, wire the outputs + // of the internal _ss or _as FIFO directly to the + // output, and do not instantiate the preload0 + // module. + //*********************************************** + + assign RD_CLK_P0_IN = 0; + assign RST_P0_IN = 0; + assign RD_EN_P0_IN = 0; + + assign RD_EN_FIFO_IN = RD_EN; + + assign DOUT = DOUT_FIFO_OUT; + assign DATA_P0_IN = 0; + assign VALID = VALID_FIFO_OUT; + assign EMPTY = EMPTY_FIFO_OUT; + assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT; + assign EMPTY_P0_IN = 0; + assign UNDERFLOW = UNDERFLOW_FIFO_OUT; + assign DATA_COUNT = DATA_COUNT_FIFO_OUT; + assign SBITERR = sbiterr_fifo_out; + assign DBITERR = dbiterr_fifo_out; + + end //if !(C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + endgenerate + + + //*********************************************** + // Connect user flags to internal signals + //*********************************************** + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT); + end //block3 + endgenerate + + //If we are using extra logic for the FWFT data count, then override the + //RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY. + //Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY. + generate + if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30 + assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT); + end //block30 + endgenerate + + //If we are not using extra logic for the FWFT data count, + //then connect RD_DATA_COUNT to the RD_DATA_COUNT from the + //internal FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31 + assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT; + end + endgenerate + + //Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal + //FIFO instance + generate + if (C_USE_FWFT_DATA_COUNT==1) begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + else begin : block4 + assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT; + end + endgenerate + + + //Connect other flags to the internal FIFO instance + assign FULL = FULL_FIFO_OUT; + assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT; + assign WR_ACK = WR_ACK_FIFO_OUT; + assign OVERFLOW = OVERFLOW_FIFO_OUT; + assign PROG_FULL = PROG_FULL_FIFO_OUT; + assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT; + + + // if an asynchronous FIFO has been selected, display a message that the FIFO + // will not be cycle-accurate in simulation + initial begin + if (C_IMPLEMENTATION_TYPE == 2) begin + $display("WARNING: Behavioral models for independent clock FIFO configurations are not cycle-accurate. You may wish to choose the structural simulation model instead of the behavioral model. This will ensure accurate behavior and latencies during simulation. You can enable this from CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + end else if (C_MEMORY_TYPE == 4) begin + $display("FAILURE : Behavioral models for Virtex-4, Virtex-5 and Virtex-6 built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information."); + $finish; + end + end //initial + + /************************************************************************** + * Internal reset logic + **************************************************************************/ + assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0; + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0; + assign rst_i = C_HAS_RST ? rst_reg : 0; + + wire rst_2_sync; + wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK; + generate + if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync + always @* begin + wr_rst_reg <= WR_RST; + rd_rst_reg <= RD_RST; + rst_reg <= 1'b0; + end + assign rst_2_sync = WR_RST; + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : gic_rst + assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg; + assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg; + assign rst_2_sync = RST; + + always @(posedge WR_CLK or posedge RST) begin + if (RST == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b1; + end else begin + if (wr_rst_asreg_d1 == 1'b1) begin + wr_rst_asreg <= #`TCQ 1'b0; + end else begin + wr_rst_asreg <= #`TCQ wr_rst_asreg; + end + end + end + + always @(posedge WR_CLK) begin + wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg; + wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1; + end + + always @(posedge WR_CLK or posedge wr_rst_comb) begin + if (wr_rst_comb == 1'b1) begin + wr_rst_reg <= #`TCQ 1'b1; + end else begin + wr_rst_reg <= #`TCQ 1'b0; + end + end + + always @(posedge RD_CLK or posedge RST) begin + if (RST == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b1; + end else begin + if (rd_rst_asreg_d1 == 1'b1) begin + rd_rst_asreg <= #`TCQ 1'b0; + end else begin + rd_rst_asreg <= #`TCQ rd_rst_asreg; + end + end + end + + always @(posedge RD_CLK) begin + rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg; + rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1; + end + + always @(posedge RD_CLK or posedge rd_rst_comb) begin + if (rd_rst_comb == 1'b1) begin + rd_rst_reg <= #`TCQ 1'b1; + end else begin + rd_rst_reg <= #`TCQ 1'b0; + end + end + end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : gcc_rst + assign rst_comb = !rst_asreg_d2 && rst_asreg; + assign rst_2_sync = RST; + + always @(posedge CLK or posedge RST) begin + if (RST == 1'b1) begin + rst_asreg <= #`TCQ 1'b1; + end else begin + if (rst_asreg_d1 == 1'b1) begin + rst_asreg <= #`TCQ 1'b0; + end else begin + rst_asreg <= #`TCQ rst_asreg; + end + end + end + + always @(posedge CLK) begin + rst_asreg_d1 <= #`TCQ rst_asreg; + rst_asreg_d2 <= #`TCQ rst_asreg_d1; + end + + always @(posedge CLK or posedge rst_comb) begin + if (rst_comb == 1'b1) begin + rst_reg <= #`TCQ 1'b1; + end else begin + rst_reg <= #`TCQ 1'b0; + end + end + end + endgenerate + + reg rst_d1 = 1'b0; + reg rst_d2 = 1'b0; + reg rst_d3 = 1'b0; + reg rst_d4 = 1'b0; + generate + if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1 + // RST_FULL_GEN replaces the reset falling edge detection used to de-assert + // FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. + + // RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & + // PROG_FULL + + always @ (posedge rst_2_sync or posedge clk_2_sync) begin + if (rst_2_sync) begin + rst_d1 <= 1'b1; + rst_d2 <= 1'b1; + rst_d3 <= 1'b1; + rst_d4 <= 1'b0; + end else begin + if (SRST) begin + rst_d1 <= #`TCQ 1'b1; + rst_d2 <= #`TCQ 1'b1; + rst_d3 <= #`TCQ 1'b1; + rst_d4 <= #`TCQ 1'b0; + end else begin + rst_d1 <= #`TCQ 1'b0; + rst_d2 <= #`TCQ rst_d1; + rst_d3 <= #`TCQ rst_d2; + rst_d4 <= #`TCQ rst_d3; + end + end + end + assign rst_full_ff_i = (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ; + assign rst_full_gen_i = rst_d4; + + end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full + assign rst_full_gen_i = 1'b0; + assign rst_full_ff_i = (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i; + end + endgenerate + +endmodule //FIFO_GENERATOR_V6_1 + + + +/******************************************************************************* + * Declaration of Independent-Clocks FIFO Module + ******************************************************************************/ +module fifo_generator_v6_1_bhv_ver_as + + /*************************************************************************** + * Declare user parameters and their defaults + ***************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /*************************************************************************** + * Declare Input and Output Ports + ***************************************************************************/ + ( + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_CLK, + input RD_EN, + input RD_EN_USER, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input WR_RST, + input RD_RST, + input WR_CLK, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + input USER_EMPTY_FB, + output reg ALMOST_EMPTY = 1'b1, + output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL, + output [C_DOUT_WIDTH-1:0] DOUT, + output reg EMPTY = 1'b1, + output reg FULL = C_FULL_FLAGS_RST_VAL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT, + output UNDERFLOW, + output WR_ACK, + output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT, + output SBITERR, + output DBITERR + ); + + reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0; + reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0; + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + parameter C_DEPTH_RATIO_WR = + (C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1; + parameter C_DEPTH_RATIO_RD = + (C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH - 1; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH - 1; + + // C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC + // -----------------|------------------|-----------------|--------------- + // 1 | 8 | C_RD_PNTR_WIDTH | 2 + // 1 | 4 | C_RD_PNTR_WIDTH | 2 + // 1 | 2 | C_RD_PNTR_WIDTH | 2 + // 1 | 1 | C_WR_PNTR_WIDTH | 2 + // 2 | 1 | C_WR_PNTR_WIDTH | 4 + // 4 | 1 | C_WR_PNTR_WIDTH | 8 + // 8 | 1 | C_WR_PNTR_WIDTH | 16 + + localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH; + wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD); + + parameter [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH; + + parameter [31:0] log2_reads_per_write = log2_val(reads_per_write); + + parameter [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH; + + parameter [31:0] log2_writes_per_read = log2_val(writes_per_read); + + + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK + // domain. + //num_wr_bits is calculated by considering the total words in the FIFO, + // and the state of the read pointer (which may not have yet crossed clock + // domains.) + //num_rd_bits is calculated by considering the total words in the FIFO, + // and the state of the write pointer (which may not have yet crossed clock + // domains.) + reg [31:0] num_wr_bits; + reg [31:0] num_rd_bits; + reg [31:0] next_num_wr_bits; + reg [31:0] next_num_rd_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0; + wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd; + reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0; + wire wr_rst_i = WR_RST; + reg wr_rst_d1 =0; + + //The read pointer - tracks read operations + // (rd_ptr Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value. + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0; + wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr; + reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0; + wire rd_rst_i = RD_RST; + wire ram_rd_en; + reg ram_rd_en_d1 = 1'b0; + + + // Delayed ram_rd_en is needed only for STD Embedded register option + generate + if (C_PRELOAD_LATENCY == 2) begin : grd_d + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + ram_rd_en_d1 <= #`TCQ 1'b0; + else + ram_rd_en_d1 <= #`TCQ ram_rd_en; + end + end + endgenerate + + // Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0; + end else begin : rdl // Read depth lesser than or equal to write depth + assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + endgenerate + + // Generate Empty and Almost Empty + // ram_rd_en used to determine EMPTY should depend on the EMPTY. + assign ram_rd_en = RD_EN & !EMPTY; + assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1)))); + assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2)))); + + // Register Empty and Almost Empty + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin + EMPTY <= #`TCQ 1'b1; + ALMOST_EMPTY <= #`TCQ 1'b1; + rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH-1{1'b0}}; + end else begin + rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0}; + + if (empty_int) + EMPTY <= #`TCQ 1'b1; + else + EMPTY <= #`TCQ 1'b0; + + if (!EMPTY) begin + if (almost_empty_int) + ALMOST_EMPTY <= #`TCQ 1'b1; + else + ALMOST_EMPTY <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + + // Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation + generate + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0; + end else begin : wdl // Write depth lesser than or equal to read depth + assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end + endgenerate + + // Generate FULL and ALMOST_FULL + // ram_wr_en used to determine FULL should depend on the FULL. + assign ram_wr_en = WR_EN & !FULL; + assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2)))); + assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3)))); + + // Register FULL and ALMOST_FULL Empty + always @ (posedge WR_CLK or posedge RST_FULL_FF) + begin + if (RST_FULL_FF) begin + FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL; + wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end else begin + wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0}; + if (full_int) begin + FULL <= #`TCQ 1'b1; + end else begin + FULL <= #`TCQ 1'b0; + end + + if (RST_FULL_GEN) begin + ALMOST_FULL <= #`TCQ 1'b0; + end else if (!FULL) begin + if (almost_full_int) + ALMOST_FULL <= #`TCQ 1'b1; + else + ALMOST_FULL <= #`TCQ 1'b0; + end + end // wr_rst_i + end // always + + // Determine which stage in FWFT registers are valid + reg stage1_valid = 0; + reg stage2_valid = 0; + generate + if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + stage1_valid <= #`TCQ 0; + stage2_valid <= #`TCQ 0; + end else begin + + if (!stage1_valid && !stage2_valid) begin + if (!EMPTY) + stage1_valid <= #`TCQ 1'b1; + else + stage1_valid <= #`TCQ 1'b0; + end else if (stage1_valid && !stage2_valid) begin + if (EMPTY) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else if (!stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b0; + end else if (!EMPTY && !RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end + end else if (stage1_valid && stage2_valid) begin + if (EMPTY && RD_EN_USER) begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b1; + end else begin + stage1_valid <= #`TCQ 1'b1; + stage2_valid <= #`TCQ 1'b1; + end + end else begin + stage1_valid <= #`TCQ 1'b0; + stage2_valid <= #`TCQ 1'b0; + end + end // rd_rst_i + end // always + end + endgenerate + + //Pointers passed into opposite clock domain + reg [31:0] wr_ptr_rdclk; + reg [31:0] wr_ptr_rdclk_next; + reg [31:0] rd_ptr_wrclk; + reg [31:0] rd_ptr_wrclk_next; + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_EMPTY. + wire [31:0] num_read_words_pe = + num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR); + + //Amount of data stored in the FIFO scaled to the narrowest (deepest) port + // (Do not include data in FWFT stages) + //Used to calculate PROG_FULL. + wire [31:0] num_write_words_pf = + num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD); + + /************************** + * Read Data Count + *************************/ + + reg [31:0] num_read_words_dc; + reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i; + + always @(num_rd_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //If using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain, + // and add two read words for FWFT stages + //This value is only a temporary value and not used in the code. + num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2); + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1]; + + end else begin + + //If not using extra logic for FWFT Data Counts, + // then scale FIFO contents to read domain. + //This value is only a temporary value and not used in the code. + num_read_words_dc = num_rd_bits/C_DOUT_WIDTH; + + //Trim the read words for use with RD_DATA_COUNT + num_read_words_sized_i = + num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + /************************** + * Write Data Count + *************************/ + + reg [31:0] num_write_words_dc; + reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i; + + always @(num_wr_bits) begin + if (C_USE_FWFT_DATA_COUNT) begin + + //Calculate the Data Count value for the number of write words, + // when using First-Word Fall-Through with extra logic for Data + // Counts. This takes into consideration the number of words that + // are expected to be stored in the FWFT register stages (it always + // assumes they are filled). + //This value is scaled to the Write Domain. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //EXTRA_WORDS_DC is the number of words added to write_words + // due to FWFT. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ; + + //Trim the write words for use with WR_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1]; + + end else begin + + //Calculate the Data Count value for the number of write words, when NOT + // using First-Word Fall-Through with extra logic for Data Counts. This + // calculates only the number of words in the internal FIFO. + //The expression (((A-1)/B))+1 divides A/B, but takes the + // ceiling of the result. + //This value is scaled to the Write Domain. + //When num_wr_bits==0, set the result manually to prevent + // division errors. + //This value is only a temporary value and not used in the code. + num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1; + + //Trim the read words for use with RD_DATA_COUNT + num_write_words_sized_i = + num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH]; + + end //if (C_USE_FWFT_DATA_COUNT) + end //always + + + + /*************************************************************************** + * Internal registers and wires + **************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire valid_i; + wire valid_out; + wire underflow_i; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0; + reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + //temporary registers for WR_RESPONSE_LATENCY feature + + integer tmp_wr_listsize; + integer tmp_rd_listsize; + + //Signal for registered version of prog full and empty + + //Threshold values for Programmable Flags + integer prog_empty_actual_thresh_assert; + integer prog_empty_actual_thresh_negate; + integer prog_full_actual_thresh_assert; + integer prog_full_actual_thresh_negate; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + begin + memory[wr_ptr] <= DIN; + wr_pntr <= #`TCQ wr_pntr + 1; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + // (Works opposite to core: wr_ptr is a DOWN counter) + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + integer i; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [C_DIN_WIDTH-1:0] memory_read; + reg [31:0] tmp_rd_ptr; + reg [31:0] rd_ptr_high; + reg [31:0] rd_ptr_low; + reg [1:0] tmp_ecc_err; + begin + rd_pntr <= #`TCQ rd_pntr + 1; + // output is wider than input + if (reads_per_write == 0) begin + tmp_dout = 0; + tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1); + for (i = writes_per_read - 1; i >= 0; i = i - 1) begin + tmp_dout = tmp_dout << C_DIN_WIDTH; + tmp_dout = tmp_dout | memory[tmp_rd_ptr]; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (tmp_rd_ptr == 0) begin + tmp_rd_ptr = C_WR_DEPTH - 1; + end else begin + tmp_rd_ptr = tmp_rd_ptr - 1; + end + end + + // output is symmetric + end else if (reads_per_write == 1) begin + tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + + // input is wider than output + end else begin + rd_ptr_high = rd_ptr >> log2_reads_per_write; + rd_ptr_low = rd_ptr & (reads_per_write - 1); + memory_read = memory[rd_ptr_high]; + tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH); + end + ideal_dout <= tmp_dout; + + // (Works opposite to core: rd_ptr is a DOWN counter) + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /*********************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_wr_bits = 0; + num_rd_bits = 0; + next_num_wr_bits = 0; + next_num_rd_bits = 0; + rd_ptr = C_RD_DEPTH - 1; + wr_ptr = C_WR_DEPTH - 1; + wr_pntr = 0; + rd_pntr = 0; + rd_ptr_wrclk = rd_ptr; + wr_ptr_rdclk = wr_ptr; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_dout_d1 = dout_reset_val; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_wr_count = 0; + ideal_rd_count = 0; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_CLK; + wire RD_EN; + wire RST; + wire WR_CLK; + wire WR_EN; + */ + + //*************************************************************************** + // Dout may change behavior based on latency + //*************************************************************************** + assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out; + + //*************************************************************************** + // Assign SBITERR and DBITERR based on latency + //*************************************************************************** + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY == 2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + (C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + + //*************************************************************************** + // Overflow may be active-low + //*************************************************************************** + generate + if (C_HAS_OVERFLOW==1) begin : blockOF1 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //*************************************************************************** + // Valid may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_VALID==1) begin : blockVL1 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + + //*************************************************************************** + // Underflow may change behavior based on latency or active-low + //*************************************************************************** + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF1 + assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + //*************************************************************************** + // Write acknowledge may be active low + //*************************************************************************** + generate + if (C_HAS_WR_ACK==1) begin : blockWK1 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext + + reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0; + reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0; + wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp; + wire [C_PNTR_WIDTH:0] diff_wr_rd; + reg [C_PNTR_WIDTH:0] wr_data_count_i = 0; + always @* begin + if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = 0; + adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr; + end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin + adjusted_rd_pntr = rd_pntr_wr; + adjusted_wr_pntr = 0; + adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr; + end else begin + adjusted_wr_pntr = wr_pntr; + adjusted_rd_pntr = rd_pntr_wr; + end + end // always @* + + assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr; + assign diff_wr_rd = {1'b0,diff_wr_rd_tmp}; + + always @ (posedge wr_rst_i or posedge WR_CLK) + begin + if (wr_rst_i) + wr_data_count_i <= #`TCQ 0; + else + wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC; + end // always @ (posedge WR_CLK or posedge WR_CLK) + + always @* begin + if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0]; + else + wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH]; + end // always @* + end // wdc_fwft_ext + endgenerate + + //*************************************************************************** + // Generate RD_DATA_COUNT if Use Extra Logic option is selected + //*************************************************************************** + reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0; + + generate + if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext + reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0; + wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp; + wire [C_RD_PNTR_WIDTH:0] diff_rd_wr; + always @* begin + if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin + adjusted_wr_pntr_rd = 0; + adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd; + end else begin + adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH]; + end + end // always @* + + assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr; + assign diff_rd_wr = {1'b0,diff_rd_wr_tmp}; + + always @ (posedge rd_rst_i or posedge RD_CLK) + begin + if (rd_rst_i) begin + rdc_fwft_ext_as <= #`TCQ 0; + end else begin + if (!stage2_valid) + rdc_fwft_ext_as <= #`TCQ 0; + else if (!stage1_valid && stage2_valid) + rdc_fwft_ext_as <= #`TCQ 1; + else + rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2; + end + end // always @ (posedge WR_CLK or posedge WR_CLK) + end // rdc_fwft_ext + endgenerate + + //*************************************************************************** + // Assign the read data count value only if it is selected, + // otherwise output zeros. + //*************************************************************************** + generate + if (C_HAS_RD_DATA_COUNT == 1) begin : grdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ? + rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] : + rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc + assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + //*************************************************************************** + // Assign the write data count value only if it is selected, + // otherwise output zeros + //*************************************************************************** + generate + if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ? + wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] : + wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH]; + end + endgenerate + + generate + if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc + assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH-1{1'b0}}; + end + endgenerate + + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL2 + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end + endgenerate + + //Capture delayed version of dout + always @(posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF2 + always @(posedge WR_CLK) begin + ideal_overflow <= #`TCQ WR_EN & FULL; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF2 + always @(posedge RD_CLK) begin + ideal_underflow <= #`TCQ EMPTY & RD_EN; + end + end + endgenerate + + /************************************************************************** + * Write Domain Logic + **************************************************************************/ + reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0; + always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w + + /****** Reset fifo (case 1)***************************************/ + if (wr_rst_i == 1'b1) begin + num_wr_bits <= #`TCQ 0; + next_num_wr_bits = #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1; + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ 0; + tmp_wr_listsize = #`TCQ 0; + rd_ptr_wrclk_next <= #`TCQ 0; + wr_pntr <= #`TCQ 0; + wr_pntr_rd1 <= #`TCQ 0; + rd_pntr_wr2 <= #`TCQ 0; + rd_pntr_wr3 <= #`TCQ 0; + rd_pntr_wr4 <= #`TCQ 0; + rd_pntr_wr <= #`TCQ 0; + + + end else begin //wr_rst_i==0 + + wr_pntr_rd1 <= #`TCQ wr_pntr; + + // Synchronize the rd_pntr in read domain + rd_pntr_wr2 <= #`TCQ rd_pntr_wr1; + rd_pntr_wr3 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr4 <= #`TCQ rd_pntr_wr2; + rd_pntr_wr <= #`TCQ rd_pntr_wr4; + + + + //Determine the current number of words in the FIFO + tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH : + num_wr_bits/C_DIN_WIDTH; + rd_ptr_wrclk_next = rd_ptr; + if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH + - rd_ptr_wrclk_next); + end else begin + next_num_wr_bits = num_wr_bits - + C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next); + end + + //If this is a write, handle the write by adding the value + // to the linked list, and updating all outputs appropriately + if (WR_EN == 1'b1) begin + if (FULL == 1'b1) begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD + >= C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full, but reporting full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //With DEPTH-1 words in the FIFO, it is almost_full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + + //If the FIFO is completely empty, but it is + // reporting FULL for some reason (like reset) + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <= + C_FIFO_WR_DEPTH-2) begin + //No change to FIFO + + //Write not successful + ideal_wr_ack <= #`TCQ 0; + //FIFO is really not close to full, so change flag status. + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end //(tmp_wr_listsize == 0) + + end else begin + + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >= + C_FIFO_WR_DEPTH) begin + //write unsuccessful - do not change contents + + //Do not acknowledge the write + ideal_wr_ack <= #`TCQ 0; + //Reminder that FIFO is still full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is one from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-1) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //This write is CAUSING the FIFO to go full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is 2 from full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD == + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Still 2 from full + + ideal_wr_count <= #`TCQ num_write_words_sized_i; + + //If the FIFO is not close to being full + end else + if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD < + C_FIFO_WR_DEPTH-2) begin + //Add value on DIN port to FIFO + write_fifo; + next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH; + //Write successful, so issue acknowledge + // and no error + ideal_wr_ack <= #`TCQ 1; + //Not even close to full. + + ideal_wr_count <= num_write_words_sized_i; + + end + + end + + end else begin //(WR_EN == 1'b1) + + //If user did not attempt a write, then do not + // give ack or err + ideal_wr_ack <= #`TCQ 0; + ideal_wr_count <= #`TCQ num_write_words_sized_i; + end + num_wr_bits <= #`TCQ next_num_wr_bits; + rd_ptr_wrclk <= #`TCQ rd_ptr; + + end //wr_rst_i==0 + end // write always + + + /*************************************************************************** + * Programmable FULL flags + ***************************************************************************/ + + always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf + + if (RST_FULL_FF == 1'b1) begin + diff_pntr <= 0; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + if (ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1); + else if (!ram_wr_en) + diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr); + + if (RST_FULL_GEN) + ideal_prog_full <= #`TCQ 0; + //Single Programmable Full Constant Threshold + else if (C_PROG_FULL_TYPE == 1) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Constant Thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if (FULL == 0) begin + if (diff_pntr >= C_PROG_FULL_THRESH_ASSERT_VAL) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < C_PROG_FULL_THRESH_NEGATE_VAL) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Single Programmable Full Threshold Input + end else if (C_PROG_FULL_TYPE == 3) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH) + ideal_prog_full <= #`TCQ 1; + else + ideal_prog_full <= #`TCQ 0; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + //Two Programmable Full Threshold Inputs + end else if (C_PROG_FULL_TYPE == 4) begin + if (FULL == 0) begin + if (diff_pntr >= PROG_FULL_THRESH_ASSERT) + ideal_prog_full <= #`TCQ 1; + else if (diff_pntr < PROG_FULL_THRESH_NEGATE) + ideal_prog_full <= #`TCQ 0; + else + ideal_prog_full <= #`TCQ ideal_prog_full; + end else + ideal_prog_full <= #`TCQ ideal_prog_full; + end // C_PROG_FULL_TYPE + + end //wr_rst_i==0 + end // + + + /************************************************************************** + * Read Domain Logic + **************************************************************************/ + + + /********************************************************* + * Programmable EMPTY flags + *********************************************************/ + //Determine the Assert and Negate thresholds for Programmable Empty + + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val = 0; + reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0; + always @* begin + + if (C_PROG_EMPTY_TYPE == 3) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH - 2'h2; + else + pe_thr_assert_val <= PROG_EMPTY_THRESH; + + end else if (C_PROG_EMPTY_TYPE == 4) begin + + // If empty input threshold is selected, then subtract 2 for FWFT to + // compensate the FWFT stage, otherwise assign the input value. + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT - 2'h2; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE - 2'h2; + end else begin + pe_thr_assert_val <= PROG_EMPTY_THRESH_ASSERT; + pe_thr_negate_val <= PROG_EMPTY_THRESH_NEGATE; + end + end else begin + + if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL - 2; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL - 2; + end else begin + pe_thr_assert_val <= C_PROG_EMPTY_THRESH_ASSERT_VAL; + pe_thr_negate_val <= C_PROG_EMPTY_THRESH_NEGATE_VAL; + end + end + end // always @* + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe + + if (rd_rst_i) begin + diff_pntr_rd <= #`TCQ 0; + ideal_prog_empty <= #`TCQ 1'b1; + end else begin + if (ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1; + else if (!ram_rd_en) + diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr); + else + diff_pntr_rd <= #`TCQ diff_pntr_rd; + + if (C_PROG_EMPTY_TYPE == 1) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 2) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 3) begin + if (EMPTY == 0) begin + if (diff_pntr_rd <= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else + ideal_prog_empty <= #`TCQ 0; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else if (C_PROG_EMPTY_TYPE == 4) begin + if (EMPTY == 0) begin + if (diff_pntr_rd >= pe_thr_assert_val) + ideal_prog_empty <= #`TCQ 1; + else if (diff_pntr_rd > pe_thr_negate_val) + ideal_prog_empty <= #`TCQ 0; + else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end else + ideal_prog_empty <= #`TCQ ideal_prog_empty; + end //C_PROG_EMPTY_TYPE + end + end + + // block memory has a synchronous reset + always @(posedge RD_CLK) begin : gen_fifo_blkmemdout + // make it consistent with the core. + if (rd_rst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2) + err_type <= #`TCQ 0; + + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r + + /****** Reset fifo (case 1)***************************************/ + if (rd_rst_i) begin + num_rd_bits <= #`TCQ 0; + next_num_rd_bits = #`TCQ 0; + rd_ptr <= #`TCQ C_RD_DEPTH -1; + rd_pntr <= #`TCQ 0; + rd_pntr_wr1 <= #`TCQ 0; + wr_pntr_rd2 <= #`TCQ 0; + wr_pntr_rd3 <= #`TCQ 0; + wr_pntr_rd <= #`TCQ 0; + wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1; + + // DRAM resets asynchronously + if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1) + ideal_dout <= #`TCQ dout_reset_val; + + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ 0; + + end else begin //rd_rst_i==0 + + rd_pntr_wr1 <= #`TCQ rd_pntr; + + // Synchronize the wr_pntr in read domain + wr_pntr_rd2 <= #`TCQ wr_pntr_rd1; + wr_pntr_rd3 <= #`TCQ wr_pntr_rd2; + wr_pntr_rd <= #`TCQ wr_pntr_rd3; + + + + //Determine the current number of words in the FIFO + tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH : + num_rd_bits/C_DOUT_WIDTH; + wr_ptr_rdclk_next = wr_ptr; + + if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH + - wr_ptr_rdclk_next); + end else begin + next_num_rd_bits = num_rd_bits + + C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next); + end + + /*****************************************************************/ + // Read Operation - Read Latency 1 + /*****************************************************************/ + if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin + ideal_valid <= #`TCQ 1'b0; + + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + end // if (tmp_rd_listsize <= 0) + + //If the FIFO is one from empty, but it is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + //If the FIFO is two from empty, and is reporting empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that the FIFO is No Longer Empty or Almost Empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + end // else: if(ideal_empty == 1'b1) + + else //if (ideal_empty == 1'b0) + begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH) + + //If the FIFO is not close to being empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + //If the FIFO is two from empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 2) + + //If the FIFO is one from empty + else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)) + begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize == 1) + + + //If the FIFO is completely empty + else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) + begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end //(RD_EN == 1'b1) + + else //if (RD_EN == 1'b0) + begin + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + + /*****************************************************************/ + // Read Operation - Read Latency 0 + /*****************************************************************/ + end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + ideal_valid <= #`TCQ 1'b0; + if (ram_rd_en == 1'b1) begin + + if (EMPTY == 1'b1) begin + + //If the FIFO is completely empty, and is reporting empty + if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty, but it is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that FIFO is no longer empty, but is almost empty (has one word left) + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty, and is reporting empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Fifo has two words, so is neither empty or almost empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to empty, but is reporting that it is + // Treat the FIFO as empty this time, but unset EMPTY flags. + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Note that the FIFO is No Longer Empty or Almost Empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1)) + + end else begin + + //If the FIFO is completely full, and we are successfully reading from it + if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is not close to being empty + end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && + (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Not close to empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is two from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Fifo is not yet empty. It is going almost_empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is one from empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin + //Read the value from the FIFO + read_fifo; + next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH; + + //Acknowledge the read from the FIFO, no error + ideal_valid <= #`TCQ 1'b1; + //Note that FIFO is GOING empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + //If the FIFO is completely empty + end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin + //Do not change the contents of the FIFO + + //Do not acknowledge the read from empty FIFO + ideal_valid <= #`TCQ 1'b0; + //Reminder that FIFO is still empty + + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // if (tmp_rd_listsize <= 0) + + end // if (ideal_empty == 1'b0) + + end else begin//(RD_EN == 1'b0) + + + //If user did not attempt a read, do not give an ack or err + ideal_valid <= #`TCQ 1'b0; + ideal_rd_count <= #`TCQ num_read_words_sized_i; + + end // else: !if(RD_EN == 1'b1) + end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + num_rd_bits <= #`TCQ next_num_rd_bits; + wr_ptr_rdclk <= #`TCQ wr_ptr; + end //rd_rst_i==0 + end //always + +endmodule // fifo_generator_v6_1_bhv_ver_as + + +/******************************************************************************* + * Declaration of top-level module + ******************************************************************************/ +module fifo_generator_v6_1_bhv_ver_ss + + /************************************************************************** + * Declare user parameters and their defaults + *************************************************************************/ + #( + parameter C_DATA_COUNT_WIDTH = 2, + parameter C_DIN_WIDTH = 8, + parameter C_DOUT_RST_VAL = "", + parameter C_DOUT_WIDTH = 8, + parameter C_FULL_FLAGS_RST_VAL = 1, + parameter C_HAS_ALMOST_EMPTY = 0, + parameter C_HAS_ALMOST_FULL = 0, + parameter C_HAS_DATA_COUNT = 0, + parameter C_HAS_OVERFLOW = 0, + parameter C_HAS_RD_DATA_COUNT = 0, + parameter C_HAS_RST = 0, + parameter C_HAS_SRST = 0, + parameter C_HAS_UNDERFLOW = 0, + parameter C_HAS_VALID = 0, + parameter C_HAS_WR_ACK = 0, + parameter C_HAS_WR_DATA_COUNT = 0, + parameter C_IMPLEMENTATION_TYPE = 0, + parameter C_MEMORY_TYPE = 1, + parameter C_OVERFLOW_LOW = 0, + parameter C_PRELOAD_LATENCY = 1, + parameter C_PRELOAD_REGS = 0, + parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0, + parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0, + parameter C_PROG_EMPTY_TYPE = 0, + parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0, + parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0, + parameter C_PROG_FULL_TYPE = 0, + parameter C_RD_DATA_COUNT_WIDTH = 2, + parameter C_RD_DEPTH = 256, + parameter C_RD_PNTR_WIDTH = 8, + parameter C_UNDERFLOW_LOW = 0, + parameter C_USE_DOUT_RST = 0, + parameter C_USE_EMBEDDED_REG = 0, + parameter C_USE_FWFT_DATA_COUNT = 0, + parameter C_VALID_LOW = 0, + parameter C_WR_ACK_LOW = 0, + parameter C_WR_DATA_COUNT_WIDTH = 2, + parameter C_WR_DEPTH = 256, + parameter C_WR_PNTR_WIDTH = 8, + parameter C_USE_ECC = 0, + parameter C_ENABLE_RST_SYNC = 1, + parameter C_ERROR_INJECTION_TYPE = 0 + ) + + /************************************************************************** + * Declare Input and Output Ports + *************************************************************************/ + ( + //Inputs + input CLK, + input [C_DIN_WIDTH-1:0] DIN, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT, + input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT, + input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE, + input RD_EN, + input RST, + input RST_FULL_GEN, + input RST_FULL_FF, + input SRST, + input WR_EN, + input INJECTDBITERR, + input INJECTSBITERR, + + //Outputs + output ALMOST_EMPTY, + output ALMOST_FULL, + output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT, + output [C_DOUT_WIDTH-1:0] DOUT, + output EMPTY, + output FULL, + output OVERFLOW, + output PROG_EMPTY, + output PROG_FULL, + output VALID, + output UNDERFLOW, + output WR_ACK, + output SBITERR, + output DBITERR + ); + + + /*************************************************************************** + * Parameters used as constants + **************************************************************************/ + //When RST is present, set FULL reset value to '1'. + //If core has no RST, make sure FULL powers-on as '0'. + //The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not + //changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0. + // Therefore, during SRST, all the FULL flags reset to 0. + parameter C_HAS_FAST_FIFO = 0; + parameter C_FIFO_WR_DEPTH = C_WR_DEPTH; + parameter C_FIFO_RD_DEPTH = C_RD_DEPTH; + + /************************************************************************** + * FIFO Contents Tracking and Data Count Calculations + *************************************************************************/ + // Memory which will be used to simulate a FIFO + reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0]; + // Local parameters used to determine whether to inject ECC error or not + localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0; + localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0; + localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION; + // Array that holds the error injection type (single/double bit error) on + // a specific write operation, which is returned on read to corrupt the + // output data. + reg [1:0] ecc_err[C_WR_DEPTH-1:0]; + + //The amount of data stored in the FIFO at any time is given + // by num_bits. + //num_bits is calculated by from the total words in the FIFO. + reg [31:0] num_bits; + + //The write pointer - tracks write operations + // (Works opposite to core: wr_ptr is a DOWN counter) + reg [31:0] wr_ptr; + + //The write pointer - tracks read operations + // (Works opposite to core: rd_ptr is a DOWN counter) + reg [31:0] rd_ptr; + + /************************** + * Data Count + *************************/ + //Amount of data stored in the FIFO scaled to read words + wire [31:0] num_read_words = num_bits/C_DOUT_WIDTH; + //num_read_words delayed 1 clock cycle + reg [31:0] num_read_words_q; + + //Amount of data stored in the FIFO scaled to write words + wire [31:0] num_write_words = num_bits/C_DIN_WIDTH; + //num_write_words delayed 1 clock cycle + reg [31:0] num_write_words_q; + + + /************************************************************************** + * Internal Registers and wires + *************************************************************************/ + + //Temporary signals used for calculating the model's outputs. These + //are only used in the assign statements immediately following wire, + //parameter, and function declarations. + wire underflow_i; + wire valid_i; + wire valid_out; + + //Ideal FIFO signals. These are the raw output of the behavioral model, + //which behaves like an ideal FIFO. + reg [1:0] err_type = 0; + reg [1:0] err_type_d1 = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout = 0; + reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0; + wire [C_DOUT_WIDTH-1:0] ideal_dout_out; + wire fwft_enabled; + reg ideal_wr_ack = 0; + reg ideal_valid = 0; + reg ideal_overflow = 0; + reg ideal_underflow = 0; + reg ideal_full = 0; + reg ideal_empty = 1; + reg ideal_almost_full = 0; + reg ideal_almost_empty = 1; + reg ideal_prog_full = 0; + reg ideal_prog_empty = 1; + + //Assorted reg values for delayed versions of signals + reg valid_d1 = 0; + reg prog_full_d = 0; + reg prog_empty_d = 1; + + wire rst_i; + wire srst_i; + + //Delayed version of RST + reg rst_q; + reg rst_qq; + + //user specified value for reseting the size of the fifo + reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0; + + + /**************************************************************************** + * Function Declarations + ***************************************************************************/ + + /************************************************************************** + * write_fifo + * This task writes a word to the FIFO memory and updates the + * write pointer. + * FIFO size is relative to write domain. + ***************************************************************************/ + task write_fifo; + reg [1:0] corrupted_data; + begin + memory[wr_ptr] <= DIN; + // Store the type of error injection (double/single) on write + case (C_ERROR_INJECTION_TYPE) + 3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR}; + 2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0}; + 1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR}; + default: ecc_err[wr_ptr] <= 0; + endcase + if (wr_ptr == 0) begin + wr_ptr <= C_WR_DEPTH - 1; + end else begin + wr_ptr <= wr_ptr - 1; + end + end + endtask // write_fifo + + /************************************************************************** + * read_fifo + * This task reads a word from the FIFO memory and updates the read + * pointer. It's output is the ideal_dout bus. + * FIFO size is relative to write domain. + ***************************************************************************/ + task read_fifo; + reg [C_DOUT_WIDTH-1:0] tmp_dout; + reg [1:0] tmp_ecc_err; + begin + tmp_dout = memory[rd_ptr][C_DOUT_WIDTH-1:0]; + // Retreive the error injection type. Based on the error injection type + // corrupt the output data. + tmp_ecc_err = ecc_err[rd_ptr]; + if (ENABLE_ERR_INJECTION) begin + if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error + if (C_DOUT_WIDTH == 1) + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + else if (C_DOUT_WIDTH == 2) + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]}; + else + tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)}; + end else begin + tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0]; + end + err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]}; + end else begin + err_type <= 0; + end + ideal_dout <= tmp_dout; + + if (rd_ptr == 0) begin + rd_ptr <= C_RD_DEPTH - 1; + end else begin + rd_ptr <= rd_ptr - 1; + end + end + endtask + + /**************************************************************************** + * log2_val + * Returns the 'log2' value for the input value for the supported ratios + ***************************************************************************/ + function [31:0] log2_val; + input [31:0] binary_val; + + begin + if (binary_val == 8) begin + log2_val = 3; + end else if (binary_val == 4) begin + log2_val = 2; + end else begin + log2_val = 1; + end + end + endfunction + + /**************************************************************************** + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***************************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + /************************************************************************* + * Initialize Signals for clean power-on simulation + *************************************************************************/ + initial begin + num_bits = 0; + num_read_words_q = 0; + num_write_words_q = 0; + rd_ptr = C_RD_DEPTH -1; + wr_ptr = C_WR_DEPTH -1; + dout_reset_val = hexstr_conv(C_DOUT_RST_VAL); + ideal_dout = dout_reset_val; + err_type = 0; + ideal_wr_ack = 1'b0; + ideal_valid = 1'b0; + valid_d1 = 1'b0; + ideal_overflow = 1'b0; + ideal_underflow = 1'b0; + ideal_full = 1'b0; + ideal_empty = 1'b1; + ideal_almost_full = 1'b0; + ideal_almost_empty = 1'b1; + ideal_prog_full = 1'b0; + ideal_prog_empty = 1'b1; + prog_full_d = 1'b0; + prog_empty_d = 1'b1; + rst_q = 1'b0; + rst_qq = 1'b0; + end + + + /************************************************************************* + * Connect the module inputs and outputs to the internal signals of the + * behavioral model. + *************************************************************************/ + //Inputs + /* + wire CLK; + wire [C_DIN_WIDTH-1:0] DIN; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT; + wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT; + wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE; + wire RD_EN; + wire RST; + wire WR_EN; + */ + + //Outputs + generate + if (C_HAS_ALMOST_EMPTY==1) begin : blockAE10 + assign ALMOST_EMPTY = ideal_almost_empty; + end + endgenerate + + generate + if (C_HAS_ALMOST_FULL==1) begin : blockAF10 + assign ALMOST_FULL = ideal_almost_full; + end + endgenerate + + //Dout may change behavior based on latency + assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)? + 1: 0; + assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + ideal_dout_d1: ideal_dout; + assign DOUT = ideal_dout_out; + + // Assign SBITERR and DBITERR based on latency + assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[0]: err_type[0]; + assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) && + ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ? + err_type_d1[1]: err_type[1]; + + assign EMPTY = ideal_empty; + assign FULL = ideal_full; + + //Overflow may be active-low + generate + if (C_HAS_OVERFLOW==1) begin : blockOF10 + assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW; + end + endgenerate + + assign PROG_EMPTY = ideal_prog_empty; + assign PROG_FULL = ideal_prog_full; + + //Valid may change behavior based on latency or active-low + generate + if (C_HAS_VALID==1) begin : blockVL10 + assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid; + assign valid_out = (C_PRELOAD_LATENCY==2 && + (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))? + valid_d1: valid_i; + assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW; + end + endgenerate + + //Trim data count differently depending on set widths + generate + if ((C_HAS_DATA_COUNT == 1) && + (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) begin : blockDC1 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH:0]; + end else if (C_HAS_DATA_COUNT == 1) begin : blockDC2 + always @(num_read_words) + DATA_COUNT = num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH]; + end //if + endgenerate + + //Underflow may change behavior based on latency or active-low + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF10 + assign underflow_i = ideal_underflow; + assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW; + end + endgenerate + + + //Write acknowledge may be active low + generate + if (C_HAS_WR_ACK==1) begin : blockWK10 + assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW; + end + endgenerate + + + /***************************************************************************** + * Internal reset logic + ****************************************************************************/ + assign srst_i = C_HAS_SRST ? SRST : 0; + assign rst_i = C_HAS_RST ? RST : 0; + + /************************************************************************** + * Assorted registers for delayed versions of signals + **************************************************************************/ + //Capture delayed version of valid + generate + if (C_HAS_VALID==1) begin : blockVL20 + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + valid_d1 <= #`TCQ 1'b0; + end else begin + valid_d1 <= #`TCQ valid_i; + end + end + end // always @ (posedge CLK or posedge rst_i) + end + endgenerate + + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout_emb + // make it consistent with the core. + if (rst_i || srst_i) begin + // BRAM resets synchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout_d1 <= #`TCQ dout_reset_val; + end + end + end //always + + reg ram_rd_en_d1 = 1'b0; + //Capture delayed version of dout + always @(posedge CLK or posedge rst_i) begin + if (rst_i == 1'b1) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + + // DRAM and SRAM reset asynchronously + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + + ram_rd_en_d1 <= #`TCQ 1'b0; + end else begin + ram_rd_en_d1 <= #`TCQ RD_EN & !EMPTY; + if (srst_i) begin + ram_rd_en_d1 <= #`TCQ 1'b0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type_d1 <= #`TCQ 0; + // Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above + if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) + ideal_dout_d1 <= #`TCQ dout_reset_val; + end else if (ram_rd_en_d1) begin + ideal_dout_d1 <= #`TCQ ideal_dout; + err_type_d1 <= #`TCQ err_type; + end + end + end + + /************************************************************************** + * Overflow and Underflow Flag calculation + * (handled separately because they don't support rst) + **************************************************************************/ + generate + if (C_HAS_OVERFLOW==1) begin : blockOF20 + always @(posedge CLK) begin + ideal_overflow <= #`TCQ WR_EN & ideal_full; + end + end + endgenerate + + generate + if (C_HAS_UNDERFLOW==1) begin : blockUF20 + always @(posedge CLK) begin + ideal_underflow <= #`TCQ ideal_empty & RD_EN; + end + end + endgenerate + + /************************************************************************* + * Write and Read Logic + ************************************************************************/ + always @(posedge CLK or posedge rst_i) + begin : gen_wr_ack_resp + + //Register reset + rst_q <= #`TCQ rst_i; + rst_qq <= #`TCQ rst_q; + + end // block: gen_wr_ack_resp + + // block memory has a synchronous reset + always @(posedge CLK) begin : gen_fifo_blkmemdout + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (rst_i || rst_q || srst_i) begin + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE == 1) + err_type <= #`TCQ 0; + /******Initialize Read Domain Signals*********************************/ + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin + ideal_dout <= #`TCQ dout_reset_val; + end + end + end //always + + // FULL_FLAG_RESET value given for SRST as well. + reg srst_i_d1 = 0; + reg srst_i_d2 = 0; + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo + + /****** Reset fifo - Asynchronous Reset**********************************/ + //Changed the latency of during async reset to '1' instead of '2' to + // make it consistent with the core. + if (RST_FULL_FF) begin //v3.2 + /******Initialize Generic FIFO constructs*****************************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0 && C_MEMORY_TYPE != 1) + err_type <= #`TCQ 0; + + + /******Initialize Write Domain Signals********************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals*********************************/ + // DRAM and SRAM reset asynchronously + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + end else begin + // Register SRST twice to be consistant with RST behavior + srst_i_d1 <= #`TCQ srst_i; + srst_i_d2 <= #`TCQ srst_i_d1; + if (srst_i) begin + // SRST is available only for Sync BRAM, DRAM and SRAM. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + /******Initialize Generic FIFO constructs***********************/ + num_bits <= #`TCQ 0; + wr_ptr <= #`TCQ C_WR_DEPTH - 1; + rd_ptr <= #`TCQ C_RD_DEPTH - 1; + num_read_words_q <= #`TCQ 0; + num_write_words_q <= #`TCQ 0; + // Reset err_type only if ECC is not selected + if (C_USE_ECC == 0) + err_type <= #`TCQ 0; + + /******Initialize Write Domain Signals**************************/ + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + + /******Initialize Read Domain Signals***************************/ + //Reset DOUT of Sync DRAM/Shift RAM. Sync BRAM DOUT was reset in the + // above always block. + if (C_USE_DOUT_RST == 1 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3)) begin + ideal_dout <= #`TCQ dout_reset_val; + end + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + end + + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin //Hold full flag reset value set during RST/SRST + ideal_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_almost_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin //normal operating conditions + /********************************************************************/ + // Synchronous FIFO Condition #1 : Writing and not reading + /********************************************************************/ + ideal_valid <= #`TCQ 1'b0; + if (WR_EN & ~RD_EN) begin + + /*********************************/ + //If the FIFO is full, do NOT perform the write, + // update flags accordingly + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + + /*********************************/ + //If the FIFO is reporting FULL + // (Startup condition) + /*********************************/ + end else if ((num_write_words < C_FIFO_WR_DEPTH) && (ideal_full == 1'b1)) begin + ideal_wr_ack <= #`TCQ 0; + + //still full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //write unsuccessful - do not change contents + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //FIFO EMPTY in this state can not be determined + //ideal_empty <= 1'b0; + //ideal_almost_empty <= 1'b0; + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //FIFO is one from FULL and going FULL + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is 2 from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-2) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //2 from full, and writing, so set almost_full + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Add input data + write_fifo; + + //no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Leaving EMPTY (still ALMOST_EMPTY) + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + // good write + ideal_wr_ack <= #`TCQ 1; + + //Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Add input data + write_fifo; + + // no read attempted + ideal_valid <= #`TCQ 1'b0; + + //Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + end // average case + + + /******************************************************************/ + // Synchronous FIFO Condition #2 : Reading and not writing + /******************************************************************/ + end else if (~WR_EN & RD_EN) begin + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + if ((num_read_words == 0) || (ideal_empty == 1'b1)) begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO is still empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No read + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //This read will make FIFO go empty + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is 2 from EMPTY + /*********************************/ + end else if (num_read_words == 2) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO is going ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Get the data from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving ALMOST FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is FULL + /*********************************/ + end else if (num_write_words >= C_FIFO_WR_DEPTH) + begin + //no write attempted + ideal_wr_ack <= #`TCQ 0; + + //FIFO is leaving FULL, but is still ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + //no write attemped + ideal_wr_ack <= #`TCQ 0; + + //Not near empty + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + end // average read + + + /******************************************************************/ + // Synchronous FIFO Condition #3 : Reading and writing + /******************************************************************/ + end else if (WR_EN & RD_EN) begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits - C_DOUT_WIDTH; + + + /*********************************/ + // FIFO is reporting FULL, but it is empty + // (This is a special case, when coming out of RST + /*********************************/ + end else if ((num_write_words == 0) && (ideal_full == 1'b1)) begin + + ideal_wr_ack <= #`TCQ 0; + + //Read will be successful, so FIFO will leave FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //Read unsuccessful + ideal_valid <= #`TCQ 1'b0; + + //Report empty condition + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //Do not read from empty FIFO + // Read from the FIFO + + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + //FIFO will remain ALMOST_FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //Not near empty + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + //FIFO will stay ALMOST_EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + end else if (num_read_words == 0) begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read will fail + ideal_valid <= #`TCQ 1'b0; + + //FIFO will leave EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + // No read + num_bits <= #`TCQ num_bits + C_DIN_WIDTH; + + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //Write successful + ideal_wr_ack <= #`TCQ 1; + + // Not near FULL + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + // put the data into the FIFO + write_fifo; + + //Read successful + ideal_valid <= #`TCQ 1'b1; + + // Not near EMPTY + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //Read from the FIFO + read_fifo; + num_bits <= #`TCQ num_bits + C_DIN_WIDTH - C_DOUT_WIDTH; + + end // average case + + /******************************************************************/ + // Synchronous FIFO Condition #4 : Not reading or writing + /******************************************************************/ + end else begin + + /*********************************/ + // FIFO is FULL + /*********************************/ + if (num_write_words >= C_FIFO_WR_DEPTH) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b1; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is one from full + /*********************************/ + end else if (num_write_words == C_FIFO_WR_DEPTH-1) begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b1; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + /*********************************/ + //If the FIFO is ALMOST EMPTY + /*********************************/ + end else if (num_read_words == 1) begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + end // almost empty + + + /*********************************/ + //If the FIFO is EMPTY + /*********************************/ + else if (num_read_words == 0) + begin + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b1; + ideal_almost_empty <= #`TCQ 1'b1; + + //No change to memory + + /*********************************/ + //If the FIFO is not near EMPTY or FULL + /*********************************/ + end else begin + + //No write + ideal_wr_ack <= #`TCQ 0; + ideal_full <= #`TCQ 1'b0; + ideal_almost_full <= #`TCQ 1'b0; + + //No read + ideal_valid <= #`TCQ 1'b0; + ideal_empty <= #`TCQ 1'b0; + ideal_almost_empty <= #`TCQ 1'b0; + + //No change to memory + + end // average case + + end // neither reading or writing + + num_read_words_q <= #`TCQ num_read_words; + num_write_words_q <= #`TCQ num_write_words; + + end //normal operating conditions + end + + end // block: gen_fifo + + + always @(posedge CLK or posedge RST_FULL_FF) begin : gen_fifo_p + + /****** Reset fifo - Async Reset****************************************/ + //The latency of de-assertion of the flags is reduced by 1 to be + // consistent with the core. + if (RST_FULL_FF) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + ideal_prog_empty <= #`TCQ 1'b1; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_empty_d <= #`TCQ 1'b1; + + end else begin + if (srst_i) begin + //SRST is available only for Sync BRAM and Sync DRAM. Not for SSHFT. + if (C_MEMORY_TYPE == 1 || C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) begin + ideal_prog_empty <= #`TCQ 1'b1; + prog_empty_d <= #`TCQ 1'b1; + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end + end else if ((srst_i_d1 || srst_i_d2) && (C_FULL_FLAGS_RST_VAL == 1)) begin + ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL; + prog_full_d <= #`TCQ C_FULL_FLAGS_RST_VAL; + end else begin + + /*************************************************************** + * Programmable FULL flags + ****************************************************************/ + //calculation for standard fifo and latency =2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + if (C_PROG_FULL_TYPE == 1) begin + if ((num_write_words >= C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if (((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL - 2) + && RD_EN && !WR_EN) || (RST_FULL_GEN)) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual constant thresholds + end else if (C_PROG_FULL_TYPE == 2) begin + if ((num_write_words == C_PROG_FULL_THRESH_ASSERT_VAL-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == C_PROG_FULL_THRESH_NEGATE_VAL - 2) + && RD_EN && !WR_EN) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_FULL_TYPE == 3) begin + if ((num_write_words == PROG_FULL_THRESH-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH - 2) + && !WR_EN && RD_EN) begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if ((num_write_words == PROG_FULL_THRESH_ASSERT-1 - 2) + && WR_EN && !RD_EN) begin + prog_full_d <= #`TCQ 1'b1; + end else if ((num_write_words == PROG_FULL_THRESH_NEGATE - 2) + && !WR_EN && RD_EN)begin + prog_full_d <= #`TCQ 1'b0; + end else if (num_write_words >= PROG_FULL_THRESH_ASSERT - 2) begin + prog_full_d <= #`TCQ 1'b1; + end else if (num_write_words < PROG_FULL_THRESH_NEGATE - 2) begin + prog_full_d <= #`TCQ 1'b0; + end + end + end // (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) + + /***************************************************************** + * Programmable EMPTY flags + ****************************************************************/ + //calculation for standard fifo and latency = 2 + if (! (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + //calculation for FWFT fifo + if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin + //Single constant threshold + if (C_PROG_EMPTY_TYPE == 1) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL - 2) + && WR_EN && !RD_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + //Dual constant thresholds + end else if (C_PROG_EMPTY_TYPE == 2) begin + if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == C_PROG_EMPTY_THRESH_NEGATE_VAL - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Single input threshold + end else if (C_PROG_EMPTY_TYPE == 3) begin + if ((num_read_words == PROG_EMPTY_THRESH+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end else if (num_read_words <= PROG_EMPTY_THRESH - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end + + //Dual input thresholds + end else begin + if (num_read_words <= PROG_EMPTY_THRESH_ASSERT - 2) begin + prog_empty_d <= #`TCQ 1'b1; + end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1 - 2) + && RD_EN && !WR_EN) begin + prog_empty_d <= #`TCQ 1'b1; + end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE - 2)begin + prog_empty_d <= #`TCQ 1'b0; + end else if ((num_read_words == PROG_EMPTY_THRESH_NEGATE - 2) + && !RD_EN && WR_EN) begin + prog_empty_d <= #`TCQ 1'b0; + end + end + end // (~ (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) ) + + ideal_prog_empty <= prog_empty_d; + if (RST_FULL_GEN) begin + ideal_prog_full <= #`TCQ 1'b0; + prog_full_d <= #`TCQ 1'b0; + end else begin + ideal_prog_full <= #`TCQ prog_full_d; + end + + end //if (srst_i) begin + end //if (rst_i) begin + end //always @(posedge CLK or posedge rst_i) begin : gen_fifo_p +endmodule // fifo_generator_v6_1_bhv_ver_ss + + + +/************************************************************************** + * First-Word Fall-Through module (preload 0) + **************************************************************************/ +module fifo_generator_v6_1_bhv_ver_preload0 + ( + RD_CLK, + RD_RST, + SRST, + RD_EN, + FIFOEMPTY, + FIFODATA, + FIFOSBITERR, + FIFODBITERR, + USERDATA, + USERVALID, + USERUNDERFLOW, + USEREMPTY, + USERALMOSTEMPTY, + RAMVALID, + FIFORDEN, + USERSBITERR, + USERDBITERR + ); + + parameter C_DOUT_RST_VAL = ""; + parameter C_DOUT_WIDTH = 8; + parameter C_HAS_RST = 0; + parameter C_ENABLE_RST_SYNC = 0; + parameter C_HAS_SRST = 0; + parameter C_USE_DOUT_RST = 0; + parameter C_USE_ECC = 0; + parameter C_USERVALID_LOW = 0; + parameter C_USERUNDERFLOW_LOW = 0; + parameter C_MEMORY_TYPE = 0; + + //Inputs + input RD_CLK; + input RD_RST; + input SRST; + input RD_EN; + input FIFOEMPTY; + input [C_DOUT_WIDTH-1:0] FIFODATA; + input FIFOSBITERR; + input FIFODBITERR; + + //Outputs + output [C_DOUT_WIDTH-1:0] USERDATA; + output USERVALID; + output USERUNDERFLOW; + output USEREMPTY; + output USERALMOSTEMPTY; + output RAMVALID; + output FIFORDEN; + output USERSBITERR; + output USERDBITERR; + + //Inputs + wire RD_CLK; + wire RD_RST; + wire RD_EN; + wire FIFOEMPTY; + wire [C_DOUT_WIDTH-1:0] FIFODATA; + wire FIFOSBITERR; + wire FIFODBITERR; + + //Outputs + reg [C_DOUT_WIDTH-1:0] USERDATA; + wire USERVALID; + wire USERUNDERFLOW; + wire USEREMPTY; + wire USERALMOSTEMPTY; + wire RAMVALID; + wire FIFORDEN; + reg USERSBITERR; + reg USERDBITERR; + + //Internal signals + wire preloadstage1; + wire preloadstage2; + reg ram_valid_i; + reg read_data_valid_i; + wire ram_regout_en; + wire ram_rd_en; + reg empty_i = 1'b1; + reg empty_q = 1'b1; + reg rd_en_q = 1'b0; + reg almost_empty_i = 1'b1; + reg almost_empty_q = 1'b1; + wire rd_rst_i; + wire srst_i; + + +/************************************************************************* +* FUNCTIONS +*************************************************************************/ + + /************************************************************************* + * hexstr_conv + * Converts a string of type hex to a binary value (for C_DOUT_RST_VAL) + ***********************************************************************/ + function [C_DOUT_WIDTH-1:0] hexstr_conv; + input [(C_DOUT_WIDTH*8)-1:0] def_data; + + integer index,i,j; + reg [3:0] bin; + + begin + index = 0; + hexstr_conv = 'b0; + for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) + begin + case (def_data[7:0]) + 8'b00000000 : + begin + bin = 4'b0000; + i = -1; + end + 8'b00110000 : bin = 4'b0000; + 8'b00110001 : bin = 4'b0001; + 8'b00110010 : bin = 4'b0010; + 8'b00110011 : bin = 4'b0011; + 8'b00110100 : bin = 4'b0100; + 8'b00110101 : bin = 4'b0101; + 8'b00110110 : bin = 4'b0110; + 8'b00110111 : bin = 4'b0111; + 8'b00111000 : bin = 4'b1000; + 8'b00111001 : bin = 4'b1001; + 8'b01000001 : bin = 4'b1010; + 8'b01000010 : bin = 4'b1011; + 8'b01000011 : bin = 4'b1100; + 8'b01000100 : bin = 4'b1101; + 8'b01000101 : bin = 4'b1110; + 8'b01000110 : bin = 4'b1111; + 8'b01100001 : bin = 4'b1010; + 8'b01100010 : bin = 4'b1011; + 8'b01100011 : bin = 4'b1100; + 8'b01100100 : bin = 4'b1101; + 8'b01100101 : bin = 4'b1110; + 8'b01100110 : bin = 4'b1111; + default : + begin + bin = 4'bx; + end + endcase + for( j=0; j<4; j=j+1) + begin + if ((index*4)+j < C_DOUT_WIDTH) + begin + hexstr_conv[(index*4)+j] = bin[j]; + end + end + index = index + 1; + def_data = def_data >> 8; + end + end + endfunction + + + //************************************************************************* + // Set power-on states for regs + //************************************************************************* + initial begin + ram_valid_i = 1'b0; + read_data_valid_i = 1'b0; + USERDATA = hexstr_conv(C_DOUT_RST_VAL); + USERSBITERR = 1'b0; + USERDBITERR = 1'b0; + end //initial + + //*************************************************************************** + // connect up optional reset + //*************************************************************************** + assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0; + assign srst_i = C_HAS_SRST ? SRST : 0; + + + //*************************************************************************** + // preloadstage2 indicates that stage2 needs to be updated. This is true + // whenever read_data_valid is false, and RAM_valid is true. + //*************************************************************************** + assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN); + + //*************************************************************************** + // preloadstage1 indicates that stage1 needs to be updated. This is true + // whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is + // false (indicating that Stage1 needs updating), or preloadstage2 is active + // (indicating that Stage2 is going to update, so Stage1, therefore, must + // also be updated to keep it valid. + //*************************************************************************** + assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY); + + //*************************************************************************** + // Calculate RAM_REGOUT_EN + // The output registers are controlled by the ram_regout_en signal. + // These registers should be updated either when the output in Stage2 is + // invalid (preloadstage2), OR when the user is reading, in which case the + // Stage2 value will go invalid unless it is replenished. + //*************************************************************************** + assign ram_regout_en = preloadstage2; + + //*************************************************************************** + // Calculate RAM_RD_EN + // RAM_RD_EN will be asserted whenever the RAM needs to be read in order to + // update the value in Stage1. + // One case when this happens is when preloadstage1=true, which indicates + // that the data in Stage1 or Stage2 is invalid, and needs to automatically + // be updated. + // The other case is when the user is reading from the FIFO, which + // guarantees that Stage1 or Stage2 will be invalid on the next clock + // cycle, unless it is replinished by data from the memory. So, as long + // as the RAM has data in it, a read of the RAM should occur. + //*************************************************************************** + assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1; + + //*************************************************************************** + // Calculate RAMVALID_P0_OUT + // RAMVALID_P0_OUT indicates that the data in Stage1 is valid. + // + // If the RAM is being read from on this clock cycle (ram_rd_en=1), then + // RAMVALID_P0_OUT is certainly going to be true. + // If the RAM is not being read from, but the output registers are being + // updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, + // therefore causing RAMVALID_P0_OUT to be false. + // Otherwise, RAMVALID_P0_OUT will remain unchanged. + //*************************************************************************** + // PROCESS regout_valid + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (srst_i) begin + // synchronous reset (active high) + ram_valid_i <= #`TCQ 1'b0; + end else begin + if (ram_rd_en == 1'b1) begin + ram_valid_i <= #`TCQ 1'b1; + end else begin + if (ram_regout_en == 1'b1) + ram_valid_i <= #`TCQ 1'b0; + else + ram_valid_i <= #`TCQ ram_valid_i; + end + end //srst_i + end //rd_rst_i + end //always + + //*************************************************************************** + // Calculate READ_DATA_VALID + // READ_DATA_VALID indicates whether the value in Stage2 is valid or not. + // Stage2 has valid data whenever Stage1 had valid data and + // ram_regout_en_i=1, such that the data in Stage1 is propogated + // into Stage2. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) + read_data_valid_i <= #`TCQ 1'b0; + else if (srst_i) + read_data_valid_i <= #`TCQ 1'b0; + else + read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN); + end //always + + + //************************************************************************** + // Calculate EMPTY + // Defined as the inverse of READ_DATA_VALID + // + // Description: + // + // If read_data_valid_i indicates that the output is not valid, + // and there is no valid data on the output of the ram to preload it + // with, then we will report empty. + // + // If there is no valid data on the output of the ram and we are + // reading, then the FIFO will go empty. + // + //************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) begin + if (rd_rst_i) begin + // asynchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + if (srst_i) begin + // synchronous reset (active high) + empty_i <= #`TCQ 1'b1; + end else begin + // rising clock edge + empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN); + end + end + end //always + + // Register RD_EN from user to calculate USERUNDERFLOW. + // Register empty_i to calculate USERUNDERFLOW. + always @ (posedge RD_CLK) begin + rd_en_q <= #`TCQ RD_EN; + empty_q <= #`TCQ empty_i; + end //always + + + //*************************************************************************** + // Calculate user_almost_empty + // user_almost_empty is defined such that, unless more words are written + // to the FIFO, the next read will cause the FIFO to go EMPTY. + // + // In most cases, whenever the output registers are updated (due to a user + // read or a preload condition), then user_almost_empty will update to + // whatever RAM_EMPTY is. + // + // The exception is when the output is valid, the user is not reading, and + // Stage1 is not empty. In this condition, Stage1 will be preloaded from the + // memory, so we need to make sure user_almost_empty deasserts properly under + // this condition. + //*************************************************************************** + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin // asynchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin // rising clock edge + if (srst_i) begin // synchronous reset (active high) + almost_empty_i <= #`TCQ 1'b1; + almost_empty_q <= #`TCQ 1'b1; + end else begin + if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin + almost_empty_i <= #`TCQ FIFOEMPTY; + end + almost_empty_q <= #`TCQ empty_i; + end + end + end //always + + + assign USEREMPTY = empty_i; + assign USERALMOSTEMPTY = almost_empty_i; + assign FIFORDEN = ram_rd_en; + assign RAMVALID = ram_valid_i; + assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i; + assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q; + + // BRAM resets synchronously + always @ (posedge RD_CLK) + begin + if (rd_rst_i || srst_i) begin + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end + end //always + + + always @ (posedge RD_CLK or posedge rd_rst_i) + begin + if (rd_rst_i) begin //asynchronous reset (active high) + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + // DRAM resets asynchronously + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin // rising clock edge + if (srst_i) begin + if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF + USERSBITERR <= #`TCQ 0; + USERDBITERR <= #`TCQ 0; + end + if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) + USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL); + end else begin + if (ram_regout_en) begin + USERDATA <= #`TCQ FIFODATA; + USERSBITERR <= #`TCQ FIFOSBITERR; + USERDBITERR <= #`TCQ FIFODBITERR; + end + end + end + end //always + +endmodule + diff --git a/fpga/usrp2/models/M24LC024B.v b/fpga/usrp2/models/M24LC024B.v index 45e04b450..5531f80fc 100644 --- a/fpga/usrp2/models/M24LC024B.v +++ b/fpga/usrp2/models/M24LC024B.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Modified 11/14/07 to simulate the 24lc024, which responds to the address pins // ******************************************************************************************************* diff --git a/fpga/usrp2/models/M24LC02B.v b/fpga/usrp2/models/M24LC02B.v index 4d9e2c6e2..00ed6f44a 100644 --- a/fpga/usrp2/models/M24LC02B.v +++ b/fpga/usrp2/models/M24LC02B.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // *******************************************************************************************************
// ** **
// ** M24LC02B.v - 24LC02B 2K-BIT I2C SERIAL EEPROM (VCC = +2.5V TO +5.5V) **
diff --git a/fpga/usrp2/models/MULT18X18S.v b/fpga/usrp2/models/MULT18X18S.v index 5d39eeaa6..3ce2a267a 100644 --- a/fpga/usrp2/models/MULT18X18S.v +++ b/fpga/usrp2/models/MULT18X18S.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Model of the Xilinx mult18x18s for signed 18x18 bit multiplies, // As in the Spartan 3 series diff --git a/fpga/usrp2/models/adc_model.v b/fpga/usrp2/models/adc_model.v index e5a3ee0d8..1d1f1c929 100644 --- a/fpga/usrp2/models/adc_model.v +++ b/fpga/usrp2/models/adc_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module adc_model (input clk, input rst, diff --git a/fpga/usrp2/models/cpld_model.v b/fpga/usrp2/models/cpld_model.v index c886433ae..900577852 100644 --- a/fpga/usrp2/models/cpld_model.v +++ b/fpga/usrp2/models/cpld_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module cpld_model (input aux_clk, input start, input mode, input done, diff --git a/fpga/usrp2/models/gpmc_model_async.v b/fpga/usrp2/models/gpmc_model_async.v index beeaee028..22b3cdf9f 100644 --- a/fpga/usrp2/models/gpmc_model_async.v +++ b/fpga/usrp2/models/gpmc_model_async.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ps/1ps module gpmc_model_async diff --git a/fpga/usrp2/models/gpmc_model_sync.v b/fpga/usrp2/models/gpmc_model_sync.v index 641720c15..0f66961e7 100644 --- a/fpga/usrp2/models/gpmc_model_sync.v +++ b/fpga/usrp2/models/gpmc_model_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module gpmc_model_sync diff --git a/fpga/usrp2/models/math_real.v b/fpga/usrp2/models/math_real.v index e30f68ee7..d88f72669 100644 --- a/fpga/usrp2/models/math_real.v +++ b/fpga/usrp2/models/math_real.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + /*
* This is a general recreation of the VHDL ieee.math_real package.
*/
diff --git a/fpga/usrp2/models/miim_model.v b/fpga/usrp2/models/miim_model.v index 936d99a80..8eb8e571d 100644 --- a/fpga/usrp2/models/miim_model.v +++ b/fpga/usrp2/models/miim_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Skeleton PHY interface simulator diff --git a/fpga/usrp2/models/serdes_model.v b/fpga/usrp2/models/serdes_model.v index f10e55554..5e1602163 100644 --- a/fpga/usrp2/models/serdes_model.v +++ b/fpga/usrp2/models/serdes_model.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module serdes_model (input ser_tx_clk, diff --git a/fpga/usrp2/models/uart_rx.v b/fpga/usrp2/models/uart_rx.v index f698a50fe..738ffb45b 100644 --- a/fpga/usrp2/models/uart_rx.v +++ b/fpga/usrp2/models/uart_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Simple printout of characters from the UART diff --git a/fpga/usrp2/models/xlnx_glbl.v b/fpga/usrp2/models/xlnx_glbl.v index 662a60e35..62e29fef4 100644 --- a/fpga/usrp2/models/xlnx_glbl.v +++ b/fpga/usrp2/models/xlnx_glbl.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module xlnx_glbl
(
GSR,
diff --git a/fpga/usrp2/sdr_lib/acc.v b/fpga/usrp2/sdr_lib/acc.v index a2da9c86d..d5fc4b910 100644 --- a/fpga/usrp2/sdr_lib/acc.v +++ b/fpga/usrp2/sdr_lib/acc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module acc #(parameter IWIDTH=16, OWIDTH=30) diff --git a/fpga/usrp2/sdr_lib/add2.v b/fpga/usrp2/sdr_lib/add2.v index 13fff803e..dcca84fd3 100644 --- a/fpga/usrp2/sdr_lib/add2.v +++ b/fpga/usrp2/sdr_lib/add2.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module add2 #(parameter WIDTH=16) diff --git a/fpga/usrp2/sdr_lib/add2_and_round.v b/fpga/usrp2/sdr_lib/add2_and_round.v index 146af28da..7c347527c 100644 --- a/fpga/usrp2/sdr_lib/add2_and_round.v +++ b/fpga/usrp2/sdr_lib/add2_and_round.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module add2_and_round #(parameter WIDTH=16) diff --git a/fpga/usrp2/sdr_lib/add2_and_round_reg.v b/fpga/usrp2/sdr_lib/add2_and_round_reg.v index e7fcbf1a1..5c783bda3 100644 --- a/fpga/usrp2/sdr_lib/add2_and_round_reg.v +++ b/fpga/usrp2/sdr_lib/add2_and_round_reg.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module add2_and_round_reg #(parameter WIDTH=16) diff --git a/fpga/usrp2/sdr_lib/add2_reg.v b/fpga/usrp2/sdr_lib/add2_reg.v index 456cf315b..58d822a61 100644 --- a/fpga/usrp2/sdr_lib/add2_reg.v +++ b/fpga/usrp2/sdr_lib/add2_reg.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module add2_reg #(parameter WIDTH=16) diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx.v b/fpga/usrp2/sdr_lib/dsp_core_rx.v index a315234cf..0e69e53f7 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_rx.v +++ b/fpga/usrp2/sdr_lib/dsp_core_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module dsp_core_rx #(parameter BASE = 160) diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx_old.v b/fpga/usrp2/sdr_lib/dsp_core_rx_old.v index ba301e91b..90d5d839f 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_rx_old.v +++ b/fpga/usrp2/sdr_lib/dsp_core_rx_old.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `define DSP_CORE_RX_BASE 160 module dsp_core_rx_old diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx_udp.v b/fpga/usrp2/sdr_lib/dsp_core_rx_udp.v index 1e689fc7f..08dab37e6 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_rx_udp.v +++ b/fpga/usrp2/sdr_lib/dsp_core_rx_udp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module dsp_core_rx #(parameter BASE = 160) diff --git a/fpga/usrp2/sdr_lib/dsp_core_tx.v b/fpga/usrp2/sdr_lib/dsp_core_tx.v index 79d92c9b3..58bd82f6e 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_tx.v +++ b/fpga/usrp2/sdr_lib/dsp_core_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module dsp_core_tx #(parameter BASE=0) diff --git a/fpga/usrp2/sdr_lib/dummy_rx.v b/fpga/usrp2/sdr_lib/dummy_rx.v index 99290ecec..b22d5f896 100644 --- a/fpga/usrp2/sdr_lib/dummy_rx.v +++ b/fpga/usrp2/sdr_lib/dummy_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `define DSP_CORE_RX_BASE 160 module dummy_rx diff --git a/fpga/usrp2/sdr_lib/halfband_ideal.v b/fpga/usrp2/sdr_lib/halfband_ideal.v index 484cfff2a..e0b04cf86 100644 --- a/fpga/usrp2/sdr_lib/halfband_ideal.v +++ b/fpga/usrp2/sdr_lib/halfband_ideal.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module halfband_ideal ( input clock, input reset, diff --git a/fpga/usrp2/sdr_lib/halfband_tb.v b/fpga/usrp2/sdr_lib/halfband_tb.v index 231dd00d7..80f46fe36 100644 --- a/fpga/usrp2/sdr_lib/halfband_tb.v +++ b/fpga/usrp2/sdr_lib/halfband_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module halfband_tb( ) ; // Parameters for instantiation diff --git a/fpga/usrp2/sdr_lib/hb/acc.v b/fpga/usrp2/sdr_lib/hb/acc.v index 195d5ea94..d7be895c6 100644 --- a/fpga/usrp2/sdr_lib/hb/acc.v +++ b/fpga/usrp2/sdr_lib/hb/acc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module acc (input clock, input reset, input clear, input enable_in, output reg enable_out, diff --git a/fpga/usrp2/sdr_lib/hb/coeff_ram.v b/fpga/usrp2/sdr_lib/hb/coeff_ram.v index 65460822f..525c22abc 100644 --- a/fpga/usrp2/sdr_lib/hb/coeff_ram.v +++ b/fpga/usrp2/sdr_lib/hb/coeff_ram.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module coeff_ram (input clock, input [3:0] rd_addr, output reg [15:0] rd_data); diff --git a/fpga/usrp2/sdr_lib/hb/coeff_rom.v b/fpga/usrp2/sdr_lib/hb/coeff_rom.v index 7f8886b4e..a43c8391a 100644 --- a/fpga/usrp2/sdr_lib/hb/coeff_rom.v +++ b/fpga/usrp2/sdr_lib/hb/coeff_rom.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module coeff_rom (input clock, input [2:0] addr, output reg [15:0] data); diff --git a/fpga/usrp2/sdr_lib/hb/halfband_interp.v b/fpga/usrp2/sdr_lib/hb/halfband_interp.v index cdb11c1f6..83bdc9fad 100644 --- a/fpga/usrp2/sdr_lib/hb/halfband_interp.v +++ b/fpga/usrp2/sdr_lib/hb/halfband_interp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module halfband_interp diff --git a/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v b/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v index 01ab5e7e0..450f90e66 100644 --- a/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v +++ b/fpga/usrp2/sdr_lib/hb/hbd_tb/test_hbd.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module test_hbd(); diff --git a/fpga/usrp2/sdr_lib/hb/mac.v b/fpga/usrp2/sdr_lib/hb/mac.v index 5a270bc73..8058a6db4 100644 --- a/fpga/usrp2/sdr_lib/hb/mac.v +++ b/fpga/usrp2/sdr_lib/hb/mac.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module mac (input clock, input reset, input enable, input clear, diff --git a/fpga/usrp2/sdr_lib/hb/mult.v b/fpga/usrp2/sdr_lib/hb/mult.v index a8d4cb1b7..a50ae69e2 100644 --- a/fpga/usrp2/sdr_lib/hb/mult.v +++ b/fpga/usrp2/sdr_lib/hb/mult.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module mult (input clock, input signed [15:0] x, input signed [15:0] y, output reg signed [30:0] product, diff --git a/fpga/usrp2/sdr_lib/hb/ram16_2port.v b/fpga/usrp2/sdr_lib/hb/ram16_2port.v index e1761a926..631cf5a41 100644 --- a/fpga/usrp2/sdr_lib/hb/ram16_2port.v +++ b/fpga/usrp2/sdr_lib/hb/ram16_2port.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ram16_2port (input clock, input write, diff --git a/fpga/usrp2/sdr_lib/hb/ram16_2sum.v b/fpga/usrp2/sdr_lib/hb/ram16_2sum.v index 559b06fd5..f9ec1837e 100644 --- a/fpga/usrp2/sdr_lib/hb/ram16_2sum.v +++ b/fpga/usrp2/sdr_lib/hb/ram16_2sum.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ram16_2sum (input clock, input write, diff --git a/fpga/usrp2/sdr_lib/hb/ram32_2sum.v b/fpga/usrp2/sdr_lib/hb/ram32_2sum.v index d1f55b7d0..f7032835e 100644 --- a/fpga/usrp2/sdr_lib/hb/ram32_2sum.v +++ b/fpga/usrp2/sdr_lib/hb/ram32_2sum.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ram32_2sum (input clock, input write, diff --git a/fpga/usrp2/sdr_lib/hb_dec.v b/fpga/usrp2/sdr_lib/hb_dec.v index 8fb5ba222..9747f0adb 100644 --- a/fpga/usrp2/sdr_lib/hb_dec.v +++ b/fpga/usrp2/sdr_lib/hb_dec.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Final halfband decimator // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] // Strobe in cannot come faster than every 2nd clock cycle diff --git a/fpga/usrp2/sdr_lib/hb_dec_tb.v b/fpga/usrp2/sdr_lib/hb_dec_tb.v index 3e5faa80a..256f6085d 100644 --- a/fpga/usrp2/sdr_lib/hb_dec_tb.v +++ b/fpga/usrp2/sdr_lib/hb_dec_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module hb_dec_tb( ) ; // Parameters for instantiation diff --git a/fpga/usrp2/sdr_lib/hb_interp.v b/fpga/usrp2/sdr_lib/hb_interp.v index d16807e15..deb4fe056 100644 --- a/fpga/usrp2/sdr_lib/hb_interp.v +++ b/fpga/usrp2/sdr_lib/hb_interp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // First halfband iterpolator // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 0 A] // Strobe in cannot come faster than every 4th clock cycle, diff --git a/fpga/usrp2/sdr_lib/hb_interp_tb.v b/fpga/usrp2/sdr_lib/hb_interp_tb.v index 52f137f28..239412155 100644 --- a/fpga/usrp2/sdr_lib/hb_interp_tb.v +++ b/fpga/usrp2/sdr_lib/hb_interp_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module hb_interp_tb( ) ; // Parameters for instantiation diff --git a/fpga/usrp2/sdr_lib/hb_tb.v b/fpga/usrp2/sdr_lib/hb_tb.v index 7e960fd13..3260ac738 100644 --- a/fpga/usrp2/sdr_lib/hb_tb.v +++ b/fpga/usrp2/sdr_lib/hb_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module hb_tb(); diff --git a/fpga/usrp2/sdr_lib/integrate.v b/fpga/usrp2/sdr_lib/integrate.v index db33de979..ce674d470 100644 --- a/fpga/usrp2/sdr_lib/integrate.v +++ b/fpga/usrp2/sdr_lib/integrate.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module integrate #(parameter INPUTW = 16, parameter ACCUMW = 32, diff --git a/fpga/usrp2/sdr_lib/med_hb_int.v b/fpga/usrp2/sdr_lib/med_hb_int.v index bc8066509..f619dc81b 100644 --- a/fpga/usrp2/sdr_lib/med_hb_int.v +++ b/fpga/usrp2/sdr_lib/med_hb_int.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Medium halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0 C 0 D 0.5 D 0 C 0 B 0 A] // diff --git a/fpga/usrp2/sdr_lib/rssi.v b/fpga/usrp2/sdr_lib/rssi.v index e45e2148c..e931ff865 100644 --- a/fpga/usrp2/sdr_lib/rssi.v +++ b/fpga/usrp2/sdr_lib/rssi.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module rssi (input clock, input reset, input enable, diff --git a/fpga/usrp2/sdr_lib/rx_control.v b/fpga/usrp2/sdr_lib/rx_control.v index 0adeb0794..12f411ffe 100644 --- a/fpga/usrp2/sdr_lib/rx_control.v +++ b/fpga/usrp2/sdr_lib/rx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `define DSP_CORE_RX_BASE 160 diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset.v b/fpga/usrp2/sdr_lib/rx_dcoffset.v index bedbd40e6..64ff4110d 100644 --- a/fpga/usrp2/sdr_lib/rx_dcoffset.v +++ b/fpga/usrp2/sdr_lib/rx_dcoffset.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module rx_dcoffset diff --git a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v index a8b4ec20f..b0dd8cb05 100644 --- a/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v +++ b/fpga/usrp2/sdr_lib/rx_dcoffset_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns/1ns module rx_dcoffset_tb(); diff --git a/fpga/usrp2/sdr_lib/small_hb_dec.v b/fpga/usrp2/sdr_lib/small_hb_dec.v index 8519b628a..151b8c287 100644 --- a/fpga/usrp2/sdr_lib/small_hb_dec.v +++ b/fpga/usrp2/sdr_lib/small_hb_dec.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Short halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0.5 B 0 A] // diff --git a/fpga/usrp2/sdr_lib/small_hb_dec_tb.v b/fpga/usrp2/sdr_lib/small_hb_dec_tb.v index 0d6a0689e..1e713321a 100644 --- a/fpga/usrp2/sdr_lib/small_hb_dec_tb.v +++ b/fpga/usrp2/sdr_lib/small_hb_dec_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module hb_dec_tb( ) ; // Parameters for instantiation diff --git a/fpga/usrp2/sdr_lib/small_hb_int.v b/fpga/usrp2/sdr_lib/small_hb_int.v index f80d3cac3..387f9e1cb 100644 --- a/fpga/usrp2/sdr_lib/small_hb_int.v +++ b/fpga/usrp2/sdr_lib/small_hb_int.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Short halfband decimator (intended to be followed by another stage) // Implements impulse responses of the form [A 0 B 0.5 B 0 A] // diff --git a/fpga/usrp2/sdr_lib/small_hb_int_tb.v b/fpga/usrp2/sdr_lib/small_hb_int_tb.v index 71d77f0a8..fe1e1a7dd 100644 --- a/fpga/usrp2/sdr_lib/small_hb_int_tb.v +++ b/fpga/usrp2/sdr_lib/small_hb_int_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module small_hb_int_tb( ) ; // Parameters for instantiation diff --git a/fpga/usrp2/sdr_lib/tx_control.v b/fpga/usrp2/sdr_lib/tx_control.v index e5fed0b93..e6866a40c 100644 --- a/fpga/usrp2/sdr_lib/tx_control.v +++ b/fpga/usrp2/sdr_lib/tx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `define DSP_CORE_TX_BASE 128 diff --git a/fpga/usrp2/serdes/serdes.v b/fpga/usrp2/serdes/serdes.v index 17049bfe6..edbc46419 100644 --- a/fpga/usrp2/serdes/serdes.v +++ b/fpga/usrp2/serdes/serdes.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // SERDES TX and RX along with all flow control logic diff --git a/fpga/usrp2/serdes/serdes_fc_rx.v b/fpga/usrp2/serdes/serdes_fc_rx.v index 4dd46e27f..9ea32cf8d 100644 --- a/fpga/usrp2/serdes/serdes_fc_rx.v +++ b/fpga/usrp2/serdes/serdes_fc_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module serdes_fc_rx diff --git a/fpga/usrp2/serdes/serdes_fc_tx.v b/fpga/usrp2/serdes/serdes_fc_tx.v index 2fe967c8d..0a62ae2e5 100644 --- a/fpga/usrp2/serdes/serdes_fc_tx.v +++ b/fpga/usrp2/serdes/serdes_fc_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module serdes_fc_tx diff --git a/fpga/usrp2/serdes/serdes_rx.v b/fpga/usrp2/serdes/serdes_rx.v index b6688e858..1950d4e2a 100644 --- a/fpga/usrp2/serdes/serdes_rx.v +++ b/fpga/usrp2/serdes/serdes_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // SERDES Interface diff --git a/fpga/usrp2/serdes/serdes_tb.v b/fpga/usrp2/serdes/serdes_tb.v index eb8e019fc..685a8580d 100644 --- a/fpga/usrp2/serdes/serdes_tb.v +++ b/fpga/usrp2/serdes/serdes_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // FIXME need to add flow control diff --git a/fpga/usrp2/serdes/serdes_tx.v b/fpga/usrp2/serdes/serdes_tx.v index 2e5e3bd80..0cd077e5c 100644 --- a/fpga/usrp2/serdes/serdes_tx.v +++ b/fpga/usrp2/serdes/serdes_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // SERDES Interface diff --git a/fpga/usrp2/simple_gemac/address_filter.v b/fpga/usrp2/simple_gemac/address_filter.v index 50a52b954..bf6194600 100644 --- a/fpga/usrp2/simple_gemac/address_filter.v +++ b/fpga/usrp2/simple_gemac/address_filter.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module address_filter diff --git a/fpga/usrp2/simple_gemac/address_filter_promisc.v b/fpga/usrp2/simple_gemac/address_filter_promisc.v index 6047e7c93..3ff05fbe1 100644 --- a/fpga/usrp2/simple_gemac/address_filter_promisc.v +++ b/fpga/usrp2/simple_gemac/address_filter_promisc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module address_filter_promisc diff --git a/fpga/usrp2/simple_gemac/crc.v b/fpga/usrp2/simple_gemac/crc.v index ac019083a..ef62f8ff8 100644 --- a/fpga/usrp2/simple_gemac/crc.v +++ b/fpga/usrp2/simple_gemac/crc.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module crc
(input clk,
diff --git a/fpga/usrp2/simple_gemac/delay_line.v b/fpga/usrp2/simple_gemac/delay_line.v index d371bb9c5..5a559a504 100644 --- a/fpga/usrp2/simple_gemac/delay_line.v +++ b/fpga/usrp2/simple_gemac/delay_line.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module delay_line diff --git a/fpga/usrp2/simple_gemac/eth_tasks.v b/fpga/usrp2/simple_gemac/eth_tasks.v index d49f30e24..731fd6d52 100644 --- a/fpga/usrp2/simple_gemac/eth_tasks.v +++ b/fpga/usrp2/simple_gemac/eth_tasks.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + task SendFlowCtrl; diff --git a/fpga/usrp2/simple_gemac/eth_tasks_f19.v b/fpga/usrp2/simple_gemac/eth_tasks_f19.v index ff3ae5407..3ff23a413 100644 --- a/fpga/usrp2/simple_gemac/eth_tasks_f19.v +++ b/fpga/usrp2/simple_gemac/eth_tasks_f19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + task SendFlowCtrl; diff --git a/fpga/usrp2/simple_gemac/eth_tasks_f36.v b/fpga/usrp2/simple_gemac/eth_tasks_f36.v index dc64971d4..dee651d80 100644 --- a/fpga/usrp2/simple_gemac/eth_tasks_f36.v +++ b/fpga/usrp2/simple_gemac/eth_tasks_f36.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + task SendFlowCtrl; diff --git a/fpga/usrp2/simple_gemac/ethrx_realign.v b/fpga/usrp2/simple_gemac/ethrx_realign.v index 0a369c914..a08feb91e 100644 --- a/fpga/usrp2/simple_gemac/ethrx_realign.v +++ b/fpga/usrp2/simple_gemac/ethrx_realign.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // NOTE: Will not work with single-line frames diff --git a/fpga/usrp2/simple_gemac/ethtx_realign.v b/fpga/usrp2/simple_gemac/ethtx_realign.v index be53abf4c..236b2d4e1 100644 --- a/fpga/usrp2/simple_gemac/ethtx_realign.v +++ b/fpga/usrp2/simple_gemac/ethtx_realign.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + //////////////////////////////////////////////////////////////////////// // Ethernet TX - Realign diff --git a/fpga/usrp2/simple_gemac/flow_ctrl_rx.v b/fpga/usrp2/simple_gemac/flow_ctrl_rx.v index d09bf377f..aa12875f2 100644 --- a/fpga/usrp2/simple_gemac/flow_ctrl_rx.v +++ b/fpga/usrp2/simple_gemac/flow_ctrl_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // RX side of flow control -- when we are running out of RX space, send a PAUSE
diff --git a/fpga/usrp2/simple_gemac/flow_ctrl_tx.v b/fpga/usrp2/simple_gemac/flow_ctrl_tx.v index f80f5a76d..bdc1e4701 100644 --- a/fpga/usrp2/simple_gemac/flow_ctrl_tx.v +++ b/fpga/usrp2/simple_gemac/flow_ctrl_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // TX side of flow control -- when other side sends PAUSE, we wait
diff --git a/fpga/usrp2/simple_gemac/ll8_to_txmac.v b/fpga/usrp2/simple_gemac/ll8_to_txmac.v index 3530a0c59..ac81afa63 100644 --- a/fpga/usrp2/simple_gemac/ll8_to_txmac.v +++ b/fpga/usrp2/simple_gemac/ll8_to_txmac.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module ll8_to_txmac (input clk, input reset, input clear, diff --git a/fpga/usrp2/simple_gemac/rxmac_to_ll8.v b/fpga/usrp2/simple_gemac/rxmac_to_ll8.v index 5ec233d95..5acb08bb7 100644 --- a/fpga/usrp2/simple_gemac/rxmac_to_ll8.v +++ b/fpga/usrp2/simple_gemac/rxmac_to_ll8.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module rxmac_to_ll8 (input clk, input reset, input clear, diff --git a/fpga/usrp2/simple_gemac/simple_gemac.v b/fpga/usrp2/simple_gemac/simple_gemac.v index 2dd8deb99..ec13d3c96 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac.v +++ b/fpga/usrp2/simple_gemac/simple_gemac.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac (input clk125, input reset, diff --git a/fpga/usrp2/simple_gemac/simple_gemac_rx.v b/fpga/usrp2/simple_gemac/simple_gemac_rx.v index 32f517bb3..e6c0424bd 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_rx.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_rx diff --git a/fpga/usrp2/simple_gemac/simple_gemac_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_tb.v index 6091751a7..ed7d796dc 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_tb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_tb; diff --git a/fpga/usrp2/simple_gemac/simple_gemac_tx.v b/fpga/usrp2/simple_gemac/simple_gemac_tx.v index dd870d04d..ecabc3dad 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_tx.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_tx (input clk125, input reset, diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wb.v b/fpga/usrp2/simple_gemac/simple_gemac_wb.v index 1ef38be11..bcf18f9a8 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module wb_reg #(parameter ADDR=0, diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v index 8390eb2c6..9763578b9 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_wrapper #(parameter RXFIFOSIZE=9, diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v index 2ac8b9be1..3e1793d82 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_wrapper19 #(parameter RXFIFOSIZE=9, diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v index b61d60d30..78f525fd7 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_wrapper19_tb; diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v index 804fa8748..2904e38d4 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_f36_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_wrapper_f36_tb; diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v index 0aadc7e93..5a3f3f832 100644 --- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v +++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_gemac_wrapper_tb; diff --git a/fpga/usrp2/top/single_u2_sim/single_u2_sim.v b/fpga/usrp2/testbench/single_u2_sim.v index 2a7b24849..f25374613 100644 --- a/fpga/usrp2/top/single_u2_sim/single_u2_sim.v +++ b/fpga/usrp2/testbench/single_u2_sim.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/timing/simple_timer.v b/fpga/usrp2/timing/simple_timer.v index 17c7f1c36..56ba8ffe8 100644 --- a/fpga/usrp2/timing/simple_timer.v +++ b/fpga/usrp2/timing/simple_timer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module simple_timer diff --git a/fpga/usrp2/timing/time_64bit.v b/fpga/usrp2/timing/time_64bit.v index 8122cc6ea..d32f4220b 100644 --- a/fpga/usrp2/timing/time_64bit.v +++ b/fpga/usrp2/timing/time_64bit.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module time_64bit diff --git a/fpga/usrp2/timing/time_compare.v b/fpga/usrp2/timing/time_compare.v index cb2b6d860..54ea000d6 100644 --- a/fpga/usrp2/timing/time_compare.v +++ b/fpga/usrp2/timing/time_compare.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Top 32 bits are integer seconds, bottom 32 are clock ticks within a second diff --git a/fpga/usrp2/timing/time_receiver.v b/fpga/usrp2/timing/time_receiver.v index 897f71186..a03337552 100644 --- a/fpga/usrp2/timing/time_receiver.v +++ b/fpga/usrp2/timing/time_receiver.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module time_receiver (input clk, input rst, diff --git a/fpga/usrp2/timing/time_sender.v b/fpga/usrp2/timing/time_sender.v index f4ee5226a..fdf6b1240 100644 --- a/fpga/usrp2/timing/time_sender.v +++ b/fpga/usrp2/timing/time_sender.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module time_sender diff --git a/fpga/usrp2/timing/time_sync.v b/fpga/usrp2/timing/time_sync.v index c0c8e195f..a823e9e1b 100644 --- a/fpga/usrp2/timing/time_sync.v +++ b/fpga/usrp2/timing/time_sync.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module time_sync diff --git a/fpga/usrp2/timing/time_transfer_tb.v b/fpga/usrp2/timing/time_transfer_tb.v index 0c164f82c..288540702 100644 --- a/fpga/usrp2/timing/time_transfer_tb.v +++ b/fpga/usrp2/timing/time_transfer_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps diff --git a/fpga/usrp2/timing/timer.v b/fpga/usrp2/timing/timer.v index 70c9746be..216a9294c 100644 --- a/fpga/usrp2/timing/timer.v +++ b/fpga/usrp2/timing/timer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module timer diff --git a/fpga/usrp2/top/u1e_passthru/.gitignore b/fpga/usrp2/top/B100/.gitignore index 1b2211df0..1b2211df0 100644 --- a/fpga/usrp2/top/u1e_passthru/.gitignore +++ b/fpga/usrp2/top/B100/.gitignore diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile new file mode 100644 index 000000000..ca6ec9320 --- /dev/null +++ b/fpga/usrp2/top/B100/Makefile @@ -0,0 +1,97 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +BUILD_DIR := build/ +export TOP_MODULE := u1plus +export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../gpif/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan3A" \ +device XC3S1400A \ +package ft256 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1plus.v \ +u1plus_core.v \ +u1plus.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPIF_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile new file mode 100755 index 000000000..b2ccc8b49 --- /dev/null +++ b/fpga/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf new file mode 100644 index 000000000..b2a455f6d --- /dev/null +++ b/fpga/usrp2/top/B100/timing.ucf @@ -0,0 +1,5 @@ +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + +NET "IFCLK" TNM_NET = "IFCLK"; +TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; diff --git a/fpga/usrp2/top/B100/u1plus.ucf b/fpga/usrp2/top/B100/u1plus.ucf new file mode 100644 index 000000000..cd89878e3 --- /dev/null +++ b/fpga/usrp2/top/B100/u1plus.ucf @@ -0,0 +1,203 @@ +## Main Clock +NET "CLK_FPGA_P" LOC = "R7" ; +NET "CLK_FPGA_N" LOC = "T7" ; + +## UART +NET "FPGA_TXD" LOC = "H16" ; +NET "FPGA_RXD" LOC = "H12" ; + +## I2C +NET "SDA_FPGA" LOC = "T13" ; +NET "SCL_FPGA" LOC = "R13" ; + +## CGEN +NET "cgen_st_ld" LOC = "M13" ; +NET "cgen_st_refmon" LOC = "J14" ; +NET "cgen_st_status" LOC = "P6" ; +NET "cgen_ref_sel" LOC = "T2" ; +NET "cgen_sync_b" LOC = "H15" ; + +## FPGA Config +#NET "fpga_cfg_din" LOC = "T14" ; +#NET "fpga_cfg_cclk" LOC = "R14" ; +#NET "fpga_cfg_init_b" LOC = "T12" ; + +## MISC +#NET "mystery_bus<2>" LOC = "T11" ; +#NET "mystery_bus<1>" LOC = "C4" ; +#NET "mystery_bus<0>" LOC = "E7" ; +NET "reset_n" LOC = "D5" ; +NET "PPS_IN" LOC = "M14" ; +NET "reset_codec" LOC = "B14" ; + +## GPIF +NET "GPIF_D<15>" LOC = "P7" ; +NET "GPIF_D<14>" LOC = "N8" ; +NET "GPIF_D<13>" LOC = "T5" ; +NET "GPIF_D<12>" LOC = "T6" ; +NET "GPIF_D<11>" LOC = "N6" ; +NET "GPIF_D<10>" LOC = "P5" ; +NET "GPIF_D<9>" LOC = "R3" ; +NET "GPIF_D<8>" LOC = "T3" ; +NET "GPIF_D<7>" LOC = "N12" ; +NET "GPIF_D<6>" LOC = "P13" ; +NET "GPIF_D<5>" LOC = "P11" ; +NET "GPIF_D<4>" LOC = "R9" ; +NET "GPIF_D<3>" LOC = "T9" ; +NET "GPIF_D<2>" LOC = "N9" ; +NET "GPIF_D<1>" LOC = "P9" ; +NET "GPIF_D<0>" LOC = "P8" ; + +NET "GPIF_CTL<3>" LOC = "N5" ; +NET "GPIF_CTL<2>" LOC = "M11" ; +NET "GPIF_CTL<1>" LOC = "M9" ; +NET "GPIF_CTL<0>" LOC = "M7" ; + +NET "GPIF_RDY<3>" LOC = "N11" ; +NET "GPIF_RDY<2>" LOC = "T10" ; +NET "GPIF_RDY<1>" LOC = "T4" ; +NET "GPIF_RDY<0>" LOC = "R5" ; + +NET "FX2_PA7_FLAGD" LOC = "P12" ; +NET "FX2_PA6_PKTEND" LOC = "R11" ; +NET "FX2_PA2_SLOE" LOC = "P10" ; + +NET "IFCLK" LOC = "T8" ; + +## LEDs +NET "debug_led<2>" LOC = "R2" ; +NET "debug_led<1>" LOC = "N4" ; +NET "debug_led<0>" LOC = "P4" ; + +## Debug bus +NET "debug_clk<0>" LOC = "K15" ; +NET "debug_clk<1>" LOC = "K14" ; +NET "debug<0>" LOC = "K16" ; +NET "debug<1>" LOC = "J16" ; +NET "debug<2>" LOC = "C16" ; +NET "debug<3>" LOC = "C15" ; +NET "debug<4>" LOC = "E13" ; +NET "debug<5>" LOC = "D14" ; +NET "debug<6>" LOC = "D16" ; +NET "debug<7>" LOC = "D15" ; +NET "debug<8>" LOC = "E14" ; +NET "debug<9>" LOC = "F13" ; +NET "debug<10>" LOC = "G13" ; +NET "debug<11>" LOC = "F14" ; +NET "debug<12>" LOC = "E16" ; +NET "debug<13>" LOC = "F15" ; +NET "debug<14>" LOC = "H13" ; +NET "debug<15>" LOC = "G14" ; +NET "debug<16>" LOC = "G16" ; +NET "debug<17>" LOC = "F16" ; +NET "debug<18>" LOC = "J12" ; +NET "debug<19>" LOC = "J13" ; +NET "debug<20>" LOC = "L14" ; +NET "debug<21>" LOC = "L16" ; +NET "debug<22>" LOC = "M15" ; +NET "debug<23>" LOC = "M16" ; +NET "debug<24>" LOC = "L13" ; +NET "debug<25>" LOC = "K13" ; +NET "debug<26>" LOC = "P16" ; +NET "debug<27>" LOC = "N16" ; +NET "debug<28>" LOC = "R15" ; +NET "debug<29>" LOC = "P15" ; +NET "debug<30>" LOC = "N13" ; +NET "debug<31>" LOC = "N14" ; + +## ADC +NET "adc<11>" LOC = "B15" ; +NET "adc<10>" LOC = "A8" ; +NET "adc<9>" LOC = "B8" ; +NET "adc<8>" LOC = "C8" ; +NET "adc<7>" LOC = "D8" ; +NET "adc<6>" LOC = "C9" ; +NET "adc<5>" LOC = "A9" ; +NET "adc<4>" LOC = "C10" ; +NET "adc<3>" LOC = "D9" ; +NET "adc<2>" LOC = "A3" ; +NET "adc<1>" LOC = "B3" ; +NET "adc<0>" LOC = "A4" ; +NET "RXSYNC" LOC = "D10" ; + +## DAC +NET "TXBLANK" LOC = "K1" ; +NET "TXSYNC" LOC = "J2" ; +NET "dac<0>" LOC = "J1" ; +NET "dac<1>" LOC = "H3" ; +NET "dac<2>" LOC = "J3" ; +NET "dac<3>" LOC = "G2" ; +NET "dac<4>" LOC = "H1" ; +NET "dac<5>" LOC = "N3" ; +NET "dac<6>" LOC = "M4" ; +NET "dac<7>" LOC = "R1" ; +NET "dac<8>" LOC = "P2" ; +NET "dac<9>" LOC = "P1" ; +NET "dac<10>" LOC = "M1" ; +NET "dac<11>" LOC = "N1" ; +NET "dac<12>" LOC = "M3" ; +NET "dac<13>" LOC = "L4" ; + +## TX DB +NET "io_tx<0>" LOC = "K4" ; +NET "io_tx<1>" LOC = "L3" ; +NET "io_tx<2>" LOC = "L2" ; +NET "io_tx<3>" LOC = "F1" ; +NET "io_tx<4>" LOC = "F3" ; +NET "io_tx<5>" LOC = "G3" ; +NET "io_tx<6>" LOC = "E3" ; +NET "io_tx<7>" LOC = "E2" ; +NET "io_tx<8>" LOC = "E4" ; +NET "io_tx<9>" LOC = "F4" ; +NET "io_tx<10>" LOC = "D1" ; +NET "io_tx<11>" LOC = "E1" ; +NET "io_tx<12>" LOC = "D4" ; +NET "io_tx<13>" LOC = "D3" ; +NET "io_tx<14>" LOC = "C2" ; +NET "io_tx<15>" LOC = "C1" ; + +## RX DB +NET "io_rx<0>" LOC = "D7" ; +NET "io_rx<1>" LOC = "C6" ; +NET "io_rx<2>" LOC = "A6" ; +NET "io_rx<3>" LOC = "B6" ; +NET "io_rx<4>" LOC = "E9" ; +NET "io_rx<5>" LOC = "A7" ; +NET "io_rx<6>" LOC = "C7" ; +NET "io_rx<7>" LOC = "B10" ; +NET "io_rx<8>" LOC = "A10" ; +NET "io_rx<9>" LOC = "C11" ; +NET "io_rx<10>" LOC = "A11" ; +NET "io_rx<11>" LOC = "D11" ; +NET "io_rx<12>" LOC = "B12" ; +NET "io_rx<13>" LOC = "A12" ; +NET "io_rx<14>" LOC = "A14" ; +NET "io_rx<15>" LOC = "A13" ; + +## SPI +#NET "SEN_AUX" LOC = "C12" ; +#NET "SCLK_AUX" LOC = "D12" ; +#NET "MISO_AUX" LOC = "J5" ; +NET "SCLK_CODEC" LOC = "K3" ; +NET "SEN_CODEC" LOC = "D13" ; +NET "MOSI_CODEC" LOC = "C13" ; +NET "MISO_CODEC" LOC = "G4" ; + +NET "MISO_RX_DB" LOC = "E6" ; +NET "SEN_RX_DB" LOC = "B4" ; +NET "MOSI_RX_DB" LOC = "A5" ; +NET "SCLK_RX_DB" LOC = "C5" ; + +NET "MISO_TX_DB" LOC = "J4" ; +NET "SEN_TX_DB" LOC = "N2" ; +NET "MOSI_TX_DB" LOC = "L1" ; +NET "SCLK_TX_DB" LOC = "G1" ; + +## Dedicated pins +#NET "TMS" LOC = "B2" ; +#NET "TDO" LOC = "B16" ; +#NET "TDI" LOC = "B1" ; +#NET "TCK" LOC = "A15" ; + +##NET "fpga_cfg_prog_b" LOC = "A2" ; +##NET "fpga_cfg_done" LOC = "T15" ; diff --git a/fpga/usrp2/top/B100/u1plus.v b/fpga/usrp2/top/B100/u1plus.v new file mode 100644 index 000000000..5e3200580 --- /dev/null +++ b/fpga/usrp2/top/B100/u1plus.v @@ -0,0 +1,173 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module u1plus + (input CLK_FPGA_P, input CLK_FPGA_N, // Diff + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output FPGA_TXD, input FPGA_RXD, + + // GPIF + inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, + output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE, + input IFCLK, + + inout SDA_FPGA, inout SCL_FPGA, // I2C + + output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI + output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI + output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + + inout [15:0] io_tx, inout [15:0] io_rx, + + output [13:0] dac, output TXSYNC, output TXBLANK, + input [11:0] adc, input RXSYNC, + + input PPS_IN, + input reset_n, output reset_codec + ); + + assign reset_codec = 1; // Believed to be active low + + // ///////////////////////////////////////////////////////////////////////// + // Clocking + wire clk_fpga, clk_fpga_in, reset; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); + + BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); + + reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset)); + + // ///////////////////////////////////////////////////////////////////////// + // SPI + wire mosi, sclk, miso; + assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0; + assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0; + assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | + (~SEN_CODEC & MISO_CODEC); + + // ///////////////////////////////////////////////////////////////////////// + // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL + + assign TXBLANK = 0; + wire [13:0] tx_i, tx_q; + + genvar i; + generate + for(i=0;i<14;i=i+1) + begin : gen_dacout + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(tx_i[i]), // 1-bit data input (associated with C0) + .D1(tx_q[i]), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_dacout + endgenerate + ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b0), // 1-bit data input (associated with C0) + .D1(1'b1), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + // ///////////////////////////////////////////////////////////////////////// + // RX ADC -- handles deinterleaving + + reg [11:0] rx_i, rx_q; + wire [11:0] rx_a, rx_b; + + genvar j; + generate + for(j=0;j<12;j=j+1) + begin : gen_adcin + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock + .Q1(rx_b[j]), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(adc[j]), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + end // block: gen_adcin + endgenerate + + IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" + .INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 + .INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 + .SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset + IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock + .Q1(rxsync_1), // 1-bit output captured with C1 clock + .C0(clk_fpga), // 1-bit clock input + .C1(~clk_fpga), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D(RXSYNC), // 1-bit DDR data input + .R(1'b0), // 1-bit reset input + .S(1'b0)); // 1-bit set input + + always @(posedge clk_fpga) + if(rxsync_0) + begin + rx_i <= rx_b; + rx_q <= rx_a; + end + else + begin + rx_i <= rx_a; + rx_q <= rx_b; + end + + // ///////////////////////////////////////////////////////////////////////// + // Main U1E Core + u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset), + .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), + .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), + .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), + .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}), + .gpif_clk(IFCLK), + + .db_sda(SDA_FPGA), .db_scl(SCL_FPGA), + .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso), + .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), + .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), + .io_tx(io_tx), .io_rx(io_rx), + .tx_i(tx_i), .tx_q(tx_q), + .rx_i(rx_i), .rx_q(rx_q), + .pps_in(PPS_IN) ); + +endmodule // u1plus diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v new file mode 100644 index 000000000..8a02f0fb8 --- /dev/null +++ b/fpga/usrp2/top/B100/u1plus_core.v @@ -0,0 +1,409 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module u1plus_core + (input clk_fpga, input rst_fpga, + output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, + output debug_txd, input debug_rxd, + + // GPIF + inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy, + output [2:0] gpif_misc, input gpif_clk, + + inout db_sda, inout db_scl, + output sclk, output [15:0] sen, output mosi, input miso, + + input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, + output tx_underrun, output rx_overrun, + inout [15:0] io_tx, inout [15:0] io_rx, + output [13:0] tx_i, output [13:0] tx_q, + input [11:0] rx_i, input [11:0] rx_q, + input pps_in + ); + + localparam TXFIFOSIZE = 11; + localparam RXFIFOSIZE = 11; + + // 64 total regs in address space + localparam SR_RX_CTRL = 0; // 9 regs (+0 to +8) + localparam SR_RX_DSP = 16; // 7 regs (+0 to +6) + localparam SR_TX_CTRL = 24; // 6 regs (+0 to +5) + localparam SR_TX_DSP = 32; // 5 regs (+0 to +4) + localparam SR_TIME64 = 40; // 6 regs (+0 to +5) + localparam SR_CLEAR_RX_FIFO = 48; // 1 reg + localparam SR_CLEAR_TX_FIFO = 49; // 1 reg + localparam SR_GLOBAL_RESET = 50; // 1 reg + localparam SR_REG_TEST32 = 52; // 1 reg + + wire [7:0] COMPAT_NUM = 8'd3; + + wire wb_clk = clk_fpga; + wire wb_rst, global_reset; + + wire pps_int; + wire [63:0] vita_time, vita_time_pps; + reg [15:0] reg_leds, reg_cgen_ctrl, reg_test, xfer_rate; + wire [7:0] test_rate; + wire [3:0] test_ctrl; + + wire [7:0] set_addr; + wire [31:0] set_data; + wire set_stb; + + wire [31:0] debug0; + wire [31:0] debug1; + + wire [31:0] debug_vt; + wire gpif_rst; + + wire rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc; + reg [7:0] frames_per_packet; + + assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp; + assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp; + + setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(global_reset)); + + reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst)); + reset_sync reset_sync_gp(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst)); + wire [15:0] test_len; + + // ///////////////////////////////////////////////////////////////////////////////////// + // GPIF Slave to Wishbone Master + localparam dw = 16; + localparam aw = 11; + localparam sw = 2; + + wire [dw-1:0] m0_dat_mosi, m0_dat_miso; + wire [aw-1:0] m0_adr; + wire [sw-1:0] m0_sel; + wire m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty; + + wire [31:0] debug_gpmc; + + wire [35:0] tx_data, rx_data, tx_err_data; + wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, + tx_err_src_rdy, tx_err_dst_rdy; + + wire bus_error; + wire clear_tx, clear_rx; + + setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_rx)); + + setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(),.changed(clear_tx)); + + gpif #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) + gpif (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d), + .gpif_ctl(gpif_ctl), .gpif_rdy(gpif_rdy), .gpif_misc(gpif_misc), + + .wb_clk(wb_clk), .wb_rst(wb_rst), + .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso), + .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we), + .wb_ack_i(m0_ack), .triggers(8'd0), + + .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx), + .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy), + .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy), + .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy), + + .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc), + + .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl), + .debug0(debug0), .debug1(debug1)); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX + wire [31:0] sample_rx; + wire strobe_rx, run_rx; + wire [31:0] debug_rx_dsp, vr_debug; + + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + (.clk(wb_clk),.rst(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .adc_a({rx_i,2'b0}),.adc_ovf_a(0),.adc_b({rx_q,2'b0}),.adc_ovf_b(0), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .debug(debug_rx_dsp) ); + + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(rx_overrun_dsp), + .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), + .rx_data_o(rx_data), .rx_dst_rdy_i(rx_dst_rdy), .rx_src_rdy_o(rx_src_rdy), + .debug(vr_debug) ); + + // /////////////////////////////////////////////////////////////////////////////////// + // DSP TX + + wire [15:0] tx_i_int, tx_q_int; + wire run_tx; + + vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), + .REPORT_ERROR(1), .DO_FLOW_CONTROL(0), + .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0), + .DSP_NUMBER(0)) + vita_tx_chain + (.clk(wb_clk), .reset(wb_rst), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), + .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy), + .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy), + .dac_a(tx_i_int),.dac_b(tx_q_int), + .underrun(tx_underrun_dsp), .run(run_tx), + .debug(debug_vt)); + + assign tx_i = tx_i_int[15:2]; + assign tx_q = tx_q_int[15:2]; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Wishbone Intercon, single master + wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso, + s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso, + s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso, + sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso; + wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; + wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr; + wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel; + wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel; + wire s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack; + wire s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack; + wire s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb; + wire s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb; + wire s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc; + wire s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc; + wire s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we; + wire s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we; + + wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4), + .s0_addr(4'h0), .s0_mask(4'hF), .s1_addr(4'h1), .s1_mask(4'hF), + .s2_addr(4'h2), .s2_mask(4'hF), .s3_addr(4'h3), .s3_mask(4'hF), + .s4_addr(4'h4), .s4_mask(4'hF), .s5_addr(4'h5), .s5_mask(4'hF), + .s6_addr(4'h6), .s6_mask(4'hF), .s7_addr(4'h7), .s7_mask(4'hF), + .s8_addr(4'h8), .s8_mask(4'hE), .s9_addr(4'hf), .s9_mask(4'hF), // slave 8 is double wide + .sa_addr(4'ha), .sa_mask(4'hF), .sb_addr(4'hb), .sb_mask(4'hF), + .sc_addr(4'hc), .sc_mask(4'hF), .sd_addr(4'hd), .sd_mask(4'hF), + .se_addr(4'he), .se_mask(4'hF), .sf_addr(4'hf), .sf_mask(4'hF)) + wb_1master + (.clk_i(wb_clk),.rst_i(wb_rst), + .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi), + .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), + .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), + .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0), + .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), + .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0), + .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), + .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0), + .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), + .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0), + .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), + .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0), + .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), + .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0), + .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), + .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0), + .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), + .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0), + .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), + .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0), + .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), + .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0), + .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb), + .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0), + .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb), + .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0), + .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb), + .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0), + .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb), + .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0), + .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb), + .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0), + .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb), + .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) ); + + assign s5_ack = 0; assign s9_ack = 0; assign sa_ack = 0; assign sb_ack = 0; + assign sc_ack = 0; assign sd_ack = 0; assign se_ack = 0; assign sf_ack = 0; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 0, Misc LEDs, Switches, controls + + localparam REG_LEDS = 7'd0; // out + localparam REG_CGEN_CTRL = 7'd4; // out + localparam REG_CGEN_ST = 7'd6; // in + localparam REG_TEST = 7'd8; // out + localparam REG_RX_FRAMELEN = 7'd10; // in + localparam REG_TX_FRAMELEN = 7'd12; // out + localparam REG_XFER_RATE = 7'd14; // out + localparam REG_COMPAT = 7'd16; // in + + always @(posedge wb_clk) + if(wb_rst) + begin + reg_leds <= 0; + reg_cgen_ctrl <= 2'b11; + reg_test <= 0; + xfer_rate <= 0; + frames_per_packet <= 0; + end + else + if(s0_cyc & s0_stb & s0_we) + case(s0_adr[6:0]) + REG_LEDS : + reg_leds <= s0_dat_mosi; + REG_CGEN_CTRL : + reg_cgen_ctrl <= s0_dat_mosi; + REG_TEST : + reg_test <= s0_dat_mosi; + REG_RX_FRAMELEN : + frames_per_packet <= s0_dat_mosi[7:0]; + REG_XFER_RATE : + xfer_rate <= s0_dat_mosi; + endcase // case (s0_adr[6:0]) + + assign test_ctrl = xfer_rate[11:8]; + assign test_rate = xfer_rate[7:0]; + assign test_len = reg_test[15:0]; + + assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds; // LEDs are arranged funny on board + assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl; + + assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : + (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : + (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : + (s0_adr[6:0] == REG_TEST) ? reg_test : + (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : + 16'hBEEF; + + assign s0_ack = s0_stb & s0_cyc; + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 1, UART + // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock + + simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart + (.clk_i(wb_clk),.rst_i(wb_rst), + .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), + .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), + .rx_int_o(),.tx_int_o(), + .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Slave 2, SPI + + spi_top16 shared_spi + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi), + .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), + .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(), + .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) ); + + // ///////////////////////////////////////////////////////////////////////// + // Slave 3, I2C + + wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o; + i2c_master_top #(.ARST_LVL(1)) i2c + (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), + .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]), + .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), + .wb_ack_o(s3_ack),.wb_inta_o(), + .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), + .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); + + assign s3_dat_miso[15:8] = 8'd0; + + // I2C -- Don't use external transistors for open drain, the FPGA implements this + IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o)); + IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o)); + + // ///////////////////////////////////////////////////////////////////////// + // GPIOs -- Slave #4 + + wire [31:0] atr_lines; + wire [31:0] debug_gpio_0, debug_gpio_1; + + nsgpio16LE + nsgpio16LE(.clk_i(wb_clk),.rst_i(wb_rst), + .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), + .dat_i(s4_dat_mosi),.dat_o(s4_dat_miso),.ack_o(s4_ack), + .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), + .gpio( {io_tx,io_rx} ) ); + + // ///////////////////////////////////////////////////////////////////////// + // Settings Bus -- Slave #8 + 9 + + // only have 64 regs, 32 bits each with current setup... + settings_bus_16LE #(.AWIDTH(11),.RWIDTH(6)) settings_bus_16LE + (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr[10:0]),.wb_dat_i(s8_dat_mosi), + .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack), + .strobe(set_stb),.addr(set_addr),.data(set_data) ); + + // ///////////////////////////////////////////////////////////////////////// + // ATR Controller -- Slave #6 + + atr_controller16 atr_controller16 + (.clk_i(wb_clk), .rst_i(wb_rst), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), + .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); + + // ///////////////////////////////////////////////////////////////////////// + // Readback mux 32 -- Slave #7 + + wire [31:0] reg_test32; + + setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 + (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(reg_test32),.changed()); + + wb_readback_mux_16LE readback_mux_32 + (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + + .word00(vita_time[63:32]), .word01(vita_time[31:0]), + .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), + .word04(reg_test32), .word05(32'b0), + .word06(32'b0), .word07(32'b0), + .word08(32'b0), .word09(32'b0), + .word10(32'b0), .word11(32'b0), + .word12(32'b0), .word13(32'b0), + .word14(32'b0), .word15(32'b0) + ); + + // ///////////////////////////////////////////////////////////////////////// + // VITA Timing + + time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit + (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); + + // ///////////////////////////////////////////////////////////////////////////////////// + // Debug circuitry + + assign debug_clk = { gpif_clk, clk_fpga }; + assign debug = debug0; + assign debug_gpio_0 = 0; + assign debug_gpio_1 = 0; + //assign {io_tx,io_rx} = {debug1}; + +endmodule // u1plus_core diff --git a/fpga/usrp2/top/u1e/.gitignore b/fpga/usrp2/top/E1x0/.gitignore index 8d872713e..8d872713e 100644 --- a/fpga/usrp2/top/u1e/.gitignore +++ b/fpga/usrp2/top/E1x0/.gitignore diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/E1x0/Makefile index 5d721979b..5d721979b 100644 --- a/fpga/usrp2/top/u1e/Makefile +++ b/fpga/usrp2/top/E1x0/Makefile diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/E1x0/Makefile.passthru index f2d835608..f2d835608 100644 --- a/fpga/usrp2/top/u1e_passthru/Makefile +++ b/fpga/usrp2/top/E1x0/Makefile.passthru diff --git a/fpga/usrp2/top/u1e/README b/fpga/usrp2/top/E1x0/README index 14c7a4955..14c7a4955 100644 --- a/fpga/usrp2/top/u1e/README +++ b/fpga/usrp2/top/E1x0/README diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/E1x0/cmdfile index 291c723b8..291c723b8 100644 --- a/fpga/usrp2/top/u1e/cmdfile +++ b/fpga/usrp2/top/E1x0/cmdfile diff --git a/fpga/usrp2/top/u1e/core_compile b/fpga/usrp2/top/E1x0/core_compile index dc0cd081e..dc0cd081e 100755 --- a/fpga/usrp2/top/u1e/core_compile +++ b/fpga/usrp2/top/E1x0/core_compile diff --git a/fpga/usrp2/top/u1e/make.sim b/fpga/usrp2/top/E1x0/make.sim index 1c163884c..1c163884c 100644 --- a/fpga/usrp2/top/u1e/make.sim +++ b/fpga/usrp2/top/E1x0/make.sim diff --git a/fpga/usrp2/top/u1e_passthru/passthru.ucf b/fpga/usrp2/top/E1x0/passthru.ucf index 64e6f0440..64e6f0440 100644 --- a/fpga/usrp2/top/u1e_passthru/passthru.ucf +++ b/fpga/usrp2/top/E1x0/passthru.ucf diff --git a/fpga/usrp2/top/E1x0/passthru.v b/fpga/usrp2/top/E1x0/passthru.v new file mode 100644 index 000000000..486257366 --- /dev/null +++ b/fpga/usrp2/top/E1x0/passthru.v @@ -0,0 +1,35 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// + +module passthru + (input overo_gpio145, + output cgen_sclk, + output cgen_sen_b, + output cgen_mosi, + input fpga_cfg_din, + input fpga_cfg_cclk + ); + + assign cgen_sclk = fpga_cfg_cclk; + assign cgen_sen_b = overo_gpio145; + assign cgen_mosi = fpga_cfg_din; + + +endmodule // passthru diff --git a/fpga/usrp2/top/u1e/tb_u1e.v b/fpga/usrp2/top/E1x0/tb_u1e.v index 5fc8134fb..188190f04 100644 --- a/fpga/usrp2/top/u1e/tb_u1e.v +++ b/fpga/usrp2/top/E1x0/tb_u1e.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ps / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf index 8df28c9d3..8df28c9d3 100644 --- a/fpga/usrp2/top/u1e/timing.ucf +++ b/fpga/usrp2/top/E1x0/timing.ucf diff --git a/fpga/usrp2/top/u1e/u1e.ucf b/fpga/usrp2/top/E1x0/u1e.ucf index 0c487a601..0c487a601 100644 --- a/fpga/usrp2/top/u1e/u1e.ucf +++ b/fpga/usrp2/top/E1x0/u1e.ucf diff --git a/fpga/usrp2/top/u1e/u1e.v b/fpga/usrp2/top/E1x0/u1e.v index 445b14a03..adf42fd07 100644 --- a/fpga/usrp2/top/u1e/u1e.v +++ b/fpga/usrp2/top/E1x0/u1e.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v index d10a3ab30..4c513587b 100644 --- a/fpga/usrp2/top/u1e/u1e_core.v +++ b/fpga/usrp2/top/E1x0/u1e_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module u1e_core diff --git a/fpga/usrp2/top/u2plus/.gitignore b/fpga/usrp2/top/N2x0/.gitignore index 1b2211df0..1b2211df0 100644 --- a/fpga/usrp2/top/u2plus/.gitignore +++ b/fpga/usrp2/top/N2x0/.gitignore diff --git a/fpga/usrp2/top/u2plus/Makefile.N200 b/fpga/usrp2/top/N2x0/Makefile.N200R3 index 9175f9304..a525836ed 100644 --- a/fpga/usrp2/top/u2plus/Makefile.N200 +++ b/fpga/usrp2/top/N2x0/Makefile.N200R3 @@ -6,7 +6,7 @@ # Project Setup ################################################## TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)-N200) +BUILD_DIR = $(abspath build$(ISE)-N200R3) ################################################## # Include other makefiles diff --git a/fpga/usrp2/top/u1e_ethdebug/Makefile b/fpga/usrp2/top/N2x0/Makefile.N200R4 index 751b52970..0ca40e1bd 100644 --- a/fpga/usrp2/top/u1e_ethdebug/Makefile +++ b/fpga/usrp2/top/N2x0/Makefile.N200R4 @@ -5,14 +5,26 @@ ################################################## # Project Setup ################################################## -TOP_MODULE = u1e -BUILD_DIR = $(abspath build$(ISE)) +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N200R4) ################################################## # Include other makefiles ################################################## include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + ################################################## # Project Properties @@ -20,8 +32,8 @@ include ../Makefile.common export PROJECT_PROPERTIES := \ family "Spartan-3A DSP" \ device xc3sd1800a \ -package cs484 \ -speed -4 \ +package fg676 \ +speed -5 \ top_level_module_type "HDL" \ synthesis_tool "XST (VHDL/Verilog)" \ simulator "ISE Simulator (VHDL/Verilog)" \ @@ -33,10 +45,15 @@ simulator "ISE Simulator (VHDL/Verilog)" \ # Sources ################################################## TOP_SRCS = \ -u1e.v \ -u1e.ucf +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf -SOURCES = $(abspath $(TOP_SRCS)) +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) ################################################## # Process Properties @@ -49,7 +66,8 @@ SYNTHESIZE_PROPERTIES = \ "Register Balancing" Yes \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" @@ -77,7 +95,6 @@ GEN_PROG_FILE_PROPERTIES = \ "Create Binary Configuration File" TRUE \ "Done (Output Events)" 5 \ "Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 \ -"Unused IOB Pins" "Pull Up" +"Enable Outputs (Output Events)" 6 SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/N2x0/Makefile.N210R3 index 38400ce62..e29251e1c 100644 --- a/fpga/usrp2/top/u2plus/Makefile +++ b/fpga/usrp2/top/N2x0/Makefile.N210R3 @@ -6,7 +6,7 @@ # Project Setup ################################################## TOP_MODULE = u2plus -BUILD_DIR = $(abspath build$(ISE)) +BUILD_DIR = $(abspath build$(ISE)-N210R3) ################################################## # Include other makefiles diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R4 b/fpga/usrp2/top/N2x0/Makefile.N210R4 new file mode 100644 index 000000000..01a9e19fd --- /dev/null +++ b/fpga/usrp2/top/N2x0/Makefile.N210R4 @@ -0,0 +1,100 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u2plus +BUILD_DIR = $(abspath build$(ISE)-N210R4) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extramfifo/Makefile.srcs + + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd3400a \ +package fg676 \ +speed -5 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +capture_ddrlvds.v \ +u2plus_core.v \ +u2plus.v \ +u2plus.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto \ +"Verilog Macros" "LVDS=1" + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 + +SIM_MODEL_PROPERTIES = "" diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/N2x0/bootloader.rmi index e5be670fb..e5be670fb 100644 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ b/fpga/usrp2/top/N2x0/bootloader.rmi diff --git a/fpga/usrp2/top/N2x0/capture_ddrlvds.v b/fpga/usrp2/top/N2x0/capture_ddrlvds.v new file mode 100644 index 000000000..e261dcbe8 --- /dev/null +++ b/fpga/usrp2/top/N2x0/capture_ddrlvds.v @@ -0,0 +1,55 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module capture_ddrlvds + #(parameter WIDTH=7) + (input clk, + input ssclk_p, + input ssclk_n, + input [WIDTH-1:0] in_p, + input [WIDTH-1:0] in_n, + output reg [(2*WIDTH)-1:0] out); + + wire [WIDTH-1:0] ddr_dat; + wire ssclk; + wire [(2*WIDTH)-1:0] out_pre1; + reg [(2*WIDTH)-1:0] out_pre2; + + IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) + clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); + + genvar i; + generate + for(i = 0; i < WIDTH; i = i + 1) + begin : gen_lvds_pins + IBUFDS #(.IOSTANDARD("LVDS_33"),.DIFF_TERM("FALSE")) ibufds + (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); + IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 + (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), + .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); + end + endgenerate + + always @(posedge clk) + out_pre2 <= out_pre1; + + always @(posedge clk) + out <= out_pre2; + +endmodule // capture_ddrlvds diff --git a/fpga/usrp2/top/u2plus/u2plus.ucf b/fpga/usrp2/top/N2x0/u2plus.ucf index 5fbe55c26..5fbe55c26 100755 --- a/fpga/usrp2/top/u2plus/u2plus.ucf +++ b/fpga/usrp2/top/N2x0/u2plus.ucf diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/N2x0/u2plus.v index 7c2270df6..be6cdeeca 100644 --- a/fpga/usrp2/top/u2plus/u2plus.v +++ b/fpga/usrp2/top/N2x0/u2plus.v @@ -1,4 +1,22 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps +//`define LVDS 1 //`define DCM_FOR_RAMCLK ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v index ee5d7efcd..8a7c6ddee 100644 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ b/fpga/usrp2/top/N2x0/u2plus_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // //////////////////////////////////////////////////////////////////////////////// // Module Name: u2_core // //////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u2_rev3/.gitignore b/fpga/usrp2/top/USRP2/.gitignore index f50a2b7e5..f50a2b7e5 100644 --- a/fpga/usrp2/top/u2_rev3/.gitignore +++ b/fpga/usrp2/top/USRP2/.gitignore diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/USRP2/Makefile index e9b43491a..e9b43491a 100644 --- a/fpga/usrp2/top/u2_rev3/Makefile +++ b/fpga/usrp2/top/USRP2/Makefile diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v index 0e6120ec6..ca9762ac5 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/USRP2/u2_core.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // //////////////////////////////////////////////////////////////////////////////// // Module Name: u2_core // //////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/USRP2/u2_rev3.ucf index 8017f61ff..8017f61ff 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf +++ b/fpga/usrp2/top/USRP2/u2_rev3.ucf diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/USRP2/u2_rev3.v index bc7ae5f16..4b0bb5541 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.v +++ b/fpga/usrp2/top/USRP2/u2_rev3.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// diff --git a/fpga/usrp2/top/eth_test/.gitignore b/fpga/usrp2/top/eth_test/.gitignore deleted file mode 100644 index b30397081..000000000 --- a/fpga/usrp2/top/eth_test/.gitignore +++ /dev/null @@ -1,43 +0,0 @@ -/xst -/_ngo -/_xmsgs -/*.stx -/*.tspec -/*.xml -/*.gyd -/*.ngr -/*.tim -/*.err -/*.lso -/*.bld -/*.cmd_log -/*.ise_ISE_Backup -/*.mfd -/*.vm6 -/*.syr -/*.xst -/*.csv -/*.html -/*.jed -/*.pad -/*.ng* -/*.pnx -/*.rpt -/*.prj -/*_html -/*_log -/*.lfp -/*.bit -/*.bin -/*.vcd -/*.unroutes -/*.drc -/*_map.* -/*_guide.* -/*.twr -/*.twx -/a.out -/*.xpi -/*_pad.txt -/*.bgn -/*.par diff --git a/fpga/usrp2/top/eth_test/eth_sim_top.v b/fpga/usrp2/top/eth_test/eth_sim_top.v deleted file mode 100644 index 640a4e60f..000000000 --- a/fpga/usrp2/top/eth_test/eth_sim_top.v +++ /dev/null @@ -1,437 +0,0 @@ -////////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_basic -////////////////////////////////////////////////////////////////////////////////// - -module eth_sim_top - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output led1, - output led2, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - input PHY_RESETn, - input PHY_CLK, // possibly use on-board osc - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_oen_a, - output adc_pdn_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_oen_b, - output adc_pdn_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] ser_debug; - - ////////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - parameter dw = 32; // Data bus width - parameter aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - parameter sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i; - wire [aw-1:0] m0_adr, m1_adr, s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr; - wire [sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel, s5_sel, s6_sel, s7_sel; - wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack, s5_ack, s6_ack, s7_ack; - wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb, s5_stb, s6_stb, s7_stb; - wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc, s5_cyc, s6_cyc, s7_cyc; - wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err, s5_err, s6_err, s7_err; - wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty, s5_rty, s6_rty, s7_rty; - wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we, s7_we; - - wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01), - .s27_addr_w(4),.s2_addr(4'b1000),.s3_addr(4'b1001),.s4_addr(4'b1010), - .s5_addr(4'b1011),.s6_addr(4'b1100),.s7_addr(4'b1101), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty) - ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - wire iram_wr_stb, iram_rd_stb, iram_wr_ack, iram_rd_ack, iram_ack, iram_wr_we; - wire [3:0] iram_wr_sel; - wire [aw-1:0] iram_wr_adr, iram_rd_adr; - wire [dw-1:0] iram_wr_dat, iram_rd_dat; - - wire bus_error, proc_int; - - assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0; - assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack; - - ram_loader #(.AWIDTH(16)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start), - .mode_o(cpld_mode), - .done_o(cpld_done), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(iram_wr_dat),.wb_adr_o(iram_wr_adr), - .wb_stb_o(iram_wr_stb),.wb_cyc_o(),.wb_sel_o(iram_wr_sel), - .wb_we_o(iram_wr_we),.wb_ack_i(iram_wr_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iram_rd_stb),.iwb_adr_o(iram_rd_adr), - .iwb_dat_i(iram_rd_dat),.iwb_ack_i(iram_rd_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - assign proc_int = 1'b0; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - ram_wb_harvard #(.AWIDTH(14)) - ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .iwb_adr_i(ram_loader_done ? iram_rd_adr : iram_wr_adr),.iwb_dat_i(iram_wr_dat),.iwb_dat_o(iram_rd_dat), - .iwb_we_i(iram_wr_we),.iwb_ack_o(iram_ack),.iwb_stb_i(ram_loader_done ? iram_rd_stb : iram_wr_stb), - .iwb_sel_i(ram_loader_done ? 4'b1111 : iram_wr_sel), - - .dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - // Buffer Pool, slave #1 - wire rd0_read, rd0_ready, rd0_done, rd0_empty; - wire rd1_read, rd1_ready, rd1_done, rd1_empty; - wire rd2_read, rd2_ready, rd2_done, rd2_empty; - wire rd3_read, rd3_ready, rd3_done, rd3_empty; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - -/* - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk),.stream_rst(dsp_rst), - // Write Interfaces - .wr0_dat_i(),.wr0_write_i(),.wr0_done_i(),.wr0_ready_o(),.wr0_full_o(), - .wr1_dat_i(),.wr1_write_i(),.wr1_done_i(),.wr1_ready_o(),.wr1_full_o(), - .wr2_dat_i(),.wr2_write_i(),.wr2_done_i(),.wr2_ready_o(),.wr2_full_o(), - .wr3_dat_i(),.wr3_write_i(),.wr3_done_i(),.wr3_ready_o(),.wr3_full_o(), - // Read Interfaces - .rd0_dat_o(rd0_dat),.rd0_read_i(rd0_read),.rd0_done_i(),.rd0_ready_o(rd0_ready),.rd0_empty_o(rd0_empty), - .rd1_dat_o(rd1_dat),.rd1_read_i(rd1_read),.rd1_done_i(),.rd1_ready_o(rd1_ready),.rd1_empty_o(rd1_empty), - .rd2_dat_o(rd2_dat),.rd2_read_i(rd2_read),.rd2_done_i(),.rd2_ready_o(rd2_ready),.rd2_empty_o(rd2_empty), - .rd3_dat_o(rd3_dat),.rd3_read_i(rd3_read),.rd3_done_i(),.rd3_ready_o(rd3_ready),.rd3_empty_o(rd3_empty) - ); -*/ - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i), - .wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack), - - .wb_err_o(s2_err),.wb_int_o(s2_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr),.wb_dat_i(s3_dat_o),.wb_dat_o(s3_dat_i), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(st_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d; - assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d; - - simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a), - .gpio(/* io_tx[7:0]*/) ); - - simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b), - .gpio(/* io_tx[15:8] */) ); - - simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c), - .gpio(/* io_rx[7:0] */) ); - - simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we), - .dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d), - .gpio(/* io_rx[15:8]*/) ); - - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Output control lines, SLAVE #5 - wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0]; - assign {led2, led1} = misc_outs[1:0]; - - wb_output_pins32 control_lines - (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s5_dat_o),.wb_dat_o(s5_dat_i), - .wb_we_i(s5_we),.wb_sel_i(s5_sel),.wb_stb_i(s5_stb),.wb_ack_o(s5_ack),.wb_cyc_i(s5_cyc), - .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Ethernet slave, #6 - eth_wrapper eth_wrapper - (.Reset(wb_rst),.Clk_125M(),.Clk_user(stream_clk),.Clk_reg(wb_clk),.Speed(), - .Gtx_clk(GMII_GTX_CLK),.Rx_clk(GMII_RX_CLK),.Tx_clk(GMII_TX_CLK),//used only in MII mode - .Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),.Rx_er(GMII_RX_ER), - .Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),.Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - // FIFO Interfaces - .wr_dat_o(),.wr_write_o(),.wr_done_o(),.wr_ready_i(),.wr_full_i(), - .rd_dat_i(),.rd_read_o(),.rd_done_o(),.rd_ready_i(),.rd_empty_i(), - // Wishbone - .wb_dat_i(s6_dat_o),.wb_dat_o(s6_dat_i),.wb_adr_i(s6_adr),.wb_stb_i(s6_stb),.wb_we_i(s6_we),.wb_ack_o(s6_ack) - ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - /////////////////////////////////////////////////////////////////////////// - // DSP - reg [13:0] adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2; - reg adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; - - always @(posedge dsp_clk) - begin - adc_a_reg1 <= adc_a; - adc_a_reg2 <= adc_a_reg1; - adc_b_reg1 <= adc_b; - adc_b_reg2 <= adc_b_reg1; - adc_ovf_a_reg1 <= adc_ovf_a; - adc_ovf_a_reg2 <= adc_ovf_a_reg1; - adc_ovf_b_reg1 <= adc_ovf_b; - adc_ovf_b_reg2 <= adc_ovf_b_reg1; - end // always @ (posedge dsp_clk) - - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .rx_dat_o(wr1_dat),.rx_write_o(wr1_write),.rx_done_o(wr1_done), - .rx_ready_i(wr1_ready),.rx_full_i(wr1_full), - .overrun() ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .tx_dat_i(rd1_dat),.tx_read_o(rd1_read),.tx_done_o(rd1_done), - .tx_ready_i(rd1_ready),.tx_empty_i(rd1_empty), - .underrun() ); - - assign dsp_rst = wb_rst; - - ///////////////////////////////////////////////////////////////////////////////////// - // SERDES - serdes_tx serdes_tx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .fifo_data_i(rd0_dat),.fifo_read_o(rd0_read),.fifo_done_o(rd0_done), - .fifo_ready_i(rd0_ready),.fifo_empty_i(rd0_empty) - ); - - serdes_rx serdes_rx - (.clk(dsp_clk),.rst(dsp_rst), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .fifo_data_o(wr0_dat),.fifo_wr_o(wr0_write),.fifo_ready_i(wr0_ready),.fifo_done_i(wr0_done) - ); - - // Debug Pins - wire [31:0] debug1={{1'b0,ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,wb_rst,dsp_rst}, - {1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached}, - {8'hAF}, - {2'b0, clk_status, sen_dac, sen_clk, sclk, mosi, miso}}; - - wire [31:0] debug_wb={{iram_wr_we,ram_loader_done,clock_ready,iram_wr_ack,iram_wr_stb,ram_loader_rst,wb_rst,dsp_rst}, - {iram_rd_adr[15:8]}, - {iram_rd_adr[7:0]}, - {serdes_outs}}; - - assign io_rx = ser_debug[31:16]; - assign io_tx = ser_debug[15:0]; - - assign debug = debug_wb; - - assign debug_clk[0] = wb_clk; - assign debug_clk[1] = dsp_clk; - -endmodule // eth_test - - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v") -// verilog-library-extensions:(".v" ".h") -// End: diff --git a/fpga/usrp2/top/eth_test/eth_tb.v b/fpga/usrp2/top/eth_test/eth_tb.v deleted file mode 100644 index 451ce1e7e..000000000 --- a/fpga/usrp2/top/eth_test/eth_tb.v +++ /dev/null @@ -1,257 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -// Nearly everything is an input - -module eth_tb(); - // Misc, debug - wire led1; - wire led2; - wire [31:0] debug; - wire [1:0] debug_clk; - - // Expansion - wire exp_pps_in; - wire exp_pps_out; - - // GMII - // GMII-CTRL - wire GMII_COL; - wire GMII_CRS; - - // GMII-TX - wire [7:0] GMII_TXD; - wire GMII_TX_EN; - wire GMII_TX_ER; - wire GMII_GTX_CLK; - wire GMII_TX_CLK; // 100mbps clk - - // GMII-RX - wire [7:0] GMII_RXD; - wire GMII_RX_CLK; - wire GMII_RX_DV; - wire GMII_RX_ER; - - // GMII-Management - wire MDIO; - wire MDC; - wire PHY_INTn; // open drain - wire PHY_RESETn; - wire PHY_CLK; // possibly use on-board osc - - // RAM - wire [17:0] RAM_D; - wire [18:0] RAM_A; - wire RAM_CE1n; - wire RAM_CENn; - wire RAM_CLK; - wire RAM_WEn; - wire RAM_OEn; - wire RAM_LDn; - - // SERDES - wire ser_enable; - wire ser_prbsen; - wire ser_loopen; - wire ser_rx_en; - - wire ser_tx_clk; - wire [15:0] ser_t; - wire ser_tklsb; - wire ser_tkmsb; - - wire ser_rx_clk; - wire [15:0] ser_r; - wire ser_rklsb; - wire ser_rkmsb; - - // CPLD interface - wire cpld_din, cpld_clk, cpld_detached, cpld_start, cpld_mode, cpld_done; - - // ADC - wire [13:0] adc_a; - wire adc_ovf_a; - wire adc_oen_a; - wire adc_pdn_a; - - wire [13:0] adc_b; - wire adc_ovf_b; - wire adc_oen_b; - wire adc_pdn_b; - - // DAC - wire [15:0] dac_a; - wire [15:0] dac_b; - - // I2C - wire SCL; - wire SDA; - - // Clock Gen Control - wire [1:0] clk_en; - wire [1:0] clk_sel; - wire clk_func; // FIXME is an input to control the 9510 - wire clk_status; - - // Clocks - reg clk_fpga; - wire clk_to_mac; - wire pps_in; - - // Generic SPI - wire sclk, mosi, miso; - wire sen_clk; - wire sen_dac; - wire sen_tx_db; - wire sen_tx_adc; - wire sen_tx_dac; - wire sen_rx_db; - wire sen_rx_adc; - wire sen_rx_dac; - - // GPIO to DBoards - wire [15:0] io_tx; - wire [15:0] io_rx; - - wire wb_clk, wb_rst; - wire start, clock_ready; - - reg aux_clk; - - initial aux_clk= 1'b0; - always #25 aux_clk = ~aux_clk; - - initial clk_fpga = 1'bx; - initial #3007 clk_fpga = 1'b0; - always #7 clk_fpga = ~clk_fpga; - - - wire div_clk; - reg [2:0] div_ctr = 0; - - always @(posedge clk_fpga or negedge clk_fpga) - if(div_ctr==5) - div_ctr = 0; - else - div_ctr = div_ctr + 1; - assign div_clk = (div_ctr == 0) | (div_ctr == 1) | (div_ctr == 2); - - assign dsp_clk = clk_fpga; - assign wb_clk = clock_ready ? div_clk : aux_clk; - - initial - $monitor($time, ,clock_ready); - - initial begin - $dumpfile("eth_tb.vcd"); - $dumpvars(0,eth_tb); - end - - initial #10000000 $finish; - - cpld_model - cpld_model (.aux_clk(aux_clk),.start(cpld_start),.mode(cpld_mode),.done(cpld_done), - .dout(cpld_din),.sclk(cpld_clk),.detached(cpld_detached)); - - eth_sim_top eth_sim_top(.dsp_clk (dsp_clk), - .wb_clk (wb_clk), - .clock_ready (clock_ready), - .clk_to_mac (clk_to_mac), - .pps_in (pps_in), - .led1 (led1), - .led2 (led2), - .debug (debug[31:0]), - .debug_clk (debug_clk[1:0]), - .exp_pps_in (exp_pps_in), - .exp_pps_out (exp_pps_out), - .GMII_COL (GMII_COL), - .GMII_CRS (GMII_CRS), - .GMII_TXD (GMII_TXD[7:0]), - .GMII_TX_EN (GMII_TX_EN), - .GMII_TX_ER (GMII_TX_ER), - .GMII_GTX_CLK (GMII_GTX_CLK), - .GMII_TX_CLK (GMII_TX_CLK), - .GMII_RXD (GMII_RXD[7:0]), - .GMII_RX_CLK (GMII_RX_CLK), - .GMII_RX_DV (GMII_RX_DV), - .GMII_RX_ER (GMII_RX_ER), - .MDIO (MDIO), - .MDC (MDC), - .PHY_INTn (PHY_INTn), - .PHY_RESETn (PHY_RESETn), - .PHY_CLK (PHY_CLK), - .ser_enable (ser_enable), - .ser_prbsen (ser_prbsen), - .ser_loopen (ser_loopen), - .ser_rx_en (ser_rx_en), - .ser_tx_clk (ser_tx_clk), - .ser_t (ser_t[15:0]), - .ser_tklsb (ser_tklsb), - .ser_tkmsb (ser_tkmsb), - .ser_rx_clk (ser_rx_clk), - .ser_r (ser_r[15:0]), - .ser_rklsb (ser_rklsb), - .ser_rkmsb (ser_rkmsb), - .cpld_start (cpld_start), - .cpld_mode (cpld_mode), - .cpld_done (cpld_done), - .cpld_din (cpld_din), - .cpld_clk (cpld_clk), - .cpld_detached (cpld_detached), - .adc_a (adc_a[13:0]), - .adc_ovf_a (adc_ovf_a), - .adc_oen_a (adc_oen_a), - .adc_pdn_a (adc_pdn_a), - .adc_b (adc_b[13:0]), - .adc_ovf_b (adc_ovf_b), - .adc_oen_b (adc_oen_b), - .adc_pdn_b (adc_pdn_b), - .dac_a (dac_a[15:0]), - .dac_b (dac_b[15:0]), - .scl_pad_i (scl_pad_i), - .scl_pad_o (scl_pad_o), - .scl_pad_oen_o (scl_pad_oen_o), - .sda_pad_i (sda_pad_i), - .sda_pad_o (sda_pad_o), - .sda_pad_oen_o (sda_pad_oen_o), - .clk_en (clk_en[1:0]), - .clk_sel (clk_sel[1:0]), - .clk_func (clk_func), - .clk_status (clk_status), - .sclk (sclk), - .mosi (mosi), - .miso (miso), - .sen_clk (sen_clk), - .sen_dac (sen_dac), - .sen_tx_db (sen_tx_db), - .sen_tx_adc (sen_tx_adc), - .sen_tx_dac (sen_tx_dac), - .sen_rx_db (sen_rx_db), - .sen_rx_adc (sen_rx_adc), - .sen_rx_dac (sen_rx_dac), - .io_tx (io_tx[15:0]), - .io_rx (io_rx[15:0])); - - // Experimental printf-like function - always @(posedge wb_clk) - begin - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC000)) - $write("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC100)) - $display("%x",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC004)) - $write("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC104)) - $display("%c",eth_sim_top.m0_dat_i); - if((eth_sim_top.m0_we == 1'd1)&&(eth_sim_top.m0_adr == 16'hC008)) - $display(""); - end - - -endmodule // u2_sim_top - -// Local Variables: -// verilog-library-directories:("." "subdir" "subdir2") -// verilog-library-files:("/home/matt/u2f/top/u2_basic/u2_basic.v") -// verilog-library-extensions:(".v" ".h") -// End: diff --git a/fpga/usrp2/top/safe_u2plus/.gitignore b/fpga/usrp2/top/safe_u2plus/.gitignore deleted file mode 100644 index a96f0be92..000000000 --- a/fpga/usrp2/top/safe_u2plus/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -build* -*impact* diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile deleted file mode 100644 index b72241050..000000000 --- a/fpga/usrp2/top/safe_u2plus/Makefile +++ /dev/null @@ -1,245 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := safe_u2plus -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family "Spartan-3A DSP" \ -device xc3sd3400a \ -package fg676 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -control_lib/reset_sync.v \ -simple_gemac/simple_gemac_wrapper.v \ -simple_gemac/simple_gemac.v \ -simple_gemac/simple_gemac_wb.v \ -simple_gemac/simple_gemac_tx.v \ -simple_gemac/simple_gemac_rx.v \ -simple_gemac/crc.v \ -simple_gemac/delay_line.v \ -simple_gemac/flow_ctrl_tx.v \ -simple_gemac/flow_ctrl_rx.v \ -simple_gemac/address_filter.v \ -simple_gemac/ll8_to_txmac.v \ -simple_gemac/rxmac_to_ll8.v \ -simple_gemac/miim/eth_miim.v \ -simple_gemac/miim/eth_clockgen.v \ -simple_gemac/miim/eth_outputcontrol.v \ -simple_gemac/miim/eth_shiftreg.v \ -control_lib/newfifo/buffer_int.v \ -control_lib/newfifo/buffer_pool.v \ -control_lib/newfifo/fifo_2clock.v \ -control_lib/newfifo/fifo_2clock_cascade.v \ -control_lib/newfifo/ll8_shortfifo.v \ -control_lib/newfifo/ll8_to_fifo36.v \ -control_lib/newfifo/fifo_short.v \ -control_lib/newfifo/fifo_long.v \ -control_lib/newfifo/fifo_cascade.v \ -control_lib/newfifo/fifo36_to_ll8.v \ -control_lib/longfifo.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -coregen/fifo_xlnx_64x36_2clk.v \ -coregen/fifo_xlnx_64x36_2clk.xco \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_rx.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2plus/capture_ddrlvds.v \ -top/safe_u2plus/u2plus.ucf \ -top/safe_u2plus/safe_u2plus.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -clean: - rm -rf $(BUILD_DIR) - - diff --git a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v b/fpga/usrp2/top/safe_u2plus/safe_u2plus.v deleted file mode 100644 index dca9688c5..000000000 --- a/fpga/usrp2/top/safe_u2plus/safe_u2plus.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module safe_u2plus - ( - input CLK_FPGA_P, input CLK_FPGA_N, // Diff - output [5:1] leds, // LED4 is shared w/INIT_B - output ETH_LED - ); - - wire clk_fpga; - - IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); - defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25"; - - reg [31:0] ctr; - - always @(posedge clk_fpga) - ctr <= ctr + 1; - - assign {leds,ETH_LED} = ~ctr[29:24]; - -endmodule // safe_u2plus diff --git a/fpga/usrp2/top/safe_u2plus/u2plus.ucf b/fpga/usrp2/top/safe_u2plus/u2plus.ucf deleted file mode 100755 index 0a9460d86..000000000 --- a/fpga/usrp2/top/safe_u2plus/u2plus.ucf +++ /dev/null @@ -1,401 +0,0 @@ -## Main 100 MHz Clock -NET "CLK_FPGA_P" LOC = "AA13" ; -NET "CLK_FPGA_N" LOC = "Y13" ; - -## ADC -#NET "ADC_clkout_p" LOC = "P1" ; -#NET "ADC_clkout_n" LOC = "P2" ; -#NET "ADCA_12_p" LOC = "Y1" ; -#NET "ADCA_12_n" LOC = "Y2" ; -#NET "ADCA_10_p" LOC = "W3" ; -#NET "ADCA_10_n" LOC = "W4" ; -#NET "ADCA_8_p" LOC = "T7" ; -#NET "ADCA_8_n" LOC = "U6" ; -#NET "ADCA_6_p" LOC = "U5" ; -#NET "ADCA_6_n" LOC = "V5" ; -#NET "ADCA_4_p" LOC = "T10" ; -#NET "ADCA_4_n" LOC = "T9" ; -#NET "ADCA_2_p" LOC = "V1" ; -#NET "ADCA_2_n" LOC = "V2" ; -#NET "ADCA_0_p" LOC = "R8" ; -#NET "ADCA_0_n" LOC = "R7" ; -#NET "ADCB_2_p" LOC = "U7" ; -#NET "ADCB_2_n" LOC = "U8" ; -#NET "ADCB_0_p" LOC = "AA2" ; -#NET "ADCB_0_n" LOC = "AA3" ; -#NET "ADCB_4_p" LOC = "AE1" ; -#NET "ADCB_4_n" LOC = "AE2" ; -#NET "ADCB_6_p" LOC = "W1" ; -#NET "ADCB_6_n" LOC = "W2" ; -#NET "ADCB_8_p" LOC = "U3" ; -#NET "ADCB_8_n" LOC = "V4" ; -#NET "ADCB_10_p" LOC = "J1" ; -#NET "ADCB_10_n" LOC = "K1" ; -#NET "ADCB_12_p" LOC = "J3" ; -#NET "ADCB_12_n" LOC = "J2" ; - -## DAC -#NET "DAC_LOCK" LOC = "P4" ; -#NET "DACA<0>" LOC = "P8" ; -#NET "DACA<1>" LOC = "P9" ; -#NET "DACA<2>" LOC = "R5" ; -#NET "DACA<3>" LOC = "R6" ; -#NET "DACA<4>" LOC = "P7" ; -#NET "DACA<5>" LOC = "P6" ; -#NET "DACA<6>" LOC = "T3" ; -#NET "DACA<7>" LOC = "T4" ; -#NET "DACA<8>" LOC = "R3" ; -#NET "DACA<9>" LOC = "R4" ; -#NET "DACA<10>" LOC = "R2" ; -#NET "DACA<11>" LOC = "N1" ; -#NET "DACA<12>" LOC = "N2" ; -#NET "DACA<13>" LOC = "N5" ; -#NET "DACA<14>" LOC = "N4" ; -#NET "DACA<15>" LOC = "M2" ; -#NET "DACB<0>" LOC = "M5" ; -#NET "DACB<1>" LOC = "M6" ; -#NET "DACB<2>" LOC = "M4" ; -#NET "DACB<3>" LOC = "M3" ; -#NET "DACB<4>" LOC = "M8" ; -#NET "DACB<5>" LOC = "M7" ; -#NET "DACB<6>" LOC = "L4" ; -#NET "DACB<7>" LOC = "L3" ; -#NET "DACB<8>" LOC = "K3" ; -#NET "DACB<9>" LOC = "K2" ; -#NET "DACB<10>" LOC = "K5" ; -#NET "DACB<11>" LOC = "K4" ; -#NET "DACB<12>" LOC = "M10" ; -#NET "DACB<13>" LOC = "M9" ; -#NET "DACB<14>" LOC = "J5" ; -#NET "DACB<15>" LOC = "J4" ; - -## TX DB GPIO -#NET "io_tx<15>" LOC = "K6" ; -#NET "io_tx<14>" LOC = "L7" ; -#NET "io_tx<13>" LOC = "H2" ; -#NET "io_tx<12>" LOC = "H1" ; -#NET "io_tx<11>" LOC = "L10" ; -#NET "io_tx<10>" LOC = "L9" ; -#NET "io_tx<9>" LOC = "G3" ; -#NET "io_tx<8>" LOC = "F3" ; -#NET "io_tx<7>" LOC = "K7" ; -#NET "io_tx<6>" LOC = "J6" ; -#NET "io_tx<5>" LOC = "E1" ; -#NET "io_tx<4>" LOC = "F2" ; -#NET "io_tx<3>" LOC = "J7" ; -#NET "io_tx<2>" LOC = "H6" ; -#NET "io_tx<1>" LOC = "F5" ; -#NET "io_tx<0>" LOC = "G4" ; - -## RX DB GPIO -#NET "io_rx<15>" LOC = "AD1" ; -#NET "io_rx<14>" LOC = "AD2" ; -#NET "io_rx<13>" LOC = "AC2" ; -#NET "io_rx<12>" LOC = "AC3" ; -#NET "io_rx<11>" LOC = "W7" ; -#NET "io_rx<10>" LOC = "W6" ; -#NET "io_rx<9>" LOC = "U9" ; -#NET "io_rx<8>" LOC = "V8" ; -#NET "io_rx<7>" LOC = "AB1" ; -#NET "io_rx<6>" LOC = "AC1" ; -#NET "io_rx<5>" LOC = "V7" ; -#NET "io_rx<4>" LOC = "V6" ; -#NET "io_rx<3>" LOC = "Y5" ; -#NET "io_rx<2>" LOC = "R10" ; -#NET "io_rx<1>" LOC = "R1" ; -#NET "io_rx<0>" LOC = "M1" ; - -## MISC -NET "leds<5>" LOC = "AF25" ; -NET "leds<4>" LOC = "AE25" ; -NET "leds<3>" LOC = "AF23" ; -NET "leds<2>" LOC = "AE23" ; -NET "leds<1>" LOC = "AB18" ; -#NET "FPGA_RESET" LOC = "K24" ; - -## Debug -#NET "debug_clk<0>" LOC = "AA10" ; -#NET "debug_clk<1>" LOC = "AD11" ; -#NET "debug<0>" LOC = "AC19" ; -#NET "debug<1>" LOC = "AF20" ; -#NET "debug<2>" LOC = "AE20" ; -#NET "debug<3>" LOC = "AC16" ; -#NET "debug<4>" LOC = "AB16" ; -#NET "debug<5>" LOC = "AF19" ; -#NET "debug<6>" LOC = "AE19" ; -#NET "debug<7>" LOC = "V15" ; -#NET "debug<8>" LOC = "U15" ; -#NET "debug<9>" LOC = "AE17" ; -#NET "debug<10>" LOC = "AD17" ; -#NET "debug<11>" LOC = "V14" ; -#NET "debug<12>" LOC = "W15" ; -#NET "debug<13>" LOC = "AC15" ; -#NET "debug<14>" LOC = "AD14" ; -#NET "debug<15>" LOC = "AC14" ; -#NET "debug<16>" LOC = "AC11" ; -#NET "debug<17>" LOC = "AB12" ; -#NET "debug<18>" LOC = "AC12" ; -#NET "debug<19>" LOC = "V13" ; -#NET "debug<20>" LOC = "W13" ; -#NET "debug<21>" LOC = "AE8" ; -#NET "debug<22>" LOC = "AF8" ; -#NET "debug<23>" LOC = "V12" ; -#NET "debug<24>" LOC = "W12" ; -#NET "debug<25>" LOC = "AB9" ; -#NET "debug<26>" LOC = "AC9" ; -#NET "debug<27>" LOC = "AC8" ; -#NET "debug<28>" LOC = "AB7" ; -#NET "debug<29>" LOC = "V11" ; -#NET "debug<30>" LOC = "U11" ; -#NET "debug<31>" LOC = "Y10" ; - -## UARTS -#NET "TXD<3>" LOC = "AD20" ; -#NET "TXD<2>" LOC = "AC20" ; -#NET "TXD<1>" LOC = "AD19" ; -#NET "RXD<3>" LOC = "AF17" ; -#NET "RXD<2>" LOC = "AF15" ; -#NET "RXD<1>" LOC = "AD12" ; - -## AD9510 -#NET "CLK_STATUS" LOC = "AD22" ; -#NET "CLK_FUNC" LOC = "AC21" ; -#NET "clk_sel<0>" LOC = "AE21" ; -#NET "clk_sel<1>" LOC = "AD21" ; -#NET "clk_en<1>" LOC = "AA17" ; -#NET "clk_en<0>" LOC = "Y17" ; - -## I2C -#NET "SDA" LOC = "V16" ; -#NET "SCL" LOC = "U16" ; - -## Timing -#NET "PPS_IN" LOC = "AB6" ; -#NET "PPS2_IN" LOC = "AA20" ; - -## SPI -#NET "SEN_CLK" LOC = "AA18" ; -#NET "MOSI_CLK" LOC = "W17" ; -#NET "SCLK_CLK" LOC = "V17" ; -#NET "MISO_CLK" LOC = "AC10" ; - -#NET "SEN_DAC" LOC = "AE7" ; -#NET "SCLK_DAC" LOC = "AF5" ; -#NET "MOSI_DAC" LOC = "AE6" ; -#NET "MISO_DAC" LOC = "Y3" ; - -#NET "SCLK_ADC" LOC = "B1" ; -#NET "MOSI_ADC" LOC = "J8" ; -#NET "SEN_ADC" LOC = "J9" ; - -#NET "MOSI_TX_ADC" LOC = "V10" ; -#NET "SEN_TX_ADC" LOC = "W10" ; -#NET "SCLK_TX_ADC" LOC = "AC6" ; -#NET "MISO_TX_ADC" LOC = "G1" ; - -#NET "MOSI_TX_DAC" LOC = "AD6" ; -#NET "SEN_TX_DAC" LOC = "AE4" ; -#NET "SCLK_TX_DAC" LOC = "AF4" ; - -#NET "SCLK_TX_DB" LOC = "AE3" ; -#NET "MOSI_TX_DB" LOC = "AF3" ; -#NET "SEN_TX_DB" LOC = "W9" ; -#NET "MISO_TX_DB" LOC = "AA5" ; - -#NET "MOSI_RX_ADC" LOC = "E3" ; -#NET "SCLK_RX_ADC" LOC = "F4" ; -#NET "SEN_RX_ADC" LOC = "D3" ; -#NET "MISO_RX_ADC" LOC = "C1" ; - -#NET "SCLK_RX_DAC" LOC = "E4" ; -#NET "SEN_RX_DAC" LOC = "K9" ; -#NET "MOSI_RX_DAC" LOC = "K8" ; - -#NET "SCLK_RX_DB" LOC = "G6" ; -#NET "MOSI_RX_DB" LOC = "H7" ; -#NET "SEN_RX_DB" LOC = "B2" ; -#NET "MISO_RX_DB" LOC = "H4" ; - -## ETH PHY -#NET "CLK_TO_MAC" LOC = "P26" ; - -#NET "GMII_TXD<7>" LOC = "G21" ; -#NET "GMII_TXD<6>" LOC = "C26" ; -#NET "GMII_TXD<5>" LOC = "C25" ; -#NET "GMII_TXD<4>" LOC = "J21" ; -#NET "GMII_TXD<3>" LOC = "H21" ; -#NET "GMII_TXD<2>" LOC = "D25" ; -#NET "GMII_TXD<1>" LOC = "D24" ; -#NET "GMII_TXD<0>" LOC = "E26" ; -#NET "GMII_TX_EN" LOC = "D26" ; -#NET "GMII_TX_ER" LOC = "J19" ; -#NET "GMII_GTX_CLK" LOC = "J20" ; -#NET "GMII_TX_CLK" LOC = "P25" ; - -#NET "GMII_RX_CLK" LOC = "P21" ; -#NET "GMII_RXD<7>" LOC = "G22" ; -#NET "GMII_RXD<6>" LOC = "K19" ; -#NET "GMII_RXD<5>" LOC = "K18" ; -#NET "GMII_RXD<4>" LOC = "E24" ; -#NET "GMII_RXD<3>" LOC = "F23" ; -#NET "GMII_RXD<2>" LOC = "L18" ; -#NET "GMII_RXD<1>" LOC = "L17" ; -#NET "GMII_RXD<0>" LOC = "F25" ; -#NET "GMII_RX_DV" LOC = "F24" ; -#NET "GMII_RX_ER" LOC = "L20" ; -#NET "GMII_CRS" LOC = "K20" ; -#NET "GMII_COL" LOC = "G23" ; - -#NET "PHY_INTn" LOC = "L22" ; -#NET "MDIO" LOC = "K21" ; -#NET "MDC" LOC = "J23" ; -#NET "PHY_RESETn" LOC = "J22" ; -NET "ETH_LED" LOC = "H20" ; - -## MIMO Interface -#NET "exp_time_out_p" LOC = "Y14" ; -#NET "exp_time_out_n" LOC = "AA14" ; -#NET "exp_time_in_p" LOC = "N18" ; -#NET "exp_time_in_n" LOC = "N17" ; -#NET "exp_user_out_p" LOC = "AF14" ; -#NET "exp_user_out_n" LOC = "AE14" ; -#NET "exp_user_in_p" LOC = "L24" ; -#NET "exp_user_in_n" LOC = "M23" ; - -## SERDES -#NET "ser_enable" LOC = "R20" ; -#NET "ser_prbsen" LOC = "U23" ; -#NET "ser_loopen" LOC = "R19" ; -#NET "ser_rx_en" LOC = "Y21" ; -#NET "ser_tx_clk" LOC = "P23" ; # SERDES TX CLK -#NET "ser_t<15>" LOC = "V23" ; -#NET "ser_t<14>" LOC = "U22" ; -#NET "ser_t<13>" LOC = "V24" ; -#NET "ser_t<12>" LOC = "V25" ; -#NET "ser_t<11>" LOC = "W23" ; -#NET "ser_t<10>" LOC = "V22" ; -#NET "ser_t<9>" LOC = "T18" ; -#NET "ser_t<8>" LOC = "T17" ; -#NET "ser_t<7>" LOC = "Y24" ; -#NET "ser_t<6>" LOC = "Y25" ; -#NET "ser_t<5>" LOC = "U21" ; -#NET "ser_t<4>" LOC = "T20" ; -#NET "ser_t<3>" LOC = "Y22" ; -#NET "ser_t<2>" LOC = "Y23" ; -#NET "ser_t<1>" LOC = "U19" ; -#NET "ser_t<0>" LOC = "U18" ; -#NET "ser_tkmsb" LOC = "AA24" ; -#NET "ser_tklsb" LOC = "AA25" ; -#NET "ser_rx_clk" LOC = "P18" ; -#NET "ser_r<15>" LOC = "V21" ; -#NET "ser_r<14>" LOC = "U20" ; -#NET "ser_r<13>" LOC = "AA22" ; -#NET "ser_r<12>" LOC = "AA23" ; -#NET "ser_r<11>" LOC = "V18" ; -#NET "ser_r<10>" LOC = "V19" ; -#NET "ser_r<9>" LOC = "AB23" ; -#NET "ser_r<8>" LOC = "AC26" ; -#NET "ser_r<7>" LOC = "AB26" ; -#NET "ser_r<6>" LOC = "AD26" ; -#NET "ser_r<5>" LOC = "AC25" ; -#NET "ser_r<4>" LOC = "W20" ; -#NET "ser_r<3>" LOC = "W21" ; -#NET "ser_r<2>" LOC = "AC23" ; -#NET "ser_r<1>" LOC = "AC24" ; -#NET "ser_r<0>" LOC = "AE26" ; -#NET "ser_rkmsb" LOC = "AD25" ; -#NET "ser_rklsb" LOC = "Y20" ; - -## SRAM -#NET "RAM_D<35>" LOC = "K16" ; -#NET "RAM_D<34>" LOC = "D20" ; -#NET "RAM_D<33>" LOC = "C20" ; -#NET "RAM_D<32>" LOC = "E21" ; -#NET "RAM_D<31>" LOC = "D21" ; -#NET "RAM_D<30>" LOC = "C21" ; -#NET "RAM_D<29>" LOC = "B21" ; -#NET "RAM_D<28>" LOC = "H17" ; -#NET "RAM_D<27>" LOC = "G17" ; -#NET "RAM_D<26>" LOC = "B23" ; -#NET "RAM_D<25>" LOC = "A22" ; -#NET "RAM_D<24>" LOC = "D23" ; -#NET "RAM_D<23>" LOC = "C23" ; -#NET "RAM_D<22>" LOC = "D22" ; -#NET "RAM_D<21>" LOC = "C22" ; -#NET "RAM_D<20>" LOC = "F19" ; -#NET "RAM_D<19>" LOC = "G20" ; -#NET "RAM_D<18>" LOC = "F20" ; -#NET "RAM_D<17>" LOC = "F7" ; -#NET "RAM_D<16>" LOC = "E7" ; -#NET "RAM_D<15>" LOC = "G9" ; -#NET "RAM_D<14>" LOC = "H9" ; -#NET "RAM_D<13>" LOC = "G10" ; -#NET "RAM_D<12>" LOC = "H10" ; -#NET "RAM_D<11>" LOC = "A4" ; -#NET "RAM_D<10>" LOC = "B4" ; -#NET "RAM_D<9>" LOC = "C5" ; -#NET "RAM_D<8>" LOC = "D6" ; -#NET "RAM_D<7>" LOC = "J11" ; -#NET "RAM_D<6>" LOC = "K11" ; -#NET "RAM_D<5>" LOC = "B7" ; -#NET "RAM_D<4>" LOC = "C7" ; -#NET "RAM_D<3>" LOC = "B6" ; -#NET "RAM_D<2>" LOC = "C6" ; -#NET "RAM_D<1>" LOC = "C8" ; -#NET "RAM_D<0>" LOC = "D8" ; -#NET "RAM_A<0>" LOC = "C11" ; -#NET "RAM_A<1>" LOC = "E12" ; -#NET "RAM_A<2>" LOC = "F12" ; -#NET "RAM_A<3>" LOC = "D13" ; -#NET "RAM_A<4>" LOC = "C12" ; -#NET "RAM_A<5>" LOC = "A12" ; -#NET "RAM_A<6>" LOC = "B12" ; -#NET "RAM_A<7>" LOC = "E14" ; -#NET "RAM_A<8>" LOC = "F14" ; -#NET "RAM_A<9>" LOC = "B15" ; -#NET "RAM_A<10>" LOC = "A15" ; -#NET "RAM_A<11>" LOC = "D16" ; -#NET "RAM_A<12>" LOC = "C15" ; -#NET "RAM_A<13>" LOC = "D17" ; -#NET "RAM_A<14>" LOC = "C16" ; -#NET "RAM_A<15>" LOC = "F15" ; -#NET "RAM_A<16>" LOC = "C17" ; -#NET "RAM_A<17>" LOC = "B17" ; -#NET "RAM_A<18>" LOC = "B18" ; -#NET "RAM_A<19>" LOC = "A18" ; -#NET "RAM_A<20>" LOC = "D18" ; -#NET "RAM_BWn<3>" LOC = "D9" ; -#NET "RAM_BWn<2>" LOC = "A9" ; -#NET "RAM_BWn<1>" LOC = "B9" ; -#NET "RAM_BWn<0>" LOC = "G12" ; -#NET "RAM_ZZ" LOC = "J12" ; -#NET "RAM_LDn" LOC = "H12" ; -#NET "RAM_OEn" LOC = "C10" ; -#NET "RAM_WEn" LOC = "D10" ; -#NET "RAM_CENn" LOC = "B10" ; -#NET "RAM_CLK" LOC = "A10" ; - -## SPI Flash -#NET "flash_miso" LOC = "AF24" ; -#NET "flash_clk" LOC = "AE24" ; -#NET "flash_mosi" LOC = "AB15" ; -#NET "flash_cs" LOC = "AA7" ; - -## MISC FPGA, unused for now -##NET "PROG_B" LOC = "A2" ; -##NET "PUDC_B" LOC = "G8" ; -##NET "DONE" LOC = "AB21" ; -##NET "INIT_B" LOC = "AA15" ; - - -##NET "unnamed_net19" LOC = "AE9" ; # VS1 -##NET "unnamed_net18" LOC = "AF9" ; # VS0 -##NET "unnamed_net17" LOC = "AA12" ; # VS2 -##NET "unnamed_net16" LOC = "Y7" ; # M2 -##NET "unnamed_net15" LOC = "AC4" ; # M1 -##NET "unnamed_net14" LOC = "AD4" ; # M0 -##NET "unnamed_net13" LOC = "D4" ; # TMS -##NET "unnamed_net12" LOC = "E23" ; # TDO -##NET "unnamed_net11" LOC = "G7" ; # TDI -##NET "unnamed_net10" LOC = "A25" ; # TCK -##NET "unnamed_net20" LOC = "V20" ; # SUSPEND diff --git a/fpga/usrp2/top/tcl/ise_helper.tcl b/fpga/usrp2/top/tcl/ise_helper.tcl index a4bee76b8..f11596f8b 100644 --- a/fpga/usrp2/top/tcl/ise_helper.tcl +++ b/fpga/usrp2/top/tcl/ise_helper.tcl @@ -1,8 +1,6 @@ # # Copyright 2008 Ettus Research LLC # -# This file is part of GNU Radio -# # GNU Radio is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 3, or (at your option) diff --git a/fpga/usrp2/top/u1e_ethdebug/.gitignore b/fpga/usrp2/top/u1e_ethdebug/.gitignore deleted file mode 100644 index 8d872713e..000000000 --- a/fpga/usrp2/top/u1e_ethdebug/.gitignore +++ /dev/null @@ -1,6 +0,0 @@ -*~ -build -*.log -*.cmd -tb_u1e -*.lxt diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf b/fpga/usrp2/top/u1e_ethdebug/u1e.ucf deleted file mode 100644 index d6a2ea4ed..000000000 --- a/fpga/usrp2/top/u1e_ethdebug/u1e.ucf +++ /dev/null @@ -1,88 +0,0 @@ - -## GPMC -NET "EM_D<15>" LOC = "D13" ; -NET "EM_D<14>" LOC = "D15" ; -NET "EM_D<13>" LOC = "C16" ; -NET "EM_D<12>" LOC = "B20" ; -NET "EM_D<11>" LOC = "A19" ; -NET "EM_D<10>" LOC = "A17" ; -NET "EM_D<9>" LOC = "E15" ; -NET "EM_D<8>" LOC = "F15" ; -NET "EM_D<7>" LOC = "E16" ; -NET "EM_D<6>" LOC = "F16" ; -NET "EM_D<5>" LOC = "B17" ; -NET "EM_D<4>" LOC = "C17" ; -NET "EM_D<3>" LOC = "B19" ; -NET "EM_D<2>" LOC = "D19" ; -NET "EM_D<1>" LOC = "C19" ; -NET "EM_D<0>" LOC = "A20" ; - -NET "EM_A<10>" LOC = "C14" ; -NET "EM_A<9>" LOC = "C10" ; -NET "EM_A<8>" LOC = "C5" ; -NET "EM_A<7>" LOC = "A18" ; -NET "EM_A<6>" LOC = "A15" ; -NET "EM_A<5>" LOC = "A12" ; -NET "EM_A<4>" LOC = "A10" ; -NET "EM_A<3>" LOC = "E7" ; -NET "EM_A<2>" LOC = "A7" ; -NET "EM_A<1>" LOC = "C15" ; - -NET "EM_NCS6" LOC = "E17" ; -NET "EM_NCS5" LOC = "E10" ; -NET "EM_NCS4" LOC = "E6" ; -#NET "EM_NCS1" LOC = "D18" ; -#NET "EM_NCS0" LOC = "D17" ; - -NET "EM_CLK" LOC = "F11" ; -NET "EM_WAIT0" LOC = "F14" ; -#NET "EM_NBE<1>" LOC = "D14" ; -#NET "EM_NBE<0>" LOC = "A13" ; -NET "EM_NWE" LOC = "B13" ; -NET "EM_NOE" LOC = "A14" ; -NET "EM_NADV_ALE" LOC = "B15" ; -#NET "EM_NWP" LOC = "F13" ; -NET "overo_gpio64" LOC = "A4" ; # nRESET -NET "overo_gpio176" LOC = "B4" ; # IRQ - -## Debug pins -NET "debug_led<3>" LOC = "Y15" ; -NET "debug_led<2>" LOC = "K16" ; -NET "debug_led<1>" LOC = "J17" ; -NET "debug_led<0>" LOC = "H22" ; -NET "debug<0>" LOC = "G22" ; -NET "debug<1>" LOC = "H17" ; -NET "debug<2>" LOC = "H18" ; -NET "debug<3>" LOC = "K20" ; -NET "debug<4>" LOC = "J20" ; -NET "debug<5>" LOC = "K19" ; -NET "debug<6>" LOC = "K18" ; -NET "debug<7>" LOC = "L22" ; -NET "debug<8>" LOC = "K22" ; -NET "debug<9>" LOC = "N22" ; -NET "debug<10>" LOC = "M22" ; -NET "debug<11>" LOC = "N20" ; -NET "debug<12>" LOC = "N19" ; -NET "debug<13>" LOC = "R22" ; -NET "debug<14>" LOC = "P22" ; -NET "debug<15>" LOC = "N17" ; -NET "debug<16>" LOC = "P16" ; -NET "debug<17>" LOC = "U22" ; -NET "debug<18>" LOC = "P19" ; -NET "debug<19>" LOC = "R18" ; -NET "debug<20>" LOC = "U20" ; -NET "debug<21>" LOC = "T20" ; -NET "debug<22>" LOC = "R19" ; -NET "debug<23>" LOC = "R20" ; -NET "debug<24>" LOC = "W22" ; -NET "debug<25>" LOC = "Y22" ; -NET "debug<26>" LOC = "T18" ; -NET "debug<27>" LOC = "T17" ; -NET "debug<28>" LOC = "W19" ; -NET "debug<29>" LOC = "V20" ; -NET "debug<30>" LOC = "Y21" ; -NET "debug<31>" LOC = "AA22" ; -NET "debug_clk<0>" LOC = "N18" ; -NET "debug_clk<1>" LOC = "M17" ; - -NET "debug_pb" LOC = "C22" ; diff --git a/fpga/usrp2/top/u1e_ethdebug/u1e.v b/fpga/usrp2/top/u1e_ethdebug/u1e.v deleted file mode 100644 index 2a543a313..000000000 --- a/fpga/usrp2/top/u1e_ethdebug/u1e.v +++ /dev/null @@ -1,28 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -//`define DCM 1 - -module u1e - (output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, - input debug_pb, - - // GPMC - input EM_CLK, input [15:0] EM_D, input [10:1] EM_A, - input EM_WAIT0, input EM_NCS4, input EM_NCS5, input EM_NCS6, input EM_NWE, input EM_NOE, - input EM_NADV_ALE, - - input overo_gpio64, input overo_gpio176 - ); - - assign debug_clk = {EM_CLK, EM_NADV_ALE}; - - assign debug_led = {1'b0, EM_A[9], EM_A[8], debug_pb}; - - assign debug = { {overo_gpio64, overo_gpio176, EM_WAIT0, EM_NCS4, EM_NCS5, EM_NCS6, EM_NWE, EM_NOE }, - { EM_A[10], EM_A[7:1] }, - { EM_D[15:8] }, - { EM_D[7:0] } }; - - -endmodule // u1e diff --git a/fpga/usrp2/top/u1e_passthru/passthru.v b/fpga/usrp2/top/u1e_passthru/passthru.v deleted file mode 100644 index 12e4db017..000000000 --- a/fpga/usrp2/top/u1e_passthru/passthru.v +++ /dev/null @@ -1,18 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// - -module passthru - (input overo_gpio145, - output cgen_sclk, - output cgen_sen_b, - output cgen_mosi, - input fpga_cfg_din, - input fpga_cfg_cclk - ); - - assign cgen_sclk = fpga_cfg_cclk; - assign cgen_sen_b = overo_gpio145; - assign cgen_mosi = fpga_cfg_din; - - -endmodule // passthru diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile deleted file mode 100644 index 334089839..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile +++ /dev/null @@ -1,253 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_2rx_iad/u2_core.v \ -top/u2_rev3_2rx_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/README b/fpga/usrp2/top/u2_rev3_2rx_iad/README deleted file mode 100644 index 3efc5305b..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/README +++ /dev/null @@ -1,32 +0,0 @@ -This is a custom build for USRP2 FPGA. It allows using a BasicRX or -LFRX board and feed two independent, real signals. In addition, instead -of the CIC/HB decimator, which optimizes frequency response, it uses an -integrate and dump decimator, which optimizes for time-domain impulse -response. - -These changes have been made in dsp_core_rx.v: - -* A second DDC has been added, sharing a frequency register with - the existing DDC. - -* The output of the two DDCs are interleaved as I1 Q1 I2 Q2I ... - into the receive FIFO. This limits the host configured decimation - to 8 intead of 4. Use gr.deinterleave to recover the streams. - -* The ADCs are hardcoded: - - RX_A ==> DDC #1 I-input - 0 ==> DDC #1 Q-input - RX_B ==> DDC #2 I-input - 0 ==> DDC #2 Q-input - - Thus, the input mux has been disabled. - -* The CIC/HB decimator has been replaced by an integrate and dump at - the decimation rate. - -* To assist with meeting timing, the external RAM has been disabled. - -The basic application is to coherently sample two real IF streams and -downconvert to baseband, while minimizing the impulse response duration -of the resampling filters. diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile b/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v deleted file mode 100644 index 4a945bd1a..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_rx.v +++ /dev/null @@ -1,212 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output reg [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic_a, q_cordic_a, i_cordic_b, q_cordic_b; - wire [31:0] i_iad_a, q_iad_a, i_iad_b, q_iad_b; - wire [15:0] i_out_a, q_out_a, i_out_b, q_out_b; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - -`ifdef MUXCTRL - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); -`endif - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - -`ifdef MUXCTRL - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) -`else // !`ifdef MUXCTRL - always @(posedge clk) - begin - adc_i <= adc_a_ofs; - adc_q <= adc_b_ofs; - end -`endif // !`ifdef MUXCTRL - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - // Route I,0 to first CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_a(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_a),.yo(q_cordic_a),.zo() ); - - // Route Q,0 to second CORDIC - cordic_z24 #(.bitwidth(24)) - cordic_b(.clock(clk), .reset(rst), .enable(run), - .xi(prod_q[24:1]),. yi(0), .zi(phase[31:8]), - .xo(i_cordic_b),.yo(q_cordic_b),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - wire strobe_iad_o; - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_a), - .stb_o(strobe_iad_o),.integ_o(i_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_a - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_a), - .stb_o(),.integ_o(q_iad_a) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic_b), - .stb_o(),.integ_o(i_iad_b) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q_b - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic_b), - .stb_o(),.integ_o(q_iad_b) ); - - round #(.bits_in(32),.bits_out(16)) round_iout_a (.in(i_iad_a),.out(i_out_a)); - round #(.bits_in(32),.bits_out(16)) round_qout_a (.in(q_iad_a),.out(q_out_a)); - round #(.bits_in(32),.bits_out(16)) round_iout_b (.in(i_iad_b),.out(i_out_b)); - round #(.bits_in(32),.bits_out(16)) round_qout_b (.in(q_iad_b),.out(q_out_b)); - - reg [31:0] sample_out_a, sample_out_b, sample_out; - reg stb_d1, stb_d2, stb_d3, stb_d4, stb_d5; - reg strobe_out; - - // Register samples on strobe_iad - // Output A on d1 - // Output B on d5 - always @(posedge clk) - begin - stb_d1 <= strobe_iad_o; - stb_d2 <= stb_d1; - stb_d3 <= stb_d2; - stb_d4 <= stb_d3; - stb_d5 <= stb_d4; - end - - always @(posedge clk) - if (strobe_iad_o) - begin - // Streaming GPIO - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - sample_out_a <= {i_out_a[15:1], gpio_ena[0] ? io_rx[15] : i_out_a[0], - q_out_a[15:1], gpio_ena[1] ? io_rx[14] : q_out_a[0] }; - sample_out_b <= {i_out_b[15:1], gpio_ena[0] ? io_rx[15] : i_out_b[0], - q_out_b[15:1], gpio_ena[1] ? io_rx[14] : q_out_b[0] }; - end - - always @(posedge clk) - begin - if (stb_d1) - sample <= sample_out_a; - else if (stb_d5) - sample <= sample_out_b; - strobe_out <= stb_d1|stb_d5; - end - - assign strobe = strobe_out; - assign debug = 0; - -endmodule // dsp_core_rx diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav deleted file mode 100644 index 12f746860..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.sav +++ /dev/null @@ -1,106 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-17.007835 70679400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -@22 -dsp_core_tb.rx_path.adc_a[13:0] -dsp_core_tb.rx_path.adc_b[13:0] -@28 -dsp_core_tb.rx_path.adc_ovf_a -dsp_core_tb.rx_path.adc_ovf_b -@22 -dsp_core_tb.rx_path.io_rx[15:0] -@200 -- -@22 -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe -@200 -- -@22 -dsp_core_tb.rx_path.phase_inc[31:0] -dsp_core_tb.rx_path.scale_i[15:0] -dsp_core_tb.rx_path.scale_q[15:0] -@28 -dsp_core_tb.rx_path.enable_hb1 -dsp_core_tb.rx_path.enable_hb2 -@22 -dsp_core_tb.rx_path.cic_decim[7:0] -dsp_core_tb.rx_path.adc_a_ofs[13:0] -dsp_core_tb.rx_path.adc_b_ofs[13:0] -dsp_core_tb.rx_path.muxctrl[3:0] -@200 -- -@22 -dsp_core_tb.rx_path.adc_i[13:0] -dsp_core_tb.rx_path.adc_q[13:0] -dsp_core_tb.rx_path.phase[31:0] -dsp_core_tb.rx_path.prod_i[35:0] -dsp_core_tb.rx_path.prod_q[35:0] -@8420 -dsp_core_tb.rx_path.i_cordic_a[23:0] -dsp_core_tb.rx_path.q_cordic_a[23:0] -dsp_core_tb.rx_path.i_cordic_b[23:0] -dsp_core_tb.rx_path.q_cordic_b[23:0] -@22 -dsp_core_tb.rx_path.decim_rate[9:0] -@28 -dsp_core_tb.rx_path.strobe_iad -@22 -dsp_core_tb.rx_path.i_iad_a[31:0] -dsp_core_tb.rx_path.q_iad_a[31:0] -@23 -dsp_core_tb.rx_path.i_iad_b[31:0] -@22 -dsp_core_tb.rx_path.q_iad_b[31:0] -@28 -dsp_core_tb.rx_path.strobe_iad_o -@8420 -dsp_core_tb.rx_path.i_out_a[15:0] -dsp_core_tb.rx_path.q_out_a[15:0] -dsp_core_tb.rx_path.i_out_b[15:0] -dsp_core_tb.rx_path.q_out_b[15:0] -@28 -dsp_core_tb.rx_path.gpio_ena[1:0] -@22 -dsp_core_tb.rx_path.sample_out_a[31:0] -dsp_core_tb.rx_path.sample_out_b[31:0] -dsp_core_tb.rx_path.sample[31:0] -@28 -dsp_core_tb.rx_path.strobe_out -dsp_core_tb.rx_path.stb_d1 -dsp_core_tb.rx_path.stb_d2 -dsp_core_tb.rx_path.stb_d3 -dsp_core_tb.rx_path.stb_d4 -dsp_core_tb.rx_path.stb_d5 -@200 -- --FIFO Bus -@22 -dsp_core_tb.master_time[31:0] -dsp_core_tb.wr_dat[31:0] -@28 -dsp_core_tb.wr_done -dsp_core_tb.wr_error -dsp_core_tb.wr_full -dsp_core_tb.wr_ready -dsp_core_tb.wr_write diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v deleted file mode 100644 index d947df40a..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/dsp_core_tb.v +++ /dev/null @@ -1,233 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - - reg [31:0] master_time = 0; - always @(posedge clk) - master_time <= master_time + 1; - - reg wr_ready = 1; - reg wr_full = 0; - - wire [31:0] wr_dat; - wire wr_write; - wire wr_done; - wire wr_error; - wire [15:0] fifo_occupied; - wire fifo_full; - wire fifo_empty; - - rx_control rx_buffer - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time), - .overrun(), // unconnected output - .wr_dat_o(wr_dat), - .wr_write_o(wr_write), - .wr_done_o(wr_done), - .wr_error_o(wr_error), - .wr_ready_i(wr_ready), - .wr_full_i(wr_full), - .sample(sample), - .run(), // unconnected output, supposed to drive 'run' - .strobe(stb), - .fifo_occupied(fifo_occupied), - .fifo_full(fifo_full), - .fifo_empty(fifo_empty), - .debug_rx() // unconnected output - ); - - - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(10); - set_zero_len(990); - set_rx_muxctrl(1); - set_ddc_freq(32'h10000000); - set_rx_scale_iq(1243, 1243); - set_decim(1, 1, 1); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v b/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v deleted file mode 100644 index fc5e3c1ed..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/impulse.v +++ /dev/null @@ -1,68 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [13:0] adc_b_int = 0; - - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - adc_b_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - adc_b_int <= amplitude >> 2; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - adc_b_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - assign adc_b = adc_b_int + dc_offset_b; - - // Ignore for now - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v b/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v deleted file mode 100755 index 3d96a4e0e..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/u2_core.v +++ /dev/null @@ -1,789 +0,0 @@ -// //////////////////////////////////////////////////////////////////////////////// -// Module Name: u2_core -// //////////////////////////////////////////////////////////////////////////////// - -module u2_core - #(parameter RAM_SIZE=32768) - (// Clocks - input dsp_clk, - input wb_clk, - output clock_ready, - input clk_to_mac, - input pps_in, - - // Misc, debug - output [7:0] leds, - output [31:0] debug, - output [1:0] debug_clk, - - // Expansion - input exp_pps_in, - output exp_pps_out, - - // GMII - // GMII-CTRL - input GMII_COL, - input GMII_CRS, - - // GMII-TX - output [7:0] GMII_TXD, - output GMII_TX_EN, - output GMII_TX_ER, - output GMII_GTX_CLK, - input GMII_TX_CLK, // 100mbps clk - - // GMII-RX - input [7:0] GMII_RXD, - input GMII_RX_CLK, - input GMII_RX_DV, - input GMII_RX_ER, - - // GMII-Management - inout MDIO, - output MDC, - input PHY_INTn, // open drain - output PHY_RESETn, - - // SERDES - output ser_enable, - output ser_prbsen, - output ser_loopen, - output ser_rx_en, - - output ser_tx_clk, - output [15:0] ser_t, - output ser_tklsb, - output ser_tkmsb, - - input ser_rx_clk, - input [15:0] ser_r, - input ser_rklsb, - input ser_rkmsb, - - // CPLD interface - output cpld_start, - output cpld_mode, - output cpld_done, - input cpld_din, - input cpld_clk, - input cpld_detached, - output cpld_misc, - input cpld_init_b, - input por, - output config_success, - - // ADC - input [13:0] adc_a, - input adc_ovf_a, - output adc_on_a, - output adc_oe_a, - - input [13:0] adc_b, - input adc_ovf_b, - output adc_on_b, - output adc_oe_b, - - // DAC - output [15:0] dac_a, - output [15:0] dac_b, - - // I2C - input scl_pad_i, - output scl_pad_o, - output scl_pad_oen_o, - input sda_pad_i, - output sda_pad_o, - output sda_pad_oen_o, - - // Clock Gen Control - output [1:0] clk_en, - output [1:0] clk_sel, - input clk_func, // FIXME is an input to control the 9510 - input clk_status, - - // Generic SPI - output sclk, - output mosi, - input miso, - output sen_clk, - output sen_dac, - output sen_tx_db, - output sen_tx_adc, - output sen_tx_dac, - output sen_rx_db, - output sen_rx_adc, - output sen_rx_dac, - - // GPIO to DBoards - inout [15:0] io_tx, - inout [15:0] io_rx, - - // External RAM - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - output RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn, - - // Debug stuff - output uart_tx_o, - input uart_rx_i, - output uart_baud_o, - input sim_mode, - input [3:0] clock_divider - ); - - wire [7:0] set_addr; - wire [31:0] set_data; - wire set_stb; - - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; - wire bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, proc_int, overrun, underrun, uart_tx_int, uart_rx_int; - - wire [31:0] debug_gpio_0, debug_gpio_1; - wire [31:0] atr_lines; - - wire [31:0] debug_rx, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp; - - wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; - wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; - wire ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2; - - wire serdes_link_up; - wire epoch; - - // /////////////////////////////////////////////////////////////////////////////////////////////// - // Wishbone Single Master INTERCON - localparam dw = 32; // Data bus width - localparam aw = 16; // Address bus width, for byte addressibility, 16 = 64K byte memory space - localparam sw = 4; // Select width -- 32-bit data bus with 8-bit granularity. - - wire [dw-1:0] m0_dat_o, m0_dat_i; - wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i, - s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i, - s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, s11_dat_i, s11_dat_o, - s12_dat_i, s12_dat_o, s13_dat_i, s13_dat_o, s14_dat_i, s14_dat_o; - wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr, s13_adr, s14_adr; - wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel, s13_sel, s14_sel; - wire m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack, s13_ack, s14_ack; - wire m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb, s13_stb, s14_stb; - wire m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc, s13_cyc, s14_cyc; - wire m0_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err, s13_err, s14_err; - wire m0_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty, s13_rty, s14_rty; - wire m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we,s13_we, s14_we; - - wb_1master #(.s0_addr_w(1),.s0_addr(1'b0),.s1_addr_w(2),.s1_addr(2'b10), - .s215_addr_w(6),.s2_addr(6'b1100_00),.s3_addr(6'b1100_01),.s4_addr(6'b1100_10), - .s5_addr(6'b1100_11),.s6_addr(6'b1101_00),.s7_addr(6'b1101_01),.s8_addr(6'b1101_10), - .s9_addr(6'b1101_11),.s10_addr(6'b1110_00),.s11_addr(6'b1110_01),.s12_addr(6'b1110_10), - .s13_addr(6'b1110_11),.s14_addr(6'b1111_00),.s15_addr(6'b1111_01), - .dw(dw),.aw(aw),.sw(sw)) wb_1master - (.clk_i(wb_clk),.rst_i(wb_rst), - .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), - .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb), - .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o (s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb), - .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty), - .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o (s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb), - .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty), - .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o (s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb), - .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty), - .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o (s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb), - .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty), - .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o (s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb), - .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty), - .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o (s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb), - .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty), - .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o (s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb), - .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty), - .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o (s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb), - .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty), - .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o (s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb), - .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(s8_err),.s8_rty_i(s8_rty), - .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o (s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb), - .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(s9_err),.s9_rty_i(s9_rty), - .s10_dat_o(s10_dat_o),.s10_adr_o(s10_adr),.s10_sel_o(s10_sel),.s10_we_o(s10_we),.s10_cyc_o(s10_cyc),.s10_stb_o(s10_stb), - .s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty), - .s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb), - .s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty), - .s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb), - .s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty), - .s13_dat_o(s13_dat_o),.s13_adr_o(s13_adr),.s13_sel_o(s13_sel),.s13_we_o(s13_we),.s13_cyc_o(s13_cyc),.s13_stb_o(s13_stb), - .s13_dat_i(s13_dat_i),.s13_ack_i(s13_ack),.s13_err_i(s13_err),.s13_rty_i(s13_rty), - .s14_dat_o(s14_dat_o),.s14_adr_o(s14_adr),.s14_sel_o(s14_sel),.s14_we_o(s14_we),.s14_cyc_o(s14_cyc),.s14_stb_o(s14_stb), - .s14_dat_i(s14_dat_i),.s14_ack_i(s14_ack),.s14_err_i(s14_err),.s14_rty_i(s14_rty), - .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0) ); - - ////////////////////////////////////////////////////////////////////////////////////////// - // Reset Controller - system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por), - .ram_loader_rst_o(ram_loader_rst), - .wb_rst_o(wb_rst), - .ram_loader_done_i(ram_loader_done)); - - assign config_success = ram_loader_done; - reg takeover = 0; - - wire cpld_start_int, cpld_mode_int, cpld_done_int; - - always @(posedge wb_clk) - if(ram_loader_done) - takeover = 1; - assign cpld_misc = ~takeover; - - wire sd_clk, sd_csn, sd_mosi, sd_miso; - - assign sd_miso = cpld_din; - assign cpld_start = takeover ? sd_clk : cpld_start_int; - assign cpld_mode = takeover ? sd_csn : cpld_mode_int; - assign cpld_done = takeover ? sd_mosi : cpld_done_int; - - // /////////////////////////////////////////////////////////////////// - // RAM Loader - - wire [31:0] ram_loader_dat, iwb_dat; - wire [15:0] ram_loader_adr, iwb_adr; - wire [3:0] ram_loader_sel; - wire ram_loader_stb, ram_loader_we, ram_loader_ack; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) - ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst), - // CPLD Interface - .cfg_clk_i(cpld_clk), - .cfg_data_i(cpld_din), - .start_o(cpld_start_int), - .mode_o(cpld_mode_int), - .done_o(cpld_done_int), - .detached_i(cpld_detached), - // Wishbone Interface - .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr), - .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel), - .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack), - .ram_loader_done_o(ram_loader_done)); - - // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr), - .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack), - // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), - // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - - // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone - // I-port connects directly to processor and ram loader - - wire flush_icache; - ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) - sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), - .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), - .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack), - .ram_loader_done_i(ram_loader_done), - - .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb), - .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack), - - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), - .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), - .flush_icache(flush_icache)); - - assign s0_err = 1'b0; - assign s0_rty = 1'b0; - - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(),.changed(flush_icache)); - - // Buffer Pool, slave #1 - wire rd0_read, rd0_sop, rd0_error, rd0_done, rd0_eop; - wire rd1_read, rd1_sop, rd1_error, rd1_done, rd1_eop; - wire rd2_read, rd2_sop, rd2_error, rd2_done, rd2_eop; - wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; - - wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full; - wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full; - wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full; - wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool buffer_pool - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), - .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(s1_err),.wb_rty_o(s1_rty), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done), - .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full), - .wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done), - .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full), - .wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done), - .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full), - .wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done), - .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full), - // Read Interfaces - .rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done), - .rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop), - .rd1_dat_o(rd1_dat), .rd1_read_i(rd1_read), .rd1_done_i(rd1_done), - .rd1_error_i(rd1_error), .rd1_sop_o(rd1_sop), .rd1_eop_o(rd1_eop), - .rd2_dat_o(rd2_dat), .rd2_read_i(rd2_read), .rd2_done_i(rd2_done), - .rd2_error_i(rd2_error), .rd2_sop_o(rd2_sop), .rd2_eop_o(rd2_eop), - .rd3_dat_o(rd3_dat), .rd3_read_i(rd3_read), .rd3_done_i(rd3_done), - .rd3_error_i(rd3_error), .rd3_sop_o(rd3_sop), .rd3_eop_o(rd3_eop) - ); - - // SPI -- Slave #2 - spi_top shared_spi - (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o), - .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb), - .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(s2_err),.wb_int_o(spi_int), - .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}), - .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) ); - - assign s2_rty = 1'b0; - - // I2C -- Slave #3 - i2c_master_top #(.ARST_LVL(1)) - i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), - .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]), - .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc), - .wb_ack_o(s3_ack),.wb_inta_o(i2c_int), - .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o), - .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) ); - - assign s3_dat_i[31:8] = 24'd0; - assign s3_err = 1'b0; - assign s3_rty = 1'b0; - - // GPIOs -- Slave #4 - nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we), - .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack), - .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1), - .gpio( {io_tx,io_rx} ) ); - assign s4_err = 1'b0; - assign s4_rty = 1'b0; - - // Buffer Pool Status -- Slave #5 - wb_readback_mux buff_pool_status - (.wb_clk_i(wb_clk), - .wb_rst_i(wb_rst), - .wb_stb_i(s5_stb), - .wb_adr_i(s5_adr), - .wb_dat_o(s5_dat_i), - .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), - .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(32'b0), - .word11(32'b0),.word12(32'b0),.word13(32'b0),.word14(32'b0),.word15(32'b0) - ); - - assign s5_err = 1'b0; - assign s5_rty = 1'b0; - - // Slave, #6 Ethernet MAC, see below - - // Settings Bus -- Slave #7 - settings_bus settings_bus - (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o), - .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack), - .sys_clk(dsp_clk),.strobe(set_stb),.addr(set_addr),.data(set_data)); - - assign s7_err = 1'b0; - assign s7_rty = 1'b0; - assign s7_dat_i = 32'd0; - - // Output control lines - wire [7:0] clock_outs, serdes_outs, adc_outs; - assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0]; - assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0]; - assign {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0]; - - wire phy_reset; - assign PHY_RESETn = ~phy_reset; - - setting_reg #(.my_addr(0)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), - .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phy_reset),.changed()); - - // ///////////////////////////////////////////////////////////////////////// - // LEDS - // register 8 determines whether leds are controlled by SW or not - // 1 = controlled by HW, 0 = by SW - // In Rev3 there are only 6 leds, and the highest one is on the ETH connector - - wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {clk_status,serdes_link_up}; - - setting_reg #(.my_addr(3)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8)) sr_led_src (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(led_src),.changed()); - - assign leds = (led_src & led_hw) | (~led_src & led_sw); - - // ///////////////////////////////////////////////////////////////////////// - // Ethernet MAC Slave #6 - - wire Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop; - wire Rx_mac_empty, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_err; - wire [31:0] Tx_mac_data, Rx_mac_data; - wire [1:0] Tx_mac_BE, Rx_mac_BE; - wire rst_mac; - - oneshot_2clk mac_rst_1shot (.clk_in(wb_clk),.in(wb_rst),.clk_out(clk_to_mac),.out(rst_mac)); - - MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11)) - MAC_top - (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk), - .rst_mac(rst_mac),.rst_user(dsp_rst), - .RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]), - .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE), - .Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD), - .Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD), - .Crs(GMII_CRS),.Col(GMII_COL), - .Mdio(MDIO),.Mdc(MDC), - .rx_fifo_occupied(eth_rx_occ2),.rx_fifo_full(eth_rx_full2),.rx_fifo_empty(eth_rx_empty2), - .tx_fifo_occupied(),.tx_fifo_full(),.tx_fifo_empty(), - .debug0(debug_mac0),.debug1(debug_mac1) ); - - assign s6_err = 1'b0; - assign s6_rty = 1'b0; - - mac_rxfifo_int mac_rxfifo_int - (.clk(dsp_clk),.rst(dsp_rst), - .Rx_mac_empty(Rx_mac_empty),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data), - .Rx_mac_BE(Rx_mac_BE),.Rx_mac_sop(Rx_mac_sop), - .Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err), - .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done), - .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full), - .fifo_occupied(eth_rx_occ),.fifo_full(eth_rx_full),.fifo_empty(eth_rx_empty) ); - - mac_txfifo_int mac_txfifo_int - (.clk(dsp_clk),.rst(dsp_rst),.mac_clk(clk_to_mac), - .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data), - .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop), - .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done), - .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop), - .fifo_occupied(eth_tx_occ),.fifo_full(eth_tx_full),.fifo_empty(eth_tx_empty) ); - - // ///////////////////////////////////////////////////////////////////////// - // Interrupt Controller, Slave #8 - - wire [15:0] irq={{4'b0, clk_status, serdes_link_up, uart_tx_int, uart_rx_int}, - {pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}}; - - simple_pic #(.is(16),.dwidth(32)) simple_pic - (.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]), - .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int), - .irq(irq) ); - assign s8_err = 0; - assign s8_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // Master Timer, Slave #9 - - wire [31:0] master_time; - timer timer - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]), - .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack), - .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) ); - assign s9_err = 0; - assign s9_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // UART, Slave #10 - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart // depth of 3 is 128 entries - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s10_we),.stb_i(s10_stb),.cyc_i(s10_cyc),.ack_o(s10_ack), - .adr_i(s10_adr[4:2]),.dat_i(s10_dat_o),.dat_o(s10_dat_i), - .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int), - .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o)); - - assign s10_err = 0; - assign s10_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // ATR Controller, Slave #11 - - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - - atr_controller atr_controller - (.clk_i(wb_clk),.rst_i(wb_rst), - .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i), - .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); - assign s11_err = 0; - assign s11_rty = 0; - - // ////////////////////////////////////////////////////////////////////////// - // Time Sync, Slave #12 - - reg pps_posedge, pps_negedge, pps_pos_d1, pps_neg_d1; - always @(negedge dsp_clk) pps_negedge <= pps_in; - always @(posedge dsp_clk) pps_posedge <= pps_in; - always @(posedge dsp_clk) pps_pos_d1 <= pps_posedge; - always @(posedge dsp_clk) pps_neg_d1 <= pps_negedge; - - wire pps_o; - time_sync time_sync - (.wb_clk_i(wb_clk),.rst_i(wb_rst), - .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]), - .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack), - .sys_clk_i(dsp_clk),.master_time_o(master_time), - .pps_posedge(pps_posedge),.pps_negedge(pps_negedge), - .exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out), - .int_o(pps_int),.epoch_o(epoch),.pps_o(pps_o) ); - assign s12_err = 0; - assign s12_rty = 0; - - // ///////////////////////////////////////////////////////////////////////// - // SD Card Reader / Writer, Slave #13 - - sd_spi_wb sd_spi_wb - (.clk(wb_clk),.rst(wb_rst), - .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .wb_cyc_i(s13_cyc),.wb_stb_i(s13_stb),.wb_we_i(s13_we), - .wb_adr_i(s13_adr[3:2]),.wb_dat_i(s13_dat_o),.wb_dat_o(s13_dat_i), - .wb_ack_o(s13_ack) ); - assign s13_err = 0; - assign s13_rty = 0; - // ///////////////////////////////////////////////////////////////////////// - // DSP - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - - rx_control #(.FIFOSIZE(10)) rx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.overrun(overrun), - .wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done), .wr_error_o(wr1_error), - .wr_ready_i(wr1_ready), .wr_full_i(wr1_full), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), - .debug_rx(debug_rx) ); - - // dummy_rx dsp_core_rx - dsp_core_rx dsp_core_rx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(io_rx),.sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); - - tx_control #(.FIFOSIZE(10)) tx_control - (.clk(dsp_clk), .rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .master_time(master_time),.underrun(underrun), - .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop), - .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), - .fifo_occupied(dsp_tx_occ),.fifo_full(dsp_tx_full),.fifo_empty(dsp_tx_empty), - .debug(debug_txc) ); - - dsp_core_tx dsp_core_tx - (.clk(dsp_clk),.rst(dsp_rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .dac_a(dac_a),.dac_b(dac_b), - .sample(sample_tx), .run(run_tx), .strobe(strobe_tx), .debug(debug_tx_dsp) ); - - assign dsp_rst = wb_rst; - - // /////////////////////////////////////////////////////////////////////////////////// - // SERDES - - serdes #(.TXFIFOSIZE(9),.RXFIFOSIZE(9)) serdes - (.clk(dsp_clk),.rst(dsp_rst), - .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_read_o(rd0_read),.rd_done_o(rd0_done),.rd_error_o(rd0_error), - .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop), - .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error), - .wr_ready_i(wr0_ready),.wr_full_i(wr0_full), - .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), - .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), - .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); - -`ifdef EXTRAM - // /////////////////////////////////////////////////////////////////////////////////// - // External RAM Interface - - localparam PAGE_SIZE = 10; // PAGE SIZE is in bytes, 10 = 1024 bytes - - wire [15:0] bus2ram, ram2bus; - wire [15:0] bridge_adr; - wire [1:0] bridge_sel; - wire bridge_stb, bridge_cyc, bridge_we, bridge_ack; - - wire [19:0] page; - wire [19:0] wb_ram_adr = {page[19:PAGE_SIZE],bridge_adr[PAGE_SIZE-1:0]}; - setting_reg #(.my_addr(6)) sr_page (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(page),.changed()); - - wb_bridge_16_32 bridge - (.wb_clk(wb_clk),.wb_rst(wb_rst), - .A_cyc_i(s14_cyc),.A_stb_i(s14_stb),.A_we_i(s14_we),.A_sel_i(s14_sel), - .A_adr_i(s14_adr),.A_dat_i(s14_dat_o),.A_dat_o(s14_dat_i),.A_ack_o(s14_ack), - .B_cyc_o(bridge_cyc),.B_stb_o(bridge_stb),.B_we_o(bridge_we),.B_sel_o(bridge_sel), - .B_adr_o(bridge_adr),.B_dat_o(bus2ram),.B_dat_i(ram2bus),.B_ack_i(bridge_ack)); - - wb_zbt16_b wb_zbt16_b - (.clk(wb_clk),.rst(wb_rst), - .wb_adr_i(wb_ram_adr),.wb_dat_i(bus2ram),.wb_dat_o(ram2bus),.wb_sel_i(bridge_sel), - .wb_cyc_i(bridge_cyc),.wb_stb_i(bridge_stb),.wb_ack_o(bridge_ack),.wb_we_i(bridge_we), - .sram_clk(RAM_CLK),.sram_a(RAM_A),.sram_d(RAM_D[15:0]),.sram_we(RAM_WEn), - .sram_bw(),.sram_adv(RAM_LDn),.sram_ce(RAM_CENn),.sram_oe(RAM_OEn), - .sram_mode(),.sram_zz() ); - - assign s14_err = 0; assign s14_rty = 0; - assign RAM_CE1n = 0; - assign RAM_D[17:16] = 2'bzz; -`endif - -`ifdef DEBUG - // ///////////////////////////////////////////////////////////////////////////////////////// - // Debug Pins - - // FIFO Level Debugging - reg [31:0] host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo; - - always @(posedge dsp_clk) - serdes_to_dsp_fifo <= { {ser_rx_full,ser_rx_empty,ser_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_serdes_fifo <= { {ser_tx_full,ser_tx_empty,ser_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - host_to_dsp_fifo <= { {eth_rx_full,eth_rx_empty,eth_rx_occ[13:0]}, - {dsp_tx_full,dsp_tx_empty,dsp_tx_occ[13:0]} }; - - always @(posedge dsp_clk) - dsp_to_host_fifo <= { {eth_tx_full,eth_tx_empty,eth_tx_occ[13:0]}, - {dsp_rx_full,dsp_rx_empty,dsp_rx_occ[13:0]} }; - - always @(posedge dsp_clk) - eth_mac_debug <= { { 6'd0, GMII_TX_EN, GMII_RX_DV, debug_mac0[7:0]}, - {eth_rx_full2, eth_rx_empty2, eth_rx_occ2[13:0]} }; - - assign debug_clk[0] = 0; - assign debug_clk[1] = dsp_clk; - - assign debug = host_to_dsp_fifo; // debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; -`endif - -endmodule // u2_core - -// wire debug_mux; -// setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), -// .in(set_data),.out(debug_mux),.changed()); - -//assign debug = debug_mux ? host_to_dsp_fifo : dsp_to_host_fifo; -//assign debug = debug_mux ? serdes_to_dsp_fifo : dsp_to_serdes_fifo; - -//assign debug = {{strobe_rx,/*adc_ovf_a*/ 1'b0,adc_a}, -// {run_rx,/*adc_ovf_b*/ 1'b0,adc_b}}; - -//assign debug = debug_tx_dsp; -//assign debug = debug_serdes0; - -//assign debug_gpio_0 = 0; //debug_serdes0; -//assign debug_gpio_1 = 0; //debug_serdes1; - -// assign debug={{3'b0, wb_clk, wb_rst, dsp_rst, por, config_success}, -// {8'b0}, -// {3'b0,ram_loader_ack, ram_loader_stb, ram_loader_we,ram_loader_rst,ram_loader_done }, -// {cpld_start,cpld_mode,cpld_done,cpld_din,cpld_clk,cpld_detached,cpld_misc,cpld_init_b} }; - -//assign debug = {dac_a,dac_b}; - -/* - assign debug = {{ram_loader_done, takeover, 6'd0}, - {1'b0, cpld_start_int, cpld_mode_int, cpld_done_int, sd_clk, sd_csn, sd_miso, sd_mosi}, - {8'd0}, - {cpld_start, cpld_mode, cpld_done, cpld_din, cpld_misc, cpld_detached, cpld_clk, cpld_init_b}}; */ - -/*assign debug = host_to_dsp_fifo; - assign debug_gpio_0 = eth_mac_debug; - assign debug_gpio_1 = 0; - */ -// Assign various commonly used debug buses. -/* - wire [31:0] debug_rx_1 = {uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV, - irq[7:0], - GMII_RXD, - GMII_TXD}; - - wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] }; - - wire [31:0] debug_time = {uart_tx_o, 7'b0, - irq[7:0], - 6'b0, GMII_RX_DV, GMII_TX_EN, - 4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int}; - - wire [31:0] debug_irq = {uart_tx_o, iwb_adr, iwb_ack, - irq[7:0], - proc_int, 7'b0 }; - - wire [31:0] debug_eth = - {{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write}, - {8'd0}, - {8'd0}, - {GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full} }; - - assign debug_serdes0 = { { rd0_dat[7:0] }, - { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, rd0_eop, rd0_read, rd0_error, rd0_done }, - { ser_t[15:8] }, - { ser_t[7:0] } }; - - assign debug_serdes1 = { {1'b0,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write}, - { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, ser_enable, ser_prbsen, ser_loopen, ser_rx_en }, - { ser_r[15:8] }, - { ser_r[7:0] } }; - - assign debug_gpio_1 = {uart_tx_o,7'd0, - 3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error, - debug_txc[15:0]}; - assign debug_gpio_1 = debug_rx; - assign debug_gpio_1 = debug_serdes1; - assign debug_gpio_1 = debug_eth; - - */ - diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh b/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/fpga/usrp2/top/u2_rev3_2rx_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/fpga/usrp2/top/u2_rev3_iad/.gitignore b/fpga/usrp2/top/u2_rev3_iad/.gitignore deleted file mode 100644 index e4daaf1ea..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/build -/*.vcd -/dsp_core_tb -/*.dat diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile deleted file mode 100644 index 15df9e43e..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/Makefile +++ /dev/null @@ -1,253 +0,0 @@ -# -# Copyright 2008 Ettus Research LLC -# -# This file is part of GNU Radio -# -# GNU Radio is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3, or (at your option) -# any later version. -# -# GNU Radio is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GNU Radio; see the file COPYING. If not, write to -# the Free Software Foundation, Inc., 51 Franklin Street, -# Boston, MA 02110-1301, USA. -# - -################################################## -# xtclsh Shell and tcl Script Path -################################################## -#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh -XTCLSH := xtclsh -ISE_HELPER := ../tcl/ise_helper.tcl - -################################################## -# Project Setup -################################################## -BUILD_DIR := build/ -export TOP_MODULE := u2_rev3 -export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise - -################################################## -# Project Properties -################################################## -export PROJECT_PROPERTIES := \ -family Spartan3 \ -device xc3s2000 \ -package fg456 \ -speed -5 \ -top_level_module_type "HDL" \ -synthesis_tool "XST (VHDL/Verilog)" \ -simulator "ISE Simulator (VHDL/Verilog)" \ -"Preferred Language" "Verilog" \ -"Enable Message Filtering" FALSE \ -"Display Incremental Messages" FALSE - -################################################## -# Sources -################################################## -export SOURCE_ROOT := ../../../ -export SOURCES := \ -control_lib/CRC16_D16.v \ -control_lib/atr_controller.v \ -control_lib/bin2gray.v \ -control_lib/buffer_int.v \ -control_lib/buffer_pool.v \ -control_lib/cascadefifo2.v \ -control_lib/dcache.v \ -control_lib/decoder_3_8.v \ -control_lib/dpram32.v \ -control_lib/fifo_2clock.v \ -control_lib/fifo_2clock_casc.v \ -control_lib/gray2bin.v \ -control_lib/gray_send.v \ -control_lib/icache.v \ -control_lib/longfifo.v \ -control_lib/mux4.v \ -control_lib/mux8.v \ -control_lib/nsgpio.v \ -control_lib/ram_2port.v \ -control_lib/ram_harv_cache.v \ -control_lib/ram_loader.v \ -control_lib/setting_reg.v \ -control_lib/settings_bus.v \ -control_lib/shortfifo.v \ -control_lib/medfifo.v \ -control_lib/srl.v \ -control_lib/system_control.v \ -control_lib/wb_1master.v \ -control_lib/wb_readback_mux.v \ -control_lib/simple_uart.v \ -control_lib/simple_uart_tx.v \ -control_lib/simple_uart_rx.v \ -control_lib/oneshot_2clk.v \ -control_lib/sd_spi.v \ -control_lib/sd_spi_wb.v \ -control_lib/wb_bridge_16_32.v \ -coregen/fifo_xlnx_2Kx36_2clk.v \ -coregen/fifo_xlnx_2Kx36_2clk.xco \ -coregen/fifo_xlnx_512x36_2clk.v \ -coregen/fifo_xlnx_512x36_2clk.xco \ -eth/mac_rxfifo_int.v \ -eth/mac_txfifo_int.v \ -eth/rtl/verilog/Clk_ctrl.v \ -eth/rtl/verilog/MAC_rx.v \ -eth/rtl/verilog/MAC_rx/Broadcast_filter.v \ -eth/rtl/verilog/MAC_rx/CRC_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_FF.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v \ -eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v \ -eth/rtl/verilog/MAC_top.v \ -eth/rtl/verilog/MAC_tx.v \ -eth/rtl/verilog/MAC_tx/CRC_gen.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_FF.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v \ -eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v \ -eth/rtl/verilog/MAC_tx/Random_gen.v \ -eth/rtl/verilog/Phy_int.v \ -eth/rtl/verilog/RMON.v \ -eth/rtl/verilog/RMON/RMON_addr_gen.v \ -eth/rtl/verilog/RMON/RMON_ctrl.v \ -eth/rtl/verilog/Reg_int.v \ -eth/rtl/verilog/eth_miim.v \ -eth/rtl/verilog/flow_ctrl_rx.v \ -eth/rtl/verilog/flow_ctrl_tx.v \ -eth/rtl/verilog/miim/eth_clockgen.v \ -eth/rtl/verilog/miim/eth_outputcontrol.v \ -eth/rtl/verilog/miim/eth_shiftreg.v \ -opencores/8b10b/decode_8b10b.v \ -opencores/8b10b/encode_8b10b.v \ -opencores/aemb/rtl/verilog/aeMB_bpcu.v \ -opencores/aemb/rtl/verilog/aeMB_core_BE.v \ -opencores/aemb/rtl/verilog/aeMB_ctrl.v \ -opencores/aemb/rtl/verilog/aeMB_edk32.v \ -opencores/aemb/rtl/verilog/aeMB_ibuf.v \ -opencores/aemb/rtl/verilog/aeMB_regf.v \ -opencores/aemb/rtl/verilog/aeMB_xecu.v \ -opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \ -opencores/i2c/rtl/verilog/i2c_master_defines.v \ -opencores/i2c/rtl/verilog/i2c_master_top.v \ -opencores/i2c/rtl/verilog/timescale.v \ -opencores/simple_pic/rtl/simple_pic.v \ -opencores/spi/rtl/verilog/spi_clgen.v \ -opencores/spi/rtl/verilog/spi_defines.v \ -opencores/spi/rtl/verilog/spi_shift.v \ -opencores/spi/rtl/verilog/spi_top.v \ -opencores/spi/rtl/verilog/timescale.v \ -sdr_lib/acc.v \ -sdr_lib/add2.v \ -sdr_lib/add2_and_round.v \ -sdr_lib/add2_and_round_reg.v \ -sdr_lib/add2_reg.v \ -sdr_lib/cic_dec_shifter.v \ -sdr_lib/cic_decim.v \ -sdr_lib/cic_int_shifter.v \ -sdr_lib/cic_interp.v \ -sdr_lib/cic_strober.v \ -sdr_lib/clip.v \ -sdr_lib/clip_reg.v \ -sdr_lib/cordic.v \ -sdr_lib/cordic_z24.v \ -sdr_lib/cordic_stage.v \ -sdr_lib/dsp_core_tx.v \ -sdr_lib/hb_dec.v \ -sdr_lib/hb_interp.v \ -sdr_lib/integrate.v \ -sdr_lib/round.v \ -sdr_lib/round_reg.v \ -sdr_lib/rx_control.v \ -sdr_lib/rx_dcoffset.v \ -sdr_lib/sign_extend.v \ -sdr_lib/small_hb_dec.v \ -sdr_lib/small_hb_int.v \ -sdr_lib/tx_control.v \ -serdes/serdes.v \ -serdes/serdes_fc_rx.v \ -serdes/serdes_fc_tx.v \ -serdes/serdes_rx.v \ -serdes/serdes_tx.v \ -timing/time_receiver.v \ -timing/time_sender.v \ -timing/time_sync.v \ -timing/timer.v \ -top/u2_core/u2_core.v \ -top/u2_rev3/u2_rev3.ucf \ -top/u2_rev3/u2_rev3.v \ -top/u2_rev3_iad/dsp_core_rx.v - -################################################## -# Process Properties -################################################## -export SYNTHESIZE_PROPERTIES := \ -"Number of Clock Buffers" 6 \ -"Pack I/O Registers into IOBs" Yes \ -"Optimization Effort" High \ -"Optimize Instantiated Primitives" TRUE \ -"Register Balancing" Yes \ -"Use Clock Enable" Auto \ -"Use Synchronous Reset" Auto \ -"Use Synchronous Set" Auto - -export TRANSLATE_PROPERTIES := \ -"Macro Search Path" "$(shell pwd)/../../coregen/" - -export MAP_PROPERTIES := \ -"Allow Logic Optimization Across Hierarchy" TRUE \ -"Map to Input Functions" 4 \ -"Optimization Strategy (Cover Mode)" Speed \ -"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ -"Perform Timing-Driven Packing and Placement" TRUE \ -"Map Effort Level" High \ -"Extra Effort" Normal \ -"Combinatorial Logic Optimization" TRUE \ -"Register Duplication" TRUE - -export PLACE_ROUTE_PROPERTIES := \ -"Place & Route Effort Level (Overall)" High - -export STATIC_TIMING_PROPERTIES := \ -"Number of Paths in Error/Verbose Report" 10 \ -"Report Type" "Error Report" - -export GEN_PROG_FILE_PROPERTIES := \ -"Configuration Rate" 6 \ -"Create Binary Configuration File" TRUE \ -"Done (Output Events)" 5 \ -"Enable Bitstream Compression" TRUE \ -"Enable Outputs (Output Events)" 6 - -export SIM_MODEL_PROPERTIES := "" - -################################################## -# Make Options -################################################## -all: - @echo make proj, check, synth, bin, testbench, or clean - -proj: - PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER) - -check: - PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER) - -synth: - PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER) - -bin: - PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER) - -testbench: - iverilog -c cmdfile -o dsp_core_tb dsp_core_tb.v - -clean: - rm -rf $(BUILD_DIR) - rm -f dsp_core_tb - rm -f *.lx2 - rm -f *.dat - rm -f *.vcd diff --git a/fpga/usrp2/top/u2_rev3_iad/cmdfile b/fpga/usrp2/top/u2_rev3_iad/cmdfile deleted file mode 100644 index 34373a676..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/cmdfile +++ /dev/null @@ -1,4 +0,0 @@ --y . --y ../../sdr_lib --y ../../control_lib --y ../../models diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v deleted file mode 100644 index 2882464ba..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/dsp_core_rx.v +++ /dev/null @@ -1,158 +0,0 @@ -`define DSP_CORE_RX_BASE 160 -module dsp_core_rx - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - input [13:0] adc_a, input adc_ovf_a, - input [13:0] adc_b, input adc_ovf_b, - - input [15:0] io_rx, - - output [31:0] sample, - input run, - output strobe, - output [31:0] debug - ); - - wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; - reg [13:0] adc_i, adc_q; - wire [31:0] phase_inc; - reg [31:0] phase; - - wire [35:0] prod_i, prod_q; - wire [23:0] i_cordic, q_cordic; - wire [31:0] i_iad, q_iad; - wire [15:0] i_out, q_out; - - wire enable_hb1, enable_hb2; // Correspond to std firmware settings - wire [7:0] cic_decim; // for combined CIC/HB decimator - wire [9:0] decim_rate; // Reconstructed original decimation setting - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(phase_inc),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({scale_i,scale_q}),.changed()); - - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1,enable_hb2,cic_decim}),.changed()); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_a),.adc_out(adc_a_ofs)); - - rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b - (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_in(adc_b),.adc_out(adc_b_ofs)); - - wire [3:0] muxctrl; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(muxctrl),.changed()); - - wire [1:0] gpio_ena; - setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9 - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(gpio_ena),.changed()); - - // The TVRX connects to what is called adc_b, thus A and B are - // swapped throughout the design. - // - // In the interest of expediency and keeping the s/w sane, we just remap them here. - // The I & Q fields are mapped the same: - // 0 -> "the real A" (as determined by the TVRX) - // 1 -> "the real B" - // 2 -> const zero - - always @(posedge clk) - case(muxctrl[1:0]) // The I mapping - 0: adc_i <= adc_b_ofs; // "the real A" - 1: adc_i <= adc_a_ofs; - 2: adc_i <= 0; - default: adc_i <= 0; - endcase // case(muxctrl[1:0]) - - always @(posedge clk) - case(muxctrl[3:2]) // The Q mapping - 0: adc_q <= adc_b_ofs; // "the real A" - 1: adc_q <= adc_a_ofs; - 2: adc_q <= 0; - default: adc_q <= 0; - endcase // case(muxctrl[3:2]) - - always @(posedge clk) - if(rst) - phase <= 0; - else if(~run) - phase <= 0; - else - phase <= phase + phase_inc; - - MULT18X18S mult_i - (.P(prod_i), // 36-bit multiplier output - .A({{4{adc_i[13]}},adc_i} ), // 18-bit multiplier input - .B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - MULT18X18S mult_q - (.P(prod_q), // 36-bit multiplier output - .A({{4{adc_q[13]}},adc_q} ), // 18-bit multiplier input - .B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input - .C(clk), // Clock input - .CE(1), // Clock enable input - .R(rst) // Synchronous reset input - ); - - - cordic_z24 #(.bitwidth(24)) - cordic(.clock(clk), .reset(rst), .enable(run), - .xi(prod_i[24:1]),. yi(prod_q[24:1]), .zi(phase[31:8]), - .xo(i_cordic),.yo(q_cordic),.zo() ); - - // Reconstruct original decimation rate from standard firmware settings - assign decim_rate = enable_hb2 ? (enable_hb1 ? {cic_decim,2'b0} : - {1'b0,cic_decim,1'b0 }) : - cic_decim; - - cic_strober #(.WIDTH(10)) // Convenient reuse of strobe generator - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(decim_rate), - .strobe_fast(1),.strobe_slow(strobe_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_i - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(i_cordic), - .stb_o(strobe),.integ_o(i_iad) ); - - integrate #(.INPUTW(24),.ACCUMW(32),.OUTPUTW(32)) integrator_q - (.clk_i(clk),.rst_i(rst),.ena_i(run), - .dump_i(strobe_iad),.data_i(q_cordic), - .stb_o(),.integ_o(q_iad) ); - - round #(.bits_in(32),.bits_out(16)) round_iout (.in(i_iad),.out(i_out)); - round #(.bits_in(32),.bits_out(16)) round_qout (.in(q_iad),.out(q_out)); - - // Streaming GPIO - // - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - - reg [31:0] sample_reg; - always @(posedge clk) - begin - sample_reg[31:17] <= i_out[15:1]; - sample_reg[15:1] <= q_out[15:1]; - sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; - sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; - end - - assign sample = sample_reg; - assign debug = {clk, rst, run, strobe}; - -endmodule // dsp_core_rx diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav deleted file mode 100644 index 17c90cdd7..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.sav +++ /dev/null @@ -1,61 +0,0 @@ -[size] 1680 975 -[pos] -1 -1 -*-24.007835 13660000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] dsp_core_tb. -@200 --SYSCON -@28 -dsp_core_tb.clk -dsp_core_tb.rst -dsp_core_tb.run -@200 -- --Settings Bus -@22 -dsp_core_tb.set_addr[7:0] -@24 -dsp_core_tb.set_data[31:0] -@28 -dsp_core_tb.set_stb -@200 -- --RX DSP CORE -- -@24 -dsp_core_tb.rx_path.decim_rate[9:0] -@200 -- -@8420 -dsp_core_tb.adc_a[13:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.adc_a_ofs[13:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_cordic[23:0] -@20000 -- -@200 -- -@8022 -dsp_core_tb.rx_path.i_iad[31:0] -@20000 -- -@200 -- -@8420 -dsp_core_tb.rx_path.i_out[15:0] -@20000 -- -@200 -- -@28 -dsp_core_tb.stb -@200 -- diff --git a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v b/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v deleted file mode 100644 index 4d5a5b537..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/dsp_core_tb.v +++ /dev/null @@ -1,196 +0,0 @@ -`timescale 1ns / 100ps - -module dsp_core_tb; - -/////////////////////////////////////////////////////////////////////////////////// -// Sim-wide wires/busses // -/////////////////////////////////////////////////////////////////////////////////// - - // System control bus - reg clk = 0; - reg rst = 1; - - // Configuration bus - reg set_stb = 0; - reg [7:0] set_addr = 0; - reg [31:0] set_data = 0; - - // ADC input bus - wire signed [13:0] adc_a; - wire signed [13:0] adc_b; - wire adc_ovf_a; - wire adc_ovf_b; - - // RX sample bus - reg run = 1; - wire [31:0] sample; - wire stb; - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation control // -/////////////////////////////////////////////////////////////////////////////////// - - // Set up output files - initial begin - $dumpfile("dsp_core_tb.vcd"); - $dumpvars(0,dsp_core_tb); - end - - // Update display every 10 us - always #1000 $monitor("Time in us ",$time/1000); - - // Generate master clock 50% @ 100 MHz - always - #5 clk = ~clk; - -/////////////////////////////////////////////////////////////////////////////////// -// Unit(s) under test // -/////////////////////////////////////////////////////////////////////////////////// - - reg [13:0] amplitude = 13'h1fff; - reg [15:0] impulse_len = 0; - reg [15:0] zero_len = 0; - reg adc_ena = 0; - - initial #500 @(posedge clk) adc_ena = 1; - - impulse adc - (.clk(clk),.rst(rst),.ena(adc_ena), - .dc_offset_a(0),.dc_offset_b(0), - .amplitude(amplitude), - .impulse_len(impulse_len),.zero_len(zero_len), - .adc_a(adc_a),.adc_b(adc_b), - .adc_ovf_a(adc_ovf_a),.adc_ovf_b(adc_ovf_b) ); - - initial rx_path.rx_dcoffset_a.integrator = 0; // so sim doesn't propagate X's - initial rx_path.rx_dcoffset_b.integrator = 0; // generated before reset - dsp_core_rx rx_path - (.clk(clk),.rst(rst), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .adc_a(adc_a),.adc_ovf_a(adc_ovf_a), - .adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .io_rx(16'b0), - .run(adc_ena),.sample(sample),.strobe(stb), - .debug() ); - -/////////////////////////////////////////////////////////////////////////////////// -// Simulation output/checking // -/////////////////////////////////////////////////////////////////////////////////// - - integer rx_file; - - initial - rx_file = $fopen("rx.dat", "wb"); - - always @(posedge clk) - begin - // Write RX sample I&Q in format Octave can load - if (stb) - begin - $fwrite(rx_file, sample[31:16]); - $fputc(32, rx_file); - $fwrite(rx_file, sample[15:0]); - $fputc(13, rx_file); - end - end - -/////////////////////////////////////////////////////////////////////////////////// -// Tasks // -/////////////////////////////////////////////////////////////////////////////////// - - task power_on; - begin - @(posedge clk) - rst = #1 1'b1; - @(posedge clk) - rst = #1 1'b0; - end - endtask // power_on - - task set_impulse_len; - input [15:0] len; - @(posedge clk) impulse_len = len-1; - endtask - - task set_zero_len; - input [15:0] len; - @(posedge clk) zero_len = len-1; - endtask - - // Strobe configuration bus with addr, data - task write_cfg_register; - input [7:0] regno; - input [31:0] value; - - begin - @(posedge clk); - set_addr <= regno; - set_data <= value; - set_stb <= 1'b1; - @(posedge clk); - set_stb <= 1'b0; - end - endtask // write_cfg_register - - // Set RX DDC frequency - task set_ddc_freq; - input [31:0] freq; - - write_cfg_register(160, freq); - endtask // set_ddc_freq - - // Set RX IQ scaling registers - task set_rx_scale_iq; - input [15:0] scale_i; - input [15:0] scale_q; - - write_cfg_register(161, {scale_i,scale_q}); - endtask // set_rx_scale_iq - - // Set RX MUX control - task set_rx_muxctrl; - input [3:0] muxctrl; - - write_cfg_register(168, muxctrl); - endtask // set_rx_muxctrl - - // Set RX CIC decim and halfband enables - task set_decim; - input hb1_ena; - input hb2_ena; - input [7:0] decim; - - write_cfg_register(162, {hb1_ena,hb2_ena,decim}); - endtask // set_decim - - -/////////////////////////////////////////////////////////////////////////////////// -// Individual tests // -/////////////////////////////////////////////////////////////////////////////////// - - task test_rx; - begin - set_impulse_len(1); - set_zero_len(999); - set_rx_muxctrl(1); - set_ddc_freq(0); - set_rx_scale_iq(1243, 1243); - set_decim(0, 1, 3); - - #100000 $finish; - end - endtask // test_rx - - -/////////////////////////////////////////////////////////////////////////////////// -// Top-level test // -/////////////////////////////////////////////////////////////////////////////////// - - // Execute tests - initial - begin - power_on(); - test_rx(); - end - -endmodule // dsp_core_tb diff --git a/fpga/usrp2/top/u2_rev3_iad/impulse.v b/fpga/usrp2/top/u2_rev3_iad/impulse.v deleted file mode 100644 index 7f0cdc9be..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/impulse.v +++ /dev/null @@ -1,63 +0,0 @@ -module impulse - (input clk, - input rst, - input ena, - - input [13:0] dc_offset_a, - input [13:0] dc_offset_b, - input [13:0] amplitude, - input [15:0] impulse_len, - input [15:0] zero_len, - - output [13:0] adc_a, - output [13:0] adc_b, - output adc_ovf_a, - output adc_ovf_b - ); - - reg [13:0] adc_a_int = 0; - reg [15:0] count; - - localparam ST_ZERO = 0; - localparam ST_HIGH = 1; - reg state; - - always @(posedge clk) - if (rst | ~ena) - begin - adc_a_int <= 0; - count <= 0; - state <= ST_ZERO; - end - else - case(state) - ST_ZERO: - if (count == zero_len) - begin - adc_a_int <= amplitude; - state <= ST_HIGH; - count <= 0; - end - else - count <= count + 1; - - ST_HIGH: - if (count == impulse_len) - begin - adc_a_int <= 0; - state <= ST_ZERO; - count <= 0; - end - else - count <= count + 1; - - endcase // case (state) - - assign adc_a = adc_a_int + dc_offset_a; - - // Ignore for now - assign adc_b = dc_offset_b; - assign adc_ovf_a = 0; - assign adc_ovf_b = 0; - -endmodule // impulse diff --git a/fpga/usrp2/top/u2_rev3_iad/wave.sh b/fpga/usrp2/top/u2_rev3_iad/wave.sh deleted file mode 100755 index 626f224e5..000000000 --- a/fpga/usrp2/top/u2_rev3_iad/wave.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -gtkwave dsp_core_tb.vcd dsp_core_tb.sav & diff --git a/fpga/usrp2/top/u2plus/capture_ddrlvds.v b/fpga/usrp2/top/u2plus/capture_ddrlvds.v deleted file mode 100644 index b9f53ff8c..000000000 --- a/fpga/usrp2/top/u2plus/capture_ddrlvds.v +++ /dev/null @@ -1,39 +0,0 @@ - - -module capture_ddrlvds - #(parameter WIDTH=7) - (input clk, - input ssclk_p, - input ssclk_n, - input [WIDTH-1:0] in_p, - input [WIDTH-1:0] in_n, - output reg [(2*WIDTH)-1:0] out); - - wire [WIDTH-1:0] ddr_dat; - wire ssclk_regional; - wire ssclk_io; - wire ssclk; - wire [(2*WIDTH)-1:0] out_pre1; - reg [(2*WIDTH)-1:0] out_pre2; - - IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n)); - - genvar i; - generate - for(i = 0; i < WIDTH; i = i + 1) - begin : gen_lvds_pins - IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds - (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) ); - IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2 - (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk), - .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0)); - end - endgenerate - - always @(negedge clk) - out_pre2 <= out_pre1; - - always @(posedge clk) - out <= out_pre2; - -endmodule // capture_ddrlvds diff --git a/fpga/usrp2/udp/add_onescomp.v b/fpga/usrp2/udp/add_onescomp.v index 048842a86..e02604114 100644 --- a/fpga/usrp2/udp/add_onescomp.v +++ b/fpga/usrp2/udp/add_onescomp.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module add_onescomp diff --git a/fpga/usrp2/udp/fifo19_rxrealign.v b/fpga/usrp2/udp/fifo19_rxrealign.v index 35ad90951..da5fd20af 100644 --- a/fpga/usrp2/udp/fifo19_rxrealign.v +++ b/fpga/usrp2/udp/fifo19_rxrealign.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + // Adds a junk line at the beginning of every packet, which the diff --git a/fpga/usrp2/udp/prot_eng_rx.v b/fpga/usrp2/udp/prot_eng_rx.v index 5df158b2b..ccb59b7ff 100644 --- a/fpga/usrp2/udp/prot_eng_rx.v +++ b/fpga/usrp2/udp/prot_eng_rx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + diff --git a/fpga/usrp2/udp/prot_eng_tx.v b/fpga/usrp2/udp/prot_eng_tx.v index b4f6e55b8..40abf3c04 100644 --- a/fpga/usrp2/udp/prot_eng_tx.v +++ b/fpga/usrp2/udp/prot_eng_tx.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module prot_eng_tx #(parameter BASE=0) diff --git a/fpga/usrp2/udp/prot_eng_tx_tb.v b/fpga/usrp2/udp/prot_eng_tx_tb.v index 138794e57..866093ef5 100644 --- a/fpga/usrp2/udp/prot_eng_tx_tb.v +++ b/fpga/usrp2/udp/prot_eng_tx_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module prot_eng_tx_tb(); localparam BASE = 128; diff --git a/fpga/usrp2/udp/udp_wrapper.v b/fpga/usrp2/udp/udp_wrapper.v index f4c642615..20bcb477b 100644 --- a/fpga/usrp2/udp/udp_wrapper.v +++ b/fpga/usrp2/udp/udp_wrapper.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module udp_wrapper #(parameter BASE=0) diff --git a/fpga/usrp2/vrt/Makefile.srcs b/fpga/usrp2/vrt/Makefile.srcs index 4851bc924..166ed44ef 100644 --- a/fpga/usrp2/vrt/Makefile.srcs +++ b/fpga/usrp2/vrt/Makefile.srcs @@ -14,4 +14,5 @@ vita_tx_deframer.v \ vita_tx_chain.v \ gen_context_pkt.v \ trigger_context_pkt.v \ +vita_pkt_gen.v \ )) diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v index cc34cceed..bdfca8237 100644 --- a/fpga/usrp2/vrt/gen_context_pkt.v +++ b/fpga/usrp2/vrt/gen_context_pkt.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module gen_context_pkt diff --git a/fpga/usrp2/vrt/trigger_context_pkt.v b/fpga/usrp2/vrt/trigger_context_pkt.v index 1d456814b..3d9c2e5c6 100644 --- a/fpga/usrp2/vrt/trigger_context_pkt.v +++ b/fpga/usrp2/vrt/trigger_context_pkt.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module trigger_context_pkt diff --git a/fpga/usrp2/vrt/vita_pkt_gen.v b/fpga/usrp2/vrt/vita_pkt_gen.v new file mode 100644 index 000000000..b962254a6 --- /dev/null +++ b/fpga/usrp2/vrt/vita_pkt_gen.v @@ -0,0 +1,59 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + + + +module vita_pkt_gen + (input clk, input reset, input clear, + input [15:0] len, + output [35:0] data_o, output src_rdy_o, input dst_rdy_i); + + reg [15:0] state; + reg [31:0] seq, data; + + wire sof = (state == 0); + wire eof = (state == (len-1)); + wire consume = src_rdy_o & dst_rdy_i; + + assign src_rdy_o = 1; + + always @(posedge clk) + if(reset | clear) + begin + state <= 0; + seq <= 0; + end + else + if(consume) + if(eof) + begin + state <= 0; + seq <= seq + 1; + end + else + state <= state + 1; + + always @* + case(state) + 0 : data <= {24'h000,seq[3:0],len}; + 1 : data <= seq; + default : data <= {~state,state}; + endcase // case (state) + + assign data_o = {2'b00, eof, sof, data}; + +endmodule // vita_pkt_gen diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index 28955d108..1986743b3 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_rx_chain #(parameter BASE=0, diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v index 4c0cef50d..39f32d7fe 100644 --- a/fpga/usrp2/vrt/vita_rx_control.v +++ b/fpga/usrp2/vrt/vita_rx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_rx_control #(parameter BASE=0, diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v index 04b636778..bd09315bc 100644 --- a/fpga/usrp2/vrt/vita_rx_framer.v +++ b/fpga/usrp2/vrt/vita_rx_framer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_rx_framer #(parameter BASE=0, diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v index 023934f39..8cd08a972 100644 --- a/fpga/usrp2/vrt/vita_rx_tb.v +++ b/fpga/usrp2/vrt/vita_rx_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_rx_tb; diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v index fa84d7a2f..542968afa 100644 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ b/fpga/usrp2/vrt/vita_tx_chain.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_tx_chain #(parameter BASE_CTRL=0, diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v index 14b97a215..5df89bdbe 100644 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ b/fpga/usrp2/vrt/vita_tx_control.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_tx_control #(parameter BASE=0, diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v index 163c2af20..06ca27767 100644 --- a/fpga/usrp2/vrt/vita_tx_deframer.v +++ b/fpga/usrp2/vrt/vita_tx_deframer.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_tx_deframer #(parameter BASE=0, diff --git a/fpga/usrp2/vrt/vita_tx_tb.v b/fpga/usrp2/vrt/vita_tx_tb.v index a118ffd4e..b686a8a16 100644 --- a/fpga/usrp2/vrt/vita_tx_tb.v +++ b/fpga/usrp2/vrt/vita_tx_tb.v @@ -1,3 +1,20 @@ +// +// Copyright 2011 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see <http://www.gnu.org/licenses/>. +// + module vita_tx_tb; |