Merge branch 'packet_router_2nd_dsp' into next

50 files changed, 1096 insertions, 2153 deletions

diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index 5ae185ee8..751b40828 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -50,9 +50,4 @@ bootram.v \
 nsgpio16LE.v \
 settings_bus_16LE.v \
 atr_controller16.v \
-newfifo/fifo_pacer.v \
-newfifo/packet_generator32.v \
-newfifo/packet_generator.v \
-newfifo/packet_verifier32.v \
-newfifo/packet_verifier.v \
 ))
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator.v b/fpga/usrp2/control_lib/newfifo/packet_generator.v
deleted file mode 100644
index 6e8b45ccd..000000000
--- a/fpga/usrp2/control_lib/newfifo/packet_generator.v
+++ /dev/null
@@ -1,59 +0,0 @@
-
-
-module packet_generator
-  (input clk, input reset, input clear,
-   output reg [7:0] data_o, output sof_o, output eof_o, 
-   output src_rdy_o, input dst_rdy_i);
-
-   localparam len = 32'd2000;
-
-   reg [31:0] state;
-   reg [31:0] seq;
-   wire [31:0] crc_out;
-   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
-   
-	
-   always @(posedge clk)
-     if(reset | clear)
-       seq <= 0;
-     else
-       if(eof_o & src_rdy_o & dst_rdy_i)
-	 seq <= seq + 1;
-   
-   always @(posedge clk)
-     if(reset | clear)
-       state <= 0;
-     else
-       if(src_rdy_o & dst_rdy_i)
-	 if(state == (len - 1))
-	   state <= 32'hFFFF_FFFC;
-	 else
-	   state <= state + 1;
-
-   always @*
-     case(state)
-       0 :   data_o <= len[7:0];
-       1 :   data_o <= len[15:8];
-       2 :   data_o <= len[23:16];
-       3 :   data_o <= len[31:24];
-       4 :   data_o <= seq[7:0];
-       5 :   data_o <= seq[15:8];
-       6 :   data_o <= seq[23:16];
-       7 :   data_o <= seq[31:24];
-       32'hFFFF_FFFC : data_o <= crc_out[31:24];
-       32'hFFFF_FFFD : data_o <= crc_out[23:16];
-       32'hFFFF_FFFE : data_o <= crc_out[15:8];
-       32'hFFFF_FFFF : data_o <= crc_out[7:0];
-       default : data_o <= state[7:0];
-     endcase // case (state)
-   
-   assign src_rdy_o = 1;
-   assign sof_o = (state == 0);
-   assign eof_o = (state == 32'hFFFF_FFFF);
-
-   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
-   
-   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
-	   .calc(calc_crc), .crc_out(crc_out), .match());
-   
-endmodule // packet_generator
diff --git a/fpga/usrp2/extram/.gitignore b/fpga/usrp2/extram/.gitignore
deleted file mode 100644
index 7fc71ccb6..000000000
--- a/fpga/usrp2/extram/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-/a.out
diff --git a/fpga/usrp2/extram/Makefile.srcs b/fpga/usrp2/extram/Makefile.srcs
deleted file mode 100644
index 90be02142..000000000
--- a/fpga/usrp2/extram/Makefile.srcs
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Copyright 2010 Ettus Research LLC
-#
-
-##################################################
-# Extram Sources
-##################################################
-EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extram/, \
-wb_zbt16_b.v \
-))
diff --git a/fpga/usrp2/extram/extram_interface.v b/fpga/usrp2/extram/extram_interface.v
deleted file mode 100644
index 7554592ba..000000000
--- a/fpga/usrp2/extram/extram_interface.v
+++ /dev/null
@@ -1,53 +0,0 @@
-
-// Temporary buffer pool storage, mostly useful for pre-generated data streams or
-//   for making more space to juggle packets in case of eth frames coming out of order
-
-module extram_interface
-  (input clk, input rst,
-   input set_stb, input [7:0] set_addr, input [31:0] set_data,
-   
-   // Buffer pool interfaces
-   input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o,
-   input rd_sop_i, input rd_eop_i,
-   output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o,
-   input wr_ready_i, input wr_full_i,
-   
-   // RAM Interface
-   inout [17:0] RAM_D,
-   output [18:0] RAM_A,
-   output RAM_CE1n,
-   output RAM_CENn,
-   input RAM_CLK,
-   output RAM_WEn,
-   output RAM_OEn,
-   output RAM_LDn );
-
-   // Command format --
-   //    Read/_Write , start address[17:0]
-   wire [18:0] cmd_in;
-   wire        cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd;
-   wire        empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd;
-   
-   // Dummy logic
-   assign RAM_OEn = 1;
-   
-   setting_reg #(.my_addr(0)) 
-     sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-		 .in(set_data),.out(cmd_in),.changed(cmd_stb));
-   
-   reg 	  cmd_stb_d1;
-   always @(posedge clk) cmd_stb_d1 <= cmd_stb;
-   assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1;
-   assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1;   
-
-   shortfifo #(.WIDTH(19)) wr_cmd_fifo
-     (.clk(clk),.rst(rst),.clear(1'b0),
-      .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd),
-      .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) );
-
-   shortfifo #(.WIDTH(19)) rd_cmd_fifo
-     (.clk(clk),.rst(rst),.clear(1'b0),
-      .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd),
-      .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) );
-
-endmodule // extram_interface
diff --git a/fpga/usrp2/extram/extram_wb.v b/fpga/usrp2/extram/extram_wb.v
deleted file mode 100644
index c8428783a..000000000
--- a/fpga/usrp2/extram/extram_wb.v
+++ /dev/null
@@ -1,146 +0,0 @@
-
-module extram_wb
-  #(parameter PAGE_SIZE = 10,
-    parameter ADDR_WIDTH = 16)
-    (input clk, input rst,
-     input wb_clk, input wb_rst,
-     input cyc_i, input stb_i,
-     input [ADDR_WIDTH-1:0] adr_i,
-     input we_i,
-     input [31:0] dat_i,
-     output reg [31:0] dat_o,
-     output reg ack_o,
-     
-     inout [17:0] RAM_D,
-     output [PAGE_SIZE-2:0] RAM_A,
-     output RAM_CE1n, output RAM_CENn,
-     output RAM_CLK, output RAM_WEn,
-     output RAM_OEn, output RAM_LDn );
-
-   wire     read_acc = stb_i & cyc_i & ~we_i;
-   wire     write_acc = stb_i & cyc_i & we_i;
-   wire     acc = stb_i & cyc_i;
-
-   assign   RAM_CLK = ~wb_clk;   // 50 MHz for now, eventually should be 200 MHz
-   assign   RAM_LDn = 0;        // No burst for now
-   assign   RAM_CENn = 0;       // Use CE1n as our main CE
-
-   reg [PAGE_SIZE-2:1] RAM_addr_reg;
-   always @(posedge wb_clk)
-     if(acc)
-       RAM_addr_reg[PAGE_SIZE-2:1] <= adr_i[PAGE_SIZE-1:2];
-   assign 	       RAM_A[PAGE_SIZE-2:1] = RAM_addr_reg; 
-
-   reg [31:0] 	       ram_out;
-   always @(posedge wb_clk)
-     if(write_acc)
-       ram_out <= dat_i;
-
-   // RAM access state machine
-   localparam RAM_idle = 0;
-   localparam RAM_read_1 = 1;
-   localparam RAM_read_2 = 2;
-   localparam RAM_read_3 = 3;
-   localparam RAM_read_4 = 4;
-   localparam RAM_write_1 = 6;
-   localparam RAM_write_2 = 7;
-   localparam RAM_write_3 = 8;
-   localparam RAM_write_4 = 9;
-
-   reg 	      myOE = 0;
-   reg 	      RAM_OE = 0;
-   reg 	      RAM_WE = 0;
-   reg 	      RAM_EN = 0;
-   reg 	      RAM_A0_reg;
-   reg [3:0]  RAM_state;
-   
-   always @(posedge wb_clk)
-     if(wb_rst)
-       begin
-	  RAM_state <= RAM_idle;
-	  myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-       end
-     else
-       case(RAM_state)
-	 RAM_idle :
-	   if(read_acc & ~ack_o)
-	     begin
-		RAM_state <= RAM_read_1;
-		myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0;
-	     end
-	   else if(write_acc & ~ack_o)
-	     begin
-		RAM_state <= RAM_write_1;
-		myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0;
-	     end
-	   else
-	     begin
-		myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-	     end
-	 RAM_read_1 : 
-	   begin
-	      RAM_state <= RAM_read_2;
-	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 1;
-	   end
-	 RAM_read_2 : 
-	   begin
-	      RAM_state <= RAM_read_3;
-	      myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-	   end
-	 RAM_read_3 : 
-	   begin
-	      RAM_state <= RAM_read_4;
-	      myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-	   end
-	 RAM_read_4 :
-	   begin
-	      RAM_state <= RAM_idle;
-	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-	   end
-	 RAM_write_1 : 
-	   begin
-	      RAM_state <= RAM_write_2;
-	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1;
-	   end
-	 RAM_write_2 : 
-	   begin
-	      RAM_state <= RAM_write_3;
-	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-	   end
-	 RAM_write_3 : 
-	   begin
-	      RAM_state <= RAM_write_4;
-	      myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-	   end
-	 RAM_write_4 : 
-	   begin
-	      RAM_state <= RAM_idle;
-	      myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0;
-	   end
-	 default : RAM_state <= RAM_idle;
-       endcase // case(RAM_state)
-   
-   assign     RAM_A[0] = RAM_A0_reg;
-   assign     RAM_WEn = ~RAM_WE;  // ((RAM_state==RAM_write_1)||(RAM_state==RAM_write_2));
-   assign     RAM_OEn = ~RAM_OE;
-   assign     RAM_CE1n = ~RAM_EN;    // Active low     (RAM_state != RAM_idle);
-   
-   assign     RAM_D[17:16] = 2'bzz;
-   assign     RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) 
-	      : 16'bzzzz_zzzz_zzzz_zzzz;
-
-   always @(posedge wb_clk)
-     if(RAM_state == RAM_read_3)
-       dat_o[15:0] <= RAM_D[15:0];
-     else
-       dat_o[31:16] <= RAM_D[15:0];
-   
-   always @(posedge wb_clk)
-     if(wb_rst)
-       ack_o <= 0;
-     else if((RAM_state == RAM_write_4)||(RAM_state == RAM_read_4))
-       ack_o <= 1;
-     else
-       ack_o <= 0;
-   
-endmodule // extram_wb
diff --git a/fpga/usrp2/extram/wb_zbt16_b.v b/fpga/usrp2/extram/wb_zbt16_b.v
deleted file mode 100644
index d93e21c99..000000000
--- a/fpga/usrp2/extram/wb_zbt16_b.v
+++ /dev/null
@@ -1,63 +0,0 @@
-
-module wb_zbt16_b
-  (input               clk,
-   input               rst,
-   // Wishbone bus A, highest priority, with prefetch
-   input      [19:0]   wb_adr_i,
-   input      [15:0]   wb_dat_i,
-   output reg [15:0]   wb_dat_o,
-   input      [ 1:0]   wb_sel_i,
-   input               wb_cyc_i,
-   input               wb_stb_i,
-   output reg          wb_ack_o,
-   input               wb_we_i,
-   // Memory connection
-   output              sram_clk,
-   output     [18:0]   sram_a,
-   inout      [15:0]   sram_d,
-   output              sram_we,
-   output     [ 1:0]   sram_bw,
-   output              sram_adv,
-   output              sram_ce,
-   output              sram_oe,
-   output              sram_mode,
-   output              sram_zz
-   );
-
-   assign 	       sram_clk = ~clk;
-   //assign 	       sram_oe = 1'b0;
-   assign 	       sram_ce = 1'b0;
-   assign 	       sram_adv = 1'b0;
-   assign 	       sram_mode = 1'b0;
-   assign 	       sram_zz = 1'b0;
-   assign 	       sram_bw = 2'b0;
-   
-   // need to drive wb_dat_o, wb_ack_o,
-   // sram_a, sram_d, sram_we
-   wire 	       myOE;
-   assign 	       sram_d = myOE ? wb_dat_i : 16'bzzzz;
-   assign 	       sram_a = wb_adr_i[19:1];
-
-   reg 		       read_d1, read_d2, read_d3, write_d1, write_d2, write_d3;
-   wire 	       acc = wb_cyc_i & wb_stb_i;
-   wire 	       read_acc = wb_cyc_i & wb_stb_i & ~wb_we_i & ~read_d1 & ~read_d2 & ~read_d3;
-   wire 	       write_acc = wb_cyc_i & wb_stb_i & wb_we_i & ~write_d1 & ~write_d2 & ~write_d3;
-
-   assign 	       sram_we = ~write_acc;
-   assign 	       sram_oe = ~(read_d2 | read_d3);
-   assign 	       myOE = write_d1 | write_d2;
-   wire 	       latch_now = read_d2;
-
-   always @(posedge clk)
-     if(latch_now)
-       wb_dat_o <= sram_d;
-
-   always @(posedge clk) wb_ack_o <= read_d2 | write_d2;
-   always @(posedge clk) read_d1 <= read_acc;
-   always @(posedge clk) read_d2 <= read_d1;
-   always @(posedge clk) read_d3 <= read_d2;
-   always @(posedge clk) write_d1 <= write_acc;
-   always @(posedge clk) write_d2 <= write_d1;
-   always @(posedge clk) write_d3 <= write_d2;
-endmodule // wb_zbt16_b
-
diff --git a/fpga/usrp2/extramfifo/fifo_extram.v b/fpga/usrp2/extramfifo/fifo_extram.v
deleted file mode 100644
index 4e1f40371..000000000
--- a/fpga/usrp2/extramfifo/fifo_extram.v
+++ /dev/null
@@ -1,188 +0,0 @@
-
-// Everything on sram_clk
-
-module fifo_extram
-  (input reset, input clear,
-   input [17:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input [15:0] occ_in,
-   output [17:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input [15:0] space_in,
-   input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we,
-   output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, 
-   output sram_mode, output sram_zz);
-
-   localparam AWIDTH   = 19; // 1 MB in x18
-   localparam RAMSIZE  = ((1<<AWIDTH) - 1);
-
-   wire   do_store, do_retrieve;
-   reg [1:0]  do_store_del, do_retr_del;
-   
-   reg [AWIDTH-1:0] addr_retrieve, addr_store;
-   always @(posedge sram_clk)
-     if(reset | clear)
-       addr_retrieve <= 0;
-     else if (do_retrieve)
-       addr_retrieve <= addr_retrieve + 1;
-   
-   always @(posedge sram_clk)
-     if(reset | clear)
-       addr_store    <= 0;
-     else if(do_store)
-       addr_store    <= addr_store + 1;
-
-   //wire [AWIDTH-1:0] fullness = (addr_store - addr_retrieve);
-   reg [AWIDTH-1:0] fullness;
-   always @(posedge sram_clk)
-     if(reset | clear)
-       fullness      <= 0;
-     else if(do_store)
-       fullness      <= fullness + 1;
-     else if(do_retrieve)
-       fullness      <= fullness - 1;
-   
-   //   wire        empty  = (fullness == 0);
-   //wire        full   = (fullness == RAMSIZE); // 19'h7FF);
-   reg 		    empty, full;
-   
-   //  The math in the following functions is 'AWIDTH wide.  Use
-   //  continuous assignments to prevent the numbers from being
-   //  promoted to 32-bit (which would make it wrap wrong).
-   //
-   wire [AWIDTH-1:0] addr_retrieve_p1, addr_store_p2;
-   assign addr_retrieve_p1 = addr_retrieve + 1;
-   assign addr_store_p2 = addr_store + 2;
-
-   always @(posedge sram_clk)
-     if(reset | clear)
-       empty 	     <= 1;
-     else if(do_store)
-       empty 	     <= 0;
-     else if(do_retrieve & (/*(addr_retrieve + 1)*/ addr_retrieve_p1 == addr_store))
-       empty 	     <= 1;
-   
-   always @(posedge sram_clk)
-     if(reset | clear)
-       full 	     <= 0;
-     else if(do_retrieve)
-       full 	     <= 0;
-     else if(do_store & (/*(addr_store+2)*/ addr_store_p2 == addr_retrieve))
-       full <= 1;
-
-   reg 	       can_store;
-   always @*
-     if(full | ~src_rdy_i)
-       can_store 	  <= 0;
-     else if(do_store_del == 0)
-       can_store 	  <= 1;
-     else if((do_store_del == 1) || (do_store_del == 2))
-       can_store 	  <= (occ_in > 1);
-     else
-       can_store 	  <= (occ_in > 2);
-     
-   reg 	       can_retrieve;
-   always @*
-     if(empty | ~dst_rdy_i)
-       can_retrieve 	     <= 0;
-     else if(do_retr_del == 0)
-       can_retrieve 	     <= 1;
-     else if((do_retr_del == 1) || (do_retr_del == 2))
-       can_retrieve 	     <= (space_in > 1);
-     else
-       can_retrieve 	     <= (space_in > 2);
-   
-   reg [1:0]  state;
-   localparam IDLE_STORE_NEXT  = 0;
-   localparam STORE 	       = 1;
-   localparam IDLE_RETR_NEXT   = 2;
-   localparam RETRIEVE 	       = 3;
-   
-   reg [7:0]  countdown;
-   wire       countdown_done 		   = (countdown == 0);
-
-   localparam CYCLE_SIZE 		   = 6;
-   
-   assign        do_store 		   = can_store & (state == STORE);
-   assign        do_retrieve 		   = can_retrieve & (state == RETRIEVE);
-   always @(posedge sram_clk)
-     if(reset)
-       do_store_del 			  <= 0;
-     else
-       do_store_del 			  <= {do_store_del[0],do_store};
-   
-   always @(posedge sram_clk) 
-     if(reset)
-       do_retr_del <= 0;
-     else
-       do_retr_del <= {do_retr_del[0],do_retrieve};
-
-   always @(posedge sram_clk)
-     if(reset | clear)
-       begin
-	  state 			  <= IDLE_STORE_NEXT;
-	  countdown 			  <= 0;
-       end
-     else
-       case(state)
-	 IDLE_STORE_NEXT :
-	   if(can_store)
-	     begin
-		state 	  <= STORE;
-		countdown <= CYCLE_SIZE;
-	     end
-	   else if(can_retrieve)
-	     begin
-		state 	  <= RETRIEVE;
-		countdown <= CYCLE_SIZE;
-	     end
-	 STORE :
-	   if(~can_store | (can_retrieve & countdown_done))
-	     state <= IDLE_RETR_NEXT;
-	   else if(~countdown_done)
-	     countdown <= countdown - 1;
-	 IDLE_RETR_NEXT :
-	   if(can_retrieve)
-	     begin
-		state 	  <= RETRIEVE;
-		countdown <= CYCLE_SIZE;
-	     end
-	   else if(can_store)
-	     begin
-		state 	  <= STORE;
-		countdown <= CYCLE_SIZE;
-	     end
-	 RETRIEVE :
-	   if(~can_retrieve | (can_store & countdown_done))
-	     state <= IDLE_STORE_NEXT;
-	   else if(~countdown_done)
-	     countdown <= countdown - 1;
-       endcase // case (state)
-
-   // RAM wires
-   assign sram_bw      = 0;
-   assign sram_adv     = 0;
-   assign sram_mode    = 0;
-   assign sram_zz      = 0;
-   assign sram_ce      = 0;
-
-   assign sram_a       = (state==STORE) ? addr_store : addr_retrieve;
-   assign sram_we      = ~do_store;
-   assign sram_oe      = ~do_retr_del[1];
-   assign my_oe        = do_store_del[1] & sram_oe;
-   assign sram_d       = my_oe ? datain : 18'bz;
-   
-   // FIFO wires
-   assign dataout      = sram_d;
-   assign src_rdy_o    = do_retr_del[1];
-   assign dst_rdy_o    = do_store_del[1];
-   
-endmodule // fifo_extram
-
-
-   //wire        have_1 		   = (fullness == 1);
-   //wire        have_2 		   = (fullness == 2);
-   //wire        have_atleast_1 	   = ~empty;
-   //wire        have_atleast_2 	   = ~(empty | have_1);
-   //wire        have_atleast_3 	   = ~(empty | have_1 | have_2);   
-   //wire        full_minus_1 	   = (fullness == (RAMSIZE-1)); // 19'h7FE);
-   //wire        full_minus_2 	   = (fullness == (RAMSIZE-2)); // 19'h7FD);
-   //wire        spacefor_atleast_1  = ~full;
-   //wire        spacefor_atleast_2  = ~(full | full_minus_1);
-   //wire        spacefor_atleast_3  = ~(full | full_minus_1 | full_minus_2);
diff --git a/fpga/usrp2/extramfifo/fifo_extram36.v b/fpga/usrp2/extramfifo/fifo_extram36.v
deleted file mode 100644
index 29342fdc4..000000000
--- a/fpga/usrp2/extramfifo/fifo_extram36.v
+++ /dev/null
@@ -1,47 +0,0 @@
-
-// 18 bit interface means we either can't handle errors or can't handle odd lengths
-//   unless we go to heroic measures
-
-module fifo_extram36
-  (input clk, input reset, input clear,
-   input [35:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space,
-   output [35:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied,
-   input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we,
-   output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, output sram_mode,
-   output sram_zz);
-
-   wire [17:0] f18_data_1, f18_data_2, f18_data_3, f18_data_4;
-   wire        f18_src_rdy_1, f18_dst_rdy_1, f18_src_rdy_2, f18_dst_rdy_2;
-   wire        f18_src_rdy_3, f18_dst_rdy_3, f18_src_rdy_4, f18_dst_rdy_4;
-   
-   fifo36_to_fifo18 f36_to_f18
-     (.clk(clk), .reset(reset), .clear(clear),
-      .f36_datain(datain), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o),
-      .f18_dataout(f18_data_1), .f18_src_rdy_o(f18_src_rdy_1), .f18_dst_rdy_i(f18_dst_rdy_1) );
-
-   wire [15:0] f1_occ, f2_space;
-   
-   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_in
-     (.wclk(clk), .datain(f18_data_1), .src_rdy_i(f18_src_rdy_1), .dst_rdy_o(f18_dst_rdy_1), .space(),
-      .rclk(sram_clk), .dataout(f18_data_2), .src_rdy_o(f18_src_rdy_2), .dst_rdy_i(f18_dst_rdy_2), .short_occupied(f1_occ),
-      .arst(reset) );
-
-   fifo_extram fifo_extram
-     (.reset(reset), .clear(clear),
-      .datain(f18_data_2), .src_rdy_i(f18_src_rdy_2), .dst_rdy_o(f18_dst_rdy_2), .space(), .occ_in(f1_occ),
-      .dataout(f18_data_3), .src_rdy_o(f18_src_rdy_3), .dst_rdy_i(f18_dst_rdy_3), .occupied(), .space_in(f2_space),
-      .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we),
-      .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe),
-      .sram_mode(sram_mode), .sram_zz(sram_zz));
-   
-   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_out
-     (.wclk(sram_clk), .datain(f18_data_3), .src_rdy_i(f18_src_rdy_3), .dst_rdy_o(f18_dst_rdy_3), .short_space(f2_space),
-      .rclk(clk), .dataout(f18_data_4), .src_rdy_o(f18_src_rdy_4), .dst_rdy_i(f18_dst_rdy_4), .occupied(),
-      .arst(reset) );
-
-   fifo18_to_fifo36 f18_to_f36
-     (.clk(clk), .reset(reset), .clear(clear),
-      .f18_datain(f18_data_4), .f18_src_rdy_i(f18_src_rdy_4), .f18_dst_rdy_o(f18_dst_rdy_4),
-      .f36_dataout(dataout), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i) );
-   
-endmodule // fifo_extram36
diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.build b/fpga/usrp2/extramfifo/fifo_extram36_tb.build
deleted file mode 100755
index ac9369758..000000000
--- a/fpga/usrp2/extramfifo/fifo_extram36_tb.build
+++ /dev/null
@@ -1 +0,0 @@
-iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v
diff --git a/fpga/usrp2/extramfifo/fifo_extram36_tb.v b/fpga/usrp2/extramfifo/fifo_extram36_tb.v
deleted file mode 100644
index e5f8cef4c..000000000
--- a/fpga/usrp2/extramfifo/fifo_extram36_tb.v
+++ /dev/null
@@ -1,475 +0,0 @@
-`timescale 1ns/1ns
-
-module fifo_extram36_tb();
-   
-   reg clk 	 = 0;
-   reg sram_clk  = 0;
-   reg rst 	 = 1;
-   reg clear 	 = 0;
-
-   reg Verbose = 0;   // 
-   integer ErrorCount = 0;
-   
-   initial #1000 rst = 0;
-//   always #125 clk = ~clk;
-   task task_CLK;
-      reg [7:0] ran;
-      begin
-	 while (1) begin
-	    ran = $random;
-	    if (ran[1])
-	      #62 clk = ~clk;
-	    else
-	      #63 clk = !clk;
-	 end
-      end
-   endtask // task_CLK
-   initial task_CLK;
-   
-//   always #100 sram_clk = ~sram_clk;
-   task task_SSRAM_clk;
-      reg [7:0] ran;
-      begin
-	 while (1) begin
-	    ran = $random;
-	    if (ran[0])
-	      #49 sram_clk = ~sram_clk;
-	    else
-	      #51 sram_clk = ~sram_clk;
-	 end
-      end
-   endtask // task_SSRAM_clk
-   initial task_SSRAM_clk;
-
-   reg [31:0] f36_data = 32'hX;
-   reg [1:0]  f36_occ = 0;
-   reg 	      f36_sof = 0, f36_eof = 0;
-   
-   wire [35:0] f36_in = {1'b0,f36_occ,f36_eof,f36_sof,f36_data};
-   reg 	       src_rdy_f36i  = 0;
-   wire        dst_rdy_f36i;
-
-   wire [35:0] f36_out;
-   wire        src_rdy_f36o;
-   reg 	       dst_rdy_f36o  = 0;
-
-   wire [17:0] sram_d;
-   wire [18:0] sram_a;
-   wire [1:0]  sram_bw;
-   wire        sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz;
-
-   reg [31:0]  ScoreBoard [524288:0];
-   reg [18:0] put_index = 0;
-   reg [18:0] get_index = 0;
-   
-//   integer     put_index = 0;
-//   integer     get_index = 0;
-   
-   wire [15:0] DUT_space, DUT_occupied;
-
-   fifo_extram36 fifo_extram36
-     (.clk(clk), .reset(rst), .clear(clear),
-      .datain(f36_in), .src_rdy_i(src_rdy_f36i), .dst_rdy_o(dst_rdy_f36i), .space(DUT_space),
-      .dataout(f36_out), .src_rdy_o(src_rdy_f36o), .dst_rdy_i(dst_rdy_f36o), .occupied(DUT_occupied),
-      .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we),
-      .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe),
-      .sram_mode(sram_mode), .sram_zz(sram_zz));
-
-`define idt 1
-`ifdef idt
-   wire [15:0] dummy16;
-   wire [1:0]  dummy2;
-   
-   idt71v65603s150 
-     ram_model(.A(sram_a[17:0]),
-	       .adv_ld_(sram_adv),                  // advance (high) / load (low)
-               .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0),   // byte write enables (low)
-               .ce1_(0), .ce2(1), .ce2_(0),          // chip enables
-               .cen_(sram_ce),                     // clock enable (low)
-	       .clk(sram_clk),                      // clock
-	       .IO({dummy16,sram_d[15:0]}), 
-	       .IOP({dummy2,sram_d[17:16]}),                  // data bus
-               .lbo_(sram_mode),                     // linear burst order (low)
-               .oe_(sram_oe),                      // output enable (low)
-               .r_w_(sram_we));                    // read (high) / write (low)
-`else 
-   cy1356 ram_model(.d(sram_d),.clk(~sram_clk),.a(sram_a),
-		    .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv),
-		    .ce1b(0),.ce2(1),.ce3b(0),
-		    .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) );
-`endif
-
-   task task_SSRAMMonitor;
-      reg last_mode;
-      reg last_clock;
-      reg last_load;
-      reg [18:0] sram_addr;
-
-      begin
-	 last_mode = 1'bX;
-	 last_clock = 1'bX;
-	 last_load = 1'bX;
-
-	 @ (posedge Verbose);
-	 $dumpvars(0,fifo_extram36_tb);
-	 
-	 $display("%t:%m\t*** Task Started",$time);
-	 while (1) @ (posedge sram_clk) begin
-	    if (sram_mode !== last_mode) begin
-	       $display("%t:%m\tSSRAM mode:         %b",$time,sram_mode);
-	       last_mode = sram_mode;
-	    end
-	    if (sram_adv !== last_load) begin
-	       $display("%t:%m\tSSRAM adv/load:     %b",$time,sram_adv);
-	       last_load = sram_adv;
-	    end
-	    if (sram_ce !== last_clock) begin
-	       $display("%t:%m\tSSRAM clock enable: %b",$time,sram_ce);
-	       last_clock = sram_ce;
-	    end
-	    if (sram_ce == 1'b0) begin
-	       if (sram_adv == 1'b0) begin
-//		  $display("%t:%m\tSSRAM Address Load A=%h",$time,sram_a);
-		  sram_addr = sram_a;
-	       end else begin
-		  sram_addr = sram_addr + 1;
-	       end
-	       if (sram_oe == 1'b0) begin
-		  $display("%t:%m\tSSRAM Read  Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d);
-	       end
-	       if (sram_we == 1'b0) begin
-		  $display("%t:%m\tSSRAM Write Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d);
-	       end
-	       if ((sram_we == 1'b0) && (sram_oe == 1'b0)) begin
-		 $display("%t:%m\t*** ERROR: _oe and _we both active",$time);
-	       end
-	       
-	    end // if (sram_ce == 1'b0)
-	    
-	 end // always @ (posedge sram_clk)
-      end
-   endtask // task_SSRAMMonitor
-   
-   task ReadFromFIFO36;
-      begin
-	 $display("%t: Read from FIFO36",$time);
-	 #1 dst_rdy_f36o <= 1;
-	 while(1)
-	   begin
-	      while(~src_rdy_f36o)
-		@(posedge clk);
-	      $display("%t: Read: %h>",$time,f36_out);
-	      @(posedge clk);
-	   end
-      end
-   endtask // ReadFromFIFO36
-
-   initial dst_rdy_f36o = 0;
-
-   task task_ReadFIFO36;
-      reg [7:0] ran;
-      begin
-      $display("%t:%m\t*** Task Started",$time);
-      while (1) begin
-	 //  Read on one of four clocks
-	 #5 dst_rdy_f36o <= 1;
-	 @(posedge clk);
-	 if (src_rdy_f36o) begin
-	    if (f36_out[31:0] != ScoreBoard[get_index]) begin
-	       $display("%t:%m\tFIFO Get Error: R:%h, E:%h (%h)",$time,f36_out[31:0],ScoreBoard[get_index],get_index);
-	       ErrorCount = ErrorCount + 1;
-	    end else begin
-	       if (Verbose)
-		 $display("%t:%m\t(%5h) %o>",$time,get_index,f36_out);
-	    end
-	    get_index = get_index+1;
-	 end else begin
-	    if (ErrorCount >= 192)
-	      $finish;
-	 end // else: !if(src_rdy_f36o)
-	 
-	 #10;
-	 ran = $random;
-	 if (ran[2:0] != 3'b000) begin
-	    dst_rdy_f36o <= 0;
-	    if (ran[2] != 1'b0) begin
-	       @(posedge clk);
-	       @(posedge clk);
-	       @(posedge clk);
-	    end
-	    if (ran[1] != 1'b0) begin
-	       @(posedge clk);
-	       @(posedge clk);
-	    end
-	    if (ran[0] != 1'b0) begin
-	       @(posedge clk);
-	    end
-	 end
-      end // while (1)
-   end
-      
-   endtask // task_ReadFIFO36
-   
-
-   reg [15:0] count;
-   
-   task PutPacketInFIFO36;
-      input [31:0] data_start;
-      input [31:0] data_len;
-
-      begin
-	 count 	      = 4;
-	 src_rdy_f36i = 1;
-	 f36_data     = data_start;
-	 f36_sof      = 1;
-	 f36_eof      = 0;
-	 f36_occ      = 0;
-	
-	 $display("%t: Put Packet in FIFO36",$time);
-	 while(~dst_rdy_f36i)
-	   #1; //@(posedge clk);
-	 @(posedge clk);
-
-	 $display("%t: <%h PPI_FIFO36: Entered First Line",$time,f36_data);
-	 f36_sof <= 0;
-	 while(count+4 < data_len)
-	   begin
-	      f36_data = f36_data + 32'h01010101;
-	      count    = count + 4;
-	      while(~dst_rdy_f36i)
-		#1; //@(posedge clk);
-	      @(posedge clk);
-	      $display("%t: <%h PPI_FIFO36: Entered New Line",$time,f36_data);
-	   end
-	 f36_data  <= f36_data + 32'h01010101;
-	 f36_eof   <= 1;
-	 if(count + 4 == data_len)
-	   f36_occ <= 0;
-	 else if(count + 3 == data_len)
-	   f36_occ <= 3;
-	 else if(count + 2 == data_len)
-	   f36_occ <= 2;
-	 else
-	   f36_occ <= 1;
-	 while(~dst_rdy_f36i)
-	   @(posedge clk);
-	 @(posedge clk);
-	 f36_occ      <= 0;
-	 f36_eof      <= 0;
-	 f36_data     <= 0;
-	 src_rdy_f36i <= 0;
-	 $display("%t: <%h PPI_FIFO36: Entered Last Line",$time,f36_data);
-      end
-   endtask // PutPacketInFIFO36
-
-   task task_WriteFIFO36;
-      integer i;
-      reg [7:0] ran;
-      
-      begin
-	 f36_data = 32'bX;
-	 if (rst != 1'b0)
-	   @ (negedge rst);
-	 $display("%t:%m\t*** Task Started",$time);
-	 #10;
-	 src_rdy_f36i = 1;
-	 f36_data = $random;
-	 for (i=0; i<64; i=i+0 ) begin
-	    @ (posedge clk) ;
-	    if (dst_rdy_f36i) begin
-	       if (Verbose)
-		 $display("%t:%m\t(%5h) %o<",$time,put_index,f36_in);
-	       ScoreBoard[put_index] = f36_in[31:0];
-	       put_index = put_index + 1;
-	       #5;
-	       f36_data = $random;
-	       i = i + 1;
-	    end
-	    ran = $random;
-	    if (ran[1:0] != 2'b00) begin
-	       @ (negedge clk);
-	       src_rdy_f36i = 0;
-	       #5;
-	       @ (negedge clk) ;
-	       src_rdy_f36i = 1;
-	    end
-	 end
-	 src_rdy_f36i = 0;
-	 f36_data = 32'bX;
-//	 if (put_index > 19'h3ff00)
-//	   Verbose = 1'b1;
-	 
-      end
-   endtask // task_WriteFIFO36
-   
-   initial $dumpfile("fifo_extram36_tb.vcd");
-//   initial $dumpvars(0,fifo_extram36_tb);
-   initial $timeformat(-9, 0, " ns", 10);
-   initial task_SSRAMMonitor;
-   
-   initial
-     begin
-	@(negedge rst);
-	#40000;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-//	ReadFromFIFO36;
-	task_ReadFIFO36;
-	
-     end
-
-   integer i;
-   
-   initial
-     begin
-	@(negedge rst);
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-	task_WriteFIFO36;
-	@(posedge clk);
-	@(posedge clk);
-	@(posedge clk);
-//	PutPacketInFIFO36(32'hA0B0C0D0,12);
-	@(posedge clk);
-	@(posedge clk);
-	#10000;
-	@(posedge clk);
-//	PutPacketInFIFO36(32'hE0F0A0B0,36);
-	@(posedge clk);
-	@(posedge clk);
-	task_WriteFIFO36;
-	@(posedge clk);
-	@(posedge clk);
-	#10000;
-	@(posedge clk);
-	@(posedge clk);
-	task_WriteFIFO36;
-//	@(posedge clk);
-//	#30000;
-//	@(posedge clk);
-//	@(posedge clk);
-	task_WriteFIFO36;
-//	@(posedge clk);
-//	#30000;
-//	@(posedge clk);
-//	@(posedge clk);
-	task_WriteFIFO36;
-//	@(posedge clk);
-//	#30000;
-//	@(posedge clk);
-//	@(posedge clk);
-	task_WriteFIFO36;
-	@(posedge clk);
-	#10000;
-	@(posedge clk);
-	@(posedge clk);
-	task_WriteFIFO36;
-	for (i=0; i<8192; i = i+1) begin
-	   @(posedge clk);
-	   #10000;
-	   @(posedge clk);
-	   @(posedge clk);
-	   task_WriteFIFO36;
-	   @(posedge clk);
-	end
-
-//	$dumpvars(0,fifo_extram36_tb);
-	@(posedge clk);
-	task_WriteFIFO36;
-	@(posedge clk);
-
-	#100000000;
-	$finish;
-	
-     end
-
-
-   initial
-     begin
-	@(negedge rst);
-	f36_occ      <= 0;
-	repeat (100)
-	  @(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= 32'h10203040;
-	f36_sof      <= 1;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= f36_data + 32'h01010101;
-	f36_sof      <= 0;
-	f36_eof      <= 0;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 1;
-	f36_data     <= 32'h1F2F3F4F;
-	f36_sof      <= 0;
-	f36_eof      <= 1;
-	@(posedge clk);
-	@(posedge clk);
-	src_rdy_f36i <= 0;
-	
-	
-	
-     end
-   
-//   initial #500000 $finish;
-endmodule // fifo_extram_tb
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.build b/fpga/usrp2/extramfifo/fifo_extram_tb.build
deleted file mode 100755
index 5607c8691..000000000
--- a/fpga/usrp2/extramfifo/fifo_extram_tb.build
+++ /dev/null
@@ -1 +0,0 @@
-iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v
diff --git a/fpga/usrp2/extramfifo/fifo_extram_tb.v b/fpga/usrp2/extramfifo/fifo_extram_tb.v
deleted file mode 100644
index 73550d9ca..000000000
--- a/fpga/usrp2/extramfifo/fifo_extram_tb.v
+++ /dev/null
@@ -1,134 +0,0 @@
-module fifo_extram_tb();
-   
-   reg clk 	 = 0;
-   reg sram_clk  = 0;
-   reg reset 	 = 1;
-   reg clear 	 = 0;
-   
-   initial #1000 reset = 0;
-   always #125 clk = ~clk;
-   always #100 sram_clk = ~sram_clk;
-   
-   reg [15:0] f18_data = 0;
-   reg f18_sof = 0, f18_eof = 0;
-   
-   wire [17:0] f18_in = {f18_eof,f18_sof,f18_data};
-   reg src_rdy_f18i  = 0;
-   wire dst_rdy_f18i;
-
-   wire [17:0] f18_out;
-   wire src_rdy_f18o;
-   reg dst_rdy_f18o  = 0;
-
-   wire [17:0] f18_int;
-   wire        src_rdy_f18int, dst_rdy_f18int;
-       
-   wire [17:0] sram_d;
-   wire [18:0] sram_a;
-   wire [1:0]  sram_bw;
-   wire        sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz;
-   wire [15:0] f1_occ;
-   
-   fifo_short #(.WIDTH(18)) fifo_short
-     (.clk(sram_clk), .reset(reset), .clear(clear),
-      .datain(f18_in), .src_rdy_i(src_rdy_f18i), .dst_rdy_o(dst_rdy_f18i), .space(),
-      .dataout(f18_int), .src_rdy_o(src_rdy_f18int), .dst_rdy_i(dst_rdy_f18int), .occupied(f1_occ[4:0]) );
-   
-   assign f1_occ[15:5] = 0;
-   
-   fifo_extram fifo_extram
-     (.reset(reset), .clear(clear),
-      .datain(f18_int), .src_rdy_i(src_rdy_f18int), .dst_rdy_o(dst_rdy_f18int), .space(), .occ_in(f1_occ),
-      .dataout(f18_out), .src_rdy_o(src_rdy_f18o), .dst_rdy_i(dst_rdy_f18o), .occupied(), .space_in(7),
-      .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we),
-      .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe),
-      .sram_mode(sram_mode), .sram_zz(sram_zz));
-
-`define idt 1
-`ifdef idt
-   wire [15:0]  dummy16;
-   wire [1:0] 	dummy2;
-   
-   idt71v65603s150 
-     ram_model(.A(sram_a[17:0]),
-	       .adv_ld_(sram_adv),                  // advance (high) / load (low)
-               .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0),   // byte write enables (low)
-               .ce1_(0), .ce2(1), .ce2_(0),          // chip enables
-               .cen_(sram_ce),                     // clock enable (low)
-	       .clk(sram_clk),                      // clock
-	       .IO({dummy16,sram_d[15:0]}), 
-	       .IOP({dummy2,sram_d[17:16]}),                  // data bus
-               .lbo_(sram_mode),                     // linear burst order (low)
-               .oe_(sram_oe),                      // output enable (low)
-               .r_w_(sram_we));                    // read (high) / write (low)
-`else
-   cy1356 ram_model(.d(sram_d),.clk(sram_clk),.a(sram_a),
-		    .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv),
-		    .ce1b(0),.ce2(1),.ce3b(0),
-		    .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) );
-`endif // !`ifdef idt
-   
-   always @(posedge sram_clk)
-     if(dst_rdy_f18o & src_rdy_f18o)
-       $display("Read: %h",f18_out);
-
-   always @(posedge sram_clk)
-     if(dst_rdy_f18int & src_rdy_f18int)
-       $display("Write: %h",f18_int);
-
-   initial $dumpfile("fifo_extram_tb.vcd");
-   initial $dumpvars(0,fifo_extram_tb);
-
-   task SendPkt;
-      input [15:0] data_start;
-      input [31:0] data_len;
-      begin
-	 @(posedge sram_clk);
-	 f18_data      = data_start;
-	 f18_sof       = 1;
-	 f18_eof       = 0;
-	 src_rdy_f18i  = 1;
-	 while(~dst_rdy_f18i)
-	   #1;
-	 @(posedge sram_clk);
-	 repeat(data_len - 2)
-	   begin
-	      f18_data 	= f18_data + 16'h0101;
-	      f18_sof 	= 0;
-	      while(~dst_rdy_f18i)
-		@(posedge sram_clk);
-
-	      @(posedge sram_clk);
-	   end
-	 f18_data 	= f18_data + 16'h0101;
-	 f18_eof 	= 1;
-	 while(~dst_rdy_f18i)
-	   #1;
-	 @(posedge sram_clk);
-	 src_rdy_f18i = 0;
-	 f18_data  = 0;
-	 f18_eof   = 0;
-      end
-   endtask // SendPkt
-   
-   initial
-     begin
-	@(negedge reset);
-	@(posedge sram_clk);
-	@(posedge sram_clk);
-	#10000;
-	@(posedge sram_clk);
-	SendPkt(16'hA0B0, 100);
-	#10000;
-	//SendPkt(16'hC0D0, 220);
-     end
-
-   initial
-     begin
-	#20000;
-	dst_rdy_f18o  = 1;
-     end
-   
-   initial #200000 $finish;
-endmodule // fifo_extram_tb
-
diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
index f0b5b7bae..31b1f505a 100644
--- a/fpga/usrp2/fifo/Makefile.srcs
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -28,4 +28,10 @@ fifo36_demux.v \
 packet_router.v \
 splitter36.v \
 valve36.v \
+fifo_pacer.v \
+packet_dispatcher36_x3.v \
+packet_generator32.v \
+packet_generator.v \
+packet_verifier32.v \
+packet_verifier.v \
 ))
diff --git a/fpga/usrp2/fifo/buffer_int2.v b/fpga/usrp2/fifo/buffer_int2.v
index 765b125fb..532980aa2 100644
--- a/fpga/usrp2/fifo/buffer_int2.v
+++ b/fpga/usrp2/fifo/buffer_int2.v
@@ -31,13 +31,15 @@ module buffer_int2
      input rd_ready_i
      );
 
-   reg [BUF_SIZE-1:0] rd_addr, wr_addr;
+   reg [15:0]         rd_addr, wr_addr;    // Handle pkt bigger than buffer
+   wire [15:0] 	      rd_addr_next = rd_addr + 1;
+   reg [15:0] 	      rd_length;
+
    wire [31:0] 	      ctrl;
    wire 	      wr_done, wr_error, wr_idle;
    wire 	      rd_done, rd_error, rd_idle;
    wire 	      we, en, go;
 
-   reg [BUF_SIZE-1:0] lastline;
    wire 	      read = ctrl[3];
    wire 	      rd_clear = ctrl[2];
    wire 	      write = ctrl[1];
@@ -72,13 +74,13 @@ module buffer_int2
 	     begin
 		rd_addr <= 0;
 		rd_state <= PRE_READ;
-		lastline <= ctrl[15+BUF_SIZE:16];
+		rd_length <= ctrl[31:16];
 	     end
 	 
 	 PRE_READ :
 	   begin
 	      rd_state <= READING;
-	      rd_addr <= rd_addr + 1;
+	      rd_addr <= rd_addr_next;
 	      rd_occ <= 2'b00;
 	      rd_sop <= 1;
 	      rd_eop <= 0;
@@ -88,8 +90,8 @@ module buffer_int2
 	   if(rd_ready_i)
 	     begin
 		rd_sop <= 0;
-		rd_addr <= rd_addr + 1;
-		if(rd_addr == lastline)
+		rd_addr <= rd_addr_next;
+		if(rd_addr_next == rd_length)
 		  begin
 		     rd_eop <= 1;
 		     // FIXME assign occ here
@@ -145,17 +147,19 @@ module buffer_int2
    assign     rd_idle = (rd_state == IDLE);
    assign     wr_idle = (wr_state == IDLE);
 
+   wire [BUF_SIZE-1:0] wr_addr_clip = (|wr_addr[15:BUF_SIZE]) ? {BUF_SIZE{1'b1}} : wr_addr[BUF_SIZE-1:0];
+   
    ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_in // CPU reads here
      (.clka(wb_clk_i),.ena(wb_stb_i),.wea(1'b0),
       .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(0),.doa(wb_dat_o),
       .clkb(clk),.enb(1'b1),.web(we),
-      .addrb(wr_addr),.dib(wr_data_i[31:0]),.dob());
+      .addrb(wr_addr_clip),.dib(wr_data_i[31:0]),.dob());
    
    ram_2port #(.DWIDTH(32),.AWIDTH(BUF_SIZE)) buffer_out // CPU writes here
      (.clka(wb_clk_i),.ena(wb_stb_i),.wea(wb_we_i),
       .addra(wb_adr_i[BUF_SIZE+1:2]),.dia(wb_dat_i),.doa(),
       .clkb(clk),.enb(en),.web(1'b0),
-      .addrb(rd_addr),.dib(0),.dob(rd_data_o[31:0]));
+      .addrb(rd_addr[BUF_SIZE-1:0]),.dib(0),.dob(rd_data_o[31:0]));
    
    always @(posedge wb_clk_i)
      if(wb_rst_i)
@@ -167,7 +171,7 @@ module buffer_int2
    sreg(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),.in(set_data),
 	.out(ctrl),.changed(go));
    
-   assign status = { {(16-BUF_SIZE){1'b0}},wr_addr,
+   assign status = { wr_addr,
 		     8'b0,1'b0,rd_idle,rd_error,rd_done, 1'b0,wr_idle,wr_error,wr_done};
 
 endmodule // buffer_int2
diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v
index f7d7fb68e..c2ae8f96c 100644
--- a/fpga/usrp2/fifo/dsp_framer36.v
+++ b/fpga/usrp2/fifo/dsp_framer36.v
@@ -2,98 +2,67 @@
 // Frame DSP packets with a header line to be handled by the protocol machine
 
 module dsp_framer36
-    #(parameter BUF_SIZE = 9, parameter PORT_SEL = 0)
-    (
-        input clk, input rst, input clr,
-        input [35:0] inp_data, input inp_valid, output inp_ready,
-        output [35:0] out_data, output out_valid, input out_ready
-    );
+  #(parameter BUF_SIZE = 9, 
+    parameter PORT_SEL = 0)
+   (input clk, input reset, input clear,
+    input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
+    output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
 
-    localparam DSP_FRM_STATE_WAIT_SOF = 0;
-    localparam DSP_FRM_STATE_WAIT_EOF = 1;
-    localparam DSP_FRM_STATE_WRITE_HDR = 2;
-    localparam DSP_FRM_STATE_WRITE = 3;
+   wire 	  dfifo_in_dst_rdy, dfifo_in_src_rdy, dfifo_out_dst_rdy, dfifo_out_src_rdy;
+   wire 	  tfifo_in_dst_rdy, tfifo_in_src_rdy, tfifo_out_dst_rdy, tfifo_out_src_rdy;
 
-    reg [1:0] dsp_frm_state;
-    reg [BUF_SIZE-1:0] dsp_frm_addr;
-    reg [BUF_SIZE-1:0] dsp_frm_count;
-    wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1;
+   wire 	  do_xfer_in = dfifo_in_src_rdy & dfifo_in_dst_rdy;
+   wire 	  do_xfer_out = src_rdy_o & dst_rdy_i;
+   
+   wire 	  have_space = dfifo_in_dst_rdy & tfifo_in_dst_rdy;
+   reg [15:0] 	  pkt_len_in, pkt_len_out;
+   wire [15:0] 	  tfifo_data;
+   wire [35:0] 	  dfifo_out_data;
+   
+   assign dst_rdy_o        = have_space;
+   assign dfifo_in_src_rdy = src_rdy_i & have_space;
+   
+   fifo_cascade #(.WIDTH(36), .SIZE(BUF_SIZE)) dfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data_i), .src_rdy_i(dfifo_in_src_rdy), .dst_rdy_o(dfifo_in_dst_rdy),
+      .dataout(dfifo_out_data), .src_rdy_o(dfifo_out_src_rdy),  .dst_rdy_i(dfifo_out_dst_rdy) );
 
-    //DSP input stream ready in the following states
-    assign inp_ready = (
-        dsp_frm_state == DSP_FRM_STATE_WAIT_SOF ||
-        dsp_frm_state == DSP_FRM_STATE_WAIT_EOF
-    )? 1'b1 : 1'b0;
+   fifo_short #(.WIDTH(16)) tfifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(pkt_len_in),  .src_rdy_i(tfifo_in_src_rdy), .dst_rdy_o(tfifo_in_dst_rdy),
+      .dataout(tfifo_data), .src_rdy_o(tfifo_out_src_rdy), .dst_rdy_i(tfifo_out_dst_rdy),
+      .space(), .occupied() );
 
-    //DSP framer output data mux (header or BRAM):
-    //The header is generated here from the count.
-    wire [31:0] dsp_frm_data_bram;
-    wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00};
-    wire [1:0] port_sel_bits = PORT_SEL;
-    assign out_data =
-        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 13'b0, port_sel_bits, 1'b1, dsp_frm_bytes} : (
-        (dsp_frm_addr == dsp_frm_count)           ? {4'b0010, dsp_frm_data_bram}    : (
-    {4'b0000, dsp_frm_data_bram}));
-    assign out_valid = (
-        (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR) ||
-        (dsp_frm_state == DSP_FRM_STATE_WRITE)
-    )? 1'b1 : 1'b0;
+   // FIXME won't handle single-line packets, will show wrong length
+   always @(posedge clk)
+     if(reset | clear)
+       pkt_len_in <= 0;
+     else if(do_xfer_in)
+       if(data_i[32])   // sof
+	 pkt_len_in <= 2;  // fixes off by one since number is stored before increment
+       else
+	 pkt_len_in <= pkt_len_in + 1;
 
-    RAMB16_S36_S36 dsp_frm_buff(
-        //port A = DSP input interface (writes to BRAM)
-        .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0),
-        .ENA(inp_ready & inp_valid),.SSRA(0),.WEA(inp_ready & inp_valid),
-        //port B = DSP framer interface (reads from BRAM)
-        .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0),
-        .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0)
-    );
+   assign tfifo_in_src_rdy = do_xfer_in & data_i[33]; // store length when at eof in
+   assign tfifo_out_dst_rdy = do_xfer_out & data_o[33]; // remove length from list at eof out
 
-    always @(posedge clk)
-    if(rst | clr) begin
-        dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
-        dsp_frm_addr <= 0;
-    end
-    else begin
-        case(dsp_frm_state)
-        DSP_FRM_STATE_WAIT_SOF: begin
-            if (inp_ready & inp_valid & inp_data[32]) begin
-                dsp_frm_addr <= dsp_frm_addr_next;
-                dsp_frm_state <= DSP_FRM_STATE_WAIT_EOF;
-            end
-        end
+   always @(posedge clk)
+     if(reset | clear)
+       pkt_len_out <= 0;
+     else if(do_xfer_out)
+       if(dfifo_out_data[33]) // eof
+	 pkt_len_out <= 0;
+       else
+	 pkt_len_out <= pkt_len_out + 1;
+   
+   assign dfifo_out_dst_rdy = do_xfer_out & (pkt_len_out != 0);
 
-        DSP_FRM_STATE_WAIT_EOF: begin
-            if (inp_ready & inp_valid) begin
-                if (inp_data[33]) begin
-                    dsp_frm_count <= dsp_frm_addr_next;
-                    dsp_frm_addr <= 0;
-                    dsp_frm_state <= DSP_FRM_STATE_WRITE_HDR;
-                end
-                else begin
-                    dsp_frm_addr <= dsp_frm_addr_next;
-                end
-            end
-        end
+   wire [1:0] 	  port_sel_bits = PORT_SEL;
+   
+   assign data_o = (pkt_len_out == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} :
+		   (pkt_len_out == 1) ? {4'b0000, dfifo_out_data[31:16],tfifo_data} : 
+		   {dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] };
 
-        DSP_FRM_STATE_WRITE_HDR: begin
-            if (out_ready & out_valid) begin
-                dsp_frm_addr <= dsp_frm_addr_next;
-                dsp_frm_state <= DSP_FRM_STATE_WRITE;
-            end
-        end
-
-        DSP_FRM_STATE_WRITE: begin
-            if (out_ready & out_valid) begin
-                if (out_data[33]) begin
-                    dsp_frm_addr <= 0;
-                    dsp_frm_state <= DSP_FRM_STATE_WAIT_SOF;
-                end
-                else begin
-                    dsp_frm_addr <= dsp_frm_addr_next;
-                end
-            end
-        end
-        endcase //dsp_frm_state
-    end
-
-endmodule //dsp_framer36
+   assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy;
+   
+endmodule // dsp_framer36
diff --git a/fpga/usrp2/fifo/fifo18_to_fifo36.v b/fpga/usrp2/fifo/fifo18_to_fifo36.v
deleted file mode 100644
index 25bb215a1..000000000
--- a/fpga/usrp2/fifo/fifo18_to_fifo36.v
+++ /dev/null
@@ -1,20 +0,0 @@
-
-// For now just assume FIFO18 is same as FIFO19 without occupancy bit
-
-module fifo18_to_fifo36
-  (input clk, input reset, input clear,
-   input [17:0] f18_datain,
-   input f18_src_rdy_i,
-   output f18_dst_rdy_o,
-
-   output [35:0] f36_dataout,
-   output f36_src_rdy_o,
-   input f36_dst_rdy_i
-   );
-
-   fifo19_to_fifo36 fifo19_to_fifo36
-     (.clk(clk), .reset(reset), .clear(clear),
-      .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o),
-      .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) );
-
-endmodule // fifo18_to_fifo36
diff --git a/fpga/usrp2/fifo/fifo19_to_fifo36.v b/fpga/usrp2/fifo/fifo19_to_fifo36.v
index ae2edddc7..502821435 100644
--- a/fpga/usrp2/fifo/fifo19_to_fifo36.v
+++ b/fpga/usrp2/fifo/fifo19_to_fifo36.v
@@ -15,60 +15,73 @@ module fifo19_to_fifo36
     input f36_dst_rdy_i,
     output [31:0] debug
     );
-
-   reg 		  f36_sof, f36_eof;
-   reg [1:0] 	  f36_occ;
    
+   // Shortfifo on input to guarantee no deadlock
+   wire [18:0] 	  f19_data_int;
+   wire 	  f19_src_rdy_int, f19_dst_rdy_int;
+   
+   fifo_short #(.WIDTH(19)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f19_datain), .src_rdy_i(f19_src_rdy_i), .dst_rdy_o(f19_dst_rdy_o),
+      .dataout(f19_data_int), .src_rdy_o(f19_src_rdy_int), .dst_rdy_i(f19_dst_rdy_int),
+      .space(),.occupied() );
+
+   // Actual f19 to f36 which could deadlock if not connected to shortfifos
+   reg 		  f36_sof_int, f36_eof_int;
+   reg [1:0] 	  f36_occ_int;
+   wire [35:0] 	  f36_data_int;
+   wire 	  f36_src_rdy_int, f36_dst_rdy_int;
+      
    reg [1:0] 	  state;
    reg [15:0] 	  dat0, dat1;
 
-   wire 	  f19_sof  = f19_datain[16];
-   wire 	  f19_eof  = f19_datain[17];
-   wire 	  f19_occ  = f19_datain[18];
+   wire 	  f19_sof_int  = f19_data_int[16];
+   wire 	  f19_eof_int  = f19_data_int[17];
+   wire 	  f19_occ_int  = f19_data_int[18];
 
-   wire 	  xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+   wire 	  xfer_out = f36_src_rdy_int & f36_dst_rdy_int;
 
    always @(posedge clk)
-     if(f19_src_rdy_i & ((state==0)|xfer_out))
-       f36_sof 	<= f19_sof;
+     if(f19_src_rdy_int & ((state==0)|xfer_out))
+       f36_sof_int 	<= f19_sof_int;
 
    always @(posedge clk)
-     if(f19_src_rdy_i & ((state != 2)|xfer_out))
-       f36_eof 	<= f19_eof;
+     if(f19_src_rdy_int & ((state != 2)|xfer_out))
+       f36_eof_int 	<= f19_eof_int;
 
    always @(posedge clk)
      if(reset)
        begin
 	  state 	<= 0;
-	  f36_occ <= 0;
+	  f36_occ_int <= 0;
        end
      else
-       if(f19_src_rdy_i)
+       if(f19_src_rdy_int)
 	 case(state)
 	   0 : 
 	     begin
-		dat0 <= f19_datain;
-		if(f19_eof)
+		dat0 <= f19_data_int;
+		if(f19_eof_int)
 		  begin
 		     state <= 2;
-		     f36_occ <= f19_occ ? 2'b01 : 2'b10;
+		     f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
 		  end
 		else
 		  state <= 1;
 	     end
 	   1 : 
 	     begin
-		dat1 <= f19_datain;
+		dat1 <= f19_data_int;
 		state <= 2;
-		if(f19_eof)
-		  f36_occ <= f19_occ ? 2'b11 : 2'b00;
+		if(f19_eof_int)
+		  f36_occ_int <= f19_occ_int ? 2'b11 : 2'b00;
 	     end
 	   2 : 
 	     if(xfer_out)
 	       begin
-		  dat0 <= f19_datain;
-		  if(f19_eof) // remain in state 2 if we are at eof
-		    f36_occ <= f19_occ ? 2'b01 : 2'b10;
+		  dat0 <= f19_data_int;
+		  if(f19_eof_int) // remain in state 2 if we are at eof
+		    f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10;
 		  else
 		    state 	   <= 1;
 	       end
@@ -77,14 +90,21 @@ module fifo19_to_fifo36
 	 if(xfer_out)
 	   begin
 	      state 	   <= 0;
-	      f36_occ <= 0;
+	      f36_occ_int <= 0;
 	   end
    
-   assign    f19_dst_rdy_o  = xfer_out | (state != 2);
-   assign    f36_dataout    = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} :
-			      {f36_occ,f36_eof,f36_sof,dat0,dat1};
-   assign    f36_src_rdy_o  = (state == 2);
+   assign    f19_dst_rdy_int  = xfer_out | (state != 2);
+   assign    f36_data_int     = LE ? {f36_occ_int,f36_eof_int,f36_sof_int,dat1,dat0} :
+				{f36_occ_int,f36_eof_int,f36_sof_int,dat0,dat1};
+   assign    f36_src_rdy_int  = (state == 2);
 
    assign    debug = state;
+
+   // Shortfifo on output to guarantee no deadlock
+   fifo_short #(.WIDTH(36)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
+      .dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
+      .space(),.occupied() );
    
 endmodule // fifo19_to_fifo36
diff --git a/fpga/usrp2/fifo/fifo36_mux.v b/fpga/usrp2/fifo/fifo36_mux.v
index c6fd40f27..7f0f803ff 100644
--- a/fpga/usrp2/fifo/fifo36_mux.v
+++ b/fpga/usrp2/fifo/fifo36_mux.v
@@ -10,6 +10,19 @@ module fifo36_mux
     input [35:0] data1_i, input src1_rdy_i, output dst1_rdy_o,
     output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
 
+   wire [35:0] 	  data0_int, data1_int;
+   wire 	  src0_rdy_int, dst0_rdy_int, src1_rdy_int, dst1_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) mux_fifo_in0
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data0_i), .src_rdy_i(src0_rdy_i), .dst_rdy_o(dst0_rdy_o),
+      .dataout(data0_int), .src_rdy_o(src0_rdy_int), .dst_rdy_i(dst0_rdy_int));
+
+   fifo_short #(.WIDTH(36)) mux_fifo_in1
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(data1_i), .src_rdy_i(src1_rdy_i), .dst_rdy_o(dst1_rdy_o),
+      .dataout(data1_int), .src_rdy_o(src1_rdy_int), .dst_rdy_i(dst1_rdy_int));
+
    localparam MUX_IDLE0 = 0;
    localparam MUX_DATA0 = 1;
    localparam MUX_IDLE1 = 2;
@@ -17,8 +30,8 @@ module fifo36_mux
    
    reg [1:0] 	  state;
 
-   wire 	  eof0 = data0_i[33];
-   wire 	  eof1 = data1_i[33];
+   wire 	  eof0 = data0_int[33];
+   wire 	  eof1 = data1_int[33];
    
    wire [35:0] 	  data_int;
    wire 	  src_rdy_int, dst_rdy_int;
@@ -29,33 +42,33 @@ module fifo36_mux
      else
        case(state)
 	 MUX_IDLE0 :
-	   if(src0_rdy_i)
+	   if(src0_rdy_int)
 	     state <= MUX_DATA0;
-	   else if(src1_rdy_i)
+	   else if(src1_rdy_int)
 	     state <= MUX_DATA1;
 
 	 MUX_DATA0 :
-	   if(src0_rdy_i & dst_rdy_int & eof0)
+	   if(src0_rdy_int & dst_rdy_int & eof0)
 	     state <= prio ? MUX_IDLE0 : MUX_IDLE1;
 
 	 MUX_IDLE1 :
-	   if(src1_rdy_i)
+	   if(src1_rdy_int)
 	     state <= MUX_DATA1;
-	   else if(src0_rdy_i)
+	   else if(src0_rdy_int)
 	     state <= MUX_DATA0;
 	   
 	 MUX_DATA1 :
-	   if(src1_rdy_i & dst_rdy_int & eof1)
+	   if(src1_rdy_int & dst_rdy_int & eof1)
 	     state <= MUX_IDLE0;
 	 
 	 default :
 	   state <= MUX_IDLE0;
        endcase // case (state)
 
-   assign dst0_rdy_o = (state==MUX_DATA0) ? dst_rdy_int : 0;
-   assign dst1_rdy_o = (state==MUX_DATA1) ? dst_rdy_int : 0;
-   assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_i : (state==MUX_DATA1) ? src1_rdy_i : 0;
-   assign data_int = (state==MUX_DATA0) ? data0_i : data1_i;
+   assign dst0_rdy_int = (state==MUX_DATA0) ? dst_rdy_int : 0;
+   assign dst1_rdy_int = (state==MUX_DATA1) ? dst_rdy_int : 0;
+   assign src_rdy_int = (state==MUX_DATA0) ? src0_rdy_int : (state==MUX_DATA1) ? src1_rdy_int : 0;
+   assign data_int = (state==MUX_DATA0) ? data0_int : data1_int;
    
    fifo_short #(.WIDTH(36)) mux_fifo
      (.clk(clk), .reset(reset), .clear(clear),
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo19.v b/fpga/usrp2/fifo/fifo36_to_fifo19.v
index e016fe2c6..0e9b2d442 100644
--- a/fpga/usrp2/fifo/fifo36_to_fifo19.v
+++ b/fpga/usrp2/fifo/fifo36_to_fifo19.v
@@ -13,25 +13,37 @@ module fifo36_to_fifo19
     output [18:0] f19_dataout,
     output f19_src_rdy_o,
     input f19_dst_rdy_i );
-   
-   wire   f36_sof  = f36_datain[32];
-   wire   f36_eof  = f36_datain[33];
-   wire [1:0] f36_occ  = f36_datain[35:34];
+      
+   wire [18:0] f19_data_int;
+   wire        f19_src_rdy_int, f19_dst_rdy_int;
+   wire [35:0] f36_data_int;
+   wire        f36_src_rdy_int, f36_dst_rdy_int;
+   
+   // Shortfifo on input to guarantee no deadlock
+   fifo_short #(.WIDTH(36)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
+      .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
+      .space(),.occupied() );
+
+   // Main fifo36_to_fifo19, needs shortfifos to guarantee no deadlock
+   wire [1:0]  f36_occ_int  = f36_data_int[35:34];
+   wire        f36_sof_int  = f36_data_int[32];
+   wire        f36_eof_int  = f36_data_int[33];
    
    reg 	  phase;
+   wire   half_line 	   = f36_eof_int & ((f36_occ_int==1)|(f36_occ_int==2));
    
-   wire   half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
-   
-   assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16];
-   assign f19_dataout[16]  = phase ? 0 : f36_sof;
-   assign f19_dataout[17]  = phase ? f36_eof : half_line;
-   assign f19_dataout[18]  = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
+   assign f19_data_int[15:0] = (LE ^ phase) ? f36_data_int[15:0] : f36_data_int[31:16];
+   assign f19_data_int[16]   = phase ? 0 : f36_sof_int;
+   assign f19_data_int[17]   = phase ? f36_eof_int : half_line;
+   assign f19_data_int[18]   = f19_data_int[17] & ((f36_occ_int==1)|(f36_occ_int==3));
    
-   assign f19_src_rdy_o    = f36_src_rdy_i;
-   assign f36_dst_rdy_o    = (phase | half_line) & f19_dst_rdy_i;
+   assign f19_src_rdy_int    = f36_src_rdy_int;
+   assign f36_dst_rdy_int    = (phase | half_line) & f19_dst_rdy_int;
    
-   wire   f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   wire   f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+   wire   f19_xfer 	   = f19_src_rdy_int & f19_dst_rdy_int;
+   wire   f36_xfer 	   = f36_src_rdy_int & f36_dst_rdy_int;
    
    always @(posedge clk)
      if(reset)
@@ -41,5 +53,11 @@ module fifo36_to_fifo19
      else if(f19_xfer)
        phase 		  <= 1;
    
-   
+   // Shortfifo on output to guarantee no deadlock
+   fifo_short #(.WIDTH(19)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int),
+      .dataout(f19_dataout), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i),
+      .space(),.occupied() );
+
 endmodule // fifo36_to_fifo19
diff --git a/fpga/usrp2/fifo/fifo36_to_fifo72.v b/fpga/usrp2/fifo/fifo36_to_fifo72.v
new file mode 100644
index 000000000..038eda9e9
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo36_to_fifo72.v
@@ -0,0 +1,125 @@
+
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+
+module fifo36_to_fifo72
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [35:0] f36_datain,
+    input f36_src_rdy_i,
+    output f36_dst_rdy_o,
+
+    output [71:0] f72_dataout,
+    output f72_src_rdy_o,
+    input f72_dst_rdy_i,
+    output [31:0] debug
+    );
+   
+   // Shortfifo on input to guarantee no deadlock
+   wire [35:0] 	  f36_data_int;
+   wire 	  f36_src_rdy_int, f36_dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
+      .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
+      .space(),.occupied() );
+
+   // Actual f36 to f72 which could deadlock if not connected to shortfifos
+   reg 		  f72_sof_int, f72_eof_int;
+   reg [2:0] 	  f72_occ_int;
+   wire [71:0] 	  f72_data_int;
+   wire 	  f72_src_rdy_int, f72_dst_rdy_int;
+      
+   reg [1:0] 	  state;
+   reg [31:0] 	  dat0, dat1;
+
+   wire 	  f36_sof_int  = f36_data_int[32];
+   wire 	  f36_eof_int  = f36_data_int[33];
+   wire [1:0]	  f36_occ_int  = f36_data_int[35:34];
+
+   wire 	  xfer_out = f72_src_rdy_int & f72_dst_rdy_int;
+
+   always @(posedge clk)
+     if(f36_src_rdy_int & ((state==0)|xfer_out))
+       f72_sof_int 	<= f36_sof_int;
+
+   always @(posedge clk)
+     if(f36_src_rdy_int & ((state != 2)|xfer_out))
+       f72_eof_int 	<= f36_eof_int;
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  state 	<= 0;
+	  f72_occ_int   <= 0;
+       end
+     else
+       if(f36_src_rdy_int)
+	 case(state)
+	   0 : 
+	     begin
+		dat0 <= f36_data_int;
+		if(f36_eof_int)
+		  begin
+		     state <= 2;
+		     case (f36_occ_int)
+		       0 : f72_occ_int <= 3'd4;
+		       1 : f72_occ_int <= 3'd1;
+		       2 : f72_occ_int <= 3'd2;
+		       3 : f72_occ_int <= 3'd3;
+		     endcase // case (f36_occ_int)
+		  end
+		else
+		  state <= 1;
+	     end
+	   1 : 
+	     begin
+		dat1 <= f36_data_int;
+		state <= 2;
+		if(f36_eof_int)
+		  case (f36_occ_int)
+		    0 : f72_occ_int <= 3'd0;
+		    1 : f72_occ_int <= 3'd5;
+		    2 : f72_occ_int <= 3'd6;
+		    3 : f72_occ_int <= 3'd7;
+		  endcase // case (f36_occ_int)
+	     end
+	   2 : 
+	     if(xfer_out)
+	       begin
+		  dat0 <= f36_data_int;
+		  if(f36_eof_int) // remain in state 2 if we are at eof
+		    case (f36_occ_int)
+		      0 : f72_occ_int <= 3'd4;
+		      1 : f72_occ_int <= 3'd1;
+		      2 : f72_occ_int <= 3'd2;
+		      3 : f72_occ_int <= 3'd3;
+		    endcase // case (f36_occ_int)
+		  else
+		    state 	   <= 1;
+	       end
+	 endcase // case(state)
+       else
+	 if(xfer_out)
+	   begin
+	      state 	   <= 0;
+	      f72_occ_int  <= 0;
+	   end
+   
+   assign    f36_dst_rdy_int  = xfer_out | (state != 2);
+   assign    f72_data_int     = LE ? {3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat1,dat0} :
+				{3'b000,f72_occ_int[2:0],f72_eof_int,f72_sof_int,dat0,dat1};
+   assign    f72_src_rdy_int  = (state == 2);
+
+   assign    debug = state;
+
+   // Shortfifo on output to guarantee no deadlock
+   fifo_short #(.WIDTH(72)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f72_data_int), .src_rdy_i(f72_src_rdy_int), .dst_rdy_o(f72_dst_rdy_int),
+      .dataout(f72_dataout), .src_rdy_o(f72_src_rdy_o), .dst_rdy_i(f72_dst_rdy_i),
+      .space(),.occupied() );
+   
+endmodule // fifo36_to_fifo72
diff --git a/fpga/usrp2/fifo/fifo36_to_ll8.v b/fpga/usrp2/fifo/fifo36_to_ll8.v
index 9604d0e38..390e49962 100644
--- a/fpga/usrp2/fifo/fifo36_to_ll8.v
+++ b/fpga/usrp2/fifo/fifo36_to_ll8.v
@@ -5,25 +5,33 @@ module fifo36_to_ll8
    input f36_src_rdy_i,
    output f36_dst_rdy_o,
 
-   output reg [7:0] ll_data,
-   output ll_sof_n,
-   output ll_eof_n,
-   output ll_src_rdy_n,
-   input ll_dst_rdy_n,
+   output [7:0] ll_data,
+   output ll_sof,
+   output ll_eof,
+   output ll_src_rdy,
+   input ll_dst_rdy,
 
    output [31:0] debug);
 
-   wire  ll_sof, ll_eof, ll_src_rdy;
-   assign ll_sof_n = ~ll_sof;
-   assign ll_eof_n = ~ll_eof;
-   assign ll_src_rdy_n = ~ll_src_rdy;
-   wire ll_dst_rdy = ~ll_dst_rdy_n;
-
-   wire   f36_sof = f36_data[32];
-   wire   f36_eof = f36_data[33];
-   wire   f36_occ = f36_data[35:34];
-   wire advance, end_early;
-   reg [1:0] state;
+   // Shortfifo on input to guarantee no deadlock
+   wire [35:0] 	 f36_data_int;
+   wire 	 f36_src_rdy_int, f36_dst_rdy_int;
+   reg [7:0] 	 ll_data_int;
+   wire 	 ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
+   
+   fifo_short #(.WIDTH(36)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f36_data), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o),
+      .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int),
+      .space(),.occupied() );
+
+   // Actual fifo36 to ll8, can deadlock if not connected to shortfifo
+   wire [1:0] 	 f36_occ_int = f36_data_int[35:34];
+   wire 	 f36_sof_int = f36_data_int[32];
+   wire 	 f36_eof_int = f36_data_int[33];
+   wire 	 advance, end_early;
+   reg [1:0] 	 state;
+   
    assign debug    = {29'b0,state};
 
    always @(posedge clk)
@@ -31,29 +39,37 @@ module fifo36_to_ll8
        state 	  <= 0;
      else
        if(advance)
-	 if(ll_eof)
+	 if(ll_eof_int)
 	   state  <= 0;
 	 else
 	   state  <= state + 1;
 
    always @*
      case(state)
-       0 : ll_data = f36_data[31:24];
-       1 : ll_data = f36_data[23:16];
-       2 : ll_data = f36_data[15:8];
-       3 : ll_data = f36_data[7:0];
-       default : ll_data = f36_data[31:24];
+       0 : ll_data_int = f36_data_int[31:24];
+       1 : ll_data_int = f36_data_int[23:16];
+       2 : ll_data_int = f36_data_int[15:8];
+       3 : ll_data_int = f36_data_int[7:0];
+       default : ll_data_int = f36_data_int[31:24];
        endcase // case (state)
    
-   assign ll_sof 	 = (state==0) & f36_sof;
-   assign ll_eof 	 = f36_eof & (((state==0)&(f36_occ==1)) |
-			       ((state==1)&(f36_occ==2)) |
-			       ((state==2)&(f36_occ==3)) |
-			       (state==3));
+   assign ll_sof_int 	 = (state==0) & f36_sof_int;
+   assign ll_eof_int 	 = f36_eof_int & (((state==0)&(f36_occ_int==1)) |
+					  ((state==1)&(f36_occ_int==2)) |
+					  ((state==2)&(f36_occ_int==3)) |
+					  (state==3));
    
-   assign ll_src_rdy 	 = f36_src_rdy_i;
-
-   assign advance 	 = ll_src_rdy & ll_dst_rdy;
-   assign f36_dst_rdy_o  = advance & ((state==3)|ll_eof);
+   assign ll_src_rdy_int = f36_src_rdy_int;
    
-endmodule // ll8_to_fifo36
+   assign advance 	 = ll_src_rdy_int & ll_dst_rdy_int;
+   assign f36_dst_rdy_int= advance & ((state==3)|ll_eof_int);
+
+   // Short FIFO on output to guarantee no deadlock
+   ll8_shortfifo tail_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(ll_data_int), .sof_i(ll_sof_int), .eof_i(ll_eof_int),
+      .error_i(0), .src_rdy_i(ll_src_rdy_int), .dst_rdy_o(ll_dst_rdy_int),
+      .dataout(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .error_o(), .src_rdy_o(ll_src_rdy), .dst_rdy_i(ll_dst_rdy));
+
+endmodule // fifo36_to_ll8
diff --git a/fpga/usrp2/fifo/fifo72_to_fifo36.v b/fpga/usrp2/fifo/fifo72_to_fifo36.v
new file mode 100644
index 000000000..1b3bc3ab7
--- /dev/null
+++ b/fpga/usrp2/fifo/fifo72_to_fifo36.v
@@ -0,0 +1,63 @@
+
+// Parameter LE tells us if we are little-endian.  
+// Little-endian means send lower 16 bits first.
+// Default is big endian (network order), send upper bits first.
+
+module fifo72_to_fifo36
+  #(parameter LE=0)
+   (input clk, input reset, input clear,
+    input [71:0] f72_datain,
+    input f72_src_rdy_i,
+    output f72_dst_rdy_o,
+    
+    output [35:0] f36_dataout,
+    output f36_src_rdy_o,
+    input f36_dst_rdy_i );
+      
+   wire [35:0] f36_data_int;
+   wire        f36_src_rdy_int, f36_dst_rdy_int;
+   wire [71:0] f72_data_int;
+   wire        f72_src_rdy_int, f72_dst_rdy_int;
+   
+   // Shortfifo on input to guarantee no deadlock
+   fifo_short #(.WIDTH(72)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f72_datain), .src_rdy_i(f72_src_rdy_i), .dst_rdy_o(f72_dst_rdy_o),
+      .dataout(f72_data_int), .src_rdy_o(f72_src_rdy_int), .dst_rdy_i(f72_dst_rdy_int),
+      .space(),.occupied() );
+
+   // Main fifo72_to_fifo36, needs shortfifos to guarantee no deadlock
+   wire [2:0]  f72_occ_int  = f72_data_int[68:66];
+   wire        f72_sof_int  = f72_data_int[64];
+   wire        f72_eof_int  = f72_data_int[65];
+   
+   reg 	  phase;
+   wire   half_line 	   = f72_eof_int & ( (f72_occ_int==1)|(f72_occ_int==2)|(f72_occ_int==3)|(f72_occ_int==4) );
+      
+   assign f36_data_int[31:0]   = (LE ^ phase) ? f72_data_int[31:0] : f72_data_int[63:32];
+   assign f36_data_int[32]     = phase ? 0 : f72_sof_int;
+   assign f36_data_int[33]     = phase ? f72_eof_int : half_line;
+   assign f36_data_int[35:34]  = f36_data_int[33] ? f72_occ_int[1:0] : 2'b00;
+      
+   assign f36_src_rdy_int    = f72_src_rdy_int;
+   assign f72_dst_rdy_int    = (phase | half_line) & f36_dst_rdy_int;
+   
+   wire   f36_xfer 	   = f36_src_rdy_int & f36_dst_rdy_int;
+   wire   f72_xfer 	   = f72_src_rdy_int & f72_dst_rdy_int;
+   
+   always @(posedge clk)
+     if(reset)
+       phase 		  <= 0;
+     else if(f72_xfer)
+       phase 		  <= 0;
+     else if(f36_xfer)
+       phase 		  <= 1;
+   
+   // Shortfifo on output to guarantee no deadlock
+   fifo_short #(.WIDTH(36)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
+      .dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
+      .space(),.occupied() );
+
+endmodule // fifo72_to_fifo36
diff --git a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v b/fpga/usrp2/fifo/fifo_pacer.v
index 1bf03ab6e..1bf03ab6e 100644
--- a/fpga/usrp2/control_lib/newfifo/fifo_pacer.v
+++ b/fpga/usrp2/fifo/fifo_pacer.v
diff --git a/fpga/usrp2/fifo/fifo_tb.v b/fpga/usrp2/fifo/fifo_tb.v
index 327da4700..3e2862a70 100644
--- a/fpga/usrp2/fifo/fifo_tb.v
+++ b/fpga/usrp2/fifo/fifo_tb.v
@@ -1,4 +1,4 @@
-module fifo_new_tb();
+module fifo_tb();
    
    reg clk = 0;
    reg rst = 1;
@@ -9,169 +9,47 @@ module fifo_new_tb();
    reg [31:0] f36_data = 0;
    reg [1:0] f36_occ = 0;
    reg f36_sof = 0, f36_eof = 0;
-   
-   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
-   reg src_rdy_f36i  = 0;
-   wire dst_rdy_f36i;
-
-   wire [35:0] f36_out, f36_out2;
-   wire src_rdy_f36o;
-   reg dst_rdy_f36o  = 0;
-   
-   //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-   //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
-
-   wire i1_sr, i1_dr;
-   wire i2_sr, i2_dr;
-   wire i3_sr, i3_dr;
-   wire i7_sr, i7_dr;
-   
-   reg i4_dr = 0;
-   wire i4_sr;
-      
-   wire [35:0] i1, i4, i7;
-   wire [18:0] i2, i3;
+   reg f36_src_rdy;
+   wire f36_dst_rdy;
    
    wire [7:0] ll_data;
-   wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+   wire ll_src_rdy, ll_dst_rdy, ll_sof, ll_eof;
    wire [35:0] err_dat;
    wire        err_src_rdy, err_dst_rdy;
 
-   reg 	       trigger = 0;
-   initial #10000 trigger = 1;
-   
-   fifo_short #(.WIDTH(36)) fifo_short1
+   fifo36_to_ll8 fifo36_to_ll8
      (.clk(clk),.reset(rst),.clear(clear),
-      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
-      .dataout(i7),.src_rdy_o(i7_sr),.dst_rdy_i(i7_dr) );
+      .f36_data({f36_occ,f36_eof,f36_sof,f36_data}),.f36_src_rdy_i(f36_src_rdy),.f36_dst_rdy_o(f36_dst_rdy),
+      .ll_data(ll_data),.ll_sof(ll_sof),.ll_eof(ll_eof),
+      .ll_src_rdy(ll_src_rdy),.ll_dst_rdy(ll_dst_rdy));
 
-   gen_context_pkt #(.PROT_ENG_FLAGS(1)) gcp
-     (.clk(clk),.reset(rst),.clear(clear),
-      .trigger(trigger), .sent(),
-      .streamid(32'hDEAD_F00D), .vita_time(64'h01234567_89ABCDEF), .message(32'hBEEF_2940),
-      .data_o(err_dat), .src_rdy_o(err_src_rdy), .dst_rdy_i(err_dst_rdy));
-   
-   fifo36_mux #(.prio(0)) fifo36_mux
-     (.clk(clk), .reset(rst), .clear(clear),
-      .data0_i(i7), .src0_rdy_i(i7_sr), .dst0_rdy_o(i7_dr),
-      .data1_i(err_dat), .src1_rdy_i(err_src_rdy), .dst1_rdy_o(err_dst_rdy),
-      .data_o(i1), .src_rdy_o(i1_sr), .dst_rdy_i(i1_dr));
+   assign ll_dst_rdy = 1;
    
-   fifo36_to_fifo19 fifo36_to_fifo19
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
-      .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
-
-   fifo19_to_ll8 fifo19_to_ll8
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
-      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
-      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
-
-   ll8_to_fifo19 ll8_to_fifo19
-     (.clk(clk),.reset(rst),.clear(clear),
-      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
-      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
-      .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
-
-   fifo19_to_fifo36 fifo19_to_fifo36
-     (.clk(clk),.reset(rst),.clear(clear),
-      .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
-      .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
-
-   task ReadFromFIFO36;
-      begin
-	 $display("Read from FIFO36");
-	 #1 i4_dr <= 1;
-	 while(1)
-	   begin
-	      while(~i4_sr)
-		@(posedge clk);
-	      $display("Read: %h",i4);
-	      @(posedge clk);
-	   end
-      end
-   endtask // ReadFromFIFO36
-
-   reg [15:0] count;
-   task PutPacketInFIFO36;
-      input [31:0] data_start;
-      input [31:0] data_len;
-      begin
-	 count 	      <= 4;
-	 src_rdy_f36i <= 1;
-	 f36_data     <= data_start;
-	 f36_sof      <= 1;
-	 f36_eof      <= 0;
-	 f36_occ      <= 0;
-	
-	 $display("Put Packet in FIFO36");
-	 while(~dst_rdy_f36i)
-	   @(posedge clk);
-	 @(posedge clk);
-	 $display("PPI_FIFO36: Entered First Line");
-	 f36_sof <= 0;
-	 while(count+4 < data_len)
-	   begin
-	      f36_data <= f36_data + 32'h01010101;
-	      count    <= count + 4;
-	      while(~dst_rdy_f36i)
-		@(posedge clk);
-	      @(posedge clk);
-	      $display("PPI_FIFO36: Entered New Line");
-	   end
-	 f36_data  <= f36_data + 32'h01010101;
-	 f36_eof   <= 1;
-	 if(count + 4 == data_len)
-	   f36_occ <= 0;
-	 else if(count + 3 == data_len)
-	   f36_occ <= 3;
-	 else if(count + 2 == data_len)
-	   f36_occ <= 2;
-	 else
-	   f36_occ <= 1;
-	 while(~dst_rdy_f36i)
-	   @(posedge clk);
-	 @(posedge clk);
-	 f36_occ      <= 0;
-	 f36_eof      <= 0;
-	 f36_data     <= 0;
-	 src_rdy_f36i <= 0;
-	 $display("PPI_FIFO36: Entered Last Line");
-      end
-   endtask // PutPacketInFIFO36
+   always @(posedge clk)
+     if(ll_src_rdy)
+       $display("LL: SOF %d, EOF %d, DAT %x",ll_sof,ll_eof,ll_data);
    
-   initial $dumpfile("fifo_new_tb.vcd");
-   initial $dumpvars(0,fifo_new_tb);
+   initial $dumpfile("fifo_tb.vcd");
+   initial $dumpvars(0,fifo_tb);
 
    initial
      begin
 	@(negedge rst);
-	//#10000;
 	@(posedge clk);
 	@(posedge clk);
 	@(posedge clk);
 	@(posedge clk);
-	ReadFromFIFO36;
-     end
-   
-   initial
-     begin
-	@(negedge rst);
-	@(posedge clk);
-	@(posedge clk);
-	PutPacketInFIFO36(32'hA0B0C0D0,12);
-	@(posedge clk);
-	@(posedge clk);
-	#10000;
-	@(posedge clk);
-	PutPacketInFIFO36(32'hE0F0A0B0,36);
-	@(posedge clk);
+	f36_src_rdy <= 1;
+	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b1,32'h00010203};
 	@(posedge clk);
+	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h04050607};
 	@(posedge clk);
+	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b00,1'b0,1'b0,32'h08090a0b};
 	@(posedge clk);
+	{f36_occ,f36_eof,f36_sof,f36_data} <= { 2'b11,1'b1,1'b0,32'h0c0d0e0f};
 	@(posedge clk);
+	f36_src_rdy <= 0;
      end
-
-   initial #20000 $finish;
+   
+   initial #4000 $finish;
 endmodule // longfifo_tb
diff --git a/fpga/usrp2/fifo/ll8_to_fifo19.v b/fpga/usrp2/fifo/ll8_to_fifo19.v
index af3b91afb..ac8ac19a6 100644
--- a/fpga/usrp2/fifo/ll8_to_fifo19.v
+++ b/fpga/usrp2/fifo/ll8_to_fifo19.v
@@ -2,41 +2,47 @@
 module ll8_to_fifo19
   (input clk, input reset, input clear,
    input [7:0] ll_data,
-   input ll_sof_n,
-   input ll_eof_n,
-   input ll_src_rdy_n,
-   output ll_dst_rdy_n,
+   input ll_sof,
+   input ll_eof,
+   input ll_src_rdy,
+   output ll_dst_rdy,
 
    output [18:0] f19_data,
    output f19_src_rdy_o,
    input f19_dst_rdy_i );
+
+   // Short FIFO on input to guarantee no deadlock
+   wire [7:0] ll_data_int;
+   wire       ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
    
+   ll8_shortfifo head_fifo
+     (.clk(clk), .reset(reset), .clear(clear),
+      .datain(ll_data), .sof_i(ll_sof), .eof_i(ll_eof),
+      .error_i(0), .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy),
+      .dataout(ll_data_int), .sof_o(ll_sof_int), .eof_o(ll_eof_int),
+      .error_o(), .src_rdy_o(ll_src_rdy_int), .dst_rdy_i(ll_dst_rdy_int));
+
+   // Actual ll8_to_fifo19 which could deadlock if not connected to a shortfifo
    localparam XFER_EMPTY       = 0;
    localparam XFER_HALF        = 1;
    localparam XFER_HALF_WRITE  = 3;
    
-   // Why anybody would use active low in an FPGA is beyond me...
-   wire  ll_sof      = ~ll_sof_n;
-   wire  ll_eof      = ~ll_eof_n;
-   wire  ll_src_rdy  = ~ll_src_rdy_n;
-   wire  ll_dst_rdy;
-   assign    ll_dst_rdy_n  = ~ll_dst_rdy;
-   
-   wire  xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
-   wire  xfer_in 	   = ll_src_rdy & ll_dst_rdy; 
-   
-   reg 	 hold_sof;
-   wire  f19_sof, f19_eof, f19_occ;
+   wire [18:0] f19_data_int;
+   wire        f19_sof_int, f19_eof_int, f19_occ_int, f19_src_rdy_int, f19_dst_rdy_int;
+
+   wire        xfer_out    = f19_src_rdy_int & f19_dst_rdy_int;
+   wire        xfer_in 	   = ll_src_rdy_int & ll_dst_rdy_int; 
+   reg 	       hold_sof;
    
-   reg [1:0] state;
-   reg [7:0] hold_reg;
+   reg [1:0]   state;
+   reg [7:0]   hold_reg;
    
    always @(posedge clk)
-     if(ll_src_rdy & (state==XFER_EMPTY))
-       hold_reg 	      <= ll_data;
+     if(ll_src_rdy_int & (state==XFER_EMPTY))
+       hold_reg 	      <= ll_data_int;
    
    always @(posedge clk)
-     if(ll_sof & (state==XFER_EMPTY))
+     if(ll_sof_int & (state==XFER_EMPTY))
        hold_sof 	      <= 1;
      else if(xfer_out)
        hold_sof 	      <= 0;
@@ -47,27 +53,35 @@ module ll8_to_fifo19
      else
        case(state)
 	 XFER_EMPTY :
-	   if(ll_src_rdy)
-	     if(ll_eof)
+	   if(ll_src_rdy_int)
+	     if(ll_eof_int)
 	       state 	      <= XFER_HALF_WRITE;
 	     else
 	       state 	      <= XFER_HALF;
 	 XFER_HALF :
-	   if(ll_src_rdy & f19_dst_rdy_i)
+	   if(ll_src_rdy_int & f19_dst_rdy_int)
 	       state 	      <= XFER_EMPTY;
          XFER_HALF_WRITE :
-	   if(f19_dst_rdy_i)
+	   if(f19_dst_rdy_int)
 	     state 	<= XFER_EMPTY;
        endcase // case (state)
       
-   assign ll_dst_rdy 	 = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i);
-   assign f19_src_rdy_o  = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy);
+   assign ll_dst_rdy_int = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_int);
+   assign f19_src_rdy_int= (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy_int);
    
-   assign f19_sof 	 = hold_sof | (ll_sof & (state==XFER_HALF));
-   assign f19_eof 	 = (state == XFER_HALF_WRITE) | ll_eof;
-   assign f19_occ 	 = (state == XFER_HALF_WRITE);
+   assign f19_sof_int 	 = hold_sof | (ll_sof_int & (state==XFER_HALF));
+   assign f19_eof_int 	 = (state == XFER_HALF_WRITE) | ll_eof_int;
+   assign f19_occ_int 	 = (state == XFER_HALF_WRITE);
    
-   assign f19_data 	 = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data};
+   assign f19_data_int 	 = {f19_occ_int,f19_eof_int,f19_sof_int,hold_reg,ll_data_int};
+
+   // Shortfifo on output to guarantee no deadlock
+   fifo_short #(.WIDTH(19)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int),
+      .dataout(f19_data), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i),
+      .space(),.occupied() );
       
+   
 endmodule // ll8_to_fifo19
 
diff --git a/fpga/usrp2/control_lib/newfifo/packet32_tb.v b/fpga/usrp2/fifo/packet32_tb.v
index 82bb09c29..82bb09c29 100644
--- a/fpga/usrp2/control_lib/newfifo/packet32_tb.v
+++ b/fpga/usrp2/fifo/packet32_tb.v
diff --git a/fpga/usrp2/fifo/packet_dispatcher36_x3.v b/fpga/usrp2/fifo/packet_dispatcher36_x3.v
new file mode 100644
index 000000000..fd762d061
--- /dev/null
+++ b/fpga/usrp2/fifo/packet_dispatcher36_x3.v
@@ -0,0 +1,270 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// Packet dispatcher with fifo36 interface and 3 outputs.
+//
+// The packet dispatcher expects 2-byte padded ethernet frames.
+// The frames will be inspected at ethernet, IPv4, UDP, and VRT layers.
+// Packets are dispatched into the following streams:
+//   * tx dsp stream
+//   * to cpu stream
+//   * to external stream
+//   * to both cpu and external
+//
+// The following registers are used for dispatcher control:
+//   * base + 0 = this ipv4 address (32 bits)
+//   * base + 1 = udp dst port (lower 16 bits)
+//
+
+module packet_dispatcher36_x3
+    #(
+        parameter BASE = 0
+    )
+    (
+        //clocking and reset interface:
+        input clk, input rst, input clr,
+
+        //setting register interface:
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        //input stream interfaces:
+        input [35:0] com_inp_data, input com_inp_valid, output com_inp_ready,
+
+        //output stream interfaces:
+        output [35:0] ext_out_data, output ext_out_valid, input ext_out_ready,
+        output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready,
+        output [35:0] cpu_out_data, output cpu_out_valid, input cpu_out_ready
+    );
+
+    //setting register to program the IP address
+    wire [31:0] my_ip_addr;
+    setting_reg #(.my_addr(BASE+0)) sreg_ip_addr(
+        .clk(clk),.rst(rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(my_ip_addr),.changed()
+    );
+
+    //setting register to program the UDP DSP port
+    wire [15:0] dsp_udp_port;
+    setting_reg #(.my_addr(BASE+1), .width(16)) sreg_data_port(
+        .clk(clk),.rst(rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(dsp_udp_port),.changed()
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // Communication input inspector
+    //   - inspect com input and send it to DSP, EXT, CPU, or BOTH
+    ////////////////////////////////////////////////////////////////////
+    localparam PD_STATE_READ_COM_PRE = 0;
+    localparam PD_STATE_READ_COM = 1;
+    localparam PD_STATE_WRITE_REGS = 2;
+    localparam PD_STATE_WRITE_LIVE = 3;
+
+    localparam PD_DEST_DSP = 0;
+    localparam PD_DEST_EXT = 1;
+    localparam PD_DEST_CPU = 2;
+    localparam PD_DEST_BOF = 3;
+
+    localparam PD_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
+    localparam PD_DREGS_DSP_OFFSET = 11; //offset to start dsp at
+
+    //output inspector interfaces
+    wire [35:0] pd_out_dsp_data;
+    wire        pd_out_dsp_valid;
+    wire        pd_out_dsp_ready;
+
+    wire [35:0] pd_out_ext_data;
+    wire        pd_out_ext_valid;
+    wire        pd_out_ext_ready;
+
+    wire [35:0] pd_out_cpu_data;
+    wire        pd_out_cpu_valid;
+    wire        pd_out_cpu_ready;
+
+    wire [35:0] pd_out_bof_data;
+    wire        pd_out_bof_valid;
+    wire        pd_out_bof_ready;
+
+    reg [1:0] pd_state;
+    reg [1:0] pd_dest;
+    reg [3:0] pd_dreg_count; //data registers to buffer headers
+    wire [3:0] pd_dreg_count_next = pd_dreg_count + 1'b1;
+    wire pd_dreg_counter_done = (pd_dreg_count_next == PD_MAX_NUM_DREGS)? 1'b1 : 1'b0;
+    reg [35:0] pd_dregs [PD_MAX_NUM_DREGS-1:0];
+
+    //extract various packet components:
+    wire [47:0] pd_dregs_eth_dst_mac   = {pd_dregs[0][15:0], pd_dregs[1][31:0]};
+    wire [15:0] pd_dregs_eth_type      = pd_dregs[3][15:0];
+    wire [7:0]  pd_dregs_ipv4_proto    = pd_dregs[6][23:16];
+    wire [31:0] pd_dregs_ipv4_dst_addr = pd_dregs[8][31:0];
+    wire [15:0] pd_dregs_udp_dst_port  = pd_dregs[9][15:0];
+    wire [15:0] pd_dregs_vrt_size      = com_inp_data[15:0];
+
+    //Inspector output flags special case:
+    //Inject SOF into flags at first DSP line.
+    wire [3:0] pd_out_flags = (
+        (pd_dreg_count == PD_DREGS_DSP_OFFSET) &&
+        (pd_dest == PD_DEST_DSP)
+    )? 4'b0001 : pd_dregs[pd_dreg_count][35:32];
+
+    //The communication inspector ouput data and valid signals:
+    //Mux between com input and data registers based on the state.
+    wire [35:0] pd_out_data = (pd_state == PD_STATE_WRITE_REGS)?
+        {pd_out_flags, pd_dregs[pd_dreg_count][31:0]} : com_inp_data
+    ;
+    wire pd_out_valid =
+        (pd_state == PD_STATE_WRITE_REGS)? 1'b1          : (
+        (pd_state == PD_STATE_WRITE_LIVE)? com_inp_valid : (
+    1'b0));
+
+    //The communication inspector ouput ready signal:
+    //Mux between the various destination ready signals.
+    wire pd_out_ready =
+        (pd_dest == PD_DEST_DSP)? pd_out_dsp_ready : (
+        (pd_dest == PD_DEST_EXT)? pd_out_ext_ready : (
+        (pd_dest == PD_DEST_CPU)? pd_out_cpu_ready : (
+        (pd_dest == PD_DEST_BOF)? pd_out_bof_ready : (
+    1'b0))));
+
+    //Always connected output data lines.
+    assign pd_out_dsp_data = pd_out_data;
+    assign pd_out_ext_data = pd_out_data;
+    assign pd_out_cpu_data = pd_out_data;
+    assign pd_out_bof_data = pd_out_data;
+
+    //Destination output valid signals:
+    //Comes from inspector valid when destination is selected, and otherwise low.
+    assign pd_out_dsp_valid = (pd_dest == PD_DEST_DSP)? pd_out_valid : 1'b0;
+    assign pd_out_ext_valid = (pd_dest == PD_DEST_EXT)? pd_out_valid : 1'b0;
+    assign pd_out_cpu_valid = (pd_dest == PD_DEST_CPU)? pd_out_valid : 1'b0;
+    assign pd_out_bof_valid = (pd_dest == PD_DEST_BOF)? pd_out_valid : 1'b0;
+
+    //The communication inspector ouput ready signal:
+    //Always ready when storing to data registers,
+    //comes from inspector ready output when live,
+    //and otherwise low.
+    assign com_inp_ready =
+        (pd_state == PD_STATE_READ_COM_PRE)  ? 1'b1         : (
+        (pd_state == PD_STATE_READ_COM)      ? 1'b1         : (
+        (pd_state == PD_STATE_WRITE_LIVE)    ? pd_out_ready : (
+    1'b0)));
+
+    always @(posedge clk)
+    if(rst | clr) begin
+        pd_state <= PD_STATE_READ_COM_PRE;
+        pd_dreg_count <= 0;
+    end
+    else begin
+        case(pd_state)
+        PD_STATE_READ_COM_PRE: begin
+            if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin
+                pd_state <= PD_STATE_READ_COM;
+                pd_dreg_count <= pd_dreg_count_next;
+                pd_dregs[pd_dreg_count] <= com_inp_data;
+            end
+        end
+
+        PD_STATE_READ_COM: begin
+            if (com_inp_ready & com_inp_valid) begin
+                pd_dregs[pd_dreg_count] <= com_inp_data;
+                if (pd_dreg_counter_done | com_inp_data[33]) begin
+                    pd_state <= PD_STATE_WRITE_REGS;
+                    pd_dreg_count <= 0;
+
+                    //---------- begin inspection decision -----------//
+                    //EOF or bcast or not IPv4 or not UDP:
+                    if (
+                        com_inp_data[33] || (pd_dregs_eth_dst_mac == 48'hffffffffffff) ||
+                        (pd_dregs_eth_type != 16'h800) || (pd_dregs_ipv4_proto != 8'h11)
+                    ) begin
+                        pd_dest <= PD_DEST_BOF;
+                    end
+
+                    //not my IP address:
+                    else if (pd_dregs_ipv4_dst_addr != my_ip_addr) begin
+                        pd_dest <= PD_DEST_EXT;
+                    end
+
+                    //UDP data port and VRT:
+                    else if ((pd_dregs_udp_dst_port == dsp_udp_port) && (pd_dregs_vrt_size != 16'h0)) begin
+                        pd_dest <= PD_DEST_DSP;
+                        pd_dreg_count <= PD_DREGS_DSP_OFFSET;
+                    end
+
+                    //other:
+                    else begin
+                        pd_dest <= PD_DEST_CPU;
+                    end
+                    //---------- end inspection decision -------------//
+
+                end
+                else begin
+                    pd_dreg_count <= pd_dreg_count_next;
+                end
+            end
+        end
+
+        PD_STATE_WRITE_REGS: begin
+            if (pd_out_ready & pd_out_valid) begin
+                if (pd_out_data[33]) begin
+                    pd_state <= PD_STATE_READ_COM_PRE;
+                    pd_dreg_count <= 0;
+                end
+                else if (pd_dreg_counter_done) begin
+                    pd_state <= PD_STATE_WRITE_LIVE;
+                    pd_dreg_count <= 0;
+                end
+                else begin
+                    pd_dreg_count <= pd_dreg_count_next;
+                end
+            end
+        end
+
+        PD_STATE_WRITE_LIVE: begin
+            if (pd_out_ready & pd_out_valid & pd_out_data[33]) begin
+                pd_state <= PD_STATE_READ_COM_PRE;
+            end
+        end
+
+        endcase //pd_state
+    end
+
+    //connect this fast-path signals directly to the DSP out
+    assign dsp_out_data = pd_out_dsp_data;
+    assign dsp_out_valid = pd_out_dsp_valid;
+    assign pd_out_dsp_ready = dsp_out_ready;
+
+    ////////////////////////////////////////////////////////////////////
+    // Splitter and output muxes for the bof packets
+    //   - split the bof packets into two streams
+    //   - mux split packets into cpu out and ext out
+    ////////////////////////////////////////////////////////////////////
+
+    //dummy signals to join the the splitter and muxes below
+    wire [35:0] _split_to_ext_data,  _split_to_cpu_data;
+    wire        _split_to_ext_valid, _split_to_cpu_valid;
+    wire        _split_to_ext_ready, _split_to_cpu_ready;
+
+    splitter36 bof_out_splitter(
+        .clk(clk), .rst(rst), .clr(clr),
+        .inp_data(pd_out_bof_data), .inp_valid(pd_out_bof_valid), .inp_ready(pd_out_bof_ready),
+        .out0_data(_split_to_ext_data), .out0_valid(_split_to_ext_valid), .out0_ready(_split_to_ext_ready),
+        .out1_data(_split_to_cpu_data), .out1_valid(_split_to_cpu_valid), .out1_ready(_split_to_cpu_ready)
+    );
+
+    fifo36_mux ext_out_mux(
+        .clk(clk), .reset(rst), .clear(clr),
+        .data0_i(pd_out_ext_data), .src0_rdy_i(pd_out_ext_valid), .dst0_rdy_o(pd_out_ext_ready),
+        .data1_i(_split_to_ext_data), .src1_rdy_i(_split_to_ext_valid), .dst1_rdy_o(_split_to_ext_ready),
+        .data_o(ext_out_data), .src_rdy_o(ext_out_valid), .dst_rdy_i(ext_out_ready)
+    );
+
+    fifo36_mux cpu_out_mux(
+        .clk(clk), .reset(rst), .clear(clr),
+        .data0_i(pd_out_cpu_data), .src0_rdy_i(pd_out_cpu_valid), .dst0_rdy_o(pd_out_cpu_ready),
+        .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready),
+        .data_o(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready)
+    );
+
+endmodule // packet_dispatcher36_x3
diff --git a/fpga/usrp2/fifo/packet_generator.v b/fpga/usrp2/fifo/packet_generator.v
new file mode 100644
index 000000000..2ae911e24
--- /dev/null
+++ b/fpga/usrp2/fifo/packet_generator.v
@@ -0,0 +1,83 @@
+
+
+module packet_generator
+  (input clk, input reset, input clear,
+   output reg [7:0] data_o, output sof_o, output eof_o,
+   input [127:0] header,
+   output src_rdy_o, input dst_rdy_i);
+
+   localparam len = 32'd2000;
+
+   reg [31:0] state;
+   reg [31:0] seq;
+   reg [31:0] crc_out;
+   wire        calc_crc = src_rdy_o & dst_rdy_i & ~(state[31:2] == 30'h3FFF_FFFF);
+   
+	
+   always @(posedge clk)
+     if(reset | clear)
+       seq <= 0;
+     else
+       if(eof_o & src_rdy_o & dst_rdy_i)
+	 seq <= seq + 1;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       state <= 0;
+     else
+       if(src_rdy_o & dst_rdy_i)
+	 if(state == (len - 1))
+	   state <= 32'hFFFF_FFFC;
+	 else
+	   state <= state + 1;
+
+   always @*
+     case(state)
+       0 :   data_o <= len[31:24];
+       1 :   data_o <= len[23:16];
+       2 :   data_o <= len[15:8];
+       3 :   data_o <= len[7:0];
+       4 :   data_o <= seq[31:24];
+       5 :   data_o <= seq[23:16];
+       6 :   data_o <= seq[15:8];
+       7 :   data_o <= seq[7:0];
+       8 :   data_o <= header[7:0];
+       9 :   data_o <= header[15:8];
+       10 :  data_o <= header[23:16];
+       11 :  data_o <= header[31:24];
+       12 :  data_o <= header[39:32];
+       13 :  data_o <= header[47:40];
+       14 :  data_o <= header[55:48];
+       15 :  data_o <= header[63:56];
+       16 :  data_o <= header[71:64];
+       17 :  data_o <= header[79:72];
+       18 :  data_o <= header[87:80];
+       19 :  data_o <= header[95:88];
+       20 :  data_o <= header[103:96];
+       21 :  data_o <= header[111:104];
+       22 :  data_o <= header[119:112];
+       23 :  data_o <= header[127:120];
+
+       32'hFFFF_FFFC : data_o <= crc_out[31:24];
+       32'hFFFF_FFFD : data_o <= crc_out[23:16];
+       32'hFFFF_FFFE : data_o <= crc_out[15:8];
+       32'hFFFF_FFFF : data_o <= crc_out[7:0];
+       default : data_o <= state[7:0];
+     endcase // case (state)
+   
+   assign src_rdy_o = 1;
+   assign sof_o = (state == 0);
+   assign eof_o = (state == 32'hFFFF_FFFF);
+
+   wire        clear_crc = eof_o & src_rdy_o & dst_rdy_i;
+   
+//   crc crc(.clk(clk), .reset(reset), .clear(clear_crc), .data(data_o), 
+//	   .calc(calc_crc), .crc_out(crc_out), .match());
+   always @(posedge clk)
+     if(reset | clear | clear_crc)
+       crc_out <= 0;
+     else
+       if(calc_crc)
+	 crc_out <= crc_out + data_o;
+   
+endmodule // packet_generator
diff --git a/fpga/usrp2/control_lib/newfifo/packet_generator32.v b/fpga/usrp2/fifo/packet_generator32.v
index 6f8004964..1dc57191d 100644
--- a/fpga/usrp2/control_lib/newfifo/packet_generator32.v
+++ b/fpga/usrp2/fifo/packet_generator32.v
@@ -2,6 +2,7 @@
 
 module packet_generator32
   (input clk, input reset, input clear,
+   input [127:0] header,
    output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
 
    wire [7:0] 	     ll_data;
@@ -10,6 +11,7 @@ module packet_generator32
    packet_generator pkt_gen
      (.clk(clk), .reset(reset), .clear(clear),
       .data_o(ll_data), .sof_o(ll_sof), .eof_o(ll_eof),
+      .header(header),
       .src_rdy_o(ll_src_rdy), .dst_rdy_i(~ll_dst_rdy_n));
 
    ll8_to_fifo36 ll8_to_f36
diff --git a/fpga/usrp2/fifo/packet_router.v b/fpga/usrp2/fifo/packet_router.v
index bad8fb7fc..7774ff076 100644
--- a/fpga/usrp2/fifo/packet_router.v
+++ b/fpga/usrp2/fifo/packet_router.v
@@ -69,28 +69,14 @@ module packet_router
 
     //setting register for mode control
     wire [31:0] _sreg_mode_ctrl;
+    wire        master_mode_flag;
+   
     setting_reg #(.my_addr(CTRL_BASE+0), .width(1)) sreg_mode_ctrl(
         .clk(stream_clk),.rst(stream_rst),
         .strobe(set_stb),.addr(set_addr),.in(set_data),
         .out(master_mode_flag),.changed()
     );
 
-    //setting register to program the IP address
-    wire [31:0] my_ip_addr;
-    setting_reg #(.my_addr(CTRL_BASE+1)) sreg_ip_addr(
-        .clk(stream_clk),.rst(stream_rst),
-        .strobe(set_stb),.addr(set_addr),.in(set_data),
-        .out(my_ip_addr),.changed()
-    );
-
-    //setting register to program the UDP data ports
-    wire [15:0] dsp_udp_port;
-    setting_reg #(.my_addr(CTRL_BASE+2), .width(16)) sreg_data_ports(
-        .clk(stream_clk),.rst(stream_rst),
-        .strobe(set_stb),.addr(set_addr),.in(set_data),
-        .out(dsp_udp_port),.changed()
-    );
-
     //assign status output signals
     wire [31:0] cpu_iface_status;
     assign status = {
@@ -118,8 +104,8 @@ module packet_router
     wire        _eth_inp_ready;
 
     // dummy signals to connect fifo_short
-    wire [35:0]	_com_inp_data;
-    wire 	_com_inp_valid;
+    wire [35:0] _com_inp_data;
+    wire        _com_inp_valid;
     wire        _com_inp_ready;
 
     valve36 eth_inp_valve (
@@ -179,36 +165,34 @@ module packet_router
 
     ////////////////////////////////////////////////////////////////////
     // Communication output source combiner (feeds UDP proto machine)
-    //   - DSP framer
+    //   - DSP input
     //   - CPU input
     //   - ERR input
     ////////////////////////////////////////////////////////////////////
 
-    //streaming signals from the dsp framer to the combiner
-    wire [35:0] dsp0_frm_data, dsp1_frm_data;
-    wire        dsp0_frm_valid, dsp1_frm_valid;
-    wire        dsp0_frm_ready, dsp1_frm_ready;
-
     //dummy signals to join the the muxes below
     wire [35:0] _combiner0_data, _combiner1_data;
     wire        _combiner0_valid, _combiner1_valid;
     wire        _combiner0_ready, _combiner1_ready;
 
-    fifo36_mux _com_output_combiner0(
+    fifo36_mux #(.prio(0)) // No priority, fair sharing
+     _com_output_combiner0(
         .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(dsp0_frm_data), .src0_rdy_i(dsp0_frm_valid), .dst0_rdy_o(dsp0_frm_ready),
-        .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready),
+        .data0_i(err_inp_data), .src0_rdy_i(err_inp_valid), .dst0_rdy_o(err_inp_ready),
+        .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
         .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready)
     );
 
-    fifo36_mux _com_output_combiner1(
+    fifo36_mux #(.prio(0)) // No priority, fair sharing
+     _com_output_combiner1(
         .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(dsp1_frm_data), .src0_rdy_i(dsp1_frm_valid), .dst0_rdy_o(dsp1_frm_ready),
-        .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready),
+        .data0_i(dsp0_inp_data), .src0_rdy_i(dsp0_inp_valid), .dst0_rdy_o(dsp0_inp_ready),
+        .data1_i(dsp1_inp_data), .src1_rdy_i(dsp1_inp_valid), .dst1_rdy_o(dsp1_inp_ready),
         .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready)
     );
 
-    fifo36_mux com_output_source(
+    fifo36_mux #(.prio(1)) // Give priority to err/cpu over dsp
+     com_output_source(
         .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
         .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready),
         .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready),
@@ -217,6 +201,7 @@ module packet_router
 
     ////////////////////////////////////////////////////////////////////
     // Interface CPU to memory mapped wishbone
+    //   - Uses 1 setting register
     ////////////////////////////////////////////////////////////////////
     buffer_int2 #(.BASE(CTRL_BASE+3), .BUF_SIZE(BUF_SIZE)) cpu_to_wb(
         .clk(stream_clk), .rst(stream_rst | stream_clr),
@@ -238,218 +223,21 @@ module packet_router
     );
 
     ////////////////////////////////////////////////////////////////////
-    // Communication input inspector
-    //   - inspect com input and send it to DSP, EXT, CPU, or BOTH
-    ////////////////////////////////////////////////////////////////////
-    localparam COM_INSP_STATE_READ_COM_PRE = 0;
-    localparam COM_INSP_STATE_READ_COM = 1;
-    localparam COM_INSP_STATE_WRITE_REGS = 2;
-    localparam COM_INSP_STATE_WRITE_LIVE = 3;
-
-    localparam COM_INSP_DEST_DSP = 0;
-    localparam COM_INSP_DEST_EXT = 1;
-    localparam COM_INSP_DEST_CPU = 2;
-    localparam COM_INSP_DEST_BOF = 3;
-
-    localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
-    localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at
-
-    //output inspector interfaces
-    wire [35:0] com_insp_out_dsp_data;
-    wire        com_insp_out_dsp_valid;
-    wire        com_insp_out_dsp_ready;
-
-    wire [35:0] com_insp_out_ext_data;
-    wire        com_insp_out_ext_valid;
-    wire        com_insp_out_ext_ready;
-
-    wire [35:0] com_insp_out_cpu_data;
-    wire        com_insp_out_cpu_valid;
-    wire        com_insp_out_cpu_ready;
-
-    wire [35:0] com_insp_out_bof_data;
-    wire        com_insp_out_bof_valid;
-    wire        com_insp_out_bof_ready;
-
-    //connect this fast-path signals directly to the DSP out
-    assign dsp_out_data = com_insp_out_dsp_data;
-    assign dsp_out_valid = com_insp_out_dsp_valid;
-    assign com_insp_out_dsp_ready = dsp_out_ready;
-
-    reg [1:0] com_insp_state;
-    reg [1:0] com_insp_dest;
-    reg [3:0] com_insp_dreg_count; //data registers to buffer headers
-    wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1;
-    wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0;
-    reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0];
-
-    //extract various packet components:
-    wire [47:0] com_insp_dregs_eth_dst_mac   = {com_insp_dregs[0][15:0], com_insp_dregs[1][31:0]};
-    wire [15:0] com_insp_dregs_eth_type      = com_insp_dregs[3][15:0];
-    wire [7:0]  com_insp_dregs_ipv4_proto    = com_insp_dregs[6][23:16];
-    wire [31:0] com_insp_dregs_ipv4_dst_addr = com_insp_dregs[8][31:0];
-    wire [15:0] com_insp_dregs_udp_dst_port  = com_insp_dregs[9][15:0];
-    wire [15:0] com_insp_dregs_vrt_size      = com_inp_data[15:0];
-
-    //Inspector output flags special case:
-    //Inject SOF into flags at first DSP line.
-    wire [3:0] com_insp_out_flags = (
-        (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) &&
-        (com_insp_dest == COM_INSP_DEST_DSP)
-    )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32];
-
-    //The communication inspector ouput data and valid signals:
-    //Mux between com input and data registers based on the state.
-    wire [35:0] com_insp_out_data = (com_insp_state == COM_INSP_STATE_WRITE_REGS)?
-        {com_insp_out_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data
-    ;
-    wire com_insp_out_valid =
-        (com_insp_state == COM_INSP_STATE_WRITE_REGS)? 1'b1          : (
-        (com_insp_state == COM_INSP_STATE_WRITE_LIVE)? com_inp_valid : (
-    1'b0));
-
-    //The communication inspector ouput ready signal:
-    //Mux between the various destination ready signals.
-    wire com_insp_out_ready =
-        (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_dsp_ready : (
-        (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_ext_ready : (
-        (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_cpu_ready : (
-        (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_bof_ready : (
-    1'b0))));
-
-    //Always connected output data lines.
-    assign com_insp_out_dsp_data = com_insp_out_data;
-    assign com_insp_out_ext_data = com_insp_out_data;
-    assign com_insp_out_cpu_data = com_insp_out_data;
-    assign com_insp_out_bof_data = com_insp_out_data;
-
-    //Destination output valid signals:
-    //Comes from inspector valid when destination is selected, and otherwise low.
-    assign com_insp_out_dsp_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0;
-    assign com_insp_out_ext_valid = (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_valid : 1'b0;
-    assign com_insp_out_cpu_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0;
-    assign com_insp_out_bof_valid = (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_valid : 1'b0;
-
-    //The communication inspector ouput ready signal:
-    //Always ready when storing to data registers,
-    //comes from inspector ready output when live,
-    //and otherwise low.
-    assign com_inp_ready =
-        (com_insp_state == COM_INSP_STATE_READ_COM_PRE)  ? 1'b1               : (
-        (com_insp_state == COM_INSP_STATE_READ_COM)      ? 1'b1               : (
-        (com_insp_state == COM_INSP_STATE_WRITE_LIVE)    ? com_insp_out_ready : (
-    1'b0)));
-
-    always @(posedge stream_clk)
-    if(stream_rst | stream_clr) begin
-        com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
-        com_insp_dreg_count <= 0;
-    end
-    else begin
-        case(com_insp_state)
-        COM_INSP_STATE_READ_COM_PRE: begin
-            if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin
-                com_insp_state <= COM_INSP_STATE_READ_COM;
-                com_insp_dreg_count <= com_insp_dreg_count_next;
-                com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
-            end
-        end
-
-        COM_INSP_STATE_READ_COM: begin
-            if (com_inp_ready & com_inp_valid) begin
-                com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
-                if (com_insp_dreg_counter_done | com_inp_data[33]) begin
-                    com_insp_state <= COM_INSP_STATE_WRITE_REGS;
-                    com_insp_dreg_count <= 0;
-
-                    //---------- begin inspection decision -----------//
-                    //EOF or bcast or not IPv4 or not UDP:
-                    if (
-                        com_inp_data[33] || (com_insp_dregs_eth_dst_mac == 48'hffffffffffff) ||
-                        (com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11)
-                    ) begin
-                        com_insp_dest <= COM_INSP_DEST_BOF;
-                    end
-
-                    //not my IP address:
-                    else if (com_insp_dregs_ipv4_dst_addr != my_ip_addr) begin
-                        com_insp_dest <= COM_INSP_DEST_EXT;
-                    end
-
-                    //UDP data port and VRT:
-                    else if ((com_insp_dregs_udp_dst_port == dsp_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin
-                        com_insp_dest <= COM_INSP_DEST_DSP;
-                        com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET;
-                    end
-
-                    //other:
-                    else begin
-                        com_insp_dest <= COM_INSP_DEST_CPU;
-                    end
-                    //---------- end inspection decision -------------//
-
-                end
-                else begin
-                    com_insp_dreg_count <= com_insp_dreg_count_next;
-                end
-            end
-        end
-
-        COM_INSP_STATE_WRITE_REGS: begin
-            if (com_insp_out_ready & com_insp_out_valid) begin
-                if (com_insp_out_data[33]) begin
-                    com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
-                    com_insp_dreg_count <= 0;
-                end
-                else if (com_insp_dreg_counter_done) begin
-                    com_insp_state <= COM_INSP_STATE_WRITE_LIVE;
-                    com_insp_dreg_count <= 0;
-                end
-                else begin
-                    com_insp_dreg_count <= com_insp_dreg_count_next;
-                end
-            end
-        end
-
-        COM_INSP_STATE_WRITE_LIVE: begin
-            if (com_insp_out_ready & com_insp_out_valid & com_insp_out_data[33]) begin
-                com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
-            end
-        end
-
-        endcase //com_insp_state
-    end
-
+    // Packet Dispatcher
+    //   - Uses 2 setting registers
+    //   - provide buffering before cpu for random + small packet bursts
     ////////////////////////////////////////////////////////////////////
-    // Splitter and output muxes for the bof packets
-    //   - split the bof packets into two streams
-    //   - mux split packets into cpu out and ext out
-    ////////////////////////////////////////////////////////////////////
-
-    //dummy signals to join the the splitter and muxes below
-    wire [35:0] _split_to_ext_data,  _split_to_cpu_data,  _cpu_out_data;
-    wire        _split_to_ext_valid, _split_to_cpu_valid, _cpu_out_valid;
-    wire        _split_to_ext_ready, _split_to_cpu_ready, _cpu_out_ready;
+    wire [35:0] _cpu_out_data;
+    wire        _cpu_out_valid;
+    wire        _cpu_out_ready;
 
-    splitter36 bof_out_splitter(
+    packet_dispatcher36_x3 #(.BASE(CTRL_BASE+1)) packet_dispatcher(
         .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
-        .inp_data(com_insp_out_bof_data), .inp_valid(com_insp_out_bof_valid), .inp_ready(com_insp_out_bof_ready),
-        .out0_data(_split_to_ext_data),   .out0_valid(_split_to_ext_valid),   .out0_ready(_split_to_ext_ready),
-        .out1_data(_split_to_cpu_data),   .out1_valid(_split_to_cpu_valid),   .out1_ready(_split_to_cpu_ready)
-    );
-
-    fifo36_mux ext_out_mux(
-        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(com_insp_out_ext_data), .src0_rdy_i(com_insp_out_ext_valid), .dst0_rdy_o(com_insp_out_ext_ready),
-        .data1_i(_split_to_ext_data),    .src1_rdy_i(_split_to_ext_valid),    .dst1_rdy_o(_split_to_ext_ready),
-        .data_o(ext_out_data),           .src_rdy_o(ext_out_valid),           .dst_rdy_i(ext_out_ready)
-    );
-
-    fifo36_mux cpu_out_mux(
-        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(com_insp_out_cpu_data), .src0_rdy_i(com_insp_out_cpu_valid), .dst0_rdy_o(com_insp_out_cpu_ready),
-        .data1_i(_split_to_cpu_data),    .src1_rdy_i(_split_to_cpu_valid),    .dst1_rdy_o(_split_to_cpu_ready),
-        .data_o(_cpu_out_data),          .src_rdy_o(_cpu_out_valid),          .dst_rdy_i(_cpu_out_ready)
+        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+        .com_inp_data(com_inp_data), .com_inp_valid(com_inp_valid), .com_inp_ready(com_inp_ready),
+        .ext_out_data(ext_out_data), .ext_out_valid(ext_out_valid), .ext_out_ready(ext_out_ready),
+        .dsp_out_data(dsp_out_data), .dsp_out_valid(dsp_out_valid), .dsp_out_ready(dsp_out_ready),
+        .cpu_out_data(_cpu_out_data), .cpu_out_valid(_cpu_out_valid), .cpu_out_ready(_cpu_out_ready)
     );
 
     fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) cpu_out_fifo (
@@ -459,28 +247,13 @@ module packet_router
     );
 
     ////////////////////////////////////////////////////////////////////
-    // DSP input framer
-    ////////////////////////////////////////////////////////////////////
-    dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(0)) dsp0_framer36(
-        .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
-        .inp_data(dsp0_inp_data), .inp_valid(dsp0_inp_valid), .inp_ready(dsp0_inp_ready),
-        .out_data(dsp0_frm_data), .out_valid(dsp0_frm_valid), .out_ready(dsp0_frm_ready)
-    );
-
-    dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(2)) dsp1_framer36(
-        .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
-        .inp_data(dsp1_inp_data), .inp_valid(dsp1_inp_valid), .inp_ready(dsp1_inp_ready),
-        .out_data(dsp1_frm_data), .out_valid(dsp1_frm_valid), .out_ready(dsp1_frm_ready)
-    );
-
-    ////////////////////////////////////////////////////////////////////
     // UDP TX Protocol machine
     ////////////////////////////////////////////////////////////////////
 
     //dummy signals to connect the components below
-    wire [18:0] _udp_r2s_data, _udp_s2p_data, _udp_p2s_data, _udp_s2r_data;
-    wire _udp_r2s_valid, _udp_s2p_valid, _udp_p2s_valid, _udp_s2r_valid;
-    wire _udp_r2s_ready, _udp_s2p_ready, _udp_p2s_ready, _udp_s2r_ready;
+    wire [18:0] _udp_r2s_data, _udp_s2r_data;
+    wire _udp_r2s_valid, _udp_s2r_valid;
+    wire _udp_r2s_ready, _udp_s2r_ready;
 
     wire [35:0] _com_out_data;
     wire _com_out_valid, _com_out_ready;
@@ -490,23 +263,11 @@ module packet_router
       .f36_datain(udp_out_data),   .f36_src_rdy_i(udp_out_valid),  .f36_dst_rdy_o(udp_out_ready),
       .f19_dataout(_udp_r2s_data), .f19_src_rdy_o(_udp_r2s_valid), .f19_dst_rdy_i(_udp_r2s_ready) );
 
-    fifo_short #(.WIDTH(19)) udp_shortfifo19_inp
-     (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-      .datain(_udp_r2s_data),  .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready),
-      .dataout(_udp_s2p_data), .src_rdy_o(_udp_s2p_valid), .dst_rdy_i(_udp_s2p_ready),
-      .space(), .occupied() );
-
     prot_eng_tx #(.BASE(UDP_BASE)) udp_prot_eng_tx
      (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .datain(_udp_s2p_data),  .src_rdy_i(_udp_s2p_valid), .dst_rdy_o(_udp_s2p_ready),
-      .dataout(_udp_p2s_data), .src_rdy_o(_udp_p2s_valid), .dst_rdy_i(_udp_p2s_ready) );
-
-    fifo_short #(.WIDTH(19)) udp_shortfifo19_out
-     (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-      .datain(_udp_p2s_data),  .src_rdy_i(_udp_p2s_valid), .dst_rdy_o(_udp_p2s_ready),
-      .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready),
-      .space(), .occupied() );
+      .datain(_udp_r2s_data),  .src_rdy_i(_udp_r2s_valid), .dst_rdy_o(_udp_r2s_ready),
+      .dataout(_udp_s2r_data), .src_rdy_o(_udp_s2r_valid), .dst_rdy_i(_udp_s2r_ready) );
 
     fifo19_to_fifo36 udp_fifo19_to_fifo36
      (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
@@ -525,8 +286,10 @@ module packet_router
     ////////////////////////////////////////////////////////////////////
 
     assign debug = {
-        //inputs to the router (8)
+        //inputs to the router (12)
         dsp0_inp_ready, dsp0_inp_valid,
+        dsp1_inp_ready, dsp1_inp_valid,
+        err_inp_ready, err_inp_valid,
         ser_inp_ready, ser_inp_valid,
         eth_inp_ready, eth_inp_valid,
         cpu_inp_ready, cpu_inp_valid,
@@ -537,17 +300,13 @@ module packet_router
         eth_out_ready, eth_out_valid,
         cpu_out_ready, cpu_out_valid,
 
-        //inspector interfaces (8)
-        com_insp_out_dsp_ready, com_insp_out_dsp_valid,
-        com_insp_out_ext_ready, com_insp_out_ext_valid,
-        com_insp_out_cpu_ready, com_insp_out_cpu_valid,
-        com_insp_out_bof_ready, com_insp_out_bof_valid,
-
         //other interfaces (8)
         ext_inp_ready, ext_inp_valid,
         com_out_ready, com_out_valid,
         ext_out_ready, ext_out_valid,
-        com_inp_ready, com_inp_valid
+        com_inp_ready, com_inp_valid,
+
+        4'b0
     };
 
 endmodule // packet_router
diff --git a/fpga/usrp2/control_lib/newfifo/packet_tb.v b/fpga/usrp2/fifo/packet_tb.v
index 3c423d2ba..3c423d2ba 100644
--- a/fpga/usrp2/control_lib/newfifo/packet_tb.v
+++ b/fpga/usrp2/fifo/packet_tb.v
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier.v b/fpga/usrp2/fifo/packet_verifier.v
index b49ad1bbb..21a4c136e 100644
--- a/fpga/usrp2/control_lib/newfifo/packet_verifier.v
+++ b/fpga/usrp2/fifo/packet_verifier.v
@@ -18,7 +18,7 @@ module packet_verifier
    reg [31:0] 	     length;
    wire 	     first_byte, last_byte;
    reg 		     second_byte, last_byte_d1;
-
+   wire 	     match_crc;
    wire 	     calc_crc = src_rdy_i & dst_rdy_o;
    
    crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i), 
diff --git a/fpga/usrp2/control_lib/newfifo/packet_verifier32.v b/fpga/usrp2/fifo/packet_verifier32.v
index 06a13d242..06a13d242 100644
--- a/fpga/usrp2/control_lib/newfifo/packet_verifier32.v
+++ b/fpga/usrp2/fifo/packet_verifier32.v
diff --git a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
index cf8b6e861..9a8e37ce9 100644
--- a/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
+++ b/fpga/usrp2/gpmc/fifo_to_gpmc_async.v
@@ -1,9 +1,4 @@
 
-// Assumes an asynchronous GPMC cycle
-//   If a packet bigger or smaller than we are told is sent, behavior is undefined.
-//   If dst_rdy_i is low when we get data, behavior is undefined and we signal bus error.
-//   If there is a bus error, we should be reset
-
 module fifo_to_gpmc_async
   (input clk, input reset, input clear,
    input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v
index 23bad56ae..02bf45b8a 100644
--- a/fpga/usrp2/gpmc/gpmc_async.v
+++ b/fpga/usrp2/gpmc/gpmc_async.v
@@ -1,7 +1,9 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module gpmc_async
-  #(parameter TXFIFOSIZE = 11, parameter RXFIFOSIZE = 11)
+  #(parameter TXFIFOSIZE = 11, 
+    parameter RXFIFOSIZE = 11,
+    parameter BUSDEBUG = 1)
    (// GPMC signals
     input arst,
     input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
@@ -21,7 +23,9 @@ module gpmc_async
     input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
     
     input [15:0] tx_frame_len, output [15:0] rx_frame_len,
-    
+
+    output tx_underrun, output rx_overrun,
+    input [7:0] test_rate, input [3:0] test_ctrl,
     output [31:0] debug
     );
 
@@ -49,8 +53,8 @@ module gpmc_async
    wire [17:0] 	  tx18_data, tx18b_data;
    wire 	  tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
    wire [15:0] 	  tx_fifo_space;
-   wire [35:0] 	  tx36_data;
-   wire 	  tx36_src_rdy, tx36_dst_rdy;
+   wire [35:0] 	  tx36_data, tx_data;
+   wire 	  tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy;
    
    gpmc_to_fifo_async gpmc_to_fifo_async
      (.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
@@ -70,9 +74,9 @@ module gpmc_async
       .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
    
    fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
       .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
-      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+      .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy));
 
    // ////////////////////////////////////////////
    // RX Data Path
@@ -80,13 +84,13 @@ module gpmc_async
    wire [17:0] 	  rx18_data, rx18b_data;
    wire 	  rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy;
    wire [15:0] 	  rx_fifo_space;
-   wire [35:0] 	  rx36_data;
-   wire 	  rx36_src_rdy, rx36_dst_rdy;
+   wire [35:0] 	  rx36_data, rx_data;
+   wire 	  rx36_src_rdy, rx36_dst_rdy, rx_src_rdy, rx_dst_rdy;
    wire 	  dummy;
    
    fifo_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_fifo36
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
-      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
       .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
 
    fifo36_to_fifo19 #(.LE(1)) f36_to_f19   // Little endian because ARM is LE
@@ -125,6 +129,100 @@ module gpmc_async
       .wb_sel_o(wb_sel_o), .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o),
       .wb_ack_i(wb_ack_i) );
    
-      assign debug = pkt_count;
+//      assign debug = pkt_count;
+
+   // ////////////////////////////////////////////
+   // Test support, traffic generator, loopback, etc.
+
+   // RX side muxes test data into the same stream
+   wire [35:0] 	timedrx_data, loopbackrx_data, testrx_data;
+   wire [35:0] 	timedtx_data, loopbacktx_data, testtx_data;
+   wire 	timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy,
+		testrx_src_rdy, testrx_dst_rdy;
+   wire 	timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy,
+		testtx_src_rdy, testtx_dst_rdy;
+   wire 	timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int;
+
+   wire [31:0] 	total, crc_err, seq_err, len_err;
+   wire 	sel_testtx = test_ctrl[0];
+   wire 	sel_loopbacktx = test_ctrl[1];
+   wire 	pkt_src_enable = test_ctrl[2];
+   wire 	pkt_sink_enable = test_ctrl[3];
+   
+   fifo36_mux rx_test_mux_lvl_1
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy),
+      .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy),
+      .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy));
+   
+   fifo36_mux rx_test_mux_lvl_2
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy),
+      .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o),
+      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+   
+   fifo_short #(.WIDTH(36)) loopback_fifo
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx),
+      .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy),
+      .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy));
    
+   // Crossbar used as a demux for switching TX stream to main DSP or to test logic
+   crossbar36 tx_crossbar_lvl_1
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .cross(sel_testtx),
+      .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy),
+      .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
+      .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i),
+      .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) );
+   
+   crossbar36 tx_crossbar_lvl_2
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .cross(sel_loopbacktx),
+      .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy),
+      .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
+      .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy),
+      .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) );
+   
+   // Fixed rate TX traffic consumer
+   fifo_pacer tx_pacer
+     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable),
+      .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy),
+      .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int),
+      .underrun(tx_underrun), .overrun());
+
+   packet_verifier32 pktver32
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+      .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int),
+      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
+
+   // Fixed rate RX traffic generator
+   packet_generator32 pktgen32
+     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .header({len_err,seq_err,crc_err,total}),
+      .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int));
+
+   fifo_pacer rx_pacer
+     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable),
+      .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int),
+      .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy),
+      .underrun(), .overrun(rx_overrun));
+
+   // FIXME -- hook up crossbar controls
+   // // FIXME -- collect error stats
+   // FIXME -- set rates and enables on pacers
+   // FIXME -- make sure packet completes before we shutoff
+   // FIXME -- handle overrun and underrun
+
+wire [0:17] dummy18;
+
+assign debug = {8'd0,
+		test_rate,
+		pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
+		timedrx_src_rdy, timedrx_dst_rdy,
+		testrx_src_rdy, testrx_dst_rdy,
+		rx_src_rdy, rx_dst_rdy,
+		rx36_src_rdy, rx36_dst_rdy,
+		rx18_src_rdy, rx18_dst_rdy,
+		rx18b_src_rdy, rx18b_dst_rdy};
+
 endmodule // gpmc_async
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
index efcf89276..b783729d5 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper.v
@@ -1,7 +1,7 @@
 
 module simple_gemac_wrapper
   #(parameter RXFIFOSIZE=9,
-    parameter TXFIFOSIZE=6)
+    parameter TXFIFOSIZE=9)
    (input clk125, input reset,
     // GMII
     output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
@@ -30,7 +30,9 @@ module simple_gemac_wrapper
    wire 	  pause_req;
    wire 	  pause_request_en, pause_respect_en;
    wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
-   
+
+   wire [31:0] 	  debug_state;
+      
    wire 	  tx_reset, rx_reset;
    reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
    reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
@@ -49,7 +51,8 @@ module simple_gemac_wrapper
       .rx_clk(rx_clk), .rx_data(rx_data),
       .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
       .tx_clk(tx_clk), .tx_data(tx_data), 
-      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
+      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
+      .debug(debug_state)
       );
    
    simple_gemac_wb simple_gemac_wb
@@ -65,14 +68,12 @@ module simple_gemac_wrapper
 
    // RX FIFO Chain
    wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire [7:0] 	  rx_ll_data;
    
-   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
-   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
-   
-   wire [7:0] 	  rx_ll_data, rx_ll_data2;
-   
-   wire [35:0] 	  rx_f36_data_int1;
-   wire 	  rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+   wire [18:0] 	  rx_f19_data_int1, rx_f19_data_int2;
+   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2;
+   wire [35:0] 	  rx_f36_data_int;
+   wire 	  rx_f36_src_rdy_int, rx_f36_dst_rdy_int;
    
    rxmac_to_ll8 rx_adapt
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
@@ -80,86 +81,69 @@ module simple_gemac_wrapper
       .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
       .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
 
-   ll8_shortfifo rx_sfifo
+   ll8_to_fifo19 ll8_to_fifo19
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
-      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
-      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy),
+      .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
 
-   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
-   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
-   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
-   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
-   
-   ll8_to_fifo36 ll8_to_fifo36
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1),
+      .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) );
+
+   fifo19_to_fifo36 rx_fifo19_to_fifo36
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
-      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
-      .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
+      .f19_datain(rx_f19_data_int2),  .f19_src_rdy_i(rx_f19_src_rdy_int2), .f19_dst_rdy_o(rx_f19_dst_rdy_int2),
+      .f36_dataout(rx_f36_data_int), .f36_src_rdy_o(rx_f36_src_rdy_int), .f36_dst_rdy_i(rx_f36_dst_rdy_int) );
 
    fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
-     (.wclk(rx_clk), .datain(rx_f36_data_int1), 
-      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
+     (.wclk(rx_clk), .datain(rx_f36_data_int), 
+      .src_rdy_i(rx_f36_src_rdy_int), .dst_rdy_o(rx_f36_dst_rdy_int), .space(rx_fifo_space),
       .rclk(sys_clk), .dataout(rx_f36_data), 
       .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
    
    // TX FIFO Chain
    wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
-   wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
-   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
-   wire [7:0] 	  tx_ll_data, tx_ll_data2;
+   wire [7:0] 	  tx_ll_data;
    wire [35:0] 	  tx_f36_data_int1;
    wire 	  tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
    
    fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
-     (.wclk(sys_clk), .datain(tx_f36_data), 
-      .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
-      .rclk(tx_clk), .dataout(tx_f36_data_int1), 
-      .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset));
+     (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
+      .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), 
+      .arst(reset));
    
    fifo36_to_ll8 fifo36_to_ll8
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1),
-      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
-      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
+      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
+      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy));
 
-   assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
-   assign tx_ll_eof2 	    = ~tx_ll_eof2_n;
-   assign tx_ll_src_rdy2    = ~tx_ll_src_rdy2_n;
-   assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
-   
-   ll8_shortfifo tx_sfifo
-     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
-      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
-      .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
-      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
-      .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
-   
    ll8_to_txmac ll8_to_txmac
      (.clk(tx_clk), .reset(tx_reset), .clear(clear),
       .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
       .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
       .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
 
+   // Flow Control
    flow_ctrl_rx flow_ctrl_rx
      (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
       .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
       .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
    
    wire [31:0] 	  debug_tx, debug_rx;
-   
+
    assign debug_tx  = { { tx_ll_data },
-			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
-			  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
+			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 4'b0 },
 			{ tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]},
 			{ tx_data} };
    assign debug_rx  = { { rx_ll_data },
-			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
-			  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
-			{ rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]},
+			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 },
+			{ rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int, rx_f36_dst_rdy_int, rx_f36_data_int[34:32]},
 			{ rx_data} };
 
    assign debug  = debug_rx;
    
 endmodule // simple_gemac_wrapper
+
diff --git a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
index 6cdbd1a59..c155b7d41 100644
--- a/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
+++ b/fpga/usrp2/simple_gemac/simple_gemac_wrapper19.v
@@ -68,14 +68,10 @@ module simple_gemac_wrapper19
 
    // RX FIFO Chain
    wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   wire [7:0] 	  rx_ll_data;
    
-   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
-   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
-   
-   wire [7:0] 	  rx_ll_data, rx_ll_data2;
-   
-   wire [18:0] 	  rx_f19_data_int1;
-   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1;
+   wire [18:0] 	  rx_f19_data_int1, rx_f19_data_int2;
+   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2;
    
    rxmac_to_ll8 rx_adapt
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
@@ -83,28 +79,21 @@ module simple_gemac_wrapper19
       .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
       .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
 
-   ll8_shortfifo rx_sfifo
-     (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
-      .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
-      .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
-      .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
-
-   assign rx_ll_dst_rdy2  = ~rx_ll_dst_rdy2_n;
-   assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2;
-   assign rx_ll_sof2_n 	  = ~rx_ll_sof2;
-   assign rx_ll_eof2_n 	  = ~rx_ll_eof2;
-   
    ll8_to_fifo19 ll8_to_fifo19
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n),
-      .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
+      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
+      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy),
       .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
 
+   fifo19_rxrealign fifo19_rxrealign
+     (.clk(rx_clk), .reset(rx_reset), .clear(0),
+      .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1),
+      .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) );
+
    //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
    fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
-     (.wclk(rx_clk), .datain(rx_f19_data_int1), 
-      .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .space(rx_fifo_space),
+     (.wclk(rx_clk), .datain(rx_f19_data_int2), 
+      .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space),
       .rclk(sys_clk), .dataout(rx_f19_data), 
       .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), .arst(reset));
    
@@ -160,8 +149,7 @@ module simple_gemac_wrapper19
 			{ tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]},
 			{ tx_data} };
    assign debug_rx  = { { rx_f19_src_rdy, rx_f19_dst_rdy, debug_state[5:0] },
-			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 
-			  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 },
+			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 },
 			{ rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]},
 			{ rx_data} };
 
diff --git a/fpga/usrp2/top/safe_u2plus/Makefile b/fpga/usrp2/top/safe_u2plus/Makefile
index 62a02ff40..b72241050 100644
--- a/fpga/usrp2/top/safe_u2plus/Makefile
+++ b/fpga/usrp2/top/safe_u2plus/Makefile
@@ -117,7 +117,6 @@ coregen/fifo_xlnx_512x36_2clk.v \
 coregen/fifo_xlnx_512x36_2clk.xco \
 coregen/fifo_xlnx_64x36_2clk.v \
 coregen/fifo_xlnx_64x36_2clk.xco \
-extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
 opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v
index 7d5924bea..a5a477202 100644
--- a/fpga/usrp2/top/u1e/u1e_core.v
+++ b/fpga/usrp2/top/u1e/u1e_core.v
@@ -1,9 +1,5 @@
 
 
-//`define LOOPBACK 1
-//`define TIMED 1
-`define DSP 1
-
 module u1e_core
   (input clk_fpga, input rst_fpga,
    output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
@@ -48,13 +44,18 @@ module u1e_core
    wire 	pps_int;
    wire [63:0] 	vita_time, vita_time_pps;
    reg [15:0] 	reg_leds, reg_cgen_ctrl, reg_test, xfer_rate;
+   wire [7:0] 	test_rate;
+   wire [3:0] 	test_ctrl;
    
    wire [7:0] 	set_addr;
    wire [31:0] 	set_data;
    wire 	set_stb;
 
    wire [31:0] 	debug_vt;
-
+   wire 	rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
+   assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp;
+   assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
+   
    setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(global_reset));
@@ -79,7 +80,6 @@ module u1e_core
 		 tx_err_src_rdy, tx_err_dst_rdy;
    reg [15:0] 	 tx_frame_len;
    wire [15:0] 	 rx_frame_len;
-   wire [7:0] 	 rate;
 
    wire 	 bus_error;
    wire 	 clear_tx, clear_rx;
@@ -111,62 +111,15 @@ module u1e_core
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 	 
 	 .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+	 .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
+
+	 .test_rate(test_rate), .test_ctrl(test_ctrl),
 	 .debug(debug_gpmc));
 
    wire 	 rx_sof = rx_data[32];
    wire 	 rx_eof = rx_data[33];
    wire 	 rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
    
-`ifdef LOOPBACK
-   wire [7:0] 	 WHOAMI = 1;
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
-      .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
-      .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-
-   assign tx_underrun = 0;
-   assign rx_overrun = 0;
-
-   wire 	 run_tx, run_rx, strobe_tx, strobe_rx;
-`endif // LOOPBACK
-
-`ifdef TIMED
-   wire [7:0] 	 WHOAMI = 2;
-   
-   // TX side
-   wire 	 tx_enable;
-   
-   fifo_pacer tx_pacer
-     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(tx_enable),
-      .src1_rdy_i(tx_src_rdy), .dst1_rdy_o(tx_dst_rdy),
-      .src2_rdy_o(tx_src_rdy_int), .dst2_rdy_i(tx_dst_rdy_int),
-      .underrun(tx_underrun), .overrun());
-   
-   packet_verifier32 pktver32
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_tx),
-      .data_i(tx_data), .src_rdy_i(tx_src_rdy_int), .dst_rdy_o(tx_dst_rdy_int),
-      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
-   // RX side
-   wire 	 rx_enable;
-
-   packet_generator32 pktgen32
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int));
-
-   fifo_pacer rx_pacer
-     (.clk(wb_clk), .reset(wb_rst), .rate(rate), .enable(rx_enable),
-      .src1_rdy_i(rx_src_rdy_int), .dst1_rdy_o(rx_dst_rdy_int),
-      .src2_rdy_o(rx_src_rdy), .dst2_rdy_i(rx_dst_rdy),
-      .underrun(), .overrun(rx_overrun));
-
-   wire 	 run_tx, run_rx, strobe_tx, strobe_rx;
-`endif //  `ifdef TIMED
-
-`ifdef DSP
-   wire [7:0] 	 WHOAMI = 0;
-   
    wire [31:0] 	 debug_rx_dsp, vrc_debug, vrf_debug;
    
    // /////////////////////////////////////////////////////////////////////////
@@ -189,7 +142,7 @@ module u1e_core
    vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
      (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .vita_time(vita_time), .overrun(rx_overrun),
+      .vita_time(vita_time), .overrun(rx_overrun_dsp),
       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
       .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy),
       .debug_rx(vrc_debug));
@@ -225,29 +178,12 @@ module u1e_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .dac_a(tx_i_int),.dac_b(tx_q_int),
-      .underrun(underrun), .run(run_tx),
+      .underrun(tx_underrun_dsp), .run(run_tx),
       .debug(debug_vt));
    
    assign tx_i = tx_i_int[15:2];
    assign tx_q = tx_q_int[15:2];
    
-`else // !`ifdef DSP
-   // Dummy DSP signal generator for test purposes
-   wire [23:0] 	 tx_i_int, tx_q_int;
-   wire [23:0] 	 freq = {reg_test,8'd0};
-   reg [23:0] 	 phase;
-   
-   always @(posedge wb_clk)
-     phase <= phase + freq;
-   
-   cordic_z24 #(.bitwidth(24)) tx_cordic
-     (.clock(wb_clk), .reset(wb_rst), .enable(1),
-      .xi(24'd2500000), .yi(24'd0), .zi(phase), .xo(tx_i_int), .yo(tx_q_int), .zo());
-
-   assign tx_i = tx_i_int[23:10];
-   assign tx_q = tx_q_int[23:10];
-`endif // !`ifdef DSP
-      
    // /////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Intercon, single master
    wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
@@ -320,7 +256,6 @@ module u1e_core
    // Slave 0, Misc LEDs, Switches, controls
    
    localparam REG_LEDS = 7'd0;         // out
-   localparam REG_SWITCHES = 7'd2;     // in
    localparam REG_CGEN_CTRL = 7'd4;    // out
    localparam REG_CGEN_ST = 7'd6;      // in
    localparam REG_TEST = 7'd8;         // out
@@ -353,20 +288,18 @@ module u1e_core
 	     xfer_rate <= s0_dat_mosi;
 	 endcase // case (s0_adr[6:0])
 
-   assign tx_enable = xfer_rate[15];
-   assign rx_enable = xfer_rate[14];
-   assign rate = xfer_rate[7:0];
+   assign test_ctrl = xfer_rate[11:8];
+   assign test_rate = xfer_rate[7:0];
    
    assign { debug_led[3:0] } = ~{run_rx,run_tx,reg_leds[1:0]};
    assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
    
    assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
-			(s0_adr[6:0] == REG_SWITCHES) ? { 16'd0 } :
 			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
 			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
 			(s0_adr[6:0] == REG_TEST) ? reg_test :
 			(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
-			(s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
+			(s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } :
 			16'hBEEF;
    
    assign s0_ack = s0_stb & s0_cyc;
@@ -475,10 +408,14 @@ module u1e_core
 
    assign debug_clk = { EM_CLK, clk_fpga };
 
+/*
    assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS5, EM_NCS4, EM_NWE, EM_NOE, rx_overrun },
 		    { tx_src_rdy, tx_src_rdy_int, tx_dst_rdy, tx_dst_rdy_int, rx_src_rdy, rx_src_rdy_int, rx_dst_rdy, rx_dst_rdy_int },
 		    { EM_D } };
 
+*/
+   assign debug = debug_gpmc;
+
    assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, 
 			   {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} };
 
diff --git a/fpga/usrp2/top/u1e_passthru/Makefile b/fpga/usrp2/top/u1e_passthru/Makefile
index d1950629b..f2d835608 100644
--- a/fpga/usrp2/top/u1e_passthru/Makefile
+++ b/fpga/usrp2/top/u1e_passthru/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
 include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
 include ../../gpmc/Makefile.srcs
 
 ##################################################
@@ -51,7 +50,7 @@ passthru.ucf
 SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
 $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
 $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \
 $(GPMC_SRCS)
 
 ##################################################
diff --git a/fpga/usrp2/top/u2_rev3/Makefile b/fpga/usrp2/top/u2_rev3/Makefile
index 05ada2476..e9b43491a 100644
--- a/fpga/usrp2/top/u2_rev3/Makefile
+++ b/fpga/usrp2/top/u2_rev3/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
 include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
 include ../../extramfifo/Makefile.srcs
 
 
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
index 10bfd5ffb..79470de9e 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core.v
@@ -152,7 +152,7 @@ module u2_core
    // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
    // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
    // localparam DSP_TX_FIFOSIZE = 9;  unused -- DSPTX uses extram fifo
-   localparam DSP_RX_FIFOSIZE = 9;
+   localparam DSP_RX_FIFOSIZE = 10;
    localparam ETH_TX_FIFOSIZE = 9;
    localparam ETH_RX_FIFOSIZE = 11;
    localparam SERDES_TX_FIFOSIZE = 9;
@@ -433,56 +433,21 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
 
-   wire [18:0] 	 rx_f19_data, tx_f19_data;
-   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
-   
-   simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+   simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), 
+			  .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19
      (.clk125(clk_to_mac),  .reset(wb_rst),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       .sys_clk(dsp_clk),
-      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
-      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+      .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+      .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
       .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
       .mdio(MDIO), .mdc(MDC),
       .debug(debug_mac));
 
-   wire [35:0] 	 rx_f36_data, tx_f36_data;
-   wire 	 rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
-
-   wire [18:0] 	 _rx_f19_data;
-   wire 	 _rx_f19_src_rdy, _rx_f19_dst_rdy;
-
-   //mac rx to eth input...
-   fifo19_rxrealign fifo19_rxrealign
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
-      .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
-
-   fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .f19_datain(_rx_f19_data),  .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
-      .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
-
-   fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
-      .dataout(wr2_dat), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-
-   //eth output to mac tx...
-   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(rd2_dat), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
-      .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
-
-   fifo36_to_fifo19 eth_out_fifo36_to_fifo19
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .f36_datain(tx_f36_data),  .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
-      .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
-
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #7
    settings_bus settings_bus
@@ -604,8 +569,7 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 0
    wire [31:0] 	 sample_rx0;
-   wire [35:0] 	 rx0_data;
-   wire 	 clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy;
+   wire 	 clear_rx0, strobe_rx0;
 
    always @(posedge dsp_clk)
      run_rx0_d1 <= run_rx0;
@@ -622,24 +586,18 @@ module u2_core
       .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
       .out(),.changed(clear_rx0));
 
-   vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0
+   vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
      (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .vita_time(vita_time), .overrun(overrun0),
       .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
-      .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy),
+      .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
       .debug() );
 
-   fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
-      .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy),
-      .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
-
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 1
    wire [31:0] 	 sample_rx1;
-   wire [35:0] 	 rx1_data;
-   wire 	 clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy;
+   wire 	 clear_rx1, strobe_rx1;
 
    always @(posedge dsp_clk)
      run_rx1_d1 <= run_rx1;
@@ -656,19 +614,14 @@ module u2_core
       .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
       .out(),.changed(clear_rx1));
 
-   vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1
+   vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
      (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .vita_time(vita_time), .overrun(overrun1),
       .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
-      .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy),
+      .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
       .debug() );
 
-   fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
-      .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
-      .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o));
-
    // ///////////////////////////////////////////////////////////////////////////////////
    // DSP TX
 
diff --git a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
index 5b7ed5a8e..334089839 100644
--- a/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
+++ b/fpga/usrp2/top/u2_rev3_2rx_iad/Makefile
@@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \
 eth/rtl/verilog/miim/eth_clockgen.v \
 eth/rtl/verilog/miim/eth_outputcontrol.v \
 eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
 opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u2_rev3_iad/Makefile b/fpga/usrp2/top/u2_rev3_iad/Makefile
index 5ae8846dd..15df9e43e 100644
--- a/fpga/usrp2/top/u2_rev3_iad/Makefile
+++ b/fpga/usrp2/top/u2_rev3_iad/Makefile
@@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \
 eth/rtl/verilog/miim/eth_clockgen.v \
 eth/rtl/verilog/miim/eth_outputcontrol.v \
 eth/rtl/verilog/miim/eth_shiftreg.v \
-extram/wb_zbt16_b.v \
 opencores/8b10b/decode_8b10b.v \
 opencores/8b10b/encode_8b10b.v \
 opencores/aemb/rtl/verilog/aeMB_bpcu.v \
diff --git a/fpga/usrp2/top/u2plus/Makefile b/fpga/usrp2/top/u2plus/Makefile
index c38bd3ec1..38400ce62 100644
--- a/fpga/usrp2/top/u2plus/Makefile
+++ b/fpga/usrp2/top/u2plus/Makefile
@@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs
 include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
 include ../../extramfifo/Makefile.srcs
 
 
diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v
index 1d568030e..ec54de73e 100644
--- a/fpga/usrp2/top/u2plus/u2plus_core.v
+++ b/fpga/usrp2/top/u2plus/u2plus_core.v
@@ -147,7 +147,7 @@ module u2plus_core
    // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
    // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
    // localparam DSP_TX_FIFOSIZE = 9;  unused -- DSPTX uses extram fifo
-   localparam DSP_RX_FIFOSIZE = 9;
+   localparam DSP_RX_FIFOSIZE = 10;
    localparam ETH_TX_FIFOSIZE = 9;
    localparam ETH_RX_FIFOSIZE = 11;
    localparam SERDES_TX_FIFOSIZE = 9;
@@ -432,56 +432,21 @@ module u2plus_core
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
 
-   wire [18:0] 	 rx_f19_data, tx_f19_data;
-   wire 	 rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy;
-   
-   simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19
+   simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), 
+			  .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19
      (.clk125(clk_to_mac),  .reset(wb_rst),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
       .sys_clk(dsp_clk),
-      .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
-      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
+      .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+      .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
       .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
       .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
       .mdio(MDIO), .mdc(MDC),
       .debug(debug_mac));
 
-   wire [35:0] 	 rx_f36_data, tx_f36_data;
-   wire 	 rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy;
-
-   wire [18:0] 	 _rx_f19_data;
-   wire 	 _rx_f19_src_rdy, _rx_f19_dst_rdy;
-
-   //mac rx to eth input...
-   fifo19_rxrealign fifo19_rxrealign
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy),
-      .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) );
-
-   fifo19_to_fifo36 eth_inp_fifo19_to_fifo36
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .f19_datain(_rx_f19_data),  .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy),
-      .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) );
-
-   fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy),
-      .dataout(wr2_dat), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o));
-
-   //eth output to mac tx...
-   fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .datain(rd2_dat), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i),
-      .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy));
-
-   fifo36_to_fifo19 eth_out_fifo36_to_fifo19
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
-      .f36_datain(tx_f36_data),  .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy),
-      .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) );
-
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #7
    settings_bus settings_bus
@@ -609,8 +574,7 @@ module u2plus_core
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 0
    wire [31:0] 	 sample_rx0;
-   wire [35:0] 	 rx0_data;
-   wire 	 clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy;
+   wire 	 clear_rx0, strobe_rx0;
 
    always @(posedge dsp_clk)
      run_rx0_d1 <= run_rx0;
@@ -627,24 +591,18 @@ module u2plus_core
       .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
       .out(),.changed(clear_rx0));
 
-   vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0
+   vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
      (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .vita_time(vita_time), .overrun(overrun0),
       .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
-      .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy),
+      .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
       .debug() );
 
-   fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
-      .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy),
-      .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
-
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 1
    wire [31:0] 	 sample_rx1;
-   wire [35:0] 	 rx1_data;
-   wire 	 clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy;
+   wire 	 clear_rx1, strobe_rx1;
 
    always @(posedge dsp_clk)
      run_rx1_d1 <= run_rx1;
@@ -661,19 +619,14 @@ module u2plus_core
       .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
       .out(),.changed(clear_rx1));
 
-   vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1
+   vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
      (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .vita_time(vita_time), .overrun(overrun1),
       .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
-      .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy),
+      .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
       .debug() );
 
-   fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
-      .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
-      .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o));
-
    // ///////////////////////////////////////////////////////////////////////////////////
    // DSP TX
 
diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v
index f5578eb15..d7498286d 100644
--- a/fpga/usrp2/vrt/vita_rx_chain.v
+++ b/fpga/usrp2/vrt/vita_rx_chain.v
@@ -1,6 +1,8 @@
 
 module vita_rx_chain
-  #(parameter BASE=0)
+  #(parameter BASE=0,
+    parameter UNIT=0,
+    parameter FIFOSIZE=10)
    (input clk, input reset, input clear,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     input [63:0] vita_time, output overrun,
@@ -9,8 +11,11 @@ module vita_rx_chain
     output [31:0] debug );
        
    wire [100:0] sample_data;
-   wire        sample_dst_rdy, sample_src_rdy;
-   wire [31:0] vrc_debug, vrf_debug;
+   wire 	sample_dst_rdy, sample_src_rdy;
+   wire [31:0] 	vrc_debug, vrf_debug;
+
+   wire [35:0] 	rx_data_int;
+   wire 	rx_src_rdy_int, rx_dst_rdy_in;
    
    vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control
      (.clk(clk), .reset(reset), .clear(clear),
@@ -24,10 +29,14 @@ module vita_rx_chain
      (.clk(clk), .reset(reset), .clear(clear),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .sample_fifo_i(sample_data), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy),
-      .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i),
-      .fifo_occupied(), .fifo_full(), .fifo_empty(),
+      .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int),
       .debug_rx(vrf_debug) );
 
+   dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36
+     (.clk(clk), .reset(reset), .clear(clear),
+      .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int),
+      .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) );
+
    assign debug = vrc_debug; //  | vrf_debug;
    
 endmodule // vita_rx_chain
diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v
index 0769f3a24..4c0cef50d 100644
--- a/fpga/usrp2/vrt/vita_rx_control.v
+++ b/fpga/usrp2/vrt/vita_rx_control.v
@@ -196,4 +196,4 @@ module vita_rx_control
 		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl },
 		       { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
    
-endmodule // rx_control
+endmodule // vita_rx_control
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
index bce8fe334..04b636778 100644
--- a/fpga/usrp2/vrt/vita_rx_framer.v
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -15,11 +15,6 @@ module vita_rx_framer
     input sample_fifo_src_rdy_i,
     output sample_fifo_dst_rdy_o,
     
-    // FIFO Levels
-    output [15:0] fifo_occupied,
-    output fifo_full,
-    output fifo_empty,
-    
     output [31:0] debug_rx
     );
 
@@ -200,8 +195,8 @@ module vita_rx_framer
      (.clk(clk), .reset(reset), .clear(clear),
       .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy),
       .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
-      .space(),.occupied(fifo_occupied[4:0]) );
-   assign fifo_occupied[15:5] = 0;
+      .space(),.occupied() );
+
    assign data_o[35:34] = 2'b00;  // Always write full lines
    assign sample_fifo_dst_rdy_o  = pkt_fifo_rdy & 
 				   ( ((vita_state==VITA_PAYLOAD) & 
@@ -211,4 +206,4 @@ module vita_rx_framer
    
    assign debug_rx  = vita_state;
    
-endmodule // rx_control
+endmodule // vita_rx_framer