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authorJosh Blum <josh@joshknows.com>2011-07-19 14:18:58 -0700
committerJosh Blum <josh@joshknows.com>2011-07-19 14:18:58 -0700
commit07c2e795b2d3fbf77d548e902c558d810c76156d (patch)
treea5a5f8536025d2ec97d697c9f528f07902aedefe /fpga/usrp2
parent64382c4c8626e429f91865ab27c9e0a69da5edf3 (diff)
downloaduhd-07c2e795b2d3fbf77d548e902c558d810c76156d.tar.gz
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fpga: squashed new_work fpga changes onto uhd next
Diffstat (limited to 'fpga/usrp2')
-rw-r--r--fpga/usrp2/control_lib/atr_controller.v7
-rw-r--r--fpga/usrp2/control_lib/atr_controller16.v7
-rw-r--r--fpga/usrp2/coregen/Makefile.srcs2
-rw-r--r--fpga/usrp2/coregen/coregen.cgp4
-rw-r--r--fpga/usrp2/coregen/fifo_generator_ug175.pdfbin1069823 -> 2895895 bytes
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.ngc3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.v3819
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.veo47
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.xco82
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.lso3
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt106
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_flist.txt8
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_readme.txt38
-rw-r--r--fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_xmdf.tcl68
-rw-r--r--fpga/usrp2/fifo/fifo_2clock.v5
-rw-r--r--fpga/usrp2/fifo/packet_dispatcher36_x3.v46
-rw-r--r--fpga/usrp2/gpmc/Makefile.srcs2
-rw-r--r--fpga/usrp2/gpmc/fifo_watcher.v7
-rw-r--r--fpga/usrp2/gpmc/gpmc_async.v62
-rw-r--r--fpga/usrp2/gpmc/new_read.v62
-rw-r--r--fpga/usrp2/gpmc/new_write.v82
-rw-r--r--fpga/usrp2/sdr_lib/dsp_core_tx.v15
-rw-r--r--fpga/usrp2/sdr_lib/small_hb_dec.v10
-rw-r--r--fpga/usrp2/top/B100/Makefile1
-rw-r--r--fpga/usrp2/top/E1x0/Makefile1
-rw-r--r--fpga/usrp2/top/E1x0/u1e.v4
-rw-r--r--fpga/usrp2/top/E1x0/u1e_core.v4
-rw-r--r--fpga/usrp2/top/Makefile.common5
-rw-r--r--fpga/usrp2/top/N2x0/Makefile.N200R31
-rw-r--r--fpga/usrp2/top/N2x0/Makefile.N200R41
-rw-r--r--fpga/usrp2/top/N2x0/Makefile.N210R31
-rw-r--r--fpga/usrp2/top/N2x0/Makefile.N210R41
-rw-r--r--fpga/usrp2/top/USRP2/Makefile1
-rwxr-xr-xfpga/usrp2/top/python/check_timing.py30
34 files changed, 150 insertions, 4385 deletions
diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v
index 2cef8ba2b..ee8b260c5 100644
--- a/fpga/usrp2/control_lib/atr_controller.v
+++ b/fpga/usrp2/control_lib/atr_controller.v
@@ -44,8 +44,11 @@ module atr_controller
atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
end // if (we_i & stb_i & cyc_i)
- always @(posedge clk_i)
- dat_o <= atr_ram[adr_i[5:2]];
+ // Removing readback allows ram to be synthesized as LUTs instead of regs
+ //always @(posedge clk_i)
+ // dat_o <= atr_ram[adr_i[5:2]];
+ always
+ dat_o <= 32'd0;
always @(posedge clk_i)
ack_o <= stb_i & cyc_i & ~ack_o;
diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v
index ff4f634c7..727f8c630 100644
--- a/fpga/usrp2/control_lib/atr_controller16.v
+++ b/fpga/usrp2/control_lib/atr_controller16.v
@@ -47,8 +47,11 @@ module atr_controller16
atr_ram[adr_i[5:2]][7:0] <= dat_i[7:0];
end // if (we_i & stb_i & cyc_i)
- always @(posedge clk_i)
- dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+ // Removing readback allows ram to be synthesized as LUTs instead of regs
+ //always @(posedge clk_i)
+ // dat_o <= adr_i[1] ? atr_ram[adr_i[5:2]][31:16] : atr_ram[adr_i[5:2]][15:0];
+ always
+ dat_o <= 16'd0;
always @(posedge clk_i)
ack_o <= stb_i & cyc_i & ~ack_o;
diff --git a/fpga/usrp2/coregen/Makefile.srcs b/fpga/usrp2/coregen/Makefile.srcs
index 5b2bc665a..a3a5d826d 100644
--- a/fpga/usrp2/coregen/Makefile.srcs
+++ b/fpga/usrp2/coregen/Makefile.srcs
@@ -24,6 +24,4 @@ fifo_xlnx_512x36_2clk_18to36.v \
fifo_xlnx_512x36_2clk_18to36.xco \
fifo_xlnx_512x36_2clk_prog_full.v \
fifo_xlnx_512x36_2clk_prog_full.xco \
-fifo_xlnx_1Kx18_2clk.v \
-fifo_xlnx_1Kx18_2clk.xco \
))
diff --git a/fpga/usrp2/coregen/coregen.cgp b/fpga/usrp2/coregen/coregen.cgp
index 01d31bf5b..dd85a7f50 100644
--- a/fpga/usrp2/coregen/coregen.cgp
+++ b/fpga/usrp2/coregen/coregen.cgp
@@ -1,4 +1,5 @@
-# Date: Fri Jun 10 23:12:37 2011
+# Date: Fri Oct 15 07:50:19 2010
+
SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
@@ -18,3 +19,4 @@ SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = /tmp/
+# CRC: 983b9b45
diff --git a/fpga/usrp2/coregen/fifo_generator_ug175.pdf b/fpga/usrp2/coregen/fifo_generator_ug175.pdf
index 2c3e3c200..5fba6029c 100644
--- a/fpga/usrp2/coregen/fifo_generator_ug175.pdf
+++ b/fpga/usrp2/coregen/fifo_generator_ug175.pdf
Binary files differ
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.ngc b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.ngc
deleted file mode 100644
index dc9519357..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.4e
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\ No newline at end of file
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.v b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.v
deleted file mode 100644
index 4737fb1bf..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.v
+++ /dev/null
@@ -1,3819 +0,0 @@
-////////////////////////////////////////////////////////////////////////////////
-// Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
-////////////////////////////////////////////////////////////////////////////////
-// ____ ____
-// / /\/ /
-// /___/ \ / Vendor: Xilinx
-// \ \ \/ Version: K.39
-// \ \ Application: netgen
-// / / Filename: fifo_xlnx_1Kx18_2clk.v
-// /___/ /\ Timestamp: Fri Jun 10 16:12:12 2011
-// \ \ / \
-// \___\/\___\
-//
-// Command : -intstyle ise -w -sim -ofmt verilog /tmp/_cg/fifo_xlnx_1Kx18_2clk.ngc /tmp/_cg/fifo_xlnx_1Kx18_2clk.v
-// Device : 3s2000fg456-5
-// Input file : /tmp/_cg/fifo_xlnx_1Kx18_2clk.ngc
-// Output file : /tmp/_cg/fifo_xlnx_1Kx18_2clk.v
-// # of Modules : 1
-// Design Name : fifo_xlnx_1Kx18_2clk
-// Xilinx : /opt/Xilinx/10.1/ISE
-//
-// Purpose:
-// This verilog netlist is a verification model and uses simulation
-// primitives which may not represent the true implementation of the
-// device, however the netlist is functionally correct and should not
-// be modified. This file cannot be synthesized and should only be used
-// with supported simulation tools.
-//
-// Reference:
-// Development System Reference Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
-//
-////////////////////////////////////////////////////////////////////////////////
-
-`timescale 1 ns/1 ps
-
-module fifo_xlnx_1Kx18_2clk (
- rd_en, wr_en, full, empty, wr_clk, rst, rd_clk, wr_data_count, rd_data_count, dout, din
-);
- input rd_en;
- input wr_en;
- output full;
- output empty;
- input wr_clk;
- input rst;
- input rd_clk;
- output [10 : 0] wr_data_count;
- output [10 : 0] rd_data_count;
- output [17 : 0] dout;
- input [17 : 0] din;
-
- // synthesis translate_off
-
- wire \BU2/U0/grf.rf/gl0.rd/ram_valid_fwft ;
- wire \BU2/N39 ;
- wire \BU2/N31 ;
- wire \BU2/N37 ;
- wire \BU2/N27 ;
- wire \BU2/N25 ;
- wire \BU2/N21 ;
- wire \BU2/N19 ;
- wire \BU2/N17 ;
- wire \BU2/N11 ;
- wire \BU2/N13 ;
- wire \BU2/N36 ;
- wire \BU2/N381 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4_470 ;
- wire \BU2/N6 ;
- wire \BU2/N7 ;
- wire \BU2/N35 ;
- wire \BU2/N41 ;
- wire \BU2/N2 ;
- wire \BU2/N40 ;
- wire \BU2/N30 ;
- wire \BU2/N4 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ;
- wire \BU2/N38 ;
- wire \BU2/N33 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ;
- wire \BU2/N351 ;
- wire \BU2/U0/grf.rf/mem/tmp_ram_rd_en ;
- wire \BU2/U0/grf.rf/ram_regout_en ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt_408 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count7 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count5 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count6 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count8 ;
- wire \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count9 ;
- wire \BU2/U0/grf.rf/ram_wr_en ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_385 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt_361 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count7 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count5 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count6 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count8 ;
- wire \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count9 ;
- wire \BU2/U0/grf.rf/ram_rd_en ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0008 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0007 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0006 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0005 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0004 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0008 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0007 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0006 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0005 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0004 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0008 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0007 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0005 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0004 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0008 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0007 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0005 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0004 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ;
- wire \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp1 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/comp1 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/comp0 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ;
- wire \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[9] ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 ;
- wire \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 ;
- wire \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_comb ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_comb ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_70 ;
- wire \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_68 ;
- wire \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 ;
- wire \BU2/N1 ;
- wire NLW_VCC_P_UNCONNECTED;
- wire NLW_GND_G_UNCONNECTED;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<15>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<14>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<13>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<12>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<11>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<10>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<9>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<8>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<7>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<6>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<5>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<4>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<3>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<2>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<1>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<0>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<1>_UNCONNECTED ;
- wire \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<0>_UNCONNECTED ;
- wire [17 : 0] din_2;
- wire [17 : 0] dout_3;
- wire [10 : 0] rd_data_count_4;
- wire [10 : 0] wr_data_count_5;
- wire [17 : 0] \BU2/U0/grf.rf/mem/dout_mem ;
- wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 ;
- wire [8 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy ;
- wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count ;
- wire [8 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy ;
- wire [9 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 ;
- wire [3 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 ;
- wire [3 : 0] \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 ;
- wire [3 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet ;
- wire [4 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 ;
- wire [3 : 0] \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet ;
- wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin ;
- wire [9 : 0] \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 ;
- wire [8 : 0] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy ;
- wire [9 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut ;
- wire [9 : 0] \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 ;
- wire [9 : 0] \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin ;
- wire [8 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy ;
- wire [1 : 1] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy ;
- wire [0 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/diff_wr_rd_tmp ;
- wire [9 : 1] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 ;
- wire [0 : 0] \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/diff_wr_rd_tmp ;
- wire [10 : 0] \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 ;
- wire [1 : 0] \BU2/U0/grf.rf/rstblk/wr_rst_reg ;
- wire [2 : 0] \BU2/U0/grf.rf/rstblk/rd_rst_reg ;
- wire [0 : 0] \BU2/data_count ;
- assign
- wr_data_count[10] = wr_data_count_5[10],
- wr_data_count[9] = wr_data_count_5[9],
- wr_data_count[8] = wr_data_count_5[8],
- wr_data_count[7] = wr_data_count_5[7],
- wr_data_count[6] = wr_data_count_5[6],
- wr_data_count[5] = wr_data_count_5[5],
- wr_data_count[4] = wr_data_count_5[4],
- wr_data_count[3] = wr_data_count_5[3],
- wr_data_count[2] = wr_data_count_5[2],
- wr_data_count[1] = wr_data_count_5[1],
- wr_data_count[0] = wr_data_count_5[0],
- rd_data_count[10] = rd_data_count_4[10],
- rd_data_count[9] = rd_data_count_4[9],
- rd_data_count[8] = rd_data_count_4[8],
- rd_data_count[7] = rd_data_count_4[7],
- rd_data_count[6] = rd_data_count_4[6],
- rd_data_count[5] = rd_data_count_4[5],
- rd_data_count[4] = rd_data_count_4[4],
- rd_data_count[3] = rd_data_count_4[3],
- rd_data_count[2] = rd_data_count_4[2],
- rd_data_count[1] = rd_data_count_4[1],
- rd_data_count[0] = rd_data_count_4[0],
- dout[17] = dout_3[17],
- dout[16] = dout_3[16],
- dout[15] = dout_3[15],
- dout[14] = dout_3[14],
- dout[13] = dout_3[13],
- dout[12] = dout_3[12],
- dout[11] = dout_3[11],
- dout[10] = dout_3[10],
- dout[9] = dout_3[9],
- dout[8] = dout_3[8],
- dout[7] = dout_3[7],
- dout[6] = dout_3[6],
- dout[5] = dout_3[5],
- dout[4] = dout_3[4],
- dout[3] = dout_3[3],
- dout[2] = dout_3[2],
- dout[1] = dout_3[1],
- dout[0] = dout_3[0],
- din_2[17] = din[17],
- din_2[16] = din[16],
- din_2[15] = din[15],
- din_2[14] = din[14],
- din_2[13] = din[13],
- din_2[12] = din[12],
- din_2[11] = din[11],
- din_2[10] = din[10],
- din_2[9] = din[9],
- din_2[8] = din[8],
- din_2[7] = din[7],
- din_2[6] = din[6],
- din_2[5] = din[5],
- din_2[4] = din[4],
- din_2[3] = din[3],
- din_2[2] = din[2],
- din_2[1] = din[1],
- din_2[0] = din[0];
- VCC VCC_0 (
- .P(NLW_VCC_P_UNCONNECTED)
- );
- GND GND_1 (
- .G(NLW_GND_G_UNCONNECTED)
- );
- LUT4_D #(
- .INIT ( 16'h0440 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>31 (
- .I0(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ),
- .LO(\BU2/N40 ),
- .O(\BU2/N33 )
- );
- LUT4_L #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8>_SW1_SW0 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .LO(\BU2/N31 )
- );
- LUT3_D #(
- .INIT ( 8'h80 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<9>_SW0_SW0 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ),
- .LO(\BU2/N39 ),
- .O(\BU2/N27 )
- );
- LUT4_L #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>21_SW1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .LO(\BU2/N19 )
- );
- LUT3_L #(
- .INIT ( 8'h80 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>21_SW0 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .LO(\BU2/N17 )
- );
- LUT4_D #(
- .INIT ( 16'h2000 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<4>111_SW0 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ),
- .I1(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .I2(\BU2/U0/grf.rf/gl0.rd/ram_valid_fwft ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]),
- .LO(\BU2/N381 ),
- .O(\BU2/N11 )
- );
- LUT3_D #(
- .INIT ( 8'h80 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>41_SW0 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .LO(\BU2/N37 ),
- .O(\BU2/N13 )
- );
- LUT3_D #(
- .INIT ( 8'h7F ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<4>111 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ),
- .LO(\BU2/N36 ),
- .O(\BU2/N38 )
- );
- LUT2_D #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/RAM_VALID_FWFT11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ),
- .LO(\BU2/N351 ),
- .O(\BU2/U0/grf.rf/gl0.rd/ram_valid_fwft )
- );
- RAMB16_S18_S18 #(
- .INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .SRVAL_A ( 18'h00000 ),
- .SRVAL_B ( 18'h00000 ),
- .INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .WRITE_MODE_B ( "WRITE_FIRST" ),
- .INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
- .SIM_COLLISION_CHECK ( "NONE" ),
- .INIT_A ( 18'h00000 ),
- .INIT_B ( 18'h00000 ),
- .WRITE_MODE_A ( "WRITE_FIRST" ),
- .INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
- \BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram (
- .CLKA(wr_clk),
- .CLKB(rd_clk),
- .ENA(\BU2/N1 ),
- .ENB(\BU2/U0/grf.rf/mem/tmp_ram_rd_en ),
- .SSRA(\BU2/data_count [0]),
- .SSRB(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .WEA(\BU2/U0/grf.rf/ram_wr_en ),
- .WEB(\BU2/data_count [0]),
- .ADDRA({\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7],
-\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4],
-\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2], \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1],
-\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]}),
- .ADDRB({\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7],
-\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4],
-\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2], \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1],
-\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]}),
- .DIA({din_2[16], din_2[15], din_2[14], din_2[13], din_2[12], din_2[11], din_2[10], din_2[9], din_2[7], din_2[6], din_2[5], din_2[4], din_2[3],
-din_2[2], din_2[1], din_2[0]}),
- .DIB({\BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0],
-\BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0],
-\BU2/data_count [0], \BU2/data_count [0], \BU2/data_count [0]}),
- .DIPA({din_2[17], din_2[8]}),
- .DIPB({\BU2/data_count [0], \BU2/data_count [0]}),
- .DOA({\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<15>_UNCONNECTED
-, \NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<14>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<13>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<12>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<11>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<10>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<9>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<8>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<7>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<6>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<5>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<4>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<3>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<2>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<1>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOA<0>_UNCONNECTED }),
- .DOPA({
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<1>_UNCONNECTED ,
-\NLW_BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v2_noinit.ram/dp18x18.ram_DOPA<0>_UNCONNECTED }),
- .DOB({\BU2/U0/grf.rf/mem/dout_mem [16], \BU2/U0/grf.rf/mem/dout_mem [15], \BU2/U0/grf.rf/mem/dout_mem [14], \BU2/U0/grf.rf/mem/dout_mem [13],
-\BU2/U0/grf.rf/mem/dout_mem [12], \BU2/U0/grf.rf/mem/dout_mem [11], \BU2/U0/grf.rf/mem/dout_mem [10], \BU2/U0/grf.rf/mem/dout_mem [9],
-\BU2/U0/grf.rf/mem/dout_mem [7], \BU2/U0/grf.rf/mem/dout_mem [6], \BU2/U0/grf.rf/mem/dout_mem [5], \BU2/U0/grf.rf/mem/dout_mem [4],
-\BU2/U0/grf.rf/mem/dout_mem [3], \BU2/U0/grf.rf/mem/dout_mem [2], \BU2/U0/grf.rf/mem/dout_mem [1], \BU2/U0/grf.rf/mem/dout_mem [0]}),
- .DOPB({\BU2/U0/grf.rf/mem/dout_mem [17], \BU2/U0/grf.rf/mem/dout_mem [8]})
- );
- INV \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<1>11_INV_0 (
- .I(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [1])
- );
- LUT4 #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9> (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ),
- .I3(\BU2/N39 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[9] )
- );
- LUT4 #(
- .INIT ( 16'h7FFF ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8>_SW1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .I3(\BU2/N31 ),
- .O(\BU2/N7 )
- );
- LUT4 #(
- .INIT ( 16'hA2AA ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>30_SW0 (
- .I0(\BU2/N33 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ),
- .I2(\BU2/N4 ),
- .I3(\BU2/N37 ),
- .O(\BU2/N21 )
- );
- LUT4 #(
- .INIT ( 16'h6CCC ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<9> (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ),
- .I3(\BU2/N27 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [9])
- );
- LUT4 #(
- .INIT ( 16'h6CCC ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<8>1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ),
- .I3(\BU2/N25 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [8])
- );
- LUT2 #(
- .INIT ( 4'h8 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>31_SW1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ),
- .O(\BU2/N25 )
- );
- LUT4 #(
- .INIT ( 16'hEAC0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>38 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4_470 ),
- .I2(\BU2/N35 ),
- .I3(\BU2/N21 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [9])
- );
- LUT4 #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8>_SW0 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ),
- .I2(\BU2/N11 ),
- .I3(\BU2/N19 ),
- .O(\BU2/N6 )
- );
- LUT4 #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>41 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .I2(\BU2/N11 ),
- .I3(\BU2/N17 ),
- .O(\BU2/N35 )
- );
- LUT4 #(
- .INIT ( 16'h7FFF ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<5>11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .O(\BU2/N4 )
- );
- LUT4 #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<10>1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ),
- .I2(\BU2/N13 ),
- .I3(\BU2/N30 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [10])
- );
- LUT4 #(
- .INIT ( 16'hFF7F ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<7>_SW0 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .I3(\BU2/N36 ),
- .O(\BU2/N41 )
- );
- LUT4 #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>21 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I3(\BU2/N381 ),
- .O(\BU2/N30 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt_408 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt_361 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8]),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 )
- );
- LUT1 #(
- .INIT ( 2'h2 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8]),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 )
- );
- LUT4 #(
- .INIT ( 16'h8000 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>41 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 )
- );
- LUT3 #(
- .INIT ( 8'h08 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<9>4_470 )
- );
- LUT4 #(
- .INIT ( 16'hD580 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<8> (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 ),
- .I1(\BU2/N33 ),
- .I2(\BU2/N7 ),
- .I3(\BU2/N6 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [8])
- );
- LUT4 #(
- .INIT ( 16'hD580 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<7> (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 ),
- .I1(\BU2/N33 ),
- .I2(\BU2/N41 ),
- .I3(\BU2/N35 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [7])
- );
- LUT4 #(
- .INIT ( 16'hEA40 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<6> (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .I2(\BU2/N30 ),
- .I3(\BU2/N2 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [6])
- );
- LUT4 #(
- .INIT ( 16'hAA2A ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<6>_SW0 (
- .I0(\BU2/N40 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .I3(\BU2/N38 ),
- .O(\BU2/N2 )
- );
- LUT4 #(
- .INIT ( 16'hD580 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<5>2 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 ),
- .I1(\BU2/N4 ),
- .I2(\BU2/N33 ),
- .I3(\BU2/N30 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [5])
- );
- LUT4 #(
- .INIT ( 16'h6CCC ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<7>1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [7])
- );
- LUT3 #(
- .INIT ( 8'h6C ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<6>1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [6])
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000<5>1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy<9>_bdd4 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [5])
- );
- LUT3 #(
- .INIT ( 8'h82 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<4>1 (
- .I0(\BU2/N33 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 ),
- .I2(\BU2/N38 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [4])
- );
- LUT4 #(
- .INIT ( 16'h6CCC ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<4>11 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [4])
- );
- LUT4 #(
- .INIT ( 16'h60C0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<3>1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 ),
- .I2(\BU2/N33 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [3])
- );
- LUT3 #(
- .INIT ( 8'h6C ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<3>11 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 ),
- .I2(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [3])
- );
- LUT3 #(
- .INIT ( 8'h28 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<2>1 (
- .I0(\BU2/N33 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [2])
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_xor<2>11 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [2])
- );
- LUT2 #(
- .INIT ( 4'h4 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<1>1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1]),
- .I1(\BU2/N33 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [1])
- );
- LUT4 #(
- .INIT ( 16'h9669 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor000611 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 )
- );
- LUT4 #(
- .INIT ( 16'h9669 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00081 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0008 )
- );
- LUT4 #(
- .INIT ( 16'h9669 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor000611 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 )
- );
- LUT4 #(
- .INIT ( 16'h9669 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00081 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0008 )
- );
- LUT3 #(
- .INIT ( 8'h69 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00071 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0007 )
- );
- LUT3 #(
- .INIT ( 8'h69 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00071 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0007 )
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00062 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006_bdd0 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006 )
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00062 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006_bdd0 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006 )
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_0_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [0])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_0_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [0])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_0_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [0])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_0_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [0])
- );
- LUT4 #(
- .INIT ( 16'hBAAA ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp1 ),
- .I1(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 ),
- .I2(wr_en),
- .I3(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 ),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 )
- );
- LUT3 #(
- .INIT ( 8'hF8 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp1 ),
- .I1(\BU2/U0/grf.rf/ram_rd_en ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp0 ),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 )
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_1_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [1])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_1_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [1])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_1_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [1])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_1_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [1])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_2_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [2])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_2_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [2])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_2_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [5]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [2])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_2_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [2])
- );
- LUT4 #(
- .INIT ( 16'h3010 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002<0>1 (
- .I0(\BU2/N351 ),
- .I1(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 ),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/diff_wr_rd_tmp [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [0])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_3_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [3])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_3_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [3])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_3_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [7]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [6]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [3])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_3_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [3])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1_4_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [4])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1_4_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9]),
- .I2(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [4])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1_4_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [9]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [8]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [4])
- );
- LUT4 #(
- .INIT ( 16'h9009 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1_4_and00001 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9]),
- .I2(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [4])
- );
- LUT2 #(
- .INIT ( 4'hE ))
- \BU2/U0/grf.rf/mem/tmp_ram_rd_en1 (
- .I0(\BU2/U0/grf.rf/ram_rd_en ),
- .I1(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .O(\BU2/U0/grf.rf/mem/tmp_ram_rd_en )
- );
- LUT4 #(
- .INIT ( 16'h5455 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/RAM_RD_EN_FWFT1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ),
- .I2(rd_en),
- .I3(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ),
- .O(\BU2/U0/grf.rf/ram_rd_en )
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00051 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0005 )
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00051 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0005 )
- );
- LUT3 #(
- .INIT ( 8'h96 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00041 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0004 )
- );
- LUT3 #(
- .INIT ( 8'h96 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00041 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0004 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00032 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00032 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 )
- );
- LUT3 #(
- .INIT ( 8'h62 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/RAM_REGOUT_EN1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ),
- .I2(rd_en),
- .O(\BU2/U0/grf.rf/ram_regout_en )
- );
- LUT2 #(
- .INIT ( 4'h4 ))
- \BU2/U0/grf.rf/gl0.wr/ram_wr_en_i1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 ),
- .I1(wr_en),
- .O(\BU2/U0/grf.rf/ram_wr_en )
- );
- LUT4 #(
- .INIT ( 16'h69A1 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ),
- .I3(rd_en),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In )
- );
- LUT4 #(
- .INIT ( 16'hCA8A ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or00001 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_385 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ),
- .I2(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ),
- .I3(rd_en),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 )
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00021 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [7]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [6]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 )
- );
- LUT4 #(
- .INIT ( 16'h6996 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00021 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [7]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [6]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]),
- .I3(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 )
- );
- LUT3 #(
- .INIT ( 8'h6E ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In11 (
- .I0(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 ),
- .I1(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 ),
- .I2(rd_en),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In )
- );
- LUT3 #(
- .INIT ( 8'h96 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00011 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [7]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 )
- );
- LUT3 #(
- .INIT ( 8'h96 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00011 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8]),
- .I2(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [7]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0000_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0001_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0002_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0003_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0004_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0004 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0005_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0005 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0006_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0006 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0007_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0007 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_rd_pntr_gc_xor0008_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0008 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0000_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0001_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0002_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0003_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0004_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0004 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0005_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0005 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0006_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0006 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0007_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0007 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/Mxor_wr_pntr_gc_xor0008_Result1 (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0008 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor00001 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]),
- .O(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h6 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor00001 (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]),
- .O(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 )
- );
- LUT2 #(
- .INIT ( 4'h4 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_comb1 (
- .I0(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_68 ),
- .I1(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 ),
- .O(\BU2/U0/grf.rf/rstblk/rd_rst_comb )
- );
- LUT2 #(
- .INIT ( 4'h4 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_comb1 (
- .I0(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_70 ),
- .I1(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 ),
- .O(\BU2/U0/grf.rf/rstblk/wr_rst_comb )
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_0 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [0]),
- .Q(dout_3[0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_1 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [1]),
- .Q(dout_3[1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_2 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [2]),
- .Q(dout_3[2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_3 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [3]),
- .Q(dout_3[3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_4 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [4]),
- .Q(dout_3[4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_5 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [5]),
- .Q(dout_3[5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_6 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [6]),
- .Q(dout_3[6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_7 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [7]),
- .Q(dout_3[7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_8 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [8]),
- .Q(dout_3[8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_9 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [9]),
- .Q(dout_3[9])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_10 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [10]),
- .Q(dout_3[10])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_11 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [11]),
- .Q(dout_3[11])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_12 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [12]),
- .Q(dout_3[12])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_13 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [13]),
- .Q(dout_3[13])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_14 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [14]),
- .Q(dout_3[14])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_15 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [15]),
- .Q(dout_3[15])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_16 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [16]),
- .Q(dout_3[16])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/mem/dout_i_17 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_regout_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0]),
- .D(\BU2/U0/grf.rf/mem/dout_mem [17]),
- .Q(dout_3[17])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_5 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [5]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_6 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [6]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_7 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [7]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_8 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [8]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_9 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [9]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_9 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [9])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_8 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_6 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_5 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_7 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [1])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d1 [2])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0> (
- .CI(\BU2/N1 ),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [0])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<0> (
- .CI(\BU2/N1 ),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<0>_rt_425 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [0]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [1])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<1> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [0]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<1>_rt_424 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [1]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [2])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<2> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [1]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<2>_rt_422 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [2]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [3])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<3> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [2]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<3>_rt_420 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [3]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [4])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<4> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [3]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<4>_rt_418 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [4]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [5])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<5> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [4]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<5>_rt_416 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count5 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [5]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [6])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<6> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [5]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<6>_rt_414 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count6 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [6]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [7])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<7> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [6]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<7>_rt_412 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count7 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [7]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [8])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<8> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [7]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy<8>_rt_410 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count8 )
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9> (
- .CI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_cy [8]),
- .LI(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count_xor<9>_rt_408 ),
- .O(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count9 )
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_2 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count2 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_0 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [0])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_1 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count1 ),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_3 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count3 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_4 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count4 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_7 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count7 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_5 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count5 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_6 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count6 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_8 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count8 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/wpntr/count_9 (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/ram_wr_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/Mcount_count9 ),
- .Q(\BU2/U0/grf.rf/gl0.wr/wpntr/count [9])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_fb_385 )
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/empty_fwft_i_or0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(empty)
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ),
- .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/user_valid_383 )
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ),
- .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_382 )
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2-In ),
- .Q(\BU2/U0/grf.rf/gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_380 )
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_5 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_6 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_7 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_8 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_9 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0> (
- .CI(\BU2/N1 ),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [0])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<0> (
- .CI(\BU2/N1 ),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<0>_rt_378 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [0]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [1])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<1> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [0]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<1>_rt_377 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [1]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [2])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<2> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [1]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<2>_rt_375 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [2]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [3])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<3> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [2]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<3>_rt_373 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [3]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [4])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<4> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [3]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<4>_rt_371 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [4]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [5])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<5> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [4]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<5>_rt_369 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count5 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [5]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [6])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<6> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [5]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<6>_rt_367 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count6 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [6]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [7])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<7> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [6]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<7>_rt_365 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count7 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [7]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [8])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<8> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [7]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy<8>_rt_363 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count8 )
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9> (
- .CI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_cy [8]),
- .LI(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count_xor<9>_rt_361 ),
- .O(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count9 )
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_2 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count2 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [2])
- );
- FDPE #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_0 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [0])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_1 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count1 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [1])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_3 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count3 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [3])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_4 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count4 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [4])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_7 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count7 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [7])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_5 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count5 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [5])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_6 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count6 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [6])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_8 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count8 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [8])
- );
- FDCE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/rpntr/count_9 (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/ram_rd_en ),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/Mcount_count9 ),
- .Q(\BU2/U0/grf.rf/gl0.rd/rpntr/count [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0008 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0007 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0006 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0005 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0004 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_5 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0003 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_6 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_7 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_8 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_9 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0008 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0007 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0006 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0005 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0004 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_5 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0003 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_6 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_7 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_8 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_9 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_5 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [5]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_6 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [6]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_7 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [7]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_8 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [8]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_9 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [5]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_6 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [6]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_7 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [7]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_8 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [8]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_9 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_5 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [5]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_6 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [6]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_7 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [7]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_8 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [8]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_9 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [0]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [1]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [2]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [3]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [4]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [5]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_6 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [6]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_7 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [7]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_8 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [8]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_9 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0008 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0007 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0006 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0005 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0004 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_5 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0003 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_6 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_7 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_8 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_9 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1 [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0008 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0007 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0006 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0005 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0004 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_5 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0003 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_6 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0002 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_7 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0001 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_8 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_xor0000 ),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_9 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0]),
- .D(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1 [9]),
- .Q(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[0].gm1.m1 (
- .CI(\BU2/N1 ),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [0])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[1].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [0]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [1])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[2].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [1]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [2])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[3].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [2]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [3])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/gmux.gm[4].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/carrynet [3]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c2/v1 [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp2 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[0].gm1.m1 (
- .CI(\BU2/N1 ),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [0])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[1].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [0]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [1])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[2].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [1]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [2])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[3].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [2]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [3])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/gmux.gm[4].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/carrynet [3]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/c1/v1 [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/comp1 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[0].gm1.m1 (
- .CI(\BU2/N1 ),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [0])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[1].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [0]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [1])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[2].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [1]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [2])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[3].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [2]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [3])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/gmux.gm[4].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/carrynet [3]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c1/v1 [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp1 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[0].gm1.m1 (
- .CI(\BU2/N1 ),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [0])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[1].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [0]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [1])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[2].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [1]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [2])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[3].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [2]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [3])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/gmux.gm[4].gms.ms (
- .CI(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/carrynet [3]),
- .DI(\BU2/data_count [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gras.rsts/c0/v1 [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/gras.rsts/comp0 )
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<9> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [8]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [9]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000016 )
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<9> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [9]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [9]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [9])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<8> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [7]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [8]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000014 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<8> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [7]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [8]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [8])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<8> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [8]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [8]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [8])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<7> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [6]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [7]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000012 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<7> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [6]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [7]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [7])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<7> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [7]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [7]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [7])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<6> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [5]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [6]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add000010 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<6> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [5]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [6]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [6])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<6> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [6]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [6]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [6])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<5> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [4]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [5]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00008 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<5> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [4]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [5]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [5])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<5> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [5]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [5]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [5])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<4> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [3]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00006 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<4> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [3]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [4])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<4> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [4]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [4]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [4])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<3> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [2]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00004 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<3> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [2]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [3])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<3> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [3]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [3]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [3])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<2> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [1]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add00002 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<2> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [1]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [2])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<2> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [2]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [2]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [2])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<1> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [0]),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[1] )
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<1> (
- .CI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [0]),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [1])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<1> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [1]),
- .I1(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [1]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [1])
- );
- XORCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_xor<0> (
- .CI(\BU2/N1 ),
- .LI(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/diff_wr_rd_tmp [0])
- );
- MUXCY \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy<0> (
- .CI(\BU2/N1 ),
- .DI(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
- .S(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_cy [0])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut<0> (
- .I0(\BU2/U0/grf.rf/gl0.wr/wpntr/count_d2 [0]),
- .I1(\BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin [0]),
- .O(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Msub_diff_wr_rd_tmp_lut [0])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<9> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [8]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [9]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000016 )
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<9> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [9]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [9]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [9])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<8> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [7]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [8]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000014 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<8> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [7]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [8]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [8])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<8> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [8]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [8]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [8])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<7> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [6]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [7]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000012 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<7> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [6]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [7]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [7])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<7> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [7]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [7]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [7])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<6> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [5]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [6]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub000010 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<6> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [5]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [6]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [6])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<6> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [6]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [6]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [6])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<5> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [4]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [5]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00008 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<5> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [4]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [5]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [5])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<5> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [5]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [5]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [5])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<4> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [3]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00006 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<4> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [3]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [4])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<4> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [4]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [4]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [4])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<3> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [2]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00004 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<3> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [2]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [3])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<3> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [3]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [3]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [3])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<2> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [1]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub00002 )
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<2> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [1]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [2])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<2> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [2]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [2]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [2])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<1> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [0]),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Madd_rd_dc_i_addsub0000_cy [1])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<1> (
- .CI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [0]),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [1])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<1> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [1]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [1]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [1])
- );
- XORCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_xor<0> (
- .CI(\BU2/N1 ),
- .LI(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/diff_wr_rd_tmp [0])
- );
- MUXCY \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy<0> (
- .CI(\BU2/N1 ),
- .DI(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
- .S(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_cy [0])
- );
- LUT2 #(
- .INIT ( 4'h9 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut<0> (
- .I0(\BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin [0]),
- .I1(\BU2/U0/grf.rf/gl0.rd/rpntr/count_d1 [0]),
- .O(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/Msub_diff_wr_rd_tmp_lut [0])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_10 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/Madd_wr_data_count_i_add0000_cy[9] ),
- .Q(wr_data_count_5[10])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_9 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [9]),
- .Q(wr_data_count_5[9])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_8 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [8]),
- .Q(wr_data_count_5[8])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_7 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [7]),
- .Q(wr_data_count_5[7])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_6 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [6]),
- .Q(wr_data_count_5[6])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_5 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [5]),
- .Q(wr_data_count_5[5])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_4 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [4]),
- .Q(wr_data_count_5[4])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_3 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [3]),
- .Q(wr_data_count_5[3])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_2 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [2]),
- .Q(wr_data_count_5[2])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_1 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_add0000 [1]),
- .Q(wr_data_count_5[1])
- );
- FDC #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/wr_data_count_i_0 (
- .C(wr_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .D(\BU2/U0/grf.rf/gl0.wr/gwdc1.wdcext/diff_wr_rd_tmp [0]),
- .Q(wr_data_count_5[0])
- );
- FDP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i_94 )
- );
- FDP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i_or0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1]),
- .Q(full)
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_10 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [10]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[10])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_9 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [9]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[9])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_8 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [8]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[8])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_7 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [7]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[7])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_6 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [6]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[6])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_5 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [5]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[5])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_4 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [4]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[4])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_3 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [3]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[3])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_2 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [2]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[2])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_1 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [1]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[1])
- );
- FDCP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_0 (
- .C(rd_clk),
- .CLR(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .D(\BU2/U0/grf.rf/gl0.rd/gr1.grdc2.rdc/rd_dc_i_mux0002 [0]),
- .PRE(\BU2/data_count [0]),
- .Q(rd_data_count_4[0])
- );
- FDP #(
- .INIT ( 1'b1 ))
- \BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_or0000 ),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2]),
- .Q(\BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i_81 )
- );
- FDP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_reg_0 (
- .C(wr_clk),
- .D(\BU2/data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [0])
- );
- FDP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_reg_1 (
- .C(wr_clk),
- .D(\BU2/data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/wr_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_reg [1])
- );
- FDP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_reg_0 (
- .C(rd_clk),
- .D(\BU2/data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [0])
- );
- FDP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_reg_1 (
- .C(rd_clk),
- .D(\BU2/data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [1])
- );
- FDP #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_reg_2 (
- .C(rd_clk),
- .D(\BU2/data_count [0]),
- .PRE(\BU2/U0/grf.rf/rstblk/rd_rst_comb ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_reg [2])
- );
- FDPE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_asreg (
- .C(rd_clk),
- .CE(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 ),
- .D(\BU2/data_count [0]),
- .PRE(rst),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1 (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 )
- );
- FDPE #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_asreg (
- .C(wr_clk),
- .CE(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 ),
- .D(\BU2/data_count [0]),
- .PRE(rst),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_72 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1 (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_71 ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2 (
- .C(wr_clk),
- .D(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1_69 ),
- .Q(\BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2_70 )
- );
- FD #(
- .INIT ( 1'b0 ))
- \BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2 (
- .C(rd_clk),
- .D(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1_67 ),
- .Q(\BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2_68 )
- );
- VCC \BU2/XST_VCC (
- .P(\BU2/N1 )
- );
- GND \BU2/XST_GND (
- .G(\BU2/data_count [0])
- );
-
-// synthesis translate_on
-
-endmodule
-
-// synthesis translate_off
-
-`timescale 1 ps / 1 ps
-
-module glbl ();
-
- parameter ROC_WIDTH = 100000;
- parameter TOC_WIDTH = 0;
-
- wire GSR;
- wire GTS;
- wire PRLD;
-
- reg GSR_int;
- reg GTS_int;
- reg PRLD_int;
-
-//-------- JTAG Globals --------------
- wire JTAG_TDO_GLBL;
- wire JTAG_TCK_GLBL;
- wire JTAG_TDI_GLBL;
- wire JTAG_TMS_GLBL;
- wire JTAG_TRST_GLBL;
-
- reg JTAG_CAPTURE_GLBL;
- reg JTAG_RESET_GLBL;
- reg JTAG_SHIFT_GLBL;
- reg JTAG_UPDATE_GLBL;
-
- reg JTAG_SEL1_GLBL = 0;
- reg JTAG_SEL2_GLBL = 0 ;
- reg JTAG_SEL3_GLBL = 0;
- reg JTAG_SEL4_GLBL = 0;
-
- reg JTAG_USER_TDO1_GLBL = 1'bz;
- reg JTAG_USER_TDO2_GLBL = 1'bz;
- reg JTAG_USER_TDO3_GLBL = 1'bz;
- reg JTAG_USER_TDO4_GLBL = 1'bz;
-
- assign (weak1, weak0) GSR = GSR_int;
- assign (weak1, weak0) GTS = GTS_int;
- assign (weak1, weak0) PRLD = PRLD_int;
-
- initial begin
- GSR_int = 1'b1;
- PRLD_int = 1'b1;
- #(ROC_WIDTH)
- GSR_int = 1'b0;
- PRLD_int = 1'b0;
- end
-
- initial begin
- GTS_int = 1'b1;
- #(TOC_WIDTH)
- GTS_int = 1'b0;
- end
-
-endmodule
-
-// synthesis translate_on
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.veo b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.veo
deleted file mode 100644
index c98e03c3b..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.veo
+++ /dev/null
@@ -1,47 +0,0 @@
-/*******************************************************************************
-* This file is owned and controlled by Xilinx and must be used *
-* solely for design, simulation, implementation and creation of *
-* design files limited to Xilinx devices or technologies. Use *
-* with non-Xilinx devices or technologies is expressly prohibited *
-* and immediately terminates your license. *
-* *
-* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
-* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
-* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
-* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
-* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
-* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
-* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
-* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
-* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
-* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
-* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
-* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
-* FOR A PARTICULAR PURPOSE. *
-* *
-* Xilinx products are not intended for use in life support *
-* appliances, devices, or systems. Use in such applications are *
-* expressly prohibited. *
-* *
-* (c) Copyright 1995-2007 Xilinx, Inc. *
-* All rights reserved. *
-*******************************************************************************/
-// The following must be inserted into your Verilog file for this
-// core to be instantiated. Change the instance name and port connections
-// (in parentheses) to your own signal names.
-
-//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
-fifo_xlnx_1Kx18_2clk YourInstanceName (
- .din(din), // Bus [17 : 0]
- .rd_clk(rd_clk),
- .rd_en(rd_en),
- .rst(rst),
- .wr_clk(wr_clk),
- .wr_en(wr_en),
- .dout(dout), // Bus [17 : 0]
- .empty(empty),
- .full(full),
- .rd_data_count(rd_data_count), // Bus [10 : 0]
- .wr_data_count(wr_data_count)); // Bus [10 : 0]
-
-// INST_TAG_END ------ End INSTANTIATION Template ---------
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.xco b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.xco
deleted file mode 100644
index 082aef22b..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk.xco
+++ /dev/null
@@ -1,82 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version K.39
-# Date: Fri Jun 10 23:12:12 2011
-#
-##############################################################
-#
-# This file contains the customisation parameters for a
-# Xilinx CORE Generator IP GUI. It is strongly recommended
-# that you do not manually alter this file as it may cause
-# unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = false
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = false
-SET simulationfiles = Structural
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator family Xilinx,_Inc. 4.3
-# END Select
-# BEGIN Parameters
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET component_name=fifo_xlnx_1Kx18_2clk
-CSET data_count=false
-CSET data_count_width=11
-CSET disable_timing_violations=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_negate_value=5
-CSET enable_ecc=false
-CSET enable_int_clk=false
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=1023
-CSET full_threshold_negate_value=1022
-CSET input_data_width=18
-CSET input_depth=1024
-CSET output_data_width=18
-CSET output_depth=1024
-CSET overflow_flag=false
-CSET overflow_sense=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET read_clock_frequency=1
-CSET read_data_count=true
-CSET read_data_count_width=11
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET underflow_flag=false
-CSET underflow_sense=Active_High
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=true
-CSET write_data_count_width=11
-# END Parameters
-GENERATE
-# CRC: c3fb8408
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.lso b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.lso
deleted file mode 100644
index f1a6f7899..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.lso
+++ /dev/null
@@ -1,3 +0,0 @@
-blkmemdp_v6_2
-blk_mem_gen_v2_6
-fifo_generator_v4_3
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
deleted file mode 100644
index be22cb8dc..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
+++ /dev/null
@@ -1,106 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
-<document OS="lin64" product="ISE" version="10.1.03">
-
- <!--The data in this file is primarily intended for consumption by Xilinx tools.
- The structure and the elements are likely to change over the next few releases.
- This means code written to parse this file will need to be revisited each subsequent release.-->
-
- <application stringID="Xst" timeStamp="Fri Jun 10 16:11:52 2011">
- <section stringID="XST_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="31">
- <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/>
- <item dataType="int" stringID="XST_10BIT_REGISTER" value="11"/>
- <item dataType="int" stringID="XST_11BIT_REGISTER" value="2"/>
- <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
- <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="76">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="76"/>
- </item>
- </section>
- <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
- <item dataType="int" stringID="XST_FSMS" value="1"/>
- <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"></item>
- <item dataType="int" stringID="XST_COUNTERS" value="2">
- <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/>
- </item>
- <item dataType="int" stringID="XST_REGISTERS" value="159">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="159"/>
- </item>
- <item dataType="int" stringID="XST_XORS" value="76">
- <item dataType="int" stringID="XST_1BIT_XOR2" value="76"/>
- </item>
- </section>
- <section stringID="XST_FINAL_REGISTER_REPORT">
- <item dataType="int" stringID="XST_REGISTERS" value="189">
- <item dataType="int" stringID="XST_FLIPFLOPS" value="189"/>
- </item>
- </section>
- <section stringID="XST_PARTITION_REPORT">
- <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- </section>
- <section stringID="XST_FINAL_REPORT">
- <section stringID="XST_FINAL_RESULTS">
- <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/tmp/_cg/fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc"/>
- <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
- <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/>
- <item stringID="XST_KEEP_HIERARCHY" value="no"/>
- </section>
- <section stringID="XST_DESIGN_STATISTICS">
- <item stringID="XST_IOS" value="153"/>
- </section>
- <section stringID="XST_CELL_USAGE">
- <item dataType="int" stringID="XST_BELS" value="248">
- <item dataType="int" stringID="XST_GND" value="1"/>
- <item dataType="int" stringID="XST_INV" value="1"/>
- <item dataType="int" stringID="XST_LUT1" value="20"/>
- <item dataType="int" stringID="XST_LUT2" value="52"/>
- <item dataType="int" stringID="XST_LUT2D" value="1"/>
- <item dataType="int" stringID="XST_LUT3" value="14"/>
- <item dataType="int" stringID="XST_LUT3D" value="3"/>
- <item dataType="int" stringID="XST_LUT3L" value="1"/>
- <item dataType="int" stringID="XST_LUT4" value="54"/>
- <item dataType="int" stringID="XST_LUT4D" value="2"/>
- <item dataType="int" stringID="XST_LUT4L" value="2"/>
- <item dataType="int" stringID="XST_MUXCY" value="56"/>
- <item dataType="int" stringID="XST_VCC" value="1"/>
- <item dataType="int" stringID="XST_XORCY" value="40"/>
- </item>
- <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="189">
- <item dataType="int" stringID="XST_FD" value="4"/>
- <item dataType="int" stringID="XST_FDC" value="94"/>
- <item dataType="int" stringID="XST_FDCE" value="65"/>
- <item dataType="int" stringID="XST_FDP" value="10"/>
- <item dataType="int" stringID="XST_FDPE" value="5"/>
- </item>
- <item dataType="int" stringID="XST_RAMS" value="1">
- <item dataType="int" stringID="XST_RAMB16S18S18" value="1"/>
- </item>
- </section>
- </section>
- <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
- <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/>
- <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="139"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="189"/>
- <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="150"/>
- <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="153"/>
- <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/>
- <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/>
- </section>
- <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
- <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
- </section>
- <section stringID="XST_ERRORS_STATISTICS">
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="136"/>
- <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="17"/>
- </section>
- </application>
-
-</document>
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_flist.txt b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_flist.txt
deleted file mode 100644
index 3bd308751..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_flist.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# Output products list for <fifo_xlnx_1Kx18_2clk>
-fifo_xlnx_1Kx18_2clk.ngc
-fifo_xlnx_1Kx18_2clk.v
-fifo_xlnx_1Kx18_2clk.veo
-fifo_xlnx_1Kx18_2clk.xco
-fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-fifo_xlnx_1Kx18_2clk_flist.txt
-fifo_xlnx_1Kx18_2clk_xmdf.tcl
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_readme.txt b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_readme.txt
deleted file mode 100644
index 72f83d6fb..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_readme.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-The following files were generated for 'fifo_xlnx_1Kx18_2clk' in directory
-/home/matt/sourcerepo/fpga/usrp2/coregen/:
-
-fifo_xlnx_1Kx18_2clk.ngc:
- Binary Xilinx implementation netlist file containing the information
- required to implement the module in a Xilinx (R) FPGA.
-
-fifo_xlnx_1Kx18_2clk.v:
- Unisim Verilog file containing the information required to simulate
- the module.
-
-fifo_xlnx_1Kx18_2clk.veo:
- VEO template file containing code that can be used as a model for
- instantiating a CORE Generator module in a Verilog design.
-
-fifo_xlnx_1Kx18_2clk.xco:
- CORE Generator input file containing the parameters used to
- regenerate a core.
-
-fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt:
- Please see the core data sheet.
-
-fifo_xlnx_1Kx18_2clk_flist.txt:
- Text file listing all of the output files produced when a customized
- core was generated in the CORE Generator.
-
-fifo_xlnx_1Kx18_2clk_readme.txt:
- Text file indicating the files generated and how they are used.
-
-fifo_xlnx_1Kx18_2clk_xmdf.tcl:
- ISE Project Navigator interface file. ISE uses this file to determine
- how the files output by CORE Generator for the core can be integrated
- into your ISE project.
-
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_xmdf.tcl b/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_xmdf.tcl
deleted file mode 100644
index 244d03d85..000000000
--- a/fpga/usrp2/coregen/fifo_xlnx_1Kx18_2clk_xmdf.tcl
+++ /dev/null
@@ -1,68 +0,0 @@
-# The package naming convention is <core_name>_xmdf
-package provide fifo_xlnx_1Kx18_2clk_xmdf 1.0
-
-# This includes some utilities that support common XMDF operations
-package require utilities_xmdf
-
-# Define a namespace for this package. The name of the name space
-# is <core_name>_xmdf
-namespace eval ::fifo_xlnx_1Kx18_2clk_xmdf {
-# Use this to define any statics
-}
-
-# Function called by client to rebuild the params and port arrays
-# Optional when the use context does not require the param or ports
-# arrays to be available.
-proc ::fifo_xlnx_1Kx18_2clk_xmdf::xmdfInit { instance } {
-# Variable containg name of library into which module is compiled
-# Recommendation: <module_name>
-# Required
-utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_1Kx18_2clk
-}
-# ::fifo_xlnx_1Kx18_2clk_xmdf::xmdfInit
-
-# Function called by client to fill in all the xmdf* data variables
-# based on the current settings of the parameters
-proc ::fifo_xlnx_1Kx18_2clk_xmdf::xmdfApplyParams { instance } {
-
-set fcount 0
-# Array containing libraries that are assumed to exist
-# Examples include unisim and xilinxcorelib
-# Optional
-# In this example, we assume that the unisim library will
-# be magically
-# available to the simulation and synthesis tool
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
-utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.ngc
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.v
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.veo
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk.xco
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_1Kx18_2clk_xmdf.tcl
-utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
-incr fcount
-
-utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_1Kx18_2clk
-incr fcount
-
-}
-
-# ::gen_comp_name_xmdf::xmdfApplyParams
diff --git a/fpga/usrp2/fifo/fifo_2clock.v b/fpga/usrp2/fifo/fifo_2clock.v
index c6aaf34dc..756ad508f 100644
--- a/fpga/usrp2/fifo/fifo_2clock.v
+++ b/fpga/usrp2/fifo/fifo_2clock.v
@@ -65,11 +65,6 @@ module fifo_2clock
(.rst(arst),
.wr_clk(wclk),.din({1'b0,datain}),.full(full),.wr_en(write),.wr_data_count(level_wclk),
.rd_clk(rclk),.dout({dummy,dataout}),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
- else if ((WIDTH==18) & (SIZE==10))
- fifo_xlnx_1Kx18_2clk fifo_xlnx_1Kx18_2clk
- (.rst(arst),
- .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
- .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
endgenerate
assign occupied = {{(16-SIZE-1){1'b0}},level_rclk};
diff --git a/fpga/usrp2/fifo/packet_dispatcher36_x3.v b/fpga/usrp2/fifo/packet_dispatcher36_x3.v
index fd762d061..0f9e752c8 100644
--- a/fpga/usrp2/fifo/packet_dispatcher36_x3.v
+++ b/fpga/usrp2/fifo/packet_dispatcher36_x3.v
@@ -93,13 +93,12 @@ module packet_dispatcher36_x3
wire pd_dreg_counter_done = (pd_dreg_count_next == PD_MAX_NUM_DREGS)? 1'b1 : 1'b0;
reg [35:0] pd_dregs [PD_MAX_NUM_DREGS-1:0];
- //extract various packet components:
- wire [47:0] pd_dregs_eth_dst_mac = {pd_dregs[0][15:0], pd_dregs[1][31:0]};
- wire [15:0] pd_dregs_eth_type = pd_dregs[3][15:0];
- wire [7:0] pd_dregs_ipv4_proto = pd_dregs[6][23:16];
- wire [31:0] pd_dregs_ipv4_dst_addr = pd_dregs[8][31:0];
- wire [15:0] pd_dregs_udp_dst_port = pd_dregs[9][15:0];
- wire [15:0] pd_dregs_vrt_size = com_inp_data[15:0];
+ reg is_eth_dst_mac_bcast;
+ reg is_eth_type_ipv4;
+ reg is_eth_ipv4_proto_udp;
+ reg is_eth_ipv4_dst_addr_here;
+ reg is_eth_udp_dst_port_here;
+ wire is_vrt_size_zero = (com_inp_data[15:0] == 16'h0); //needed on the same cycle, so it cant be registered
//Inspector output flags special case:
//Inject SOF into flags at first DSP line.
@@ -150,6 +149,31 @@ module packet_dispatcher36_x3
(pd_state == PD_STATE_WRITE_LIVE) ? pd_out_ready : (
1'b0)));
+ //inspect the incoming data and mark register booleans
+ always @(posedge clk)
+ if (com_inp_ready & com_inp_valid) begin
+ case(pd_dreg_count)
+ 0: begin
+ is_eth_dst_mac_bcast <= (com_inp_data[15:0] == 16'hffff);
+ end
+ 1: begin
+ is_eth_dst_mac_bcast <= is_eth_dst_mac_bcast && (com_inp_data[31:0] == 32'hffffffff);
+ end
+ 3: begin
+ is_eth_type_ipv4 <= (com_inp_data[15:0] == 16'h800);
+ end
+ 6: begin
+ is_eth_ipv4_proto_udp <= (com_inp_data[23:16] == 8'h11);
+ end
+ 8: begin
+ is_eth_ipv4_dst_addr_here <= (com_inp_data[31:0] == my_ip_addr);
+ end
+ 9: begin
+ is_eth_udp_dst_port_here <= (com_inp_data[15:0] == dsp_udp_port);
+ end
+ endcase //pd_dreg_count
+ end
+
always @(posedge clk)
if(rst | clr) begin
pd_state <= PD_STATE_READ_COM_PRE;
@@ -175,19 +199,19 @@ module packet_dispatcher36_x3
//---------- begin inspection decision -----------//
//EOF or bcast or not IPv4 or not UDP:
if (
- com_inp_data[33] || (pd_dregs_eth_dst_mac == 48'hffffffffffff) ||
- (pd_dregs_eth_type != 16'h800) || (pd_dregs_ipv4_proto != 8'h11)
+ com_inp_data[33] || is_eth_dst_mac_bcast ||
+ ~is_eth_type_ipv4 || ~is_eth_ipv4_proto_udp
) begin
pd_dest <= PD_DEST_BOF;
end
//not my IP address:
- else if (pd_dregs_ipv4_dst_addr != my_ip_addr) begin
+ else if (~is_eth_ipv4_dst_addr_here) begin
pd_dest <= PD_DEST_EXT;
end
//UDP data port and VRT:
- else if ((pd_dregs_udp_dst_port == dsp_udp_port) && (pd_dregs_vrt_size != 16'h0)) begin
+ else if (is_eth_udp_dst_port_here && ~is_vrt_size_zero) begin
pd_dest <= PD_DEST_DSP;
pd_dreg_count <= PD_DREGS_DSP_OFFSET;
end
diff --git a/fpga/usrp2/gpmc/Makefile.srcs b/fpga/usrp2/gpmc/Makefile.srcs
index bf0c0ecfd..bff6ae3e0 100644
--- a/fpga/usrp2/gpmc/Makefile.srcs
+++ b/fpga/usrp2/gpmc/Makefile.srcs
@@ -17,6 +17,4 @@ gpmc_to_fifo_async.v \
gpmc_to_fifo_sync.v \
gpmc_wb.v \
ram_to_fifo.v \
-new_write.v \
-new_read.v \
))
diff --git a/fpga/usrp2/gpmc/fifo_watcher.v b/fpga/usrp2/gpmc/fifo_watcher.v
index 3971e3c54..b139f5143 100644
--- a/fpga/usrp2/gpmc/fifo_watcher.v
+++ b/fpga/usrp2/gpmc/fifo_watcher.v
@@ -30,11 +30,10 @@ module fifo_watcher
reg [15:0] counter;
wire [4:0] pkt_count;
assign debug = pkt_count;
- wire space;
fifo_short #(.WIDTH(16)) frame_lengths
(.clk(clk), .reset(reset), .clear(clear),
- .datain(counter), .src_rdy_i(write), .dst_rdy_o(space),
+ .datain(counter), .src_rdy_i(write), .dst_rdy_o(),
.dataout(length), .src_rdy_o(have_packet_int), .dst_rdy_i(read),
.occupied(pkt_count), .space());
@@ -54,9 +53,7 @@ module fifo_watcher
bus_error <= 1;
else if(read & ~have_packet_int)
bus_error <= 1;
- else if(write & ~space)
- bus_error <= 1;
-
+
reg in_packet;
always @(posedge clk)
if(reset | clear)
diff --git a/fpga/usrp2/gpmc/gpmc_async.v b/fpga/usrp2/gpmc/gpmc_async.v
index 9972e81b0..c0bec683a 100644
--- a/fpga/usrp2/gpmc/gpmc_async.v
+++ b/fpga/usrp2/gpmc/gpmc_async.v
@@ -22,7 +22,7 @@ module gpmc_async
parameter RXFIFOSIZE = 11,
parameter BUSDEBUG = 1)
(// GPMC signals
- input arst, input bus_clk,
+ input arst,
input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,
@@ -67,21 +67,27 @@ module gpmc_async
// ////////////////////////////////////////////
// TX Data Path
- wire [17:0] tx18_data;
- wire tx18_src_rdy, tx18_dst_rdy;
+ wire [17:0] tx18_data, tx18b_data;
+ wire tx18_src_rdy, tx18_dst_rdy, tx18b_src_rdy, tx18b_dst_rdy;
wire [15:0] tx_fifo_space;
wire [35:0] tx36_data, tx_data;
wire tx36_src_rdy, tx36_dst_rdy, tx_src_rdy, tx_dst_rdy;
- new_write new_write
+ gpmc_to_fifo_async gpmc_to_fifo_async
(.EM_D(EM_D), .EM_NBE(EM_NBE), .EM_NCS(EM_NCS4), .EM_NWE(EM_NWE),
- .bus_clk(bus_clk), .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx),
+ .fifo_clk(fifo_clk), .fifo_rst(fifo_rst), .clear(clear_tx),
.data_o(tx18_data), .src_rdy_o(tx18_src_rdy), .dst_rdy_i(tx18_dst_rdy),
- .frame_len(tx_frame_len), .fifo_ready(tx_have_space), .bus_error(bus_error_tx) );
+ .frame_len(tx_frame_len), .fifo_space(tx_fifo_space), .fifo_ready(tx_have_space),
+ .bus_error(bus_error_tx) );
+ fifo_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
+ .datain(tx18_data), .src_rdy_i(tx18_src_rdy), .dst_rdy_o(tx18_dst_rdy), .space(tx_fifo_space),
+ .dataout(tx18b_data), .src_rdy_o(tx18b_src_rdy), .dst_rdy_i(tx18b_dst_rdy), .occupied());
+
fifo19_to_fifo36 #(.LE(1)) f19_to_f36 // Little endian because ARM is LE
(.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
- .f19_datain({1'b0,tx18_data}), .f19_src_rdy_i(tx18_src_rdy), .f19_dst_rdy_o(tx18_dst_rdy),
+ .f19_datain({1'b0,tx18b_data}), .f19_src_rdy_i(tx18b_src_rdy), .f19_dst_rdy_o(tx18b_dst_rdy),
.f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
@@ -104,20 +110,31 @@ module gpmc_async
.datain(rx_data), .src_rdy_i(rx_src_rdy), .dst_rdy_o(rx_dst_rdy),
.dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
- wire [31:0] pkt_count;
- wire throttle = pkt_count == 16;
-
fifo36_to_fifo19 #(.LE(1)) f36_to_f19 // Little endian because ARM is LE
(.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
.f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
.f19_dataout({dummy,rx18_data}), .f19_src_rdy_o(rx18_src_rdy), .f19_dst_rdy_i(rx18_dst_rdy) );
- new_read new_read
+ fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .datain(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy), .space(rx_fifo_space),
+ .dataout(rx18b_data), .src_rdy_o(rx18b_src_rdy), .dst_rdy_i(rx18b_dst_rdy), .occupied());
+
+ fifo_to_gpmc_async fifo_to_gpmc_async
(.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
- .data_i(rx18_data), .src_rdy_i(rx18_src_rdy), .dst_rdy_o(rx18_dst_rdy),
+ .data_i(rx18b_data), .src_rdy_i(rx18b_src_rdy), .dst_rdy_o(rx18b_dst_rdy),
.EM_D(EM_D_fifo), .EM_NCS(EM_NCS4), .EM_NOE(EM_NOE),
- .have_packet(rx_have_data), .frame_len(rx_frame_len), .bus_error(bus_error_rx) );
+ .frame_len(rx_frame_len) );
+
+ wire [31:0] pkt_count;
+ fifo_watcher fifo_watcher
+ (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+ .src_rdy1(rx18_src_rdy), .dst_rdy1(rx18_dst_rdy), .sof1(rx18_data[16]), .eof1(rx18_data[17]),
+ .src_rdy2(rx18b_src_rdy), .dst_rdy2(rx18b_dst_rdy), .sof2(rx18b_data[16]), .eof2(rx18b_data[17]),
+ .have_packet(rx_have_data), .length(rx_frame_len), .bus_error(bus_error_rx),
+ .debug(pkt_count));
+
// ////////////////////////////////////////////
// Control path on CS6
@@ -213,13 +230,16 @@ module gpmc_async
// FIXME -- make sure packet completes before we shutoff
// FIXME -- handle overrun and underrun
- wire [0:17] dummy18;
-
- assign debug = {rx_overrun, tx_underrun, bus_error_tx, bus_error_rx, tx_have_space, rx_have_data, EM_NCS4, EM_NCS6,
- 6'd0, EM_NOE, EM_NWE,
- pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
- timedrx_src_rdy, timedrx_dst_rdy,
- testrx_src_rdy, testrx_dst_rdy,
- rx_src_rdy, rx_dst_rdy, rx36_src_rdy, rx36_dst_rdy, rx18_src_rdy, rx18_dst_rdy, rx18b_src_rdy, rx18b_dst_rdy};
+wire [0:17] dummy18;
+
+assign debug = {8'd0,
+ test_rate,
+ pkt_src_enable, pkt_sink_enable, timedrx_src_rdy_int, timedrx_dst_rdy_int,
+ timedrx_src_rdy, timedrx_dst_rdy,
+ testrx_src_rdy, testrx_dst_rdy,
+ rx_src_rdy, rx_dst_rdy,
+ rx36_src_rdy, rx36_dst_rdy,
+ rx18_src_rdy, rx18_dst_rdy,
+ rx18b_src_rdy, rx18b_dst_rdy};
endmodule // gpmc_async
diff --git a/fpga/usrp2/gpmc/new_read.v b/fpga/usrp2/gpmc/new_read.v
deleted file mode 100644
index ae3db23cf..000000000
--- a/fpga/usrp2/gpmc/new_read.v
+++ /dev/null
@@ -1,62 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-
-
-module new_read
- (input clk, input reset, input clear,
- input [17:0] data_i, input src_rdy_i, output dst_rdy_o,
- output reg [15:0] EM_D, input EM_NCS, input EM_NOE,
- output have_packet, output [15:0] frame_len, output bus_error);
-
- wire [17:0] data_int;
- wire src_rdy_int, dst_rdy_int;
-
- fifo_cascade #(.WIDTH(18), .SIZE(12)) rx_fifo
- (.clk(clk), .reset(reset), .clear(clear),
- .datain(data_i), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
- .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied());
-
- fifo_watcher fifo_watcher
- (.clk(clk), .reset(reset), .clear(clear),
- .src_rdy1(src_rdy_i), .dst_rdy1(dst_rdy_o), .sof1(data_i[16]), .eof1(data_i[17]),
- .src_rdy2(src_rdy_int), .dst_rdy2(dst_rdy_int), .sof2(data_int[16]), .eof2(data_int[17]),
- .have_packet(have_packet), .length(frame_len), .bus_error(bus_error),
- .debug());
-
- // Synchronize the async control signals
- reg [1:0] cs_del, oe_del;
- reg [15:0] counter;
-
- always @(posedge clk)
- if(reset)
- begin
- cs_del <= 2'b11;
- oe_del <= 2'b11;
- end
- else
- begin
- cs_del <= { cs_del[0], EM_NCS };
- oe_del <= { oe_del[0], EM_NOE };
- end
-
- assign dst_rdy_int = ( ~cs_del[1] & ~oe_del[1] & oe_del[0]); // change output on trailing edge
-
- //always @(posedge clk) // 3 cycle latency ( OE -> OE_del -> FIFO -> output REG )
- always @* // 2 cycle latency ( OE -> OE_del -> FIFO )
- EM_D <= data_int[15:0];
-
-endmodule // new_read
diff --git a/fpga/usrp2/gpmc/new_write.v b/fpga/usrp2/gpmc/new_write.v
deleted file mode 100644
index df0ce19db..000000000
--- a/fpga/usrp2/gpmc/new_write.v
+++ /dev/null
@@ -1,82 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program. If not, see <http://www.gnu.org/licenses/>.
-//
-
-
-module new_write
- (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE,
-
- input bus_clk,
- input fifo_clk, input fifo_rst, input clear,
- output [17:0] data_o, output src_rdy_o, input dst_rdy_i,
-
- input [15:0] frame_len, output reg fifo_ready,
- output reg bus_error );
-
- wire [15:0] fifo_space;
- reg [15:0] counter;
-
- // Synchronize the async control signals
- reg [1:0] cs_del, we_del;
- reg [15:0] data_del[0:1];
-
- always @(posedge bus_clk)
- if(fifo_rst)
- begin
- cs_del <= 2'b11;
- we_del <= 2'b11;
- end
- else
- begin
- cs_del <= { cs_del[0], EM_NCS };
- we_del <= { we_del[0], EM_NWE };
- data_del[1] <= data_del[0];
- data_del[0] <= EM_D;
- end
-
- wire first_write = (counter == 0);
- wire last_write = ((counter+1) == frame_len);
-
- wire [17:0] data_int = {last_write,first_write,data_del[1]};
- wire src_rdy_int = (~cs_del[1] & ~we_del[1] & we_del[0]); // rising edge
- wire dst_rdy_int;
-
- always @(posedge bus_clk)
- if(fifo_rst | clear)
- counter <= 0;
- else if(src_rdy_int)
- if(last_write)
- counter <= 0;
- else
- counter <= counter + 1;
-
- always @(posedge bus_clk)
- if(fifo_rst | clear)
- fifo_ready <= 0;
- else
- fifo_ready <= /* first_write & */ (fifo_space > 16'd1023);
-
- always @(posedge bus_clk)
- if(fifo_rst | clear)
- bus_error <= 0;
- else if(src_rdy_int & ~dst_rdy_int)
- bus_error <= 1;
-
- fifo_2clock_cascade #(.WIDTH(18), .SIZE(10)) tx_fifo
- (.wclk(bus_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space),
- .rclk(fifo_clk), .dataout(data_o), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), .occupied(), .arst(fifo_rst));
-
-endmodule // new_write
diff --git a/fpga/usrp2/sdr_lib/dsp_core_tx.v b/fpga/usrp2/sdr_lib/dsp_core_tx.v
index f02c63b42..4e0163e0a 100644
--- a/fpga/usrp2/sdr_lib/dsp_core_tx.v
+++ b/fpga/usrp2/sdr_lib/dsp_core_tx.v
@@ -36,7 +36,8 @@ module dsp_core_tx
wire [7:0] interp_rate;
wire [3:0] dacmux_a, dacmux_b;
wire enable_hb1, enable_hb2;
-
+ wire rate_change;
+
setting_reg #(.my_addr(BASE+0)) sr_0
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_inc),.changed());
@@ -47,7 +48,7 @@ module dsp_core_tx
setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
- .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
+ .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change));
// Strobes are all now delayed by 1 cycle for timing reasons
wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
@@ -56,13 +57,13 @@ module dsp_core_tx
reg strobe_hb2 = 1;
cic_strober #(.WIDTH(8))
- cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+ cic_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
.strobe_fast(1),.strobe_slow(strobe_cic_pre) );
cic_strober #(.WIDTH(2))
- hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 : 1),
+ hb2_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb2 ? 2 : 1),
.strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) );
cic_strober #(.WIDTH(2))
- hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 : 1),
+ hb1_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb1 ? 2 : 1),
.strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) );
always @(posedge clk) strobe_hb1 <= strobe_hb1_pre;
@@ -104,12 +105,12 @@ module dsp_core_tx
.output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q));
cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
- cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+ cic_interp_i(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
.strobe_in(strobe_cic),.strobe_out(1),
.signal_in(hb2_i),.signal_out(i_interp));
cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7))
- cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+ cic_interp_q(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate),
.strobe_in(strobe_cic),.strobe_out(1),
.signal_in(hb2_q),.signal_out(q_interp));
diff --git a/fpga/usrp2/sdr_lib/small_hb_dec.v b/fpga/usrp2/sdr_lib/small_hb_dec.v
index a7f93e056..c05a48b81 100644
--- a/fpga/usrp2/sdr_lib/small_hb_dec.v
+++ b/fpga/usrp2/sdr_lib/small_hb_dec.v
@@ -103,22 +103,24 @@ module small_hb_dec
wire [17:0] coeff = go_d1 ? coeff_b : coeff_a;
wire [35:0] prod;
MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), .B(sum) );
+
+ localparam ACCWIDTH = 30;
+ reg [ACCWIDTH-1:0] accum;
- reg [35:0] accum;
always @(posedge clk)
if(rst)
accum <= 0;
else if(go_d2)
- accum <= {middle_d1[17],middle_d1[17],middle_d1,16'd0} + {prod};
+ accum <= {middle_d1[17],middle_d1[17],middle_d1,{(16+ACCWIDTH-36){1'b0}}} + {prod[35:36-ACCWIDTH]};
else if(go_d3)
- accum <= accum + {prod};
+ accum <= accum + {prod[35:36-ACCWIDTH]};
wire [WIDTH:0] accum_rnd;
wire [WIDTH-1:0] accum_rnd_clip;
wire stb_round;
- round_sd #(.WIDTH_IN(36),.WIDTH_OUT(WIDTH+1)) round_acc
+ round_sd #(.WIDTH_IN(ACCWIDTH),.WIDTH_OUT(WIDTH+1)) round_acc
(.clk(clk), .reset(rst), .in(accum), .strobe_in(go_d4), .out(accum_rnd), .strobe_out(stb_round));
clip #(.bits_in(WIDTH+1),.bits_out(WIDTH)) clip (.in(accum_rnd), .out(accum_rnd_clip));
diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile
index ca6ec9320..7ab56f9bd 100644
--- a/fpga/usrp2/top/B100/Makefile
+++ b/fpga/usrp2/top/B100/Makefile
@@ -69,6 +69,7 @@ TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
diff --git a/fpga/usrp2/top/E1x0/Makefile b/fpga/usrp2/top/E1x0/Makefile
index 5d721979b..19fb93ebf 100644
--- a/fpga/usrp2/top/E1x0/Makefile
+++ b/fpga/usrp2/top/E1x0/Makefile
@@ -72,6 +72,7 @@ TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v
index 4f85b7d6e..dbd6173f3 100644
--- a/fpga/usrp2/top/E1x0/u1e.v
+++ b/fpga/usrp2/top/E1x0/u1e.v
@@ -76,7 +76,7 @@ module u1e
clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst),
.DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(),
.CLKDV(), .CLKFX(), .CLKFX180(),
- .CLK2X(clk_2x), .CLK2X180(),
+ .CLK2X(), .CLK2X180(),
.CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(),
.LOCKED(dcm_locked), .STATUS());
@@ -141,7 +141,7 @@ module u1e
// /////////////////////////////////////////////////////////////////////////
// Main U1E Core
- u1e_core u1e_core(.clk_fpga(clk_fpga), .bus_clk(clk_2x), .rst_fpga(~debug_pb),
+ u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb),
.debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
.debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index d481867e3..c4fc16444 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -18,7 +18,7 @@
module u1e_core
- (input clk_fpga, input bus_clk, input rst_fpga,
+ (input clk_fpga, input rst_fpga,
output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
output debug_txd, input debug_rxd,
@@ -117,7 +117,7 @@ module u1e_core
.in(set_data),.out(),.changed(clear_tx));
gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
- gpmc (.arst(wb_rst), .bus_clk(bus_clk),
+ gpmc (.arst(wb_rst),
.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
.EM_NOE(EM_NOE),
diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common
index 6f855a070..3a35e71e7 100644
--- a/fpga/usrp2/top/Makefile.common
+++ b/fpga/usrp2/top/Makefile.common
@@ -1,5 +1,5 @@
#
-# Copyright 2008, 2009, 2010 Ettus Research LLC
+# Copyright 2008-2011 Ettus Research LLC
#
##################################################
@@ -14,10 +14,12 @@ endif
BASE_DIR = $(abspath ..)
ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py
+TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py
ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs
+TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr
##################################################
# Global Targets
@@ -35,6 +37,7 @@ synth: $(ISE_FILE)
bin: check $(BIN_FILE)
$(ISE_HELPER) "Generate Programming File"
+ $(TIMING_CHECKER) $(TWR_FILE)
mcs: $(MCS_FILE)
diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R3 b/fpga/usrp2/top/N2x0/Makefile.N200R3
index a525836ed..9ed5ece00 100644
--- a/fpga/usrp2/top/N2x0/Makefile.N200R3
+++ b/fpga/usrp2/top/N2x0/Makefile.N200R3
@@ -71,6 +71,7 @@ TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R4 b/fpga/usrp2/top/N2x0/Makefile.N200R4
index 0ca40e1bd..f8640224f 100644
--- a/fpga/usrp2/top/N2x0/Makefile.N200R4
+++ b/fpga/usrp2/top/N2x0/Makefile.N200R4
@@ -73,6 +73,7 @@ TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R3 b/fpga/usrp2/top/N2x0/Makefile.N210R3
index e29251e1c..2937dc409 100644
--- a/fpga/usrp2/top/N2x0/Makefile.N210R3
+++ b/fpga/usrp2/top/N2x0/Makefile.N210R3
@@ -71,6 +71,7 @@ TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
diff --git a/fpga/usrp2/top/N2x0/Makefile.N210R4 b/fpga/usrp2/top/N2x0/Makefile.N210R4
index 01a9e19fd..39a2508f9 100644
--- a/fpga/usrp2/top/N2x0/Makefile.N210R4
+++ b/fpga/usrp2/top/N2x0/Makefile.N210R4
@@ -73,6 +73,7 @@ TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
diff --git a/fpga/usrp2/top/USRP2/Makefile b/fpga/usrp2/top/USRP2/Makefile
index e9b43491a..8ebb43639 100644
--- a/fpga/usrp2/top/USRP2/Makefile
+++ b/fpga/usrp2/top/USRP2/Makefile
@@ -71,6 +71,7 @@ TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"
MAP_PROPERTIES = \
+"Generate Detailed MAP Report" TRUE \
"Allow Logic Optimization Across Hierarchy" TRUE \
"Map to Input Functions" 4 \
"Optimization Strategy (Cover Mode)" Speed \
diff --git a/fpga/usrp2/top/python/check_timing.py b/fpga/usrp2/top/python/check_timing.py
new file mode 100755
index 000000000..c57e889d0
--- /dev/null
+++ b/fpga/usrp2/top/python/check_timing.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python
+#
+# Copyright 2011 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+import sys
+import re
+
+def print_timing_constraint_summary(twr_file):
+ output = ""
+ keep = False
+ for line in open(twr_file).readlines():
+ if 'Derived Constraint Report' in line: keep = True
+ if keep: output += line
+ if 'constraint' in line and 'met' in line: break
+ print("\n\n"+output)
+
+if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])