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| author | Josh Blum <josh@joshknows.com> | 2012-04-09 16:37:46 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-04-09 16:37:46 -0700 |
| commit | 1e143bddd2a246ca6ffae6fb54aa416b35293078 (patch) | |
| tree | 6257015af38732f6ecc0837e33b817ea8ff4c5f4 /fpga/usrp2/vrt | |
| parent | 00c241844a62c22cac538316d507c524acc1c393 (diff) | |
| parent | f136b06211dc0fe572d77219b6ce579963d435fe (diff) | |
| download | uhd-1e143bddd2a246ca6ffae6fb54aa416b35293078.tar.gz uhd-1e143bddd2a246ca6ffae6fb54aa416b35293078.tar.bz2 uhd-1e143bddd2a246ca6ffae6fb54aa416b35293078.zip | |
Merge branch 'fpga_maint' into maint
Diffstat (limited to 'fpga/usrp2/vrt')
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_chain.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index ca2f847bc..2788dc9d5 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -41,7 +41,7 @@ module vita_rx_chain wire clear; assign clear_o = clear; wire clear_int; - setting_reg #(.my_addr(BASE+3)) sr + setting_reg #(.my_addr(BASE+8)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_int)); |