Merge branch 'next'

Conflicts:
	host/lib/usrp/usrp2/codec_impl.cpp

3 files changed, 38 insertions, 10 deletions

diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v
index 44bb7b548..cc34cceed 100644
--- a/fpga/usrp2/vrt/gen_context_pkt.v
+++ b/fpga/usrp2/vrt/gen_context_pkt.v
@@ -1,7 +1,8 @@
 
 
 module gen_context_pkt
-  #(parameter PROT_ENG_FLAGS=1)
+  #(parameter PROT_ENG_FLAGS=1,
+    parameter DSP_NUMBER=0)
    (input clk, input reset, input clear,
     input trigger, output sent,
     input [31:0] streamid,
@@ -67,10 +68,10 @@ module gen_context_pkt
        endcase // case (ctxt_state)
 
    assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) );
-   
+
    always @*
      case(ctxt_state)
-       CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 };
+       CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd28 }; // UDP port 1 or 3
        CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 };
        CTXT_STREAMID : data_int <= { 2'b00, streamid };
        CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v
index 2ec78189b..6f567668d 100644
--- a/fpga/usrp2/vrt/vita_tx_chain.v
+++ b/fpga/usrp2/vrt/vita_tx_chain.v
@@ -5,7 +5,8 @@ module vita_tx_chain
     parameter REPORT_ERROR=0,
     parameter DO_FLOW_CONTROL=0,
     parameter PROT_ENG_FLAGS=0,
-    parameter USE_TRANS_HEADER=0)
+    parameter USE_TRANS_HEADER=0,
+    parameter DSP_NUMBER=0)
    (input clk, input reset,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     input [63:0] vita_time,
@@ -71,7 +72,7 @@ module vita_tx_chain
    wire [35:0] 		flow_data, err_data_int;
    wire 		flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int;
    
-   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt
+   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(32'd0),
@@ -82,7 +83,7 @@ module vita_tx_chain
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .packet_consumed(packet_consumed), .trigger(trigger));
    
-   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
+   gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(message),
diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v
index ab6da8bd0..e966d987c 100644
--- a/fpga/usrp2/vrt/vita_tx_control.v
+++ b/fpga/usrp2/vrt/vita_tx_control.v
@@ -17,14 +17,12 @@ module vita_tx_control
     
     // To DSP Core
     output [WIDTH-1:0] sample,
-    output run,
+    output reg run,
     input strobe,
 
     output [31:0] debug
     );
 
-   assign sample = sample_fifo_i[5+64+16+WIDTH-1:5+64+16];
-
    wire [63:0] send_time = sample_fifo_i[63:0];
    wire [15:0] seqnum = sample_fifo_i[79:64];
    wire        eop = sample_fifo_i[80];
@@ -169,11 +167,39 @@ module vita_tx_control
 	   send_error <= 0;
        endcase // case (ibs_state)
 
+   
    assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN));  // FIXME also cleanout
-   assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
+
+   assign sample = (ibs_state == IBS_RUN) ? sample_fifo_i[5+64+16+WIDTH-1:5+64+16] : {WIDTH{1'b0}};
+   //assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
    assign error = send_error;
    assign ack = send_ack;
 
+   localparam MAX_IDLE = 1000000; 
+   // approx 10 ms timeout with a 100 MHz clock, but burning samples will slow that down
+   reg [19:0] countdown;
+   
+   always @(posedge clk)
+     if(reset | clear)
+       begin
+	  run <= 0;
+	  countdown <= 0;
+       end
+     else 
+       if (ibs_state == IBS_RUN)
+	 if(eob & eop & strobe & sample_fifo_src_rdy_i)
+	   run <= 0;
+	 else 
+	   begin
+	      run <= 1;
+	      countdown <= MAX_IDLE;
+	   end
+       else
+	 if (countdown == 0)
+	   run <= 0;
+	 else
+	   countdown <= countdown - 1;
+   	   
    always @(posedge clk)
      if(reset | clear)
        packet_consumed <= 0;