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authorJosh Blum <josh@joshknows.com>2012-04-21 11:06:38 -0700
committerJosh Blum <josh@joshknows.com>2012-04-21 11:06:38 -0700
commitf84d7579aecaf2a90965331b200f6b298cd0c1d4 (patch)
tree4787f725f7c6b0a7efd5d91a4719b12f1591e6cc /fpga/usrp2/vrt
parent20ea7b7bc90c02a61f5284d38d18969b9710302a (diff)
parent00f515da98ccd2b123e15d7e724a9d91ad5c46d9 (diff)
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Merge branch 'timed_cmds_work_fpga' into timed_cmds_work
Diffstat (limited to 'fpga/usrp2/vrt')
-rw-r--r--fpga/usrp2/vrt/vita_rx_framer.v8
-rw-r--r--fpga/usrp2/vrt/vita_tx_deframer.v3
2 files changed, 7 insertions, 4 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
index 514df1151..6e4b8025d 100644
--- a/fpga/usrp2/vrt/vita_rx_framer.v
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -85,9 +85,11 @@ module vita_rx_framer
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(samples_per_packet),.changed());
- setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan
+ assign numchan = 0;/*
+ setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(0)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
+ */
// Output FIFO for packetized data
localparam VITA_IDLE = 0;
@@ -164,7 +166,7 @@ module vita_rx_framer
VITA_PAYLOAD :
if(sample_fifo_src_rdy_i)
begin
- if(sample_phase == (numchan-4'd1))
+ if(sample_phase == numchan)
begin
sample_phase <= 0;
sample_ctr <= sample_ctr + 1;
@@ -213,7 +215,7 @@ module vita_rx_framer
assign data_o[35:34] = 2'b00; // Always write full lines
assign sample_fifo_dst_rdy_o = pkt_fifo_rdy &
( ((vita_state==VITA_PAYLOAD) &
- (sample_phase == (numchan-4'd1)) &
+ (sample_phase == numchan) &
~|flags_fifo_o[4:1]) |
(vita_state==VITA_ERR_PAYLOAD));
diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v
index 6919da11a..ed3916311 100644
--- a/fpga/usrp2/vrt/vita_tx_deframer.v
+++ b/fpga/usrp2/vrt/vita_tx_deframer.v
@@ -43,10 +43,11 @@ module vita_tx_deframer
localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
- wire [1:0] numchan;
+ wire [1:0] numchan = 0;/*
setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(numchan),.changed());
+ */
reg [3:0] vita_state;
wire has_streamid, has_classid, has_secs, has_tics, has_trailer;