fpga: performed a forceful checkout of fpga to overwrite with current fpga code

9 files changed, 155 insertions, 132 deletions

diff --git a/fpga/usrp2/vrt/gen_context_pkt.v b/fpga/usrp2/vrt/gen_context_pkt.v
index 0eb035f3e..bf83aeae5 100644
--- a/fpga/usrp2/vrt/gen_context_pkt.v
+++ b/fpga/usrp2/vrt/gen_context_pkt.v
@@ -7,8 +7,7 @@ module gen_context_pkt
     input [31:0] streamid,
     input [63:0] vita_time,
     input [31:0] message,
-    input [31:0] seqnum0,
-    input [31:0] seqnum1,
+    input [31:0] seqnum,
     output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
    
    localparam CTXT_IDLE = 0;
@@ -19,9 +18,8 @@ module gen_context_pkt
    localparam CTXT_TICS = 5;
    localparam CTXT_TICS2 = 6;
    localparam CTXT_MESSAGE = 7;
-   localparam CTXT_FLOWCTRL0 = 8;
-   localparam CTXT_FLOWCTRL1 = 9;
-   localparam CTXT_DONE = 10;
+   localparam CTXT_FLOWCTRL = 8;
+   localparam CTXT_DONE = 9;
 
    reg [33:0] 	 data_int;
    wire 	 src_rdy_int, dst_rdy_int;
@@ -36,11 +34,12 @@ module gen_context_pkt
      else
        if(trigger)
 	 stored_message <= message;
-       else if(ctxt_state == CTXT_FLOWCTRL1)
+       else if(ctxt_state == CTXT_DONE)
 	 stored_message <= 0;
-   
+
+   // Don't want to clear most of this to avoid getting stuck with a half packet in the pipe
    always @(posedge clk)
-     if(reset | clear)
+     if(reset)
        begin
 	  ctxt_state <= CTXT_IDLE;
 	  seqno <= 0;
@@ -72,19 +71,18 @@ module gen_context_pkt
    always @*
      case(ctxt_state)
        CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd32 };
-       CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd8 };
+       CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 };
        CTXT_STREAMID : data_int <= { 2'b00, streamid };
        CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
        CTXT_TICS : data_int <= { 2'b00, 32'd0 };
        CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] };
        CTXT_MESSAGE : data_int <= { 2'b00, message };
-       CTXT_FLOWCTRL0 : data_int <= { 2'b00, seqnum0 };
-       CTXT_FLOWCTRL1 : data_int <= { 2'b10, seqnum1 };
+       CTXT_FLOWCTRL : data_int <= { 2'b10, seqnum };
        default : data_int <= {2'b00, 32'b00};
      endcase // case (ctxt_state)
 
    fifo_short #(.WIDTH(34)) ctxt_fifo
-     (.clk(clk), .reset(reset), .clear(clear),
+     (.clk(clk), .reset(reset), .clear(0),
       .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int),
       .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i));
    assign data_o[35:34] = 2'b00;
diff --git a/fpga/usrp2/vrt/vita_rx_control.v b/fpga/usrp2/vrt/vita_rx_control.v
index 93673d292..0769f3a24 100644
--- a/fpga/usrp2/vrt/vita_rx_control.v
+++ b/fpga/usrp2/vrt/vita_rx_control.v
@@ -9,7 +9,7 @@ module vita_rx_control
     output overrun,
 
     // To vita_rx_framer
-    output [4+64+WIDTH-1:0] sample_fifo_o,
+    output [5+64+WIDTH-1:0] sample_fifo_o,
     output sample_fifo_src_rdy_o,
     input sample_fifo_dst_rdy_i,
     
@@ -25,16 +25,14 @@ module vita_rx_control
    
    wire [63:0] 	  new_time;
    wire [31:0] 	  new_command;
-   wire 	  sc_pre1, clear_int, clear_reg;
+   wire 	  sc_pre1;
 
-   assign clear_int  = clear | clear_reg;
-   
    wire [63:0] 	  rcvtime_pre;
    reg [63:0] 	  rcvtime;
    wire [28:0] 	  numlines_pre;
    wire 	  send_imm_pre, chain_pre, reload_pre;
    reg 		  send_imm, chain, reload;
-   wire 	  full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+   wire 	  read_ctrl, not_empty_ctrl, write_ctrl;
    reg 		  sc_pre2;
    wire [33:0] 	  fifo_line;
    reg [28:0] 	  lines_left, lines_total;
@@ -54,21 +52,22 @@ module vita_rx_control
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(new_time[31:0]),.changed(sc_pre1));
    
-   setting_reg #(.my_addr(BASE+3)) sr_clear
-     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_reg));
-
    // FIFO to store commands sent from the settings bus
    always @(posedge clk)
-     sc_pre2 		  <= sc_pre1;
+     if(reset | clear)
+       sc_pre2 <= 0;
+     else
+       sc_pre2 <= sc_pre1;
+   
    assign      write_ctrl  = sc_pre1 & ~sc_pre2;
 
    wire [4:0]  command_queue_len;
-   shortfifo #(.WIDTH(96)) commandfifo
-     (.clk(clk),.rst(reset),.clear(clear_int),
-      .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl),
+
+   fifo_short #(.WIDTH(96)) commandfifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(),
       .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
-      .read(read_ctrl), .empty(empty_ctrl),
+      .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl),
       .occupied(command_queue_len), .space() );
    
    reg [33:0]  pkt_fifo_line;
@@ -79,20 +78,23 @@ module vita_rx_control
    localparam IBS_OVERRUN = 4;
    localparam IBS_BROKENCHAIN = 5;
    localparam IBS_LATECMD = 6;
-
-   wire signal_cmd_done     = (lines_left == 1) & (~chain | (~empty_ctrl & (numlines_pre==0)));
+   localparam IBS_ZEROLEN = 7;
+   
+   wire signal_cmd_done     = (lines_left == 1) & (~chain | (not_empty_ctrl & (numlines_pre==0)));
    wire signal_overrun 	    = (ibs_state == IBS_OVERRUN);
    wire signal_brokenchain  = (ibs_state == IBS_BROKENCHAIN);
    wire signal_latecmd 	    = (ibs_state == IBS_LATECMD);
+   wire signal_zerolen 	    = (ibs_state == IBS_ZEROLEN);
 
    // Buffer of samples for while we're writing the packet headers
-   wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
+   wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
 
    wire       attempt_sample_write    = ((run & strobe) | (ibs_state==IBS_OVERRUN) |
-				       (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD));
+					 (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD) |
+					 (ibs_state==IBS_ZEROLEN));
    
-   fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo
-     (.clk(clk),.reset(reset),.clear(clear_int),
+   fifo_short #(.WIDTH(5+64+WIDTH)) rx_sample_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
       .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy),
       .dataout(sample_fifo_o), 
       .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
@@ -107,7 +109,7 @@ module vita_rx_control
    wire full 		    = ~sample_fifo_in_rdy;
    
    always @(posedge clk)
-     if(reset | clear_int)
+     if(reset | clear)
        begin
 	  ibs_state 	   <= IBS_IDLE;
 	  lines_left 	   <= 0;
@@ -120,12 +122,15 @@ module vita_rx_control
      else
        case(ibs_state)
 	 IBS_IDLE :
-	   if(~empty_ctrl)
+	   if(not_empty_ctrl)
 	     begin
 		lines_left <= numlines_pre;
 		lines_total <= numlines_pre;
 		rcvtime <= rcvtime_pre;
-		ibs_state <= IBS_WAITING;
+		if(numlines_pre == 0)
+		  ibs_state <= IBS_ZEROLEN;
+		else
+		  ibs_state <= IBS_WAITING;
 		send_imm <= send_imm_pre;
 		chain <= chain_pre;
 		reload <= reload_pre;
@@ -145,12 +150,12 @@ module vita_rx_control
 		  if(lines_left == 1)
 		    if(~chain)
 		      ibs_state      <= IBS_IDLE;
-		    else if(empty_ctrl & reload)
+		    else if(~not_empty_ctrl & reload)
 		      begin
 		        ibs_state      <= IBS_RUNNING;
 		        lines_left     <= lines_total;
 		      end
-		    else if(empty_ctrl)
+		    else if(~not_empty_ctrl)
 		      ibs_state      <= IBS_BROKENCHAIN;
 		    else
 		      begin
@@ -175,17 +180,20 @@ module vita_rx_control
 	 IBS_BROKENCHAIN :
 	   if(sample_fifo_in_rdy)
 	     ibs_state <= IBS_IDLE;
+	 IBS_ZEROLEN :
+	   if(sample_fifo_in_rdy)
+	     ibs_state <= IBS_IDLE;
        endcase // case(ibs_state)
    
    assign overrun = (ibs_state == IBS_OVERRUN);
    assign run = (ibs_state == IBS_RUNNING);
 
    assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) )
-     & ~empty_ctrl;
+     & not_empty_ctrl;
    
    assign debug_rx = { { ibs_state[2:0], command_queue_len },
 		       { 8'd0 },
-		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, full_ctrl, empty_ctrl },
+		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl },
 		       { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
    
 endmodule // rx_control
diff --git a/fpga/usrp2/vrt/vita_rx_framer.v b/fpga/usrp2/vrt/vita_rx_framer.v
index 235817941..bce8fe334 100644
--- a/fpga/usrp2/vrt/vita_rx_framer.v
+++ b/fpga/usrp2/vrt/vita_rx_framer.v
@@ -11,7 +11,7 @@ module vita_rx_framer
     output src_rdy_o,
     
     // From vita_rx_control
-    input [4+64+(32*MAXCHAN)-1:0] sample_fifo_i,
+    input [5+64+(32*MAXCHAN)-1:0] sample_fifo_i,
     input sample_fifo_src_rdy_i,
     output sample_fifo_dst_rdy_o,
     
@@ -23,11 +23,11 @@ module vita_rx_framer
     output [31:0] debug_rx
     );
 
-   localparam SAMP_WIDTH  = 4+64+(32*MAXCHAN);
+   localparam SAMP_WIDTH  = 5+64+(32*MAXCHAN);
    reg [3:0] 	  sample_phase;
    wire [3:0] 	  numchan;
-   wire [3:0] 	  flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-4];
-   wire [63:0] 	  vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68];
+   wire [4:0] 	  flags_fifo_o = sample_fifo_i[SAMP_WIDTH-1:SAMP_WIDTH-5];
+   wire [63:0] 	  vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-6:SAMP_WIDTH-69];
 
    reg [31:0] 	  data_fifo_o;
 
@@ -55,14 +55,7 @@ module vita_rx_framer
    reg [3:0] 	  pkt_count;
    
    wire [15:0] 	  vita_pkt_len = samples_per_packet + 6;
-   //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
-
-   wire 	  clear_reg;
-   wire 	  clear_int  = clear | clear_reg;
-
-   setting_reg #(.my_addr(BASE+3)) sr_clear
-     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_reg));
+   //wire [4:0] flags = {signal_zerolen,signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
 
    setting_reg #(.my_addr(BASE+4)) sr_header
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
@@ -76,11 +69,11 @@ module vita_rx_framer
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(vita_trailer),.changed());
 
-   setting_reg #(.my_addr(BASE+7)) sr_samples_per_pkt
+   setting_reg #(.my_addr(BASE+7),.width(16)) sr_samples_per_pkt
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(samples_per_packet),.changed());
 
-   setting_reg #(.my_addr(BASE+8), .at_reset(1)) sr_numchan
+   setting_reg #(.my_addr(BASE+8),.width(4), .at_reset(1)) sr_numchan
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(numchan),.changed());
 
@@ -102,7 +95,7 @@ module vita_rx_framer
    localparam VITA_ERR_TRAILER 	 = 15; // Extension context packets have no trailer
       
    always @(posedge clk)
-     if(reset | clear_pkt_count)
+     if(reset | clear | clear_pkt_count)
        pkt_count <= 0;
      else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
        pkt_count <= pkt_count + 1;
@@ -114,7 +107,8 @@ module vita_rx_framer
    always @*
      case(vita_state)
        // Data packets are IF Data packets with or w/o streamid, no classid, with trailer
-       VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len};
+       VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:24],
+				       vita_header[23:20],pkt_count[3:0],vita_pkt_len[15:0]};
        VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
        VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
        VITA_TICS : pkt_fifo_line <= {2'b00,32'd0};
@@ -128,14 +122,14 @@ module vita_rx_framer
        VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
        VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
        VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
-       VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,28'd0,flags_fifo_o};
+       VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b10,27'd0,flags_fifo_o};
        //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
        
        default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
        endcase // case (vita_state)
 
    always @(posedge clk)
-     if(reset)
+     if(reset | clear)
        begin
 	  vita_state   <= VITA_IDLE;
 	  sample_ctr   <= 0;
@@ -147,7 +141,7 @@ module vita_rx_framer
 	    sample_ctr <= 1;
 	    sample_phase <= 0;
 	    if(sample_fifo_src_rdy_i)
-	      if(|flags_fifo_o[3:1])
+	      if(|flags_fifo_o[4:1])
 		vita_state <= VITA_ERR_HEADER;
 	      else
 		vita_state <= VITA_HEADER;
@@ -192,7 +186,7 @@ module vita_rx_framer
 	 req_write_pkt_fifo <= 1;
        VITA_PAYLOAD :
 	 // Write if sample ready and no error flags
-     	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
+     	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[4:1]);
        VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
 	 req_write_pkt_fifo <= 1;
        default :
@@ -203,7 +197,7 @@ module vita_rx_framer
    
    // Short FIFO to buffer between us and the FIFOs outside
    fifo_short #(.WIDTH(34)) rx_pkt_fifo 
-     (.clk(clk), .reset(reset), .clear(clear_int),
+     (.clk(clk), .reset(reset), .clear(clear),
       .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy),
       .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
       .space(),.occupied(fifo_occupied[4:0]) );
@@ -212,7 +206,7 @@ module vita_rx_framer
    assign sample_fifo_dst_rdy_o  = pkt_fifo_rdy & 
 				   ( ((vita_state==VITA_PAYLOAD) & 
 				      (sample_phase == (numchan-4'd1)) & 
-				      ~|flags_fifo_o[3:1]) |
+				      ~|flags_fifo_o[4:1]) |
 				     (vita_state==VITA_ERR_PAYLOAD));
    
    assign debug_rx  = vita_state;
diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v
index 3e01e2ee2..023934f39 100644
--- a/fpga/usrp2/vrt/vita_rx_tb.v
+++ b/fpga/usrp2/vrt/vita_rx_tb.v
@@ -37,7 +37,7 @@ module vita_rx_tb;
    
    wire        sample_dst_rdy, sample_src_rdy;
    //wire [99:0] sample_data_o;
-   wire [64+4+(MAXCHAN*32)-1:0] sample_data_o;
+   wire [64+5+(MAXCHAN*32)-1:0] sample_data_o;
 
    vita_rx_control #(.BASE(0), .WIDTH(32*MAXCHAN)) vita_rx_control
      (.clk(clk), .reset(reset), .clear(0),
@@ -92,58 +92,68 @@ module vita_rx_tb;
      begin
 	@(negedge reset);
 	@(posedge clk);
-	write_setting(4,32'hDEADBEEF);  // VITA header
+	write_setting(4,32'h15F00000);  // VITA header
 	write_setting(5,32'hF00D1234);  // VITA streamid
-	write_setting(6,32'hF0000000);  // VITA trailer
+	write_setting(6,32'hE0000000);  // VITA trailer
 	write_setting(7,8);  // Samples per VITA packet
-	write_setting(8,NUMCHAN);  // Samples per VITA packet
-	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
-	queue_rx_cmd(1,0,16,32'h0,32'h0);  // send imm, 2 packets worth
-	queue_rx_cmd(1,0,7,32'h0,32'h0);  // send imm, 1 short packet worth
-	queue_rx_cmd(1,0,9,32'h0,32'h0);  // send imm, just longer than 1 packet
+	write_setting(8,NUMCHAN);  // Vector length
+
+	queue_rx_cmd(1,1,0,10,32'h0,32'h0);  // send imm, single packet
+	#10000;
+	
+	queue_rx_cmd(1,0,0,0,32'h0,32'h0);  // send imm, single packet
+	//queue_rx_cmd(1,1,0,0,32'h0,32'h0);  // send imm, single packet
+	
+	//queue_rx_cmd(1,0,0,0,32'h0,32'h0);  // send imm, single packet
+	
+	/*
+	queue_rx_cmd(1,0,0,8,32'h0,32'h0);  // send imm, single packet
+	queue_rx_cmd(1,0,0,16,32'h0,32'h0);  // send imm, 2 packets worth
+	queue_rx_cmd(1,0,0,7,32'h0,32'h0);  // send imm, 1 short packet worth
+	queue_rx_cmd(1,0,0,9,32'h0,32'h0);  // send imm, just longer than 1 packet
 	
-	queue_rx_cmd(1,1,16,32'h0,32'h0);  // chained
-	queue_rx_cmd(0,0,8,32'h0,32'h0);  // 2nd in chain
+	queue_rx_cmd(1,1,0,16,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,8,32'h0,32'h0);  // 2nd in chain
 	
-	queue_rx_cmd(1,1,17,32'h0,32'h0);  // chained, odd length
-	queue_rx_cmd(0,0,9,32'h0,32'h0);  // 2nd in chain, also odd length
+	queue_rx_cmd(1,1,0,17,32'h0,32'h0);  // chained, odd length
+	queue_rx_cmd(0,0,0,9,32'h0,32'h0);  // 2nd in chain, also odd length
 	
-	queue_rx_cmd(0,0,8,32'h0,32'h340);  // send at, on time
-	queue_rx_cmd(0,0,8,32'h0,32'h100);  // send at, but late
+	queue_rx_cmd(0,0,0,8,32'h0,32'h340);  // send at, on time
+	queue_rx_cmd(0,0,0,8,32'h0,32'h100);  // send at, but late
 
 	#100000;
 	$display("\nChained, break chain\n");
-	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained, but break chain
+	queue_rx_cmd(1,1,0,8,32'h0,32'h0);  // chained, but break chain
 	#100000;
 	$display("\nSingle packet\n");
-	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
+	queue_rx_cmd(1,0,0,8,32'h0,32'h0);  // send imm, single packet
 	#100000;
 	$display("\nEnd chain with zero samples, shouldn't error\n");
-	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained
-	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	queue_rx_cmd(1,1,0,8,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
 	#100000;
 
 	$display("\nEnd chain with zero samples on odd-length, shouldn't error\n");
-	queue_rx_cmd(1,1,14,32'h0,32'h0);  // chained
-	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
+	queue_rx_cmd(1,1,0,14,32'h0,32'h0);  // chained
+	queue_rx_cmd(0,0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error
 	#100000;
 	$display("Should have gotten 14 samples and EOF by now\n");
 	
-	queue_rx_cmd(1,1,9,32'h0,32'h0);  // chained, but break chain, odd length
+	queue_rx_cmd(1,1,0,9,32'h0,32'h0);  // chained, but break chain, odd length
 	#100000;
 	dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
-	queue_rx_cmd(1,0,100,32'h0,32'h0);  // long enough to fill the fifos
-	queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	queue_rx_cmd(1,0,0,100,32'h0,32'h0);  // long enough to fill the fifos
+	queue_rx_cmd(1,0,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
 	#100000;
 	dst_rdy <= 1;  // restart the reads so we can see what we got
 	#100000;
 	dst_rdy <= 0;  // stop pulling out of fifo so we can get an overrun
-	queue_rx_cmd(1,1,100,32'h0,32'h0);  // long enough to fill the fifos
-	//queue_rx_cmd(1,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
+	queue_rx_cmd(1,1,0,100,32'h0,32'h0);  // long enough to fill the fifos
+	//queue_rx_cmd(1,0,0,5,32'h0,32'h0);  // this command waits until the previous error packet is sent
 	#100000;
 	@(posedge clk);
 	dst_rdy <= 1;
-	  
+	 */
 	#100000 $finish;
      end
 
@@ -164,11 +174,12 @@ module vita_rx_tb;
    task queue_rx_cmd;
       input send_imm;
       input chain;
-      input [29:0] lines;
+      input reload;
+      input [28:0] lines;
       input [31:0] secs;
       input [31:0] tics;
       begin
-	 write_setting(0,{send_imm,chain,lines});
+	 write_setting(0,{send_imm,chain,reload,lines});
 	 write_setting(1,secs);
 	 write_setting(2,tics);
       end
diff --git a/fpga/usrp2/vrt/vita_tx.build b/fpga/usrp2/vrt/vita_tx.build
index 902929c08..e7106aa10 100755
--- a/fpga/usrp2/vrt/vita_tx.build
+++ b/fpga/usrp2/vrt/vita_tx.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v
+iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v
diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v
index 00da4c6e1..2ec78189b 100644
--- a/fpga/usrp2/vrt/vita_tx_chain.v
+++ b/fpga/usrp2/vrt/vita_tx_chain.v
@@ -31,9 +31,13 @@ module vita_tx_chain
    wire 		clear_seqnum;
    wire [31:0] 		current_seqnum;
    
-   assign underrun = error & ~(error_code == 1);
+   assign underrun = error;
    assign message = error_code;
-      
+   
+   setting_reg #(.my_addr(BASE_CTRL+1)) sr
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_vita));
+
    setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(streamid),.changed(clear_seqnum));
@@ -52,7 +56,7 @@ module vita_tx_chain
    vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .vita_time(vita_time),.error(error),.error_code(error_code),
+      .vita_time(vita_time), .error(error), .ack(ack), .error_code(error_code),
       .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
       .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed),
       .debug(debug_vtc) );
@@ -71,7 +75,7 @@ module vita_tx_chain
      (.clk(clk), .reset(reset), .clear(clear_vita),
       .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(32'd0),
-      .seqnum0(current_seqnum), .seqnum1(32'd0),
+      .seqnum(current_seqnum),
       .data_o(flow_data), .src_rdy_o(flow_src_rdy), .dst_rdy_i(flow_dst_rdy));
    trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
@@ -80,15 +84,15 @@ module vita_tx_chain
    
    gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
      (.clk(clk), .reset(reset), .clear(clear_vita),
-      .trigger(error & (REPORT_ERROR==1)), .sent(), 
+      .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), 
       .streamid(streamid), .vita_time(vita_time), .message(message),
-      .seqnum0(current_seqnum), .seqnum1(32'd0),
+      .seqnum(current_seqnum),
       .data_o(err_data_int), .src_rdy_o(err_src_rdy_int), .dst_rdy_i(err_dst_rdy_int));
       
    assign debug = debug_vtc | debug_vtd;
    
    fifo36_mux #(.prio(1)) mux_err_and_flow  // Priority to err messages
-     (.clk(clk), .reset(reset), .clear(clear_vita),
+     (.clk(clk), .reset(reset), .clear(0),  // Don't clear this or it could get clogged
       .data0_i(err_data_int), .src0_rdy_i(err_src_rdy_int), .dst0_rdy_o(err_dst_rdy_int),
       .data1_i(flow_data), .src1_rdy_i(flow_src_rdy), .dst1_rdy_o(flow_dst_rdy),
       .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v
index 936762212..20ad6b995 100644
--- a/fpga/usrp2/vrt/vita_tx_control.v
+++ b/fpga/usrp2/vrt/vita_tx_control.v
@@ -6,7 +6,7 @@ module vita_tx_control
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     
     input [63:0] vita_time,
-    output error,
+    output error, output ack,
     output reg [31:0] error_code,
     output reg packet_consumed,
     
@@ -38,9 +38,8 @@ module vita_tx_control
    // FIXME ignore too_early for now for timing reasons
    assign too_early = 0;
    time_compare 
-     time_compare (.time_now(vita_time), .trigger_time(send_time), .now(now), .early(early), 
-		   .late(late), .too_early());
-//		   .late(late), .too_early(too_early));
+     time_compare (.time_now(vita_time), .trigger_time(send_time), 
+		   .now(now), .early(early), .late(late), .too_early());
    
    localparam IBS_IDLE = 0;
    localparam IBS_RUN = 1;  // FIXME do we need this?
@@ -58,11 +57,6 @@ module vita_tx_control
    
    reg [2:0] ibs_state;
 
-   wire      clear_state;
-   setting_reg #(.my_addr(BASE+1)) sr
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_state));
-   
    wire [31:0] error_policy;
    setting_reg #(.my_addr(BASE+3)) sr_error_policy
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -71,13 +65,15 @@ module vita_tx_control
    wire        policy_wait = error_policy[0];
    wire        policy_next_packet = error_policy[1];
    wire        policy_next_burst = error_policy[2];
-   reg 	       send_error;
+   reg 	       send_error, send_ack;
    
    always @(posedge clk)
-     if(reset | clear_state)
+     if(reset | clear)
        begin
 	  ibs_state <= IBS_IDLE;
 	  send_error <= 0;
+	  send_ack <= 0;
+	  error_code <= 0;
        end
      else
        case(ibs_state)
@@ -111,7 +107,7 @@ module vita_tx_control
 		 begin
 		    ibs_state <= IBS_ERROR_DONE;  // Not really an error
 		    error_code <= CODE_EOB_ACK;
-		    send_error <= 1;
+		    send_ack <= 1;
 		 end
 	       else
 		 ibs_state <= IBS_CONT_BURST;
@@ -151,6 +147,7 @@ module vita_tx_control
 	 IBS_ERROR_DONE :
 	   begin
 	      send_error <= 0;
+	      send_ack <= 0;
 	      ibs_state <= IBS_IDLE;
 	   end
 	 
@@ -161,14 +158,15 @@ module vita_tx_control
    assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN));  // FIXME also cleanout
    assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST);
    assign error = send_error;
+   assign ack = send_ack;
 
    always @(posedge clk)
-     if(reset)
+     if(reset | clear)
        packet_consumed <= 0;
      else
        packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o;
    
-   assign debug = { { now,early,late,too_early,eop,eob,sob,send_at },
+   assign debug = { { now,early,late,ack,eop,eob,sob,send_at },
 		    { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] },
 		    { 8'b0 },
 		    { 8'b0 } };
diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v
index 7fb8e3893..eb39feaec 100644
--- a/fpga/usrp2/vrt/vita_tx_deframer.v
+++ b/fpga/usrp2/vrt/vita_tx_deframer.v
@@ -80,7 +80,7 @@ module vita_tx_deframer
    wire        fifo_space;
 
    always @(posedge clk)
-     if(reset | clear_seqnum)
+     if(reset | clear | clear_seqnum)
        begin
 	  seqnum_reg <= 32'hFFFF_FFFF;
 	  vita_seqnum_reg <= 4'hF;
@@ -201,8 +201,6 @@ module vita_tx_deframer
 	 send_time[63:32] <= data_i[31:0];
        VITA_TICS2 :
 	 send_time[31:0] <= data_i[31:0];
-       VITA_STORE, VITA_HEADER :
-	 send_time[63:0] <= 64'd0;
      endcase // case (vita_state)
    
    always @(posedge clk)
diff --git a/fpga/usrp2/vrt/vita_tx_tb.v b/fpga/usrp2/vrt/vita_tx_tb.v
index 0223d6850..a118ffd4e 100644
--- a/fpga/usrp2/vrt/vita_tx_tb.v
+++ b/fpga/usrp2/vrt/vita_tx_tb.v
@@ -33,7 +33,7 @@ module vita_tx_tb;
    wire [31:0] set_data_dsp;
 
    wire        sample_dst_rdy, sample_src_rdy;
-   wire [64+4+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx;
+   wire [5+64+16+(MAXCHAN*32)-1:0] sample_data_o, sample_data_tx;
 
    time_64bit #(.TICKS_PER_SEC(100000000), .BASE(0)) time_64bit
      (.clk(clk), .rst(reset),
@@ -49,8 +49,8 @@ module vita_tx_tb;
       .datain(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
       .dataout(data_tx), .src_rdy_o(src_rdy_tx), .dst_rdy_i(dst_rdy_tx));
    
-   vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN)) vita_tx_deframer
-     (.clk(clk), .reset(reset), .clear(0),
+   vita_tx_deframer #(.BASE(16), .MAXCHAN(MAXCHAN), .USE_TRANS_HEADER(0)) vita_tx_deframer
+     (.clk(clk), .reset(reset), .clear(0), .clear_seqnum(0),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .data_i(data_tx), .dst_rdy_o(dst_rdy_tx), .src_rdy_i(src_rdy_tx),
       .sample_fifo_o(sample_data_tx), 
@@ -60,7 +60,7 @@ module vita_tx_tb;
    vita_tx_control #(.BASE(16), .WIDTH(MAXCHAN*32)) vita_tx_control
      (.clk(clk), .reset(reset), .clear(0),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .vita_time(vita_time), .underrun(underrun),
+      .vita_time(vita_time), .error(underrun), .error_code(),
       .sample_fifo_i(sample_data_tx), 
       .sample_fifo_dst_rdy_o(sample_dst_rdy_tx), .sample_fifo_src_rdy_i(sample_src_rdy_tx),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx));
@@ -92,35 +92,47 @@ module vita_tx_tb;
 	write_setting(7,8);  // Samples per VITA packet
 	write_setting(8,NUMCHAN);  // Samples per VITA packet
 	#10000;
-	queue_vita_packets(32'h300, 106, 32'hF00D_1234, 32'h55AA_AA55);
-	//queue_vita_packets(32'h300, 6, 32'hF00D_1234, 32'h0);
-	queue_vita_packets(32'h600, 9, 32'h9876_ABCD, 32'h0);
-	
+	queue_vita_packets(0, 32'h300, 5, 32'h0000_1000, 32'h0, 4'h0, 1, 0, 1);
+	queue_vita_packets(0, 32'h0,   5, 32'h0000_2000, 32'h0, 4'h1, 0, 0, 0);
+	queue_vita_packets(0, 32'h0,   5, 32'h0000_3000, 32'h0, 4'h2, 0, 0, 0);
+
+	queue_vita_packets(0, 32'h400, 3, 32'h0000_4000, 32'h0, 4'h3, 1, 0, 1);
+	queue_vita_packets(0, 32'h0,   3, 32'h0000_5000, 32'h0, 4'h4, 0, 0, 0);
+	queue_vita_packets(0, 32'h0,   3, 32'h0000_6000, 32'h0, 4'h5, 0, 1, 0);
+
 	#300000 $finish;
      end
 
    task queue_vita_packets;
+      input [31:0] send_secs;
       input [31:0] sendtime;
       input [15:0] samples;
       input [15:0] word;
       input [31:0] trailer;
+      input [3:0]  seqnum;
+      input 	   sob;
+      input 	   eob;
+      input 	   sendat;
       
       reg [15:0]   i;
       
       begin
+	 src_rdy <= 0;
 	 @(posedge clk);
 	 src_rdy <= 1;
-	 data_o <= {4'b0001,4'h1,1'b0,|trailer,2'h3,8'hF0,(16'd5+samples+|trailer)}; // header
-	 @(posedge clk);
-	 data_o <= {4'b0000,32'h0}; // streamid
-	 @(posedge clk);
-	 data_o <= {4'b0000,32'h0}; // SECS
-	 @(posedge clk);
-	 data_o <= {4'b0000,32'h0}; // TICS
+	 data_o <= {4'b0001,4'h0,1'b0,|trailer,sob,eob,{2{sendat}},1'b0,sendat,seqnum,(16'd1+samples+|trailer+sendat+sendat+sendat)}; // header
 	 @(posedge clk);
-	 data_o <= {4'b0000,sendtime}; // TICS
-	 @(posedge clk);
-
+	 //data_o <= {4'b0000,32'h0}; // streamid
+	 //@(posedge clk);
+	 if(sendat)
+	   begin
+	      data_o <= {4'b0000,send_secs}; // SECS
+	      @(posedge clk);
+	      data_o <= {4'b0000,32'h0}; // TICS
+	      @(posedge clk);
+	      data_o <= {4'b0000,sendtime}; // TICS
+	      @(posedge clk);
+	   end
 	 for(i=0;i<samples-1;i=i+1)
 	   begin
 	      data_o <= {4'b0000,i,word}; // Payload