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| author | Josh Blum <josh@joshknows.com> | 2012-04-10 12:02:27 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-04-10 12:02:27 -0700 |
| commit | 76f794330649b4fed0bff3617b13c9aa648b5382 (patch) | |
| tree | 280e105505d463762b46a4f192f88b7beced0ee7 /fpga/usrp2/vrt | |
| parent | a1d8b94647b6149ca38282eefac6a5f1e89fad5b (diff) | |
| parent | 510632d8968eb95d383da4cf2d72184d66da0bee (diff) | |
| download | uhd-76f794330649b4fed0bff3617b13c9aa648b5382.tar.gz uhd-76f794330649b4fed0bff3617b13c9aa648b5382.tar.bz2 uhd-76f794330649b4fed0bff3617b13c9aa648b5382.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/vrt')
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_chain.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index ca2f847bc..2788dc9d5 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -41,7 +41,7 @@ module vita_rx_chain wire clear; assign clear_o = clear; wire clear_int; - setting_reg #(.my_addr(BASE+3)) sr + setting_reg #(.my_addr(BASE+8)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_int)); |