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authorJosh Blum <josh@joshknows.com>2010-08-09 16:56:53 -0700
committerJosh Blum <josh@joshknows.com>2010-08-09 16:56:53 -0700
commit349d99c988b2eeb3d13d6229cbd4b80bc9f8153a (patch)
tree1c902bf9199f9f131987e6dec42156c56f481eea /fpga/usrp2/vrt/vita_rx_tb.v
parent55658336cf67810ab8cd7829b9a1fa86c8cd4539 (diff)
parentc174bf9acb2b2d142456f1186bd3e41e40d8a6d1 (diff)
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Merge branch 'features' into uhd_fpga_features
Conflicts: fpga/usrp2/vrt/vita_rx_control.v
Diffstat (limited to 'fpga/usrp2/vrt/vita_rx_tb.v')
-rw-r--r--fpga/usrp2/vrt/vita_rx_tb.v11
1 files changed, 8 insertions, 3 deletions
diff --git a/fpga/usrp2/vrt/vita_rx_tb.v b/fpga/usrp2/vrt/vita_rx_tb.v
index b4fda9622..3e01e2ee2 100644
--- a/fpga/usrp2/vrt/vita_rx_tb.v
+++ b/fpga/usrp2/vrt/vita_rx_tb.v
@@ -3,8 +3,8 @@
module vita_rx_tb;
localparam DECIM = 8'd4;
- localparam MAXCHAN=4;
- localparam NUMCHAN=4;
+ localparam MAXCHAN=1;
+ localparam NUMCHAN=1;
reg clk = 0;
reg reset = 1;
@@ -94,7 +94,7 @@ module vita_rx_tb;
@(posedge clk);
write_setting(4,32'hDEADBEEF); // VITA header
write_setting(5,32'hF00D1234); // VITA streamid
- write_setting(6,32'h98765432); // VITA trailer
+ write_setting(6,32'hF0000000); // VITA trailer
write_setting(7,8); // Samples per VITA packet
write_setting(8,NUMCHAN); // Samples per VITA packet
queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
@@ -111,8 +111,13 @@ module vita_rx_tb;
queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time
queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late
+ #100000;
+ $display("\nChained, break chain\n");
queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain
#100000;
+ $display("\nSingle packet\n");
+ queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet
+ #100000;
$display("\nEnd chain with zero samples, shouldn't error\n");
queue_rx_cmd(1,1,8,32'h0,32'h0); // chained
queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error