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| author | Josh Blum <josh@joshknows.com> | 2010-08-09 16:56:53 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-08-09 16:56:53 -0700 |
| commit | 349d99c988b2eeb3d13d6229cbd4b80bc9f8153a (patch) | |
| tree | 1c902bf9199f9f131987e6dec42156c56f481eea /fpga/usrp2/vrt/vita_rx.build | |
| parent | 55658336cf67810ab8cd7829b9a1fa86c8cd4539 (diff) | |
| parent | c174bf9acb2b2d142456f1186bd3e41e40d8a6d1 (diff) | |
| download | uhd-349d99c988b2eeb3d13d6229cbd4b80bc9f8153a.tar.gz uhd-349d99c988b2eeb3d13d6229cbd4b80bc9f8153a.tar.bz2 uhd-349d99c988b2eeb3d13d6229cbd4b80bc9f8153a.zip | |
Merge branch 'features' into uhd_fpga_features
Conflicts:
fpga/usrp2/vrt/vita_rx_control.v
Diffstat (limited to 'fpga/usrp2/vrt/vita_rx.build')
| -rwxr-xr-x | fpga/usrp2/vrt/vita_rx.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/vrt/vita_rx.build b/fpga/usrp2/vrt/vita_rx.build index f6d2d75a3..010d1be6e 100755 --- a/fpga/usrp2/vrt/vita_rx.build +++ b/fpga/usrp2/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v |