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authorJosh Blum <josh@joshknows.com>2011-11-11 17:53:04 -0800
committerJosh Blum <josh@joshknows.com>2011-11-11 17:53:04 -0800
commitb23126d3a0fca7d56a933e7f2f0011a9d625b006 (patch)
tree175055e4af6ec2a950b5e2b331e0e85a9363db4a /fpga/usrp2/top
parent88e02e0d55f7a80180402c7c86132d22a43ec551 (diff)
parent52b552f43bc1925ce27b4f49dff1669cb019ecfc (diff)
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Merge branch 'fpga_cal_work' into calibration
Diffstat (limited to 'fpga/usrp2/top')
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v2
-rw-r--r--fpga/usrp2/top/E1x0/u1e_core.v2
-rw-r--r--fpga/usrp2/top/N2x0/u2plus_core.v2
-rw-r--r--fpga/usrp2/top/USRP2/u2_core.v2
4 files changed, 4 insertions, 4 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 86bf747a0..c883c5ca8 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -391,7 +391,7 @@ module u1plus_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd0}; //major, minor
+ localparam compat_num = {16'd8, 16'd1}; //major, minor
wire [31:0] reg_test32;
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index 496a7ef4c..aede63bac 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -436,7 +436,7 @@ module u1e_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd0}; //major, minor
+ localparam compat_num = {16'd8, 16'd1}; //major, minor
wire [31:0] reg_test32;
diff --git a/fpga/usrp2/top/N2x0/u2plus_core.v b/fpga/usrp2/top/N2x0/u2plus_core.v
index dd3d33b37..ba9569778 100644
--- a/fpga/usrp2/top/N2x0/u2plus_core.v
+++ b/fpga/usrp2/top/N2x0/u2plus_core.v
@@ -435,7 +435,7 @@ module u2plus_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd0}; //major, minor
+ localparam compat_num = {16'd8, 16'd1}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v
index d3524c304..bc651978d 100644
--- a/fpga/usrp2/top/USRP2/u2_core.v
+++ b/fpga/usrp2/top/USRP2/u2_core.v
@@ -441,7 +441,7 @@ module u2_core
// Buffer Pool Status -- Slave #5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd8, 16'd0}; //major, minor
+ localparam compat_num = {16'd8, 16'd1}; //major, minor
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),