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| author | Josh Blum <josh@joshknows.com> | 2010-12-22 19:25:06 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-12-22 19:25:06 -0800 |
| commit | aebd62b626a8910f5ca92694b56162940f9a09fa (patch) | |
| tree | fbe15be93391be35e837fec567f97d07fe8c6e3d /fpga/usrp2/top | |
| parent | d34565968a4f764252a492de42c0e8f93f2e7666 (diff) | |
| parent | 195c8f9a53b4737478ca4c46fe226bd1d8c6857f (diff) | |
| download | uhd-aebd62b626a8910f5ca92694b56162940f9a09fa.tar.gz uhd-aebd62b626a8910f5ca92694b56162940f9a09fa.tar.bz2 uhd-aebd62b626a8910f5ca92694b56162940f9a09fa.zip | |
Merge branch 'fpga_next' into uhd_next
Diffstat (limited to 'fpga/usrp2/top')
| -rw-r--r-- | fpga/usrp2/top/u2_rev3/u2_core.v | 152 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2_rev3/u2_rev3.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/bootloader.rmi | 461 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus_core.v | 223 |
4 files changed, 424 insertions, 414 deletions
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v index 30b47b818..413931ec9 100644 --- a/fpga/usrp2/top/u2_rev3/u2_core.v +++ b/fpga/usrp2/top/u2_rev3/u2_core.v @@ -3,7 +3,7 @@ // //////////////////////////////////////////////////////////////////////////////// module u2_core - #(parameter RAM_SIZE=32768) + #(parameter RAM_SIZE=16384, parameter RAM_AW=14) (// Clocks input dsp_clk, input wb_clk, @@ -163,7 +163,7 @@ module u2_core wire ram_loader_rst, wb_rst, dsp_rst; assign dsp_rst = wb_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; @@ -286,13 +286,11 @@ module u2_core // /////////////////////////////////////////////////////////////////// // RAM Loader - wire [31:0] ram_loader_dat, if_dat; + wire [31:0] ram_loader_dat; wire [15:0] ram_loader_adr; - wire [14:0] if_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we; - wire iwb_ack, iwb_stb; - ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE)) + ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), @@ -308,36 +306,34 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Processor - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done), // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; + .stack_start(16'h3ff8), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); // ///////////////////////////////////////////////////////////////////////// // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone // I-port connects directly to processor and ram loader wire flush_icache; - ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), - .if_adr(if_adr), - .if_data(if_dat), + .if_adr(16'b0), .if_data(), - .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), .flush_icache(flush_icache)); @@ -359,33 +355,32 @@ module u2_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) - ); - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + ); // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 @@ -427,23 +422,23 @@ module u2_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd3; + localparam compat_num = 32'd4; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), @@ -459,37 +454,39 @@ module u2_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] udp_tx_data, udp_rx_data; - wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; - - udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), - .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), - .debug(debug_udp) ); + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - wire [35:0] tx_err_data, udp1_tx_data; - wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), - .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); + // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -691,7 +688,8 @@ module u2_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), @@ -721,13 +719,13 @@ module u2_core // VITA Timing wire [31:0] debug_sync; - + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int), .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .debug(debug_sync)); - + // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v index f2bba6c50..759f7b7b8 100644 --- a/fpga/usrp2/top/u2_rev3/u2_rev3.v +++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v @@ -471,7 +471,7 @@ module u2_rev3 // - u2_core #(.RAM_SIZE(32768)) + u2_core #(.RAM_SIZE(16384), .RAM_AW(14)) u2_core(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi index 7c15699db..4c7d918c0 100644 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -1,245 +1,216 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_b80801c0_00000000_b808175c_00000000_b8080050; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_b8081764; -defparam bootram.RAM0.INIT_02=256'h3020ffe0_b0000000_30401e70_31a01e98_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_03=256'h3021ffe4_e060f800_b0000000_b8000000_30a30000_b9f40668_80000000_b9f400cc; -defparam bootram.RAM0.INIT_04=256'he8830000_e8601e78_80000000_99fc2000_f8601e78_b8000044_bc030014_f9e10000; -defparam bootram.RAM0.INIT_05=256'h80000000_99fc1800_30a01e8c_bc030010_30600000_b0000000_30630004_be24ffec; -defparam bootram.RAM0.INIT_06=256'h30600000_b0000000_3021001c_b60f0008_e9e10000_f060f800_b0000000_30600001; -defparam bootram.RAM0.INIT_07=256'h80000000_99fc1800_bc03000c_30c0f804_b0000000_30a01e8c_f9e10000_3021ffe4; -defparam bootram.RAM0.INIT_08=256'h80000000_99fc2000_bc04000c_30a01e90_bc030014_30800000_b0000000_e8601e90; -defparam bootram.RAM0.INIT_09=256'h06463800_20e01e98_20c01e98_f9e10000_2021ffec_3021001c_b60f0008_e9e10000; -defparam bootram.RAM0.INIT_0A=256'hb0000000_20c0f800_b0000000_bc92fff4_06463800_20c60004_f8060000_bc720014; -defparam bootram.RAM0.INIT_0B=256'hb9f415f8_bc92fff4_06463800_20c60004_f8060000_bc720014_06463800_20e0f82c; -defparam bootram.RAM0.INIT_0C=256'h32630000_20a00000_b9f401c8_20e00000_20c00000_80000000_b9f41778_80000000; -defparam bootram.RAM0.INIT_0D=256'h20210014_b60f0008_30730000_c9e10000_80000000_b9f415c4_80000000_b9f41780; -defparam bootram.RAM0.INIT_0E=256'he9e10000_f9610004_fa410010_95608001_fa21000c_f9610008_f9e10000_3021ffec; -defparam bootram.RAM0.INIT_0F=256'hbc050018_30210014_b62e0000_ea410010_ea21000c_e9610008_940bc001_e9610004; -defparam bootram.RAM0.INIT_10=256'h3021ff2c_80000000_b60f0008_bc32fff4_16432800_30630001_80000000_10600000; -defparam bootram.RAM0.INIT_11=256'hb9f4062c_32c1001c_3261004c_f8610028_f9e10000_fac100d0_fa6100cc_3061002c; -defparam bootram.RAM0.INIT_12=256'h22407fff_e8610024_bc230038_30a01984_10b30000_b9f40da4_10d60000_10b30000; -defparam bootram.RAM0.INIT_13=256'h30a01984_bc120040_aa430001_30a0194c_e061001c_10a30000_be520034_16439003; -defparam bootram.RAM0.INIT_14=256'he8e10020_e8c10028_b800ffa8_80000000_b9f406c0_b800ffb4_80000000_b9f406cc; -defparam bootram.RAM0.INIT_15=256'h80000000_b9f40694_b800ff88_80000000_b9f406a0_30a0194c_80000000_b9f4155c; -defparam bootram.RAM0.INIT_16=256'hb800ff60_80000000_b9f40678_30a01950_80000000_b9f411e8_30a08000_b0000000; -defparam bootram.RAM0.INIT_17=256'hbe030020_30a00050_31000001_30e1001c_30c000f7_f9e10000_a46500ff_3021ffe0; -defparam bootram.RAM0.INIT_18=256'hb810ffe8_30210020_b60f0008_e9e10000_80000000_b9f40330_f081001c_3080005e; -defparam bootram.RAM0.INIT_19=256'h31000001_b9f40280_f9e10000_30e1001c_30c000f7_30a00050_3021ffe0_308000dc; -defparam bootram.RAM0.INIT_1A=256'h3021ffdc_30210020_b60f0008_6463001f_3063ffff_a863005e_e9e10000_e061001c; -defparam bootram.RAM0.INIT_1B=256'h30a0a120_b0000007_9403c001_ac640002_94808001_fac10020_fa61001c_f9e10000; -defparam bootram.RAM0.INIT_1C=256'hb9f40ea8_80000000_b9f4082c_f800200c_80000000_b9f4fe74_f860200c_306000ff; -defparam bootram.RAM0.INIT_1D=256'h80000000_b9f4ff6c_80000000_b9f4059c_30a01988_80000000_b9f409ec_80000000; -defparam bootram.RAM0.INIT_1E=256'h30a00000_b0000030_bc160100_bc130134_a6632000_e8603334_12c30000_be23017c; -defparam bootram.RAM0.INIT_1F=256'hb0000000_80000000_b9f40558_30a01b04_12c30000_be030068_80000000_b9f41180; -defparam bootram.RAM0.INIT_20=256'hb9f41094_30a08000_b0000000_30c07c00_b9f40e70_30a00000_b0000030_30e08000; -defparam bootram.RAM0.INIT_21=256'he9e10000_30600001_10a00000_b9f41244_80000000_b9f40524_30a01b30_80000000; -defparam bootram.RAM0.INIT_22=256'hb000003f_80000000_b9f404f8_30a01b6c_30210024_b60f0008_eac10020_ea61001c; -defparam bootram.RAM0.INIT_23=256'h80000000_b9f404d4_30a019f8_12630000_be230024_80000000_b9f410fc_30a00000; -defparam bootram.RAM0.INIT_24=256'h30a00000_b000003f_30e08000_b0000000_10730000_b810ffb4_80000000_b9f4fd9c; -defparam bootram.RAM0.INIT_25=256'hb9f40490_30a019bc_80000000_b9f41000_30a08000_b0000000_30c07c00_b9f40ddc; -defparam bootram.RAM0.INIT_26=256'h80000000_b9f40474_30a01a50_30600001_b810ff70_10b60000_b9f411b0_80000000; -defparam bootram.RAM0.INIT_27=256'h80000000_b9f40454_30a01ab4_bc230098_80000000_b9f41000_30a00000_b0000018; -defparam bootram.RAM0.INIT_28=256'h80000000_b9f41048_30a00000_b000003f_80000000_b9f40444_30a0199c_b800fed8; -defparam bootram.RAM0.INIT_29=256'hb9f4fda4_b800fe9c_80000000_b9f4fcec_80000000_b9f40424_30a019f8_bc230028; -defparam bootram.RAM0.INIT_2A=256'h30c07c00_b9f40d24_30a00000_b000003f_30e08000_b0000000_b800fe84_10a00000; -defparam bootram.RAM0.INIT_2B=256'hb9f410f8_80000000_b9f403d8_30a019bc_80000000_b9f40f48_30a08000_b0000000; -defparam bootram.RAM0.INIT_2C=256'hb9f4fc60_30a00001_b9f4fd4c_80000000_b9f403c0_30a01a7c_b800fe50_10b30000; -defparam bootram.RAM0.INIT_2D=256'hfa610020_3021ffd4_b800ff40_80000000_b9f410c8_30a00000_b0000018_30a07530; -defparam bootram.RAM0.INIT_2E=256'hfac10024_30e00001_30c1001c_12e70000_f0c1001c_fae10028_10b30000_a66500ff; -defparam bootram.RAM0.INIT_2F=256'h10b30000_10f60000_10d70000_10830000_be030030_12c80000_b9f40898_f9e10000; -defparam bootram.RAM0.INIT_30=256'h10640000_a8830001_6463001f_3063ffff_80000000_b9f407d0_30800001_be76001c; -defparam bootram.RAM0.INIT_31=256'hfac10024_3021ffcc_3021002c_b60f0008_eae10028_eac10024_ea610020_e9e10000; -defparam bootram.RAM0.INIT_32=256'hf9e10000_12c80000_12e70000_13250000_13060000_fb210030_fb01002c_fae10028; -defparam bootram.RAM0.INIT_33=256'h32d6ffff_e0770000_f301001c_30e00002_be76005c_30c1001c_10b90000_fa610020; -defparam bootram.RAM0.INIT_34=256'hbe33ffcc_32f70001_b9f4089c_30a0000a_12630000_33180001_b9f407f8_f061001d; -defparam bootram.RAM0.INIT_35=256'heb210030_eb01002c_eae10028_eac10024_ea610020_e9e10000_10730000_10b90000; -defparam bootram.RAM0.INIT_36=256'h80000000_b9f4f998_f9e10000_3021ffe4_30600001_b810ffe0_30210034_b60f0008; -defparam bootram.RAM0.INIT_37=256'h12660000_fb21002c_fb010028_fae10024_fa61001c_3021ffd0_80000000_b60f0008; -defparam bootram.RAM0.INIT_38=256'haa43ffff_12c00000_b810001c_f9e10000_fac10020_13260000_12e70000_13050000; -defparam bootram.RAM0.INIT_39=256'h10960000_90630060_10b80000_b9f405ec_32730001_bcb2002c_16572001_bc120030; -defparam bootram.RAM0.INIT_3A=256'he9e10000_10640000_f0130000_14999800_32d60001_be32ffd4_aa43000a_f0730000; -defparam bootram.RAM0.INIT_3B=256'h3021ffd0_30210030_b60f0008_eb21002c_eb010028_eae10024_eac10020_ea61001c; -defparam bootram.RAM0.INIT_3C=256'h13260000_12e70000_13050000_12660000_fb21002c_fb010028_fae10024_fa61001c; -defparam bootram.RAM0.INIT_3D=256'hb9f4051c_32730001_bcb2002c_16572001_12c00000_b8100014_f9e10000_fac10020; -defparam bootram.RAM0.INIT_3E=256'h14999800_32d60001_be32ffdc_aa43000a_f0730000_10960000_90630060_10b80000; -defparam bootram.RAM0.INIT_3F=256'heb21002c_eb010028_eae10024_eac10020_ea61001c_e9e10000_10640000_f0130000; -defparam bootram.RAM1.INIT_00=256'h12e60000_12c50000_fae10024_fac10020_fa61001c_3021ffd8_30210030_b60f0008; -defparam bootram.RAM1.INIT_01=256'hbe32ffec_aa43000a_f0730000_90630060_10b60000_b9f404b0_12660000_f9e10000; -defparam bootram.RAM1.INIT_02=256'heae10024_eac10020_ea61001c_e9e10000_10770000_f0130000_3273ffff_32730001; -defparam bootram.RAM1.INIT_03=256'he9e10000_10a00000_b9f4ff94_f9e10000_3021ffe4_10c50000_30210028_b60f0008; -defparam bootram.RAM1.INIT_04=256'hb60f0008_e9e10000_80000000_b9f40448_f9e10000_3021ffe4_3021001c_b60f0008; -defparam bootram.RAM1.INIT_05=256'h3021001c_b60f0008_e9e10000_10a00000_b9f4ffdc_f9e10000_3021ffe4_3021001c; -defparam bootram.RAM1.INIT_06=256'hbe060024_90c30060_12660000_e0660000_f9e10000_fac10020_fa61001c_3021ffdc; -defparam bootram.RAM1.INIT_07=256'h10b60000_be26fff0_90c30060_e0730000_32730001_b9f40324_10b60000_12c50000; -defparam bootram.RAM1.INIT_08=256'hfac1001c_3021ffe0_30210024_b60f0008_10600000_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_09=256'heac1001c_e9e10000_30c0000a_b9f402dc_10b60000_12c50000_b9f4ff9c_f9e10000; -defparam bootram.RAM1.INIT_0A=256'h10a00000_b9f4ffc0_f9e10000_3021ffe4_10c50000_30210020_b60f0008_10600000; -defparam bootram.RAM1.INIT_0B=256'h10a00000_b9f4ff48_f9e10000_3021ffe4_10c50000_3021001c_b60f0008_e9e10000; -defparam bootram.RAM1.INIT_0C=256'he9e10000_30c0000a_b9f40278_f9e10000_3021ffe4_3021001c_b60f0008_e9e10000; -defparam bootram.RAM1.INIT_0D=256'hb9f40250_f9e10000_10a00000_12c50000_fac1001c_3021ffe0_3021001c_b60f0008; -defparam bootram.RAM1.INIT_0E=256'hfac1001c_3021ffe0_30210020_b60f0008_eac1001c_e9e10000_10760000_10d60000; -defparam bootram.RAM1.INIT_0F=256'h30210020_b60f0008_eac1001c_e9e10000_10760000_12c60000_b9f40228_f9e10000; -defparam bootram.RAM1.INIT_10=256'h94e08001_3021001c_b60f0008_e9e10000_80000000_b9f401b8_f9e10000_3021ffe4; -defparam bootram.RAM1.INIT_11=256'h80633000_84632000_84c62800_a866ffff_e880f81c_b0000000_9404c001_ac870002; -defparam bootram.RAM1.INIT_12=256'h9404c001_80843800_ac840002_94808001_a4e70002_f860f81c_b0000000_f860200c; -defparam bootram.RAM1.INIT_13=256'h88a52000_e880f81c_b0000000_9406c001_acc30002_94608001_80000000_b60f0008; -defparam bootram.RAM1.INIT_14=256'h9404c001_80841800_ac840002_94808001_a4630002_f8a0f81c_b0000000_f8a0200c; -defparam bootram.RAM1.INIT_15=256'ha866ffff_e880f820_b0000000_9404c001_ac870002_94e08001_80000000_b60f0008; -defparam bootram.RAM1.INIT_16=256'h94808001_a4e70002_f860f820_b0000000_f8602020_80633000_84632000_84c62800; -defparam bootram.RAM1.INIT_17=256'hfae10024_fa61001c_3021ffd4_80000000_b60f0008_9404c001_80843800_ac840002; -defparam bootram.RAM1.INIT_18=256'hbe060040_90c30060_13050000_12e60000_e0660000_fac10020_f9e10000_fb010028; -defparam bootram.RAM1.INIT_19=256'h10730000_be120028_16569800_32c70001_b8100014_32600001_be670038_12660000; -defparam bootram.RAM1.INIT_1A=256'h10730000_3273ffff_32730001_be26ffe4_90c30060_c0779800_10b80000_b9f400cc; -defparam bootram.RAM1.INIT_1B=256'h3021ffe4_3021002c_b60f0008_eb010028_eae10024_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_1C=256'hf0c51e7c_3021001c_b60f0008_e9e10000_30c0000a_b9f40084_f9e10000_10a00000; -defparam bootram.RAM1.INIT_1D=256'h80000000_b60f0008_f8653700_64a50405_e4661bac_10c63000_80000000_b60f0008; -defparam bootram.RAM1.INIT_1E=256'h90c60060_b9f4ffc4_10b30000_e0d31e7c_12600000_f9e10000_fa61001c_3021ffe0; -defparam bootram.RAM1.INIT_1F=256'he9e10000_bc32ffd8_aa530003_90c60060_b9f4ffbc_32730001_10b30000_e0d31ba8; -defparam bootram.RAM1.INIT_20=256'h12c60000_f9e10000_fac10020_fa61001c_3021ffdc_30210020_b60f0008_ea61001c; -defparam bootram.RAM1.INIT_21=256'hfac5000c_bc03fffc_e8650004_30a33700_64730405_12650000_be120030_aa46000a; -defparam bootram.RAM1.INIT_22=256'hbc32ffd0_aa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000; -defparam bootram.RAM1.INIT_23=256'hf9e10000_fac10020_fa61001c_3021ffdc_64730405_b810ffc8_30c0000d_b9f4ffac; -defparam bootram.RAM1.INIT_24=256'hbc040008_e8830004_30633700_64730405_12650000_be120030_aa46000a_12c60000; -defparam bootram.RAM1.INIT_25=256'haa430001_e0651e7c_30210024_b60f0008_eac10020_ea61001c_e9e10000_fac3000c; -defparam bootram.RAM1.INIT_26=256'h30a53700_64a50405_64730405_b810ffc4_80000000_b9f4ff44_30c0000d_be32ffd0; -defparam bootram.RAM1.INIT_27=256'he8650008_30a53700_64a50405_80000000_b60f0008_e8650010_bc03fffc_e8650008; -defparam bootram.RAM1.INIT_28=256'h64a50405_80000000_b60f0008_90630060_be24fff8_e8850008_e8650010_bc030014; -defparam bootram.RAM1.INIT_29=256'h32600001_be230040_e8760008_32c53700_fa61001c_f9e10000_fac10020_3021ffdc; -defparam bootram.RAM1.INIT_2A=256'hbe03ffe8_e8760008_30a00001_b9f401e0_3060ffff_be120034_aa53012d_b8000010; -defparam bootram.RAM1.INIT_2B=256'he9e10000_e8760010_3060ffff_be52000c_16539001_3240012b_3273ffff_32730001; -defparam bootram.RAM1.INIT_2C=256'h32400004_a463000f_e8603324_f8003108_30210024_b60f0008_eac10020_ea61001c; -defparam bootram.RAM1.INIT_2D=256'ha46300ff_64a30008_e4641bb8_10831800_30600004_10831800_beb20010_16439001; -defparam bootram.RAM1.INIT_2E=256'ha4a500ff_be070088_80000000_b60f0008_f8603108_30600080_f8a03104_f8603100; -defparam bootram.RAM1.INIT_2F=256'hf8803110_30800090_f860310c_a0630001_10652800_be23fff8_a4630040_e8603110; -defparam bootram.RAM1.INIT_30=256'haa470001_10800000_be230058_a4630080_e8603110_bc23fff8_a4630002_e8603110; -defparam bootram.RAM1.INIT_31=256'h30e7ffff_e860310c_bc23fff8_a4630002_e8603110_f8603110_30600020_be120038; -defparam bootram.RAM1.INIT_32=256'h30600068_b810ffd0_30600020_be32ffd8_aa470001_30c60001_be07001c_f0660000; -defparam bootram.RAM1.INIT_33=256'ha4a500ff_10640000_b60f0008_f8603110_30600040_10640000_b60f0008_30800001; -defparam bootram.RAM1.INIT_34=256'h306000d0_30600090_be27000c_f860310c_10652800_be23fff8_a4630040_e8603110; -defparam bootram.RAM1.INIT_35=256'h10800000_be23005c_a4630080_e8603110_bc23fff8_a4630002_e8603110_f8603110; -defparam bootram.RAM1.INIT_36=256'hf8803110_bc120030_aa470001_f860310c_30800010_e0660000_30800001_be070068; -defparam bootram.RAM1.INIT_37=256'hbe070028_30e7ffff_be23001c_a4630080_e8603110_bc23fff8_a4630002_e8603110; -defparam bootram.RAM1.INIT_38=256'hb60f0008_f8603110_30600040_10800000_30800050_b810ffd4_b800ffc4_30c60001; -defparam bootram.RAM1.INIT_39=256'hbc260054_a4c30000_b0008000_e8603324_10640000_b60f0008_30800001_10640000; -defparam bootram.RAM1.INIT_3A=256'h80000000_10800000_bc660030_e8c01e80_10660000_be650048_bc430054_e8601e80; -defparam bootram.RAM1.INIT_3B=256'h16443000_30840001_80000000_80000000_80000000_80000000_80000000_80000000; -defparam bootram.RAM1.INIT_3C=256'ha4630007_e8603324_80000000_b60f0008_bc32ffc8_16432800_30630001_bc32ffdc; -defparam bootram.RAM1.INIT_3D=256'h16459001_3240005a_3065ffa9_90a50060_b800ff9c_f8801e80_e4831bc4_10631800; -defparam bootram.RAM1.INIT_3E=256'h3085ffd0_be52000c_16459001_32400039_a46300ff_3065ffc9_a46300ff_be520024; -defparam bootram.RAM1.INIT_3F=256'hf9e10000_fb610034_13250000_fb21002c_3021ffc8_80000000_b60f0008_a46400ff; -defparam bootram.RAM2.INIT_00=256'haa43003a_13660000_e0790000_fb410030_fb010028_fae10024_fac10020_fa61001c; -defparam bootram.RAM2.INIT_01=256'heb010028_eae10024_eac10020_ea61001c_e9e10000_10650000_30a0ffff_be120034; -defparam bootram.RAM2.INIT_02=256'hc085c800_30a00001_e8c01e84_30210038_b60f0008_eb610034_eb410030_eb21002c; -defparam bootram.RAM2.INIT_03=256'hb810ffac_bc23ffe4_a4630044_c0662000_a4a300ff_be04001c_90840060_30650001; -defparam bootram.RAM2.INIT_04=256'h12761800_66c30404_b9f4ff1c_e0b90002_80000000_b9f4ff28_e0b90001_30a0fffe; -defparam bootram.RAM2.INIT_05=256'he0b90005_30a0fffd_be38ff74_93040060_e083000b_10791800_fa7b0004_10739800; -defparam bootram.RAM2.INIT_06=256'h66c3040c_b9f4fed8_e0b90004_66e30404_b9f4fee4_e0b90003_13530000_b9f4fef0; -defparam bootram.RAM2.INIT_07=256'he0b90007_fafb0008_12f7b000_12d61800_12d61800_b9f4fec8_64630408_e0b90006; -defparam bootram.RAM2.INIT_08=256'hbe130060_f07b0000_1063b000_66c30404_b9f4fea4_e0b90008_80000000_b9f4feb0; -defparam bootram.RAM2.INIT_09=256'hb9f4fe74_c0b6c800_a6d600ff_32d60009_12d8c000_ea7b000c_13580000_10f30000; -defparam bootram.RAM2.INIT_0A=256'he8fb0004_ea7b000c_d0789800_1063b800_66e30404_b9f4fe68_e0b60001_12d9b000; -defparam bootram.RAM2.INIT_0B=256'headb0008_a74300ff_be52ffb8_1647c003_107a1800_a70400ff_c073c000_30980001; -defparam bootram.RAM2.INIT_0C=256'h107a1800_12c7b000_10632000_e0b70009_12f9b800_64760008_12e73800_e09b0000; -defparam bootram.RAM2.INIT_0D=256'ha6d600ff_1063c000_16d60000_67030404_b9f4fe04_e0b7000a_12d61800_b9f4fe10; -defparam bootram.RAM2.INIT_0E=256'ha4630100_e8603b10_10a00000_b810fe58_30a0fffb_be32fe60_1643b000_a46300ff; -defparam bootram.RAM2.INIT_0F=256'ha4a500ff_80884800_a1292000_a508007f_a5290600_80000000_b60f0008_bc23fff8; -defparam bootram.RAM2.INIT_10=256'ha0840100_f8603b18_a46600ff_f8803b10_f8e03b00_bc23fff8_a4630100_e8603b10; -defparam bootram.RAM2.INIT_11=256'hb60f0008_e8603b00_bc23fff8_a4630100_e8603b10_10650000_be050018_f8803b10; -defparam bootram.RAM2.INIT_12=256'h31200400_31000008_10a00000_f9e10000_3021ffe4_10e60000_10c00000_80000000; -defparam bootram.RAM2.INIT_13=256'h3021ffc4_3021001c_b60f0008_e9e10000_80000000_b9f4ff84_f8603b14_30600001; -defparam bootram.RAM2.INIT_14=256'hb9f4ff3c_fae10034_13060000_f9e10000_fb010038_fa61002c_12c50000_fac10030; -defparam bootram.RAM2.INIT_15=256'hfac03b00_f8603b04_3060000b_66d60408_f8603b10_f8003b18_30600400_12670000; -defparam bootram.RAM2.INIT_16=256'h80000000_b9f4ff00_f8603b10_30600528_f8803b10_30800428_f8603b18_30600001; -defparam bootram.RAM2.INIT_17=256'hf8803b10_30800500_f8603b10_30600400_3261001c_12e00000_12d30000_be18009c; -defparam bootram.RAM2.INIT_18=256'he8803b04_f8610020_e8603b08_f881001c_14b7c000_e8803b0c_80000000_b9f4fed8; -defparam bootram.RAM2.INIT_19=256'h30a00010_10800000_beb20034_16459003_22400010_f8610028_e8603b00_f8810024; -defparam bootram.RAM2.INIT_1A=256'hbeb20020_1658b803_12f72800_bc32fff0_16442800_30840001_d0762000_c0732000; -defparam bootram.RAM2.INIT_1B=256'hf8003b18_12d62800_be52ff7c_1658b803_12f72800_bc25ffd8_b800ff8c_12d62800; -defparam bootram.RAM2.INIT_1C=256'hb0009f00_3021003c_b60f0008_eb010038_eae10034_eac10030_ea61002c_e9e10000; -defparam bootram.RAM2.INIT_1D=256'h31200400_b9f4fe34_f9e10000_31000020_30c00001_30a00001_3021ffe4_30e00000; -defparam bootram.RAM2.INIT_1E=256'h3021ffe4_e860f828_b0000000_3021001c_b60f0008_a463ffff_b00000ff_e9e10000; -defparam bootram.RAM2.INIT_1F=256'h64830008_80000000_b9f4ffa8_3021001c_b60f0008_e9e10000_bc030010_f9e10000; -defparam bootram.RAM2.INIT_20=256'h16439001_32400015_80000000_b9f40330_a46300ff_be120010_aa440020_a48400ff; -defparam bootram.RAM2.INIT_21=256'hb0000000_b800ffb0_f860f828_b0000000_bc52ffe4_16439001_32400018_bcb2fff0; -defparam bootram.RAM2.INIT_22=256'hb9f4ff40_3021001c_b60f0008_e9e10000_bc030010_f9e10000_3021ffe4_e860f824; -defparam bootram.RAM2.INIT_23=256'h80000000_b9f402c8_a4a300ff_be120010_aa440020_a48400ff_64830008_80000000; -defparam bootram.RAM2.INIT_24=256'hb0000000_e0651bbe_bc52ffe4_16459001_32400018_bcb2fff0_16459001_32400015; -defparam bootram.RAM2.INIT_25=256'h10c50000_12c00000_fac1001c_3021ffe0_b800ffa4_f860f824_b0000000_f8a0f828; -defparam bootram.RAM2.INIT_26=256'heac1001c_e9e10000_80000000_99fcb000_30e00024_b9f40334_f9e10000_10b60000; -defparam bootram.RAM2.INIT_27=256'hb810001c_30e1001c_b9f4fd88_f9e10000_30c00040_3021ffa4_30210020_b60f0008; -defparam bootram.RAM2.INIT_28=256'he063001c_10612800_10600000_be520044_16459001_3240003e_30a50001_10a00000; -defparam bootram.RAM2.INIT_29=256'haa440099_e083001c_10612800_30a50001_bc32ffd8_aa4300aa_bc12ffe0_aa4300ff; -defparam bootram.RAM2.INIT_2A=256'h3021005c_b60f0008_e9e10000_3021005c_b60f0008_e9e10000_30600001_be32ffc8; -defparam bootram.RAM2.INIT_2B=256'h10b60000_30c00006_b9f4fd08_f9e10000_10f60000_32c1001c_fac10028_3021ffd4; -defparam bootram.RAM2.INIT_2C=256'heac10028_e9e10000_a884ffff_80841800_14830000_30e00006_b9f401f8_30c01bd8; -defparam bootram.RAM2.INIT_2D=256'h65040403_64e40003_64a40007_64c40005_e0803a03_3021002c_b60f0008_6464001f; -defparam bootram.RAM2.INIT_2E=256'ha4a50008_80e73000_90a40041_a4e70004_80c62800_a4c60002_64640407_65240405; -defparam bootram.RAM2.INIT_2F=256'h81294000_a5290040_81082000_a5080020_80842800_a4840010_80a53800_10842000; -defparam bootram.RAM2.INIT_30=256'h64e50403_64c50003_64650007_64850005_a4a500ff_a46300ff_b60f0008_80634800; -defparam bootram.RAM2.INIT_31=256'ha4630008_80c62000_90650041_a4c60004_80841800_a4840002_65250407_65050405; -defparam bootram.RAM2.INIT_32=256'h81083800_a5080040_80e72800_a4e70020_80a51800_a4a50010_80633000_10a52800; -defparam bootram.RAM2.INIT_33=256'hb00000ff_fac1001c_3021ffe0_80000000_b60f0008_f9203a00_a52900ff_81294000; -defparam bootram.RAM2.INIT_34=256'h30a0ffaa_b9f4ff74_30a0ffff_b9f4ff7c_30a0ffff_b9f4ff84_f9e10000_a6c5ffff; -defparam bootram.RAM2.INIT_35=256'h30a00061_b9f4ff54_30a00032_b9f4ff5c_a2d60000_b0000b00_30a0ff99_b9f4ff6c; -defparam bootram.RAM2.INIT_36=256'h30a0ff81_b9f4ff34_30a00032_b9f4ff3c_10b60000_b9f4ff44_64b60008_b9f4ff4c; -defparam bootram.RAM2.INIT_37=256'h30a0ffa1_b9f4ff14_30a00030_b9f4ff1c_64b60010_b9f4ff24_30a0000b_b9f4ff2c; -defparam bootram.RAM2.INIT_38=256'h10a00000_b9f4fef4_30a00020_b9f4fefc_30a0000e_b9f4ff04_10a00000_b9f4ff0c; -defparam bootram.RAM2.INIT_39=256'h30210020_b60f0008_eac1001c_e9e10000_10a00000_b9f4fee4_30a00020_b9f4feec; -defparam bootram.RAM2.INIT_3A=256'hb6110000_30a0ffff_b9f4e91c_80000000_b9f4f220_f9e10000_3021ffe4_30a01be0; -defparam bootram.RAM2.INIT_3B=256'h22400003_80000000_b60f0008_80000000_b60f0008_80000000_b6910000_80000000; -defparam bootram.RAM2.INIT_3C=256'h16432000_e8660000_e8850000_bc230050_a4630003_80653000_beb2005c_16479003; -defparam bootram.RAM2.INIT_3D=256'h30e7ffff_30c60004_be52ffe0_16479003_22400003_30a50004_30e7fffc_bc320040; -defparam bootram.RAM2.INIT_3E=256'h30c60001_30a50001_be320020_16434000_e0660000_e1050000_bc120028_aa47ffff; -defparam bootram.RAM2.INIT_3F=256'h2240000f_14634000_b60f0008_10600000_b60f0008_bc32ffe0_aa47ffff_30e7ffff; -defparam bootram.RAM3.INIT_00=256'hbc070024_11050000_be030034_a4630003_80662800_10850000_beb20018_16479003; -defparam bootram.RAM3.INIT_01=256'h30c60001_be32fff0_16474000_31080001_f0680000_e0660000_10e72000_11040000; -defparam bootram.RAM3.INIT_02=256'he8860008_f8680004_e8660004_f8880000_30e7fff0_e8860000_10650000_b60f0008; -defparam bootram.RAM3.INIT_03=256'h31080010_be52ffd0_16479003_2240000f_f868000c_30c60010_e866000c_f8880008; -defparam bootram.RAM3.INIT_04=256'h22400003_d8682000_30e7fffc_c8662000_10800000_bcb2002c_16479003_22400003; -defparam bootram.RAM3.INIT_05=256'he860193c_10880000_b810ff68_11044000_10c43000_30840004_be52ffec_16479003; -defparam bootram.RAM3.INIT_06=256'h3273fffc_99fc1800_bc120018_aa43ffff_3260193c_f9e10000_fa61001c_3021ffe0; -defparam bootram.RAM3.INIT_07=256'h3021fff8_30210020_b60f0008_ea61001c_e9e10000_bc32fff0_aa43ffff_e8730000; -defparam bootram.RAM3.INIT_08=256'h30210008_b60f0008_c9e00800_80000000_b9f4ffb0_80000000_b9f4e7d4_d9e00800; -defparam bootram.RAM3.INIT_09=256'hffffffff_30210008_b60f0008_c9e00800_80000000_b9f4e74c_d9e00800_3021fff8; -defparam bootram.RAM3.INIT_0A=256'h696d6167_61696e20_523a206d_4552524f_4f4b0000_00000000_ffffffff_00000000; -defparam bootram.RAM3.INIT_0B=256'h64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e_65207265; -defparam bootram.RAM3.INIT_0C=256'h53746172_720a0000_6f616465_6f6f746c_322b2062_55535250_4e4f4b00_64652e00; -defparam bootram.RAM3.INIT_0D=256'h4552524f_2e000000_6d6f6465_61666520_696e2073_50322b20_20555352_74696e67; -defparam bootram.RAM3.INIT_0E=256'h20546869_72616d21_70726f67_61696e20_6f6d206d_6e206672_65747572_523a2072; -defparam bootram.RAM3.INIT_0F=256'h523a206e_4552524f_6e210000_61707065_65722068_206e6576_6f756c64_73207368; -defparam bootram.RAM3.INIT_10=256'h626c652e_61696c61_65206176_696d6167_61726520_69726d77_66652066_6f207361; -defparam bootram.RAM3.INIT_11=256'h6c6f6164_20746f20_66726565_65656c20_6b2e2046_62726963_6d206120_20492061; -defparam bootram.RAM3.INIT_12=256'h2076616c_20666f72_6b696e67_43686563_2e000000_2052414d_5820746f_20494845; -defparam bootram.RAM3.INIT_13=256'h56616c69_2e2e2e00_6d616765_47412069_6e204650_6374696f_726f6475_69642070; -defparam bootram.RAM3.INIT_14=256'h642e2041_666f756e_61676520_4120696d_20465047_74696f6e_6f647563_64207072; -defparam bootram.RAM3.INIT_15=256'h2070726f_616c6964_4e6f2076_742e0000_20626f6f_6720746f_7074696e_7474656d; -defparam bootram.RAM3.INIT_16=256'h74656d70_2e0a4174_6f756e64_67652066_20696d61_46504741_696f6e20_64756374; -defparam bootram.RAM3.INIT_17=256'h77617265_6669726d_696f6e20_64756374_2070726f_6c6f6164_20746f20_74696e67; -defparam bootram.RAM3.INIT_18=256'h6520666f_6d776172_20666972_74696f6e_6f647563_64207072_56616c69_2e2e2e00; -defparam bootram.RAM3.INIT_19=256'h6e206672_65747572_523a2052_4552524f_2e2e2e00_64696e67_204c6f61_756e642e; -defparam bootram.RAM3.INIT_1A=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; -defparam bootram.RAM3.INIT_1B=256'h696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000_61707065_65722068; -defparam bootram.RAM3.INIT_1C=256'h6669726d_61666520_6e672073_54727969_6e642e20_20666f75_77617265_6669726d; -defparam bootram.RAM3.INIT_1D=256'h0018000f_ffff0031_01b200d9_05160364_14580a2c_05050400_2e2e2e00_77617265; -defparam bootram.RAM3.INIT_1E=256'hb8080000_b0000000_10101200_06820594_09c407d0_13880d05_00002710_000b0000; -defparam bootram.RAM3.INIT_1F=256'h20202020_28282820_20202828_20202020_00202020_00000000_6f72740a_0a0a6162; -defparam bootram.RAM3.INIT_20=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; -defparam bootram.RAM3.INIT_21=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; -defparam bootram.RAM3.INIT_22=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; -defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; -defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2B=256'h28282020_20282828_20202020_20202020_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2C=256'h10101010_10101010_10101010_88101010_20202020_20202020_20202020_20202020; -defparam bootram.RAM3.INIT_2D=256'h01010101_01010101_41414101_10414141_10101010_04041010_04040404_04040404; -defparam bootram.RAM3.INIT_2E=256'h02020202_02020202_42424202_10424242_10101010_01010110_01010101_01010101; -defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_10101020_02020210_02020202_02020202; -defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_33=256'h01010100_00001948_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001d70_ffffffff; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4b70400_3a0b0b0b_0bae9c0c_80700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4f42d_88080b0b_80088408; +defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; +defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; +defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; +defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722473; +defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; +defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; +defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88; +defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06; +defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; +defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; +defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_0F=256'h00000000_00000000_00000000_53510400_0a098106_81050906_72050970_72098105; +defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_52040000_71098105; +defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; +defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; +defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_88738306_0b0b0bae_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ae2d5050_0b0b0b9e_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_e02d5050_0b0b0b9f_88087575_80088408; +defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; +defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; +defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae980c_810b0b0b; +defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; +defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; +defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_943f0410_81f33f9e; +defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; +defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; +defparam bootram.RAM0.INIT_23=256'hec0c8290_a0800bb5_b5e80c82_0b0b0b0b_38838080_08822eb9_a138ae9c_9808802e; +defparam bootram.RAM0.INIT_24=256'h80808480_b5ec0cf8_8082800b_e80cf880_0b0b0bb5_8080a40b_0c04f880_800bb5f0; +defparam bootram.RAM0.INIT_25=256'h0ba6c40b_ec0c0b0b_80940bb5_0c80c0a8_0b0bb5e8_808c0b0b_0480c0a8_0bb5f00c; +defparam bootram.RAM0.INIT_26=256'haea40c70_92388412_5270802e_08700852_a338aea4_f4335170_ff3d0db5_b5f00c04; +defparam bootram.RAM0.INIT_27=256'he408802e_0b0b0bb5_04803d0d_833d0d04_0bb5f434_70f03881_70085252_2daea408; +defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5e4_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; +defparam bootram.RAM0.INIT_29=256'h518bc93f_d0055273_3fb23dfe_525486a0_59923d70_3dfee005_d03d0db2_3d0d0404; +defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_c93fa6c8_52735198_38765378_ff74278f_775481ff_8008b238; +defparam bootram.RAM0.INIT_2B=256'hb039803d_859e3fff_39a78051_a6cc5184_3f91d73f_c85185ac_068f38a6_812e0981; +defparam bootram.RAM0.INIT_2C=256'h0ca78851_0b81a08c_3d0d81ff_3d0d04fc_51f63982_380bff11_70ff2e87_0dff1351; +defparam bootram.RAM0.INIT_2D=256'h81ff0655_ee3f8008_84e23f83_3fa78451_e13f86d6_85e13f8e_81a08c0c_dd3f800b; +defparam bootram.RAM0.INIT_2E=256'h81fc8080_5184bd3f_c338a7b0_51547380_70810651_08708d2a_3f81c6b4_805182ed; +defparam bootram.RAM0.INIT_2F=256'h8eab3f90_fc808051_ffff5281_80805380_82c33f82_a6388151_8008802e_5190b63f; +defparam bootram.RAM0.INIT_30=256'he45183f8_74b238a8_3ffe8d3f_8c518484_3f8a39a8_73519192_5184913f_c53fa7d0; +defparam bootram.RAM0.INIT_31=256'hfec03fb0_3f82ac51_815181f9_5183e53f_9938a990_8008802e_518fa13f_3fb0800a; +defparam bootram.RAM0.INIT_32=256'h83ba3f82_38aa9851_08802eaa_8fc73f80_98800a51_5183cd3f_d93fa9c8_800a5190; +defparam bootram.RAM0.INIT_33=256'h3faae851_853f8fca_82ac51fe_5183a53f_bc3faac4_800a518d_ffff5298_80805380; +defparam bootram.RAM0.INIT_34=256'h5380ffff_38828080_08802eb5_80085480_518f8a3f_81fc8080_5183913f_ba39aba4; +defparam bootram.RAM0.INIT_35=256'hdb3f82ac_a7d05182_3f8f8f3f_ac51fdca_82ea3f82_3faac451_80518d81_5281fc80; +defparam bootram.RAM0.INIT_36=256'h04f83d0d_0c863d0d_cf3f7380_82c63ffc_39a88c51_3f81548a_80518fd6_51fdbb3f; +defparam bootram.RAM0.INIT_37=256'h70810558_8a3d3476_17575473_b7387581_54807425_74ff1656_5a575758_7a7c7f7f; +defparam bootram.RAM0.INIT_38=256'h8a5186fd_81ff0654_cf3f8008_ff065185_05527781_538a3dfc_a1053482_33028405; +defparam bootram.RAM0.INIT_39=256'h748338dc_5580de56_02a30533_04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e; +defparam bootram.RAM0.INIT_3A=256'h7c5702ab_04f93d0d_3f883d0d_d051ff89_81f75280_3dfc0553_34815488_5675883d; +defparam bootram.RAM0.INIT_3B=256'h56547380_81ff0670_ef3f8008_70525684_02a70533_3dfc0552_34815389_0533893d; +defparam bootram.RAM0.INIT_3C=256'h83388155_5473802e_ff067056_3f800881_755183b2_76537b52_77259738_2e9e3880; +defparam bootram.RAM0.INIT_3D=256'h883d3356_a03f800b_80d051ff_5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89; +defparam bootram.RAM0.INIT_3E=256'h7081ff06_56567433_3d0d7779_3d0d04fb_75800c88_83388156_2e098106_567480de; +defparam bootram.RAM0.INIT_3F=256'h0d04fe3d_800c873d_e539800b_5581bb3f_06537652_157481ff_2e903881_54547280; +defparam bootram.RAM1.INIT_00=256'h528051de_ff3d0d73_843d0d04_800b800c_51819f3f_3f8a5272_705253cb_0d747653; +defparam bootram.RAM1.INIT_01=256'h800881ff_80087334_5181b23f_81135374_55558439_76787055_04fc3d0d_3f833d0d; +defparam bootram.RAM1.INIT_02=256'h3f833d0d_528051c9_ff3d0d73_863d0d04_3473800c_e7388073_2e098106_0652718a; +defparam bootram.RAM1.INIT_03=256'h7510abe0_81ce8005_0d73a029_0d04ff3d_1234823d_0533aea8_7251028f_04803d0d; +defparam bootram.RAM1.INIT_04=256'h33527251_3faeac13_527251c9_aea81333_3d0d8053_3d0d04fe_0c535183_05702272; +defparam bootram.RAM1.INIT_05=256'h38aea814_09810694_54748a2e_0d767856_0d04fc3d_e738843d_53827325_d13f8113; +defparam bootram.RAM1.INIT_06=256'h72802ef8_84140853_ce800554_73a02981_7351df3f_87388d52_2e098106_33537281; +defparam bootram.RAM1.INIT_07=256'h38901208_70802ef8_88120851_ce800552_73a02981_04ff3d0d_0c863d0d_38748c15; +defparam bootram.RAM1.INIT_08=256'h38845170_84712583_8f065151_c6a40870_c2880c81_0d800b81_0d04ff3d_800c833d; +defparam bootram.RAM1.INIT_09=256'h880c833d_800b81c2_0c515181_2a81c284_800c7088_ff0681c2_70227081_10aeb005; +defparam bootram.RAM1.INIT_0A=256'h70862a70_81c29008_2e818638_81517180_33555354_88059705_0d767802_0d04fd3d; +defparam bootram.RAM1.INIT_0B=256'h812a7081_c2900870_c2900c81_81900b81_81c28c0c_72108107_5170f138_81065151; +defparam bootram.RAM1.INIT_0C=256'h3871802e_70802eba_51515151_06708132_872a7081_c2900870_70f13881_06515151; +defparam bootram.RAM1.INIT_0D=256'h515170f1_70810651_0870812a_0c81c290_7081c290_8338a051_5171812e_b13880e8; +defparam bootram.RAM1.INIT_0E=256'h0c70800c_0b81c290_883980c0_cc398151_34ff1252_70810556_08517074_3881c28c; +defparam bootram.RAM1.INIT_0F=256'h51515170_2a708106_90087086_535481c2_97053355_78028805_fd3d0d76_853d0d04; +defparam bootram.RAM1.INIT_10=256'h70812a70_81c29008_81c2900c_81905170_802e8438_81d05171_81c28c0c_f1387210; +defparam bootram.RAM1.INIT_11=256'h80cf3871_5170802e_32515151_81067081_70872a70_81c29008_5170f138_81065151; +defparam bootram.RAM1.INIT_12=256'h90087081_900c81c2_517081c2_2e833890_d0517181_c28c0c80_38733381_802e80c5; +defparam bootram.RAM1.INIT_13=256'h802e8e38_51515170_70813251_2a708106_90087087_f13881c2_51515170_2a708106; +defparam bootram.RAM1.INIT_14=256'h04ff3d0d_0c853d0d_80517080_81c2900c_3980c00b_3981518a_5354ffb7_8114ff13; +defparam bootram.RAM1.INIT_15=256'hc01122ae_108e06ae_c6a40870_25923881_aebc0880_7124a638_08525280_7381c6a4; +defparam bootram.RAM1.INIT_16=256'hffa91170_028f0533_04ff3d0d_38833d0d_115170fb_387151ff_80722589_bc0c5151; +defparam bootram.RAM1.INIT_17=256'h81ff0651_38d01270_71b92689_ff065151_c9127081_da269638_52527180_81ff0651; +defparam bootram.RAM1.INIT_18=256'h82ef3881_2e098106_ff5371ba_76335358_7b585680_f93d0d79_833d0d04_5170800c; +defparam bootram.RAM1.INIT_19=256'hc4065151_11337080_7033abf5_ff067219_81147081_2eaa3872_53537178_0b811733; +defparam bootram.RAM1.INIT_1A=256'h08842b9f_fefb3f80_81163351_5271d838_16703351_82bd3872_5271802e_51535154; +defparam bootram.RAM1.INIT_1B=256'h5354fd53_8b113357_0c701017_05708419_81ff0672_ec3f8008_335252fe_f0068217; +defparam bootram.RAM1.INIT_1C=256'h08882b83_febb3f80_17335253_e0800684_088c2bbf_fecb3f80_83163351_74828a38; +defparam bootram.RAM1.INIT_1D=256'h983f8008_335253fe_73058617_2b9ff006_3f800884_5253fea9_05851733_fe800673; +defparam bootram.RAM1.INIT_1E=256'hf83f8008_335252fd_f0068817_08842b9f_fe873f80_87163351_0588180c_81ff0673; +defparam bootram.RAM1.INIT_1F=256'h05523355_19707081_19081771_81ff068c_10890570_80d23874_34747427_12527177; +defparam bootram.RAM1.INIT_20=256'h8c170815_53727434_3f800813_5253fdc1_f0067233_08842b9f_fdcf3f80_52565152; +defparam bootram.RAM1.INIT_21=256'h84170888_26ffb038_84170875_5b515152_ff065a52_81197081_7081ff06_7033701a; +defparam bootram.RAM1.INIT_22=256'h5b515354_11335654_73101a89_7081ff06_05197030_2a055473_72057188_18087833; +defparam bootram.RAM1.INIT_23=256'h5377722e_065152fb_127081ff_e43f8008_335252fc_f0068a15_08842b9f_fcf33f80; +defparam bootram.RAM1.INIT_24=256'h882a7081_d6900870_803d0d81_893d0d04_5372800c_53833980_388539fe_09810689; +defparam bootram.RAM1.INIT_25=256'hc0800753_80060780_ff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151; +defparam bootram.RAM1.INIT_26=256'h81ff0681_d6900c75_800c7181_387681d6_515170f1_70810651_0870882a_5381d690; +defparam bootram.RAM1.INIT_27=256'h51515170_2a708106_90087088_963881d6_5172802e_d6900c72_82800781_d6980c71; +defparam bootram.RAM1.INIT_28=256'h80538052_80558854_d6940c88_0d810b81_0d04fc3d_800c843d_80085170_f13881d6; +defparam bootram.RAM1.INIT_29=256'h900c8b0b_800b81d6_d6980c88_3f800b81_7d56fee4_04f63d0d_3f863d0d_8051ff87; +defparam bootram.RAM1.INIT_2A=256'hd6900cfe_8aa80b81_81d6900c_0c88a80b_0b81d698_d6800c81_7c882b81_81d6840c; +defparam bootram.RAM1.INIT_2B=256'h3f81d68c_900cfe98_800b81d6_d6900c8a_88800b81_2780d338_80547376_b33f7e55; +defparam bootram.RAM1.INIT_2C=256'h27833870_90537073_75315257_5b883d76_81d68008_d684085a_88085981_085881d6; +defparam bootram.RAM1.INIT_2D=256'ha939800b_721454ff_1252ec39_05573481_33757081_71175170_73279138_53805271; +defparam bootram.RAM1.INIT_2E=256'h9d055755_80028405_51fed23f_80c05268_3d705457_ea3d0d88_8c3d0d04_81d6980c; +defparam bootram.RAM1.INIT_2F=256'h81992e09_33515473_38741670_09810694_7381aa2e_ff2e9d38_51547381_74177033; +defparam bootram.RAM1.INIT_30=256'h863d7054_04f93d0d_0c983d0d_80547380_7527d138_811555be_81548b39_81068538; +defparam bootram.RAM1.INIT_31=256'h38815574_09810683_8008752e_5185f73f_abec5273_80558653_51fe823f_54865279; +defparam bootram.RAM1.INIT_32=256'h0771832a_0671872a_70852a82_02970533_04fd3d0d_81a0940c_0d04810b_800c893d; +defparam bootram.RAM1.INIT_33=256'h76852b80_7081ff06_71730707_832ba006_10900674_73070773_2a880671_84067281; +defparam bootram.RAM1.INIT_34=256'h0d04fe3d_5552853d_51555255_0c515253_0681d480_077081ff_0778872b_c0067072; +defparam bootram.RAM1.INIT_35=256'h819951ff_51ff923f_983f81aa_81ff51ff_51ff9e3f_075381ff_0681d00a_0d74d00a; +defparam bootram.RAM1.INIT_36=256'h0651feed_3f7281ff_5252fef5_7081ff06_3f72882a_e151ff81_ff873f80_8c3fb251; +defparam bootram.RAM1.INIT_37=256'hfecf3fb0_ff065253_902a7081_fedb3f72_72982a51_51fee23f_e83f8181_3fb251fe; +defparam bootram.RAM1.INIT_38=256'hb03fa051_3f8051fe_a051feb5_51feba3f_febf3f8e_c43f8051_81a151fe_51feca3f; +defparam bootram.RAM1.INIT_39=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_ff398c08_843d0d04_51fea63f_feab3f80; +defparam bootram.RAM1.INIT_3A=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; +defparam bootram.RAM1.INIT_3B=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; +defparam bootram.RAM1.INIT_3C=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; +defparam bootram.RAM1.INIT_3D=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; +defparam bootram.RAM1.INIT_3E=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; +defparam bootram.RAM1.INIT_3F=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; +defparam bootram.RAM2.INIT_00=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; +defparam bootram.RAM2.INIT_01=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; +defparam bootram.RAM2.INIT_02=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM2.INIT_03=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; +defparam bootram.RAM2.INIT_04=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; +defparam bootram.RAM2.INIT_05=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; +defparam bootram.RAM2.INIT_06=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; +defparam bootram.RAM2.INIT_07=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; +defparam bootram.RAM2.INIT_08=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; +defparam bootram.RAM2.INIT_09=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; +defparam bootram.RAM2.INIT_0A=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; +defparam bootram.RAM2.INIT_0B=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; +defparam bootram.RAM2.INIT_0C=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; +defparam bootram.RAM2.INIT_0D=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; +defparam bootram.RAM2.INIT_0E=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; +defparam bootram.RAM2.INIT_0F=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; +defparam bootram.RAM2.INIT_10=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; +defparam bootram.RAM2.INIT_11=256'hae9c0854_3d0d800b_ff8339fd_ed387054_52718326_530cfc12_71708405_84055408; +defparam bootram.RAM2.INIT_12=256'h3f72b5f8_8008519b_51e6bc3f_aed05281_3fe3b13f_f80ce493_983873b5_5472812e; +defparam bootram.RAM2.INIT_13=256'hd40882c8_3d0d7bae_00ff39f7_0851843f_e6a53f80_d0528151_e39a3fae_0ce3fc3f; +defparam bootram.RAM2.INIT_14=256'h80e93880_59807424_712b5955_08ff0581_88188419_80d93881_5a77802e_11085a54; +defparam bootram.RAM2.INIT_15=256'h08535379_38781670_72802eb5_08770653_56818019_11880556_73822b78_7424b538; +defparam bootram.RAM2.INIT_16=256'hffad38ae_77085877_8025d638_57575473_79812c5a_fc17fc17_722dff14_51740853; +defparam bootram.RAM2.INIT_17=256'h57575473_79812c5a_fc17fc17_722dff14_3f740853_7951f8c0_1308a538_d40853bc; +defparam bootram.RAM2.INIT_18=256'hb5d80bfc_3fff3d0d_7951f894_0853722d_7251bc13_57ff9439_38d23980_8025ffa9; +defparam bootram.RAM2.INIT_19=256'h0d0404e3_f138833d_2e098106_525270ff_fc127008_9138702d_5270ff2e_05700852; +defparam bootram.RAM2.INIT_1A=256'h65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040_833f0400; +defparam bootram.RAM2.INIT_1B=256'h64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120_7475726e; +defparam bootram.RAM2.INIT_1C=256'h756c7472_70657220_72207375_6f616465_6f6f746c_322b2062_55535250_4e4f4b00; +defparam bootram.RAM2.INIT_1D=256'h50322b20_20555352_74696e67_53746172_6e0a0000_6974696f_55206564_61205a50; +defparam bootram.RAM2.INIT_1E=256'h6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520_696e2073; +defparam bootram.RAM2.INIT_1F=256'h206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20_6f6d206d; +defparam bootram.RAM2.INIT_20=256'h69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065_65722068; +defparam bootram.RAM2.INIT_21=256'h62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167_61726520; +defparam bootram.RAM2.INIT_22=256'h2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20_6b2e2046; +defparam bootram.RAM2.INIT_23=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_2e000000; +defparam bootram.RAM2.INIT_24=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM2.INIT_25=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM2.INIT_26=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM2.INIT_27=256'h6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066_20696d61; +defparam bootram.RAM2.INIT_28=256'h64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374_2070726f; +defparam bootram.RAM2.INIT_29=256'h64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e_6f647563; +defparam bootram.RAM2.INIT_2A=256'h6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69_2e2e2e00; +defparam bootram.RAM2.INIT_2B=256'h61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000_6d616765; +defparam bootram.RAM2.INIT_2C=256'h61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67; +defparam bootram.RAM2.INIT_2D=256'h77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076_6e210000; +defparam bootram.RAM2.INIT_2E=256'h2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20_20666f75; +defparam bootram.RAM2.INIT_2F=256'h20202828_20202020_00202020_80700000_0b0b0b0b_01b200d9_05160364_14580a2c; +defparam bootram.RAM2.INIT_30=256'h10101010_10101010_20881010_20202020_20202020_20202020_20202020_28282820; +defparam bootram.RAM2.INIT_31=256'h01010101_41414141_10104141_10101010_04040410_04040404_10040404_10101010; +defparam bootram.RAM2.INIT_32=256'h02020202_42424242_10104242_10101010_01010101_01010101_01010101_01010101; +defparam bootram.RAM2.INIT_33=256'h00000000_00000000_20000000_10101010_02020202_02020202_02020202_02020202; +defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_37=256'h792e6578_64756d6d_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_38=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_43000000_65000000; +defparam bootram.RAM2.INIT_39=256'hffffffff_000b0000_0018000f_ffff0031_05050400_01010100_00001ae0_00000000; +defparam bootram.RAM2.INIT_3A=256'h000019c0_00000000_00001758_000016f8_06820594_09c407d0_13880d05_00002710; +defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00001a78_00001a1c; +defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00001704_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001; +defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_16=256'hffffffff_00000000_ffffffff_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v index 4e0b190ef..c152f083e 100644 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -131,7 +131,7 @@ module u2plus_core output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); - localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_BUF_POOL = 64; // router localparam SR_UDP_SM = 96; // 64 regs localparam SR_RX_DSP = 160; // 16 localparam SR_RX_CTRL = 176; // 16 @@ -155,7 +155,7 @@ module u2plus_core wire wb_rst, dsp_rst; - wire [31:0] status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; wire proc_int, overrun, underrun; wire [3:0] uart_tx_int, uart_rx_int; @@ -197,21 +197,21 @@ module u2plus_core wb_1master #(.decode_w(8), .s0_addr(8'b0000_0000),.s0_mask(8'b1110_0000), // 0-8K, Boot RAM - .s1_addr(8'b0100_0000),.s1_mask(8'b1100_0000), // 16K-32K, Buffer Pool - .s2_addr(8'b0011_0000),.s2_mask(8'b1111_1111), // SPI - .s3_addr(8'b0011_0001),.s3_mask(8'b1111_1111), // I2C - .s4_addr(8'b0011_0010),.s4_mask(8'b1111_1111), // GPIO - .s5_addr(8'b0011_0011),.s5_mask(8'b1111_1111), // Readback - .s6_addr(8'b0011_0100),.s6_mask(8'b1111_1111), // Ethernet MAC - .s7_addr(8'b0010_0000),.s7_mask(8'b1111_0000), // 8-12K, Settings Bus (only uses 1K) - .s8_addr(8'b0011_0101),.s8_mask(8'b1111_1111), // PIC - .s9_addr(8'b0011_0110),.s9_mask(8'b1111_1111), // Unused - .sa_addr(8'b0011_0111),.sa_mask(8'b1111_1111), // UART - .sb_addr(8'b0011_1000),.sb_mask(8'b1111_1111), // ATR - .sc_addr(8'b0011_1001),.sc_mask(8'b1111_1111), // Unused - .sd_addr(8'b0011_1010),.sd_mask(8'b1111_1111), // ICAP - .se_addr(8'b0011_1011),.se_mask(8'b1111_1111), // SPI Flash - .sf_addr(8'b1000_0000),.sf_mask(8'b1000_0000), // 32-64K, Main RAM + .s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000), // 16K-20K, Buffer Pool + .s2_addr(8'b0110_0000),.s2_mask(8'b1111_1111), // SPI + .s3_addr(8'b0110_0001),.s3_mask(8'b1111_1111), // I2C + .s4_addr(8'b0110_0010),.s4_mask(8'b1111_1111), // GPIO + .s5_addr(8'b0110_0011),.s5_mask(8'b1111_1111), // Readback + .s6_addr(8'b0110_0100),.s6_mask(8'b1111_1111), // Ethernet MAC + .s7_addr(8'b0101_0000),.s7_mask(8'b1111_0000), // 20K-24K, Settings Bus (only uses 1K) + .s8_addr(8'b0110_0101),.s8_mask(8'b1111_1111), // PIC + .s9_addr(8'b0110_0110),.s9_mask(8'b1111_1111), // Unused + .sa_addr(8'b0110_0111),.sa_mask(8'b1111_1111), // UART + .sb_addr(8'b0110_1000),.sb_mask(8'b1111_1111), // ATR + .sc_addr(8'b0110_1001),.sc_mask(8'b1111_1111), // Unused + .sd_addr(8'b0110_1010),.sd_mask(8'b1111_1111), // ICAP + .se_addr(8'b0110_1011),.se_mask(8'b1111_1111), // SPI Flash + .sf_addr(8'b1000_0000),.sf_mask(8'b1100_0000), // 32-48K, Main RAM .dw(dw),.aw(aw),.sw(sw)) wb_1master (.clk_i(wb_clk),.rst_i(wb_rst), .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i), @@ -251,35 +251,72 @@ module u2plus_core ////////////////////////////////////////////////////////////////////////////////////////// // Reset Controller - + + reg cpu_bldr_ctrl_state; + localparam CPU_BLDR_CTRL_WAIT = 0; + localparam CPU_BLDR_CTRL_DONE = 1; + + wire bldr_done; + reg cpu_rst; + wire cpu_enb = ~cpu_rst; + wire [aw-1:0] cpu_adr; + wire [aw-1:0] cpu_sp_init = (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_DONE)? + 16'hfff8 : //top of 8K boot ram re-purposed at 56K + 16'h1ff8 ; //top of 8K boot ram + + //When the main program runs, it will try to access system ram at 0. + //This logic re-maps the cpu address to force select the system ram. + assign m0_adr = + (cpu_bldr_ctrl_state == CPU_BLDR_CTRL_WAIT)? cpu_adr : ( //in bootloader + (cpu_adr[15:14] == 2'b00)? {2'b10, cpu_adr[13:0]} : ( //map 0-16 to 32-48 (main ram) + (cpu_adr[15:13] == 3'b111)? {3'b000, cpu_adr[12:0]} : ( //map 56-64 to 0-8 (boot ram) + cpu_adr))); //otherwise + + always @(posedge wb_clk) + if(wb_rst) begin + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_WAIT; + cpu_rst <= 1'b1; + end + else begin + case(cpu_bldr_ctrl_state) + + CPU_BLDR_CTRL_WAIT: begin + cpu_rst <= 1'b0; + if (bldr_done == 1'b1) begin //set by the bootloader + cpu_bldr_ctrl_state <= CPU_BLDR_CTRL_DONE; + cpu_rst <= 1'b1; + end + end + + CPU_BLDR_CTRL_DONE: begin //stay here forever + cpu_rst <= 1'b0; + end + + endcase //cpu_bldr_ctrl_state + end + // ///////////////////////////////////////////////////////////////////////// // Processor - wire [31:0] if_dat; - wire [15:0] if_adr; - - aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1)) - aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst), - // Instruction Wishbone bus to I-RAM - .if_adr(if_adr), - .if_dat(if_dat), + + assign bus_error = m0_err | m0_rty; + + wire [63:0] zpu_status; + zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw)) + zpu_top0 (.clk(wb_clk), .rst(wb_rst | cpu_rst), .enb(cpu_enb), // Data Wishbone bus to system bus fabric - .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr), - .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc), + .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(cpu_adr), + .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc), // Interrupts and exceptions - .sys_int_i(proc_int),.sys_exc_i(bus_error) ); - - assign bus_error = m0_err | m0_rty; - + .stack_start(cpu_sp_init), .zpu_status(zpu_status), .interrupt(proc_int & 1'b0)); + + // ///////////////////////////////////////////////////////////////////////// // Dual Ported Boot RAM -- D-Port is Slave #0 on main Wishbone // Dual Ported Main RAM -- D-Port is Slave #F on main Wishbone // I-port connects directly to processor - wire [31:0] if_dat_boot, if_dat_main; - assign if_dat = if_adr[15] ? if_dat_main : if_dat_boot; - bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(if_adr[12:0]), .if_data(if_dat_boot), + .if_adr(13'b0), .if_data(), .dwb_adr_i(s0_adr[12:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel)); @@ -289,10 +326,10 @@ module u2plus_core `include "bootloader.rmi" - ram_harvard2 #(.AWIDTH(15),.RAM_SIZE(32768)) + ram_harvard2 #(.AWIDTH(14),.RAM_SIZE(16384)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .if_adr(if_adr[14:0]), .if_data(if_dat_main), - .dwb_adr_i(sf_adr[14:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); // ///////////////////////////////////////////////////////////////////////// @@ -310,34 +347,33 @@ module u2plus_core wire wr3_ready_i, wr3_ready_o; wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; - - buffer_pool #(.BUF_SIZE(9), .SET_ADDR(SR_BUF_POOL)) buffer_pool + + wire [35:0] tx_err_data; + wire tx_err_src_rdy, tx_err_dst_rdy; + + wire [31:0] router_debug; + + packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), + .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o), .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(), - - .stream_clk(dsp_clk), .stream_rst(dsp_rst), + .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .status(status),.sys_int_o(buffer_int), - - .s0(status_b0),.s1(status_b1),.s2(status_b2),.s3(status_b3), - .s4(status_b4),.s5(status_b5),.s6(status_b6),.s7(status_b7), - - // Write Interfaces - .wr0_data_i(wr0_dat), .wr0_flags_i(wr0_flags), .wr0_ready_i(wr0_ready_i), .wr0_ready_o(wr0_ready_o), - .wr1_data_i(wr1_dat), .wr1_flags_i(wr1_flags), .wr1_ready_i(wr1_ready_i), .wr1_ready_o(wr1_ready_o), - .wr2_data_i(wr2_dat), .wr2_flags_i(wr2_flags), .wr2_ready_i(wr2_ready_i), .wr2_ready_o(wr2_ready_o), - .wr3_data_i(wr3_dat), .wr3_flags_i(wr3_flags), .wr3_ready_i(wr3_ready_i), .wr3_ready_o(wr3_ready_o), - // Read Interfaces - .rd0_data_o(rd0_dat), .rd0_flags_o(rd0_flags), .rd0_ready_i(rd0_ready_i), .rd0_ready_o(rd0_ready_o), - .rd1_data_o(rd1_dat), .rd1_flags_o(rd1_flags), .rd1_ready_i(rd1_ready_i), .rd1_ready_o(rd1_ready_o), - .rd2_data_o(rd2_dat), .rd2_flags_o(rd2_flags), .rd2_ready_i(rd2_ready_i), .rd2_ready_o(rd2_ready_o), - .rd3_data_o(rd3_dat), .rd3_flags_o(rd3_flags), .rd3_ready_i(rd3_ready_i), .rd3_ready_o(rd3_ready_o) + + .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0), + + .status(status), .sys_int_o(buffer_int), .debug(router_debug), + + .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), + .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), + + .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); - wire [31:0] status_enc; - priority_enc priority_enc (.in({16'b0,status[15:0]}), .out(status_enc)); - // ///////////////////////////////////////////////////////////////////////// // SPI -- Slave #2 spi_top shared_spi @@ -378,23 +414,23 @@ module u2plus_core cycle_count <= cycle_count + 1; //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd3; + localparam compat_num = 32'd4; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - .word00(status_b0),.word01(status_b1),.word02(status_b2),.word03(status_b3), - .word04(status_b4),.word05(status_b5),.word06(status_b6),.word07(status_b7), + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), + .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), - .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(status_enc),.word15(cycle_count) + .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),.word14(32'b0),.word15(cycle_count) ); // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, rx_f36_src_rdy, rx_f36_dst_rdy; + wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), @@ -410,36 +446,38 @@ module u2plus_core .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] udp_tx_data, udp_rx_data; - wire udp_tx_src_rdy, udp_tx_dst_rdy, udp_rx_src_rdy, udp_rx_dst_rdy; - - udp_wrapper #(.BASE(SR_UDP_SM)) udp_wrapper + wire [35:0] rx_f36_data, tx_f36_data; + wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; + + wire [18:0] _rx_f19_data; + wire _rx_f19_src_rdy, _rx_f19_dst_rdy; + + //mac rx to eth input... + fifo19_rxrealign fifo19_rxrealign (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy_i(rx_f19_src_rdy), .rx_f19_dst_rdy_o(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy_o(tx_f19_src_rdy), .tx_f19_dst_rdy_i(tx_f19_dst_rdy), - .rx_f36_data(udp_rx_data), .rx_f36_src_rdy_o(udp_rx_src_rdy), .rx_f36_dst_rdy_i(udp_rx_dst_rdy), - .tx_f36_data(udp_tx_data), .tx_f36_src_rdy_i(udp_tx_src_rdy), .tx_f36_dst_rdy_o(udp_tx_dst_rdy), - .debug(debug_udp) ); + .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), + .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - wire [35:0] tx_err_data, udp1_tx_data; - wire tx_err_src_rdy, tx_err_dst_rdy, udp1_tx_src_rdy, udp1_tx_dst_rdy; - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(udp1_tx_data), .src_rdy_o(udp1_tx_src_rdy), .dst_rdy_i(udp1_tx_dst_rdy)); + .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - fifo36_mux #(.prio(0)) mux_err_stream - (.clk(dsp_clk), .reset(dsp_reset), .clear(0), - .data0_i(udp1_tx_data), .src0_rdy_i(udp1_tx_src_rdy), .dst0_rdy_o(udp1_tx_dst_rdy), - .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy), - .data_o(udp_tx_data), .src_rdy_o(udp_tx_src_rdy), .dst_rdy_i(udp_tx_dst_rdy)); - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(udp_rx_data), .src_rdy_i(udp_rx_src_rdy), .dst_rdy_o(udp_rx_dst_rdy), + .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); + + //eth output to mac tx... + fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), + .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); + + fifo36_to_fifo19 eth_out_fifo36_to_fifo19 + (.clk(dsp_clk), .reset(dsp_rst), .clear(0), + .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), + .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 @@ -471,6 +509,8 @@ module u2plus_core .in(set_data),.out(adc_outs),.changed()); setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); + setting_reg #(.my_addr(5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + .in(set_data),.out(bldr_done),.changed()); // ///////////////////////////////////////////////////////////////////////// // LEDS @@ -652,7 +692,8 @@ module u2plus_core vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), - .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) + .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), + .DSP_NUMBER(0)) vita_tx_chain (.clk(dsp_clk), .reset(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), |