Merge branch 'flow_ctrl' into next

6 files changed, 379 insertions, 182 deletions

diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common
index 4da64ac28..9a180d10e 100644
--- a/fpga/usrp2/top/Makefile.common
+++ b/fpga/usrp2/top/Makefile.common
@@ -31,6 +31,7 @@ synth: $(ISE_FILE)
 	$(ISE_HELPER) "Synthesize - XST"
 
 bin: $(BIN_FILE)
+	$(ISE_HELPER) "Generate Programming File"
 
 mcs: $(MCS_FILE)
 
diff --git a/fpga/usrp2/top/u2_rev3/Makefile.udp b/fpga/usrp2/top/u2_rev3/Makefile.udp
index 9962887d4..99effb038 100644
--- a/fpga/usrp2/top/u2_rev3/Makefile.udp
+++ b/fpga/usrp2/top/u2_rev3/Makefile.udp
@@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extram/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
 
 ##################################################
 # Project Properties
diff --git a/fpga/usrp2/top/u2_rev3/u2_core.v b/fpga/usrp2/top/u2_rev3/u2_core.v
index 9ba3cc136..a5963f6b1 100755
--- a/fpga/usrp2/top/u2_rev3/u2_core.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core.v
@@ -123,7 +123,7 @@ module u2_core
    output [18:0] RAM_A,
    output RAM_CE1n,
    output RAM_CENn,
-   output RAM_CLK,
+ //  output RAM_CLK,
    output RAM_WEn,
    output RAM_OEn,
    output RAM_LDn,
diff --git a/fpga/usrp2/top/u2_rev3/u2_core_udp.v b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
index c9502898b..b47e7e311 100644
--- a/fpga/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/fpga/usrp2/top/u2_rev3/u2_core_udp.v
@@ -119,11 +119,13 @@ module u2_core
    inout [15:0] io_rx,
 
    // External RAM
-   inout [17:0] RAM_D,
+   input [17:0] RAM_D_pi,
+   output [17:0] RAM_D_po,   
+   output RAM_D_poe,
    output [18:0] RAM_A,
    output RAM_CE1n,
    output RAM_CENn,
-   output RAM_CLK,
+ //  output RAM_CLK,
    output RAM_WEn,
    output RAM_OEn,
    output RAM_LDn,
@@ -169,7 +171,7 @@ module u2_core
    wire [31:0] 	atr_lines;
 
    wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
-		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2;
 
    wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
    wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
@@ -412,7 +414,7 @@ module u2_core
 		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
 		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
 		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
-		 .gpio( {io_tx,io_rx} ) );
+		 .gpio({io_tx,io_rx}) );
 
    // /////////////////////////////////////////////////////////////////////////
    // Buffer Pool Status -- Slave #5   
@@ -425,7 +427,7 @@ module u2_core
        cycle_count <= cycle_count + 1;
 
    //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = 32'd2;
+   localparam compat_num = 32'd3;
 
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
@@ -539,10 +541,17 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Interrupt Controller, Slave #8
 
+   // Pass interrupts on dsp_clk to wb_clk.  These need edge triggering in the pic
+   wire 	 underrun_wb, overrun_wb, pps_wb;
+
+   oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb));
+   oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb));
+   oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb));
+   
    assign irq= {{8'b0},
 		{8'b0},
 		{3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
-		{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
+		{pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
    
    pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
 	   .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
@@ -653,14 +662,47 @@ module u2_core
    wire [35:0] 	 tx_data;
    wire 	 tx_src_rdy, tx_dst_rdy;
    wire [31:0] 	 debug_vt;
+
+   // FIFO cascade draws from buffer pool, feeds vita tx deframer
+/* -----\/----- EXCLUDED -----\/-----
    
    fifo_cascade #(.WIDTH(36), .SIZE(DSP_TX_FIFOSIZE)) tx_fifo_cascade
      (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
       .datain({rd1_flags,rd1_dat}), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i),
       .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy) );
+ -----/\----- EXCLUDED -----/\----- */
+
+   ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) 
+     ext_fifo_i1
+       (
+	.int_clk(dsp_clk),
+	.ext_clk(clk_to_mac),
+//	.ext_clk(wb_clk),
+	.rst(dsp_rst),
+	.RAM_D_pi(RAM_D_pi),
+	.RAM_D_po(RAM_D_po),
+	.RAM_D_poe(RAM_D_poe),
+	.RAM_A(RAM_A),
+	.RAM_WEn(RAM_WEn),
+	.RAM_CENn(RAM_CENn),
+	.RAM_LDn(RAM_LDn),
+	.RAM_OEn(RAM_OEn),
+	.RAM_CE1n(RAM_CE1n),
+//	.datain({rd1_flags,rd1_dat}),
+	.datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}),
+	.src_rdy_i(rd1_ready_o),               // WRITE
+	.dst_rdy_o(rd1_ready_i),               // not FULL
+//	.dataout(tx_data),
+	.dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}),
+	.src_rdy_o(tx_src_rdy),               // not EMPTY
+	.dst_rdy_i(tx_dst_rdy),
+	.debug(debug_extfifo),
+	.debug2(debug_extfifo2)
+	);
 
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
-		   .REPORT_ERROR(1), .PROT_ENG_FLAGS(1)) 
+		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
+		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1)) 
    vita_tx_chain
      (.clk(dsp_clk), .reset(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
@@ -719,7 +761,30 @@ module u2_core
 
    assign      RAM_CE1n = 0;
    assign      RAM_D[17:16] = 2'bzz;
-   */
+/* -----\/----- EXCLUDED -----\/-----
+   *-/
+
+   test_sram_if test_sram_if_i1
+     (
+    //  .clk(wb_clk),
+      .clk(clk_to_mac),
+      .rst(wb_rst),
+      .RAM_D_pi(RAM_D_pi),
+      .RAM_D_po(RAM_D_po),
+      .RAM_D_poe(RAM_D_poe),
+      .RAM_A(RAM_A),
+      .RAM_WEn(RAM_WEn),
+      .RAM_CENn(RAM_CENn),
+      .RAM_LDn(RAM_LDn),
+      .RAM_OEn(RAM_OEn),
+      .RAM_CE1n(RAM_CE1n),
+      .correct()
+      );
+ -----/\----- EXCLUDED -----/\----- */
+   
+   //assign RAM_CLK = wb_clk;
+   //assign RAM_CLK = clk_to_mac;
+   
    
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
@@ -731,8 +796,8 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
   
-   assign debug_clk = 2'b00;
-   assign debug = 32'd0;
+   assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac};
+   assign debug = 32'd0; // debug_extfifo;
    assign debug_gpio_0 = 32'd0;
    assign debug_gpio_1 = 32'd0;
    
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
index 6aa699d2a..deaeecb53 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -74,49 +74,49 @@ NET "MDC"  LOC = "V18"  ;
 NET "PHY_INTn"  LOC = "AB13"  ; 
 NET "PHY_RESETn"  LOC = "AA19"  ; 
 NET "PHY_CLK"  LOC = "V15"  ; 
-NET "RAM_D[0]"  LOC = "N20"  ;
-NET "RAM_D[1]"  LOC = "N21"  ;
-NET "RAM_D[2]"  LOC = "N22"  ;
-NET "RAM_D[3]"  LOC = "M17"  ;
-NET "RAM_D[4]"  LOC = "M18"  ;
-NET "RAM_D[5]"  LOC = "M19"  ;
-NET "RAM_D[6]"  LOC = "M20"  ;
-NET "RAM_D[7]"  LOC = "M21"  ;
-NET "RAM_D[8]"  LOC = "M22"  ;
-NET "RAM_D[9]"  LOC = "Y22"  ;
-NET "RAM_D[10]"  LOC = "Y21"  ;
-NET "RAM_D[11]"  LOC = "Y20"  ;
-NET "RAM_D[12]"  LOC = "Y19"  ;
-NET "RAM_D[13]"  LOC = "W22"  ;
-NET "RAM_D[14]"  LOC = "W21"  ;
-NET "RAM_D[15]"  LOC = "W20"  ;
-NET "RAM_D[16]"  LOC = "W19"  ;
-NET "RAM_D[17]"  LOC = "V22"  ;
-NET "RAM_A[0]"  LOC = "U21"  ;
-NET "RAM_A[1]"  LOC = "T19"  ;
-NET "RAM_A[2]"  LOC = "V21"  ;
-NET "RAM_A[3]"  LOC = "V20"  ;
-NET "RAM_A[4]"  LOC = "T20"  ;
-NET "RAM_A[5]"  LOC = "T21"  ;
-NET "RAM_A[6]"  LOC = "T22"  ;
-NET "RAM_A[7]"  LOC = "T18"  ;
-NET "RAM_A[8]"  LOC = "R18"  ;
-NET "RAM_A[9]"  LOC = "P19"  ;
-NET "RAM_A[10]"  LOC = "P21"  ;
-NET "RAM_A[11]"  LOC = "P22"  ;
-NET "RAM_A[12]"  LOC = "N19"  ;
-NET "RAM_A[13]"  LOC = "N17"  ;
-NET "RAM_A[14]"  LOC = "N18"  ;
-NET "RAM_A[15]"  LOC = "T17"  ;
-NET "RAM_A[16]"  LOC = "U19"  ;
-NET "RAM_A[17]"  LOC = "U18"  ;
-NET "RAM_A[18]"  LOC = "V19"  ;
-NET "RAM_CE1n"  LOC = "U20"  ; 
-NET "RAM_CENn"  LOC = "P18"  ; 
-NET "RAM_CLK"  LOC = "P17"  ; 
-NET "RAM_WEn"  LOC = "R22"  ; 
-NET "RAM_OEn"  LOC = "R21"  ; 
-NET "RAM_LDn"  LOC = "R19"  ; 
+NET "RAM_D[0]"  LOC = "N20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[1]"  LOC = "N21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[2]"  LOC = "N22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[3]"  LOC = "M17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[4]"  LOC = "M18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[5]"  LOC = "M19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[6]"  LOC = "M20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[7]"  LOC = "M21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[8]"  LOC = "M22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[9]"  LOC = "Y22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[10]"  LOC = "Y21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_D[11]"  LOC = "Y20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_D[12]"  LOC = "Y19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_D[13]"  LOC = "W22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_D[14]"  LOC = "W21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_D[15]"  LOC = "W20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_D[16]"  LOC = "W19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_D[17]"  LOC = "V22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[0]"  LOC = "U21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[1]"  LOC = "T19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[2]"  LOC = "V21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[3]"  LOC = "V20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[4]"  LOC = "T20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[5]"  LOC = "T21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[6]"  LOC = "T22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[7]"  LOC = "T18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[8]"  LOC = "R18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[9]"  LOC = "P19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[10]"  LOC = "P21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[11]"  LOC = "P22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[12]"  LOC = "N19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[13]"  LOC = "N17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[14]"  LOC = "N18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[15]"  LOC = "T17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[16]"  LOC = "U19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[17]"  LOC = "U18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ;
+NET "RAM_A[18]"  LOC = "V19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW  ;
+NET "RAM_CE1n"  LOC = "U20" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
+NET "RAM_CENn"  LOC = "P18" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
+NET "RAM_CLK"  LOC = "P17" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
+NET "RAM_WEn"  LOC = "R22" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
+NET "RAM_OEn"  LOC = "R21" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
+NET "RAM_LDn"  LOC = "R19" |IOSTANDARD = LVCMOS25  |DRIVE = 8  |SLEW = SLOW ; 
 NET "ser_enable"  LOC = "W11"  ; 
 NET "ser_prbsen"  LOC = "AA3"  ; 
 NET "ser_loopen"  LOC = "Y4"  ; 
@@ -264,22 +264,22 @@ NET "sdi_tx_adc"  LOC = "J4"  ;
 NET "sen_tx_dac"  LOC = "H4"  ; 
 NET "sclk_tx_dac"  LOC = "J5"  ; 
 NET "sdi_tx_dac"  LOC = "J6"  ; 
-NET "io_tx[0]"  LOC = "K4"  ;
-NET "io_tx[1]"  LOC = "K3"  ;
-NET "io_tx[2]"  LOC = "G1"  ;
-NET "io_tx[3]"  LOC = "G5"  ;
-NET "io_tx[4]"  LOC = "H5"  ;
-NET "io_tx[5]"  LOC = "F3"  ;
-NET "io_tx[6]"  LOC = "F2"  ;
-NET "io_tx[7]"  LOC = "F5"  ;
-NET "io_tx[8]"  LOC = "G6"  ;
-NET "io_tx[9]"  LOC = "E2"  ;
-NET "io_tx[10]"  LOC = "E1"  ;
-NET "io_tx[11]"  LOC = "E3"  ;
-NET "io_tx[12]"  LOC = "F4"  ;
-NET "io_tx[13]"  LOC = "D2"  ;
-NET "io_tx[14]"  LOC = "D4"  ;
-NET "io_tx[15]"  LOC = "E4"  ;
+NET "io_tx[0]"  LOC = "K4"   ;
+NET "io_tx[1]"  LOC = "K3"   ;
+NET "io_tx[2]"  LOC = "G1"   ;
+NET "io_tx[3]"  LOC = "G5"   ;
+NET "io_tx[4]"  LOC = "H5"   ;
+NET "io_tx[5]"  LOC = "F3"   ;
+NET "io_tx[6]"  LOC = "F2"   ;
+NET "io_tx[7]"  LOC = "F5"   ;
+NET "io_tx[8]"  LOC = "G6"   ;
+NET "io_tx[9]"  LOC = "E2"   ;
+NET "io_tx[10]"  LOC = "E1"   ;
+NET "io_tx[11]"  LOC = "E3"   ;
+NET "io_tx[12]"  LOC = "F4"   ;
+NET "io_tx[13]"  LOC = "D2"   ;
+NET "io_tx[14]"  LOC = "D4"   ;
+NET "io_tx[15]"  LOC = "E4"   ;
 NET "sen_rx_db"  LOC = "D22"  ; 
 NET "sclk_rx_db"  LOC = "F19"  ; 
 NET "sdo_rx_db"  LOC = "G20"  ; 
@@ -291,22 +291,22 @@ NET "sdi_rx_adc"  LOC = "H22"  ;
 NET "sen_rx_dac"  LOC = "J18"  ; 
 NET "sclk_rx_dac"  LOC = "J19"  ; 
 NET "sdi_rx_dac"  LOC = "J21"  ; 
-NET "io_rx[0]"  LOC = "L21"  ;
-NET "io_rx[1]"  LOC = "L20"  ;
-NET "io_rx[2]"  LOC = "L19"  ;
-NET "io_rx[3]"  LOC = "L18"  ;
-NET "io_rx[4]"  LOC = "L17"  ;
-NET "io_rx[5]"  LOC = "K22"  ;
-NET "io_rx[6]"  LOC = "K21"  ;
-NET "io_rx[7]"  LOC = "K20"  ;
-NET "io_rx[8]"  LOC = "G22"  ;
-NET "io_rx[9]"  LOC = "G21"  ;
-NET "io_rx[10]"  LOC = "F21"  ;
-NET "io_rx[11]"  LOC = "F20"  ;
-NET "io_rx[12]"  LOC = "G19"  ;
-NET "io_rx[13]"  LOC = "G18"  ;
-NET "io_rx[14]"  LOC = "G17"  ;
-NET "io_rx[15]"  LOC = "E22"  ;
+NET "io_rx[0]"  LOC = "L21"   ;
+NET "io_rx[1]"  LOC = "L20"   ;
+NET "io_rx[2]"  LOC = "L19"   ;
+NET "io_rx[3]"  LOC = "L18"   ;
+NET "io_rx[4]"  LOC = "L17"   ;
+NET "io_rx[5]"  LOC = "K22"   ;
+NET "io_rx[6]"  LOC = "K21"   ;
+NET "io_rx[7]"  LOC = "K20"   ;
+NET "io_rx[8]"  LOC = "G22"   ;
+NET "io_rx[9]"  LOC = "G21"   ;
+NET "io_rx[10]"  LOC = "F21"   ;
+NET "io_rx[11]"  LOC = "F20"   ;
+NET "io_rx[12]"  LOC = "G19"   ;
+NET "io_rx[13]"  LOC = "G18"   ;
+NET "io_rx[14]"  LOC = "G17"   ;
+NET "io_rx[15]"  LOC = "E22"   ;
 
 NET "clk_to_mac" TNM_NET = "clk_to_mac";
 TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
@@ -324,6 +324,7 @@ NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
 TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
 
 NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
 
 #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
 #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
diff --git a/fpga/usrp2/top/u2_rev3/u2_rev3.v b/fpga/usrp2/top/u2_rev3/u2_rev3.v
index 4daa66212..4f7f9bf1a 100644
--- a/fpga/usrp2/top/u2_rev3/u2_rev3.v
+++ b/fpga/usrp2/top/u2_rev3/u2_rev3.v
@@ -330,8 +330,8 @@ module u2_rev3
    wire [15:0] dac_a_int, dac_b_int;
    // DAC A and B are swapped in schematic to facilitate clean layout
    // DAC A is also inverted in schematic to facilitate clean layout
-   always @(negedge dsp_clk) dac_a <= ~dac_b_int;
-   always @(negedge dsp_clk) dac_b <= dac_a_int;
+   always @(posedge dsp_clk) dac_a <= ~dac_b_int;
+   always @(posedge dsp_clk) dac_b <= dac_a_int;
 
    /*
    OFDDRRSE OFDDRRSE_serdes_inst 
@@ -345,100 +345,228 @@ module u2_rev3
       .S(0)       // Synchronous preset input
       );
    */
+
+   wire [17:0] RAM_D_pi;
+   wire [17:0] RAM_D_po;
+   wire        RAM_D_poe;
+   
+   genvar      i;
+
+   //
+   // Instantiate IO for Bidirectional bus to SRAM
+   //
+   
+   generate  
+      for (i=0;i<18;i=i+1)
+        begin : gen_RAM_D_IO
+
+	   IOBUF #(
+		   .DRIVE(12),
+		   .IOSTANDARD("LVCMOS25"),
+		   .SLEW("FAST")
+		   )
+	     RAM_D_i (
+		      .O(RAM_D_pi[i]),
+		      .I(RAM_D_po[i]),
+		      .IO(RAM_D[i]),
+		      .T(RAM_D_poe)
+		      );
+	end // block: gen_RAM_D_IO
+   endgenerate
+
+   //
+   // DCM edits start here
+   //
+
+ 
+   wire RAM_CLK_buf;
+   wire clk_to_mac_buf;
+   wire clk125_ext_clk0;
+   wire clk125_ext_clk180;
+   wire clk125_ext_clk0_buf;
+   wire clk125_ext_clk180_buf;
+   wire clk125_int_buf;
+   wire clk125_int;
+   
+   IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), 
+			    .O(clk_to_mac_buf));
+   
+   DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), 
+                  .CLKIN(clk_to_mac_buf), 
+                  .DSSEN(1'b0), 
+                  .PSCLK(1'b0), 
+                  .PSEN(1'b0), 
+                  .PSINCDEC(1'b0), 
+                  .RST(1'b0), 
+                  .CLK0(clk125_ext_clk0), 
+                  .CLK180(clk125_ext_clk180) );
+   defparam DCM_INST1.CLK_FEEDBACK = "1X";
+   defparam DCM_INST1.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST1.CLKFX_DIVIDE = 1;
+   defparam DCM_INST1.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST1.CLKIN_PERIOD = 8.000;
+   defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED";
+   defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST1.FACTORY_JF = 16'h8080;
+   defparam DCM_INST1.PHASE_SHIFT = -64;
+   defparam DCM_INST1.STARTUP_WAIT = "FALSE";
+   
+   IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), 
+			 .O(RAM_CLK_buf));
+   BUFG  clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), 
+				   .O(clk125_ext_clk0_buf));
+   BUFG  clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), 
+				   .O(clk125_ext_clk180_buf));
+
+   OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
+			.C0(clk125_ext_clk0_buf),
+			.C1(clk125_ext_clk180_buf),
+			.CE(1'b1),
+			.D0(1'b1),
+			.D1(1'b0),
+			.R(1'b0),
+			.S(1'b0));
+
+//   SRL16 dcm2_rst_i1 (.D(1'b0),
+//		      .CLK(clk_to_mac_buf),
+//		      .Q(dcm2_rst),
+//		      .A0(1'b1),
+//		      .A1(1'b1),
+//		      .A2(1'b1),
+//		      .A3(1'b1));
+   // synthesis attribute init of dcm2_rst_i1 is "000F";
+      
+   DCM DCM_INST2 (.CLKFB(clk125_int_buf), 
+                  .CLKIN(clk_to_mac_buf), 
+                  .DSSEN(1'b0), 
+                  .PSCLK(1'b0), 
+                  .PSEN(1'b0), 
+                  .PSINCDEC(1'b0), 
+                  .RST(1'b0),
+                  .CLK0(clk125_int));
+   defparam DCM_INST2.CLK_FEEDBACK = "1X";
+   defparam DCM_INST2.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST2.CLKFX_DIVIDE = 1;
+   defparam DCM_INST2.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST2.CLKIN_PERIOD = 8.000;
+   defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST2.FACTORY_JF = 16'h8080;
+   defparam DCM_INST2.PHASE_SHIFT = 0;
+   defparam DCM_INST2.STARTUP_WAIT = "FALSE";
+  
+   BUFG clk125_int_buf_i1 (.I(clk125_int), 
+                           .O(clk125_int_buf));
+   
+   //
+   // DCM edits end here
+   //
+   
+   
    u2_core #(.RAM_SIZE(32768))
-	u2_core(.dsp_clk           (dsp_clk),
-		     .wb_clk            (wb_clk),
-		     .clock_ready       (clock_ready),
-		     .clk_to_mac	(clk_to_mac),
-		     .pps_in		(pps_in),
-		     .leds		(leds_int),
-		     .debug		(debug[31:0]),
-		     .debug_clk		(debug_clk[1:0]),
-		     .exp_pps_in	(exp_pps_in),
-		     .exp_pps_out	(exp_pps_out),
-		     .GMII_COL		(GMII_COL),
-		     .GMII_CRS		(GMII_CRS),
-		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
-		     .GMII_TX_EN	(GMII_TX_EN_unreg),
-		     .GMII_TX_ER	(GMII_TX_ER_unreg),
-		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
-		     .GMII_TX_CLK	(GMII_TX_CLK),
-		     .GMII_RXD		(GMII_RXD[7:0]),
-		     .GMII_RX_CLK	(GMII_RX_CLK),
-		     .GMII_RX_DV	(GMII_RX_DV),
-		     .GMII_RX_ER	(GMII_RX_ER),
-		     .MDIO		(MDIO),
-		     .MDC		(MDC),
-		     .PHY_INTn		(PHY_INTn),
-		     .PHY_RESETn	(PHY_RESETn),
-		     .ser_enable	(ser_enable),
-		     .ser_prbsen	(ser_prbsen),
-		     .ser_loopen	(ser_loopen),
-		     .ser_rx_en		(ser_rx_en),
-		     .ser_tx_clk	(ser_tx_clk_int),
-		     .ser_t		(ser_t_unreg[15:0]),
-		     .ser_tklsb		(ser_tklsb_unreg),
-		     .ser_tkmsb		(ser_tkmsb_unreg),
-		     .ser_rx_clk	(ser_rx_clk_buf),
-		     .ser_r		(ser_r_int[15:0]),
-		     .ser_rklsb		(ser_rklsb_int),
-		     .ser_rkmsb		(ser_rkmsb_int),
-		     .cpld_start        (cpld_start),
-		     .cpld_mode         (cpld_mode),
-		     .cpld_done         (cpld_done),
-		     .cpld_din          (cpld_din),
-		     .cpld_clk          (cpld_clk),
-		     .cpld_detached     (cpld_detached),
-		     .cpld_misc         (cpld_misc),
-		     .cpld_init_b       (cpld_init_b),
-		     .por               (~POR),
-		     .config_success    (config_success),
-		     .adc_a		(adc_a_reg2),
-		     .adc_ovf_a		(adc_ovf_a_reg2),
-		     .adc_on_a		(adc_on_a),
-		     .adc_oe_a		(adc_oe_a),
-		     .adc_b		(adc_b_reg2),
-		     .adc_ovf_b		(adc_ovf_b_reg2),
-		     .adc_on_b		(adc_on_b),
-		     .adc_oe_b		(adc_oe_b),
-		     .dac_a		(dac_a_int),
-		     .dac_b		(dac_b_int),
-		     .scl_pad_i		(scl_pad_i),
-		     .scl_pad_o		(scl_pad_o),
-		     .scl_pad_oen_o	(scl_pad_oen_o),
-		     .sda_pad_i		(sda_pad_i),
-		     .sda_pad_o		(sda_pad_o),
-		     .sda_pad_oen_o	(sda_pad_oen_o),
-		     .clk_en		(clk_en[1:0]),
-		     .clk_sel		(clk_sel[1:0]),
-		     .clk_func		(clk_func),
-		     .clk_status	(clk_status),
-		     .sclk		(sclk_int),
-		     .mosi		(mosi),
-		     .miso		(miso),
-		     .sen_clk		(sen_clk),
-		     .sen_dac		(sen_dac),
-		     .sen_tx_db		(sen_tx_db),
-		     .sen_tx_adc	(sen_tx_adc),
-		     .sen_tx_dac	(sen_tx_dac),
-		     .sen_rx_db		(sen_rx_db),
-		     .sen_rx_adc	(sen_rx_adc),
-		     .sen_rx_dac	(sen_rx_dac),
-		     .io_tx		(io_tx[15:0]),
-		     .io_rx		(io_rx[15:0]),
-		     .RAM_D             (RAM_D),
-		     .RAM_A             (RAM_A),
-		     .RAM_CE1n          (RAM_CE1n),
-		     .RAM_CENn          (RAM_CENn),
-		     .RAM_CLK           (RAM_CLK),
-		     .RAM_WEn           (RAM_WEn),
-		     .RAM_OEn           (RAM_OEn),
-		     .RAM_LDn           (RAM_LDn), 
-		     .uart_tx_o         (uart_tx_o),
-		     .uart_rx_i         (uart_rx_i),
-		     .uart_baud_o       (),
-		     .sim_mode          (1'b0),
-		     .clock_divider     (2)
-		     );
+     u2_core(.dsp_clk           (dsp_clk),
+	     .wb_clk            (wb_clk),
+	     .clock_ready       (clock_ready),
+	     .clk_to_mac	(clk125_int_buf),
+	     .pps_in		(pps_in),
+	     .leds		(leds_int),
+	     .debug		(debug[31:0]),
+	     .debug_clk		(debug_clk[1:0]),
+	     .exp_pps_in	(exp_pps_in),
+	     .exp_pps_out	(exp_pps_out),
+	     .GMII_COL		(GMII_COL),
+	     .GMII_CRS		(GMII_CRS),
+	     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+	     .GMII_TX_EN	(GMII_TX_EN_unreg),
+	     .GMII_TX_ER	(GMII_TX_ER_unreg),
+	     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+	     .GMII_TX_CLK	(GMII_TX_CLK),
+	     .GMII_RXD		(GMII_RXD[7:0]),
+	     .GMII_RX_CLK	(GMII_RX_CLK),
+	     .GMII_RX_DV	(GMII_RX_DV),
+	     .GMII_RX_ER	(GMII_RX_ER),
+	     .MDIO		(MDIO),
+	     .MDC		(MDC),
+	     .PHY_INTn		(PHY_INTn),
+	     .PHY_RESETn	(PHY_RESETn),
+	     .ser_enable	(ser_enable),
+	     .ser_prbsen	(ser_prbsen),
+	     .ser_loopen	(ser_loopen),
+	     .ser_rx_en		(ser_rx_en),
+	     .ser_tx_clk	(ser_tx_clk_int),
+	     .ser_t		(ser_t_unreg[15:0]),
+	     .ser_tklsb		(ser_tklsb_unreg),
+	     .ser_tkmsb		(ser_tkmsb_unreg),
+	     .ser_rx_clk	(ser_rx_clk_buf),
+	     .ser_r		(ser_r_int[15:0]),
+	     .ser_rklsb		(ser_rklsb_int),
+	     .ser_rkmsb		(ser_rkmsb_int),
+	     .cpld_start        (cpld_start),
+	     .cpld_mode         (cpld_mode),
+	     .cpld_done         (cpld_done),
+	     .cpld_din          (cpld_din),
+	     .cpld_clk          (cpld_clk),
+	     .cpld_detached     (cpld_detached),
+	     .cpld_misc         (cpld_misc),
+	     .cpld_init_b       (cpld_init_b),
+	     .por               (~POR),
+	     .config_success    (config_success),
+	     .adc_a		(adc_a_reg2),
+	     .adc_ovf_a		(adc_ovf_a_reg2),
+	     .adc_on_a		(adc_on_a),
+	     .adc_oe_a		(adc_oe_a),
+	     .adc_b		(adc_b_reg2),
+	     .adc_ovf_b		(adc_ovf_b_reg2),
+	     .adc_on_b		(adc_on_b),
+	     .adc_oe_b		(adc_oe_b),
+	     .dac_a		(dac_a_int),
+	     .dac_b		(dac_b_int),
+	     .scl_pad_i		(scl_pad_i),
+	     .scl_pad_o		(scl_pad_o),
+	     .scl_pad_oen_o	(scl_pad_oen_o),
+	     .sda_pad_i		(sda_pad_i),
+	     .sda_pad_o		(sda_pad_o),
+	     .sda_pad_oen_o	(sda_pad_oen_o),
+	     .clk_en		(clk_en[1:0]),
+	     .clk_sel		(clk_sel[1:0]),
+	     .clk_func		(clk_func),
+	     .clk_status	(clk_status),
+	     .sclk		(sclk_int),
+	     .mosi		(mosi),
+	     .miso		(miso),
+	     .sen_clk		(sen_clk),
+	     .sen_dac		(sen_dac),
+	     .sen_tx_db		(sen_tx_db),
+	     .sen_tx_adc	(sen_tx_adc),
+	     .sen_tx_dac	(sen_tx_dac),
+	     .sen_rx_db		(sen_rx_db),
+	     .sen_rx_adc	(sen_rx_adc),
+	     .sen_rx_dac	(sen_rx_dac),
+	     .io_tx		(io_tx[15:0]),
+	     .io_rx		(io_rx[15:0]),
+	     .RAM_D_pi             (RAM_D_pi),
+	     .RAM_D_po             (RAM_D_po),
+	     .RAM_D_poe             (RAM_D_poe),
+	     .RAM_A             (RAM_A),
+	     .RAM_CE1n          (RAM_CE1n),
+	     .RAM_CENn          (RAM_CENn),
+	//     .RAM_CLK           (RAM_CLK),
+	     .RAM_WEn           (RAM_WEn),
+	     .RAM_OEn           (RAM_OEn),
+	     .RAM_LDn           (RAM_LDn), 
+	     .uart_tx_o         (uart_tx_o),
+	     .uart_rx_i         (uart_rx_i),
+	     .uart_baud_o       (),
+	     .sim_mode          (1'b0),
+	     .clock_divider     (2)
+	     );
    
 endmodule // u2_rev2