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authorJosh Blum <josh@joshknows.com>2012-07-16 18:51:19 -0700
committerJosh Blum <josh@joshknows.com>2012-07-16 18:51:19 -0700
commitff0c19d9639f77faf360235ad18cb3b1ed5b7ddf (patch)
tree709ab3a483685734adeb62c71b6199b91acea00b /fpga/usrp2/top
parent31c6581317bee6810f252f2e85dcb7b9dfec5a4d (diff)
parent1b31a8780d44e5e466afe4b23fd98c74e534c7a3 (diff)
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Merge branch 'fpga_master'
Diffstat (limited to 'fpga/usrp2/top')
-rw-r--r--fpga/usrp2/top/E1x0/u1e_core.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index 77be1bfb0..fef988e62 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -454,7 +454,7 @@ module u1e_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd10, 16'd1}; //major, minor
+ localparam compat_num = {16'd10, 16'd2}; //major, minor
wire [31:0] reg_test32;