Merge branch 'fpga_master'

3 files changed, 0 insertions, 390 deletions

diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile
deleted file mode 100644
index 3ddef1024..000000000
--- a/fpga/usrp2/top/B100/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright 2011 Ettus Research LLC
-#
-
-all: B100
-	find -name "*.twr" | xargs grep constraint | grep met
-
-clean:
-	rm -rf build*
-
-B100:
-	make -f Makefile.$@ bin
-
-.PHONY: all clean
diff --git a/fpga/usrp2/top/B100/u1plus.ucf b/fpga/usrp2/top/B100/u1plus.ucf
deleted file mode 100644
index 3ecc4daf2..000000000
--- a/fpga/usrp2/top/B100/u1plus.ucf
+++ /dev/null
@@ -1,203 +0,0 @@
-## Main Clock
-NET "CLK_FPGA_P"  LOC = "R7"  ;
-NET "CLK_FPGA_N"  LOC = "T7"  ;
-
-## UART
-NET "FPGA_TXD"  LOC = "H16"  ;
-NET "FPGA_RXD"  LOC = "H12"  ;
-
-## I2C
-NET "SDA_FPGA"  LOC = "T13"  ;
-NET "SCL_FPGA"  LOC = "R13"  ;
-
-## CGEN
-NET "cgen_st_ld"  LOC = "M13"  ;
-NET "cgen_st_refmon"  LOC = "J14"  ;
-NET "cgen_st_status"  LOC = "P6"  ;
-NET "cgen_ref_sel"  LOC = "T2"  ;
-NET "cgen_sync_b"  LOC = "H15"  ;
-
-## FPGA Config
-#NET "fpga_cfg_din"  LOC = "T14"  ;
-#NET "fpga_cfg_cclk"  LOC = "R14"  ;
-#NET "fpga_cfg_init_b"  LOC = "T12"  ;
-
-## MISC
-#NET "mystery_bus<2>"  LOC = "T11"  ;
-#NET "mystery_bus<1>"  LOC = "C4"  ;
-#NET "mystery_bus<0>"  LOC = "E7"  ;
-NET "reset_n"  LOC = "D5"  ;
-NET "PPS_IN"  LOC = "M14"  ;
-NET "reset_codec"  LOC = "B14"  ;
-
-## GPIF
-NET "GPIF_D<15>"  LOC = "P7"  ;
-NET "GPIF_D<14>"  LOC = "N8"  ;
-NET "GPIF_D<13>"  LOC = "T5"  ;
-NET "GPIF_D<12>"  LOC = "T6"  ;
-NET "GPIF_D<11>"  LOC = "N6"  ;
-NET "GPIF_D<10>"  LOC = "P5"  ;
-NET "GPIF_D<9>"  LOC = "R3"  ;
-NET "GPIF_D<8>"  LOC = "T3"  ;
-NET "GPIF_D<7>"  LOC = "N12"  ;
-NET "GPIF_D<6>"  LOC = "P13"  ;
-NET "GPIF_D<5>"  LOC = "P11"  ;
-NET "GPIF_D<4>"  LOC = "R9"  ;
-NET "GPIF_D<3>"  LOC = "T9"  ;
-NET "GPIF_D<2>"  LOC = "N9"  ;
-NET "GPIF_D<1>"  LOC = "P9"  ;
-NET "GPIF_D<0>"  LOC = "P8"  ;
-
-NET "GPIF_CTL<3>"  LOC = "N5"  ;
-NET "GPIF_CTL<2>"  LOC = "M11"  ;
-NET "GPIF_CTL<1>"  LOC = "M9"  ;
-NET "GPIF_CTL<0>"  LOC = "M7"  ;
-
-NET "GPIF_RDY<3>"  LOC = "N11"  ;
-NET "GPIF_RDY<2>"  LOC = "T10"  ;
-NET "GPIF_RDY<1>"  LOC = "T4"  ;
-NET "GPIF_RDY<0>"  LOC = "R5"  ;
-
-NET "FX2_PA7_FLAGD"  LOC = "P12"  ;
-NET "FX2_PA6_PKTEND"  LOC = "R11"  ;
-NET "FX2_PA2_SLOE"  LOC = "P10"  ;
-
-NET "IFCLK"  LOC = "T8"  ;
-
-## LEDs
-NET "debug_led<2>"  LOC = "R2"  ;
-NET "debug_led<1>"  LOC = "N4"  ;
-NET "debug_led<0>"  LOC = "P4"  ;
-
-## Debug bus
-NET "debug_clk<0>"  LOC = "K15"  ;
-NET "debug_clk<1>"  LOC = "K14"  ;
-NET "debug<0>"  LOC = "K16"  ;
-NET "debug<1>"  LOC = "J16"  ;
-NET "debug<2>"  LOC = "C16"  ;
-NET "debug<3>"  LOC = "C15"  ;
-NET "debug<4>"  LOC = "E13"  ;
-NET "debug<5>"  LOC = "D14"  ;
-NET "debug<6>"  LOC = "D16"  ;
-NET "debug<7>"  LOC = "D15"  ;
-NET "debug<8>"  LOC = "E14"  ;
-NET "debug<9>"  LOC = "F13"  ;
-NET "debug<10>"  LOC = "G13"  ;
-NET "debug<11>"  LOC = "F14"  ;
-NET "debug<12>"  LOC = "E16"  ;
-NET "debug<13>"  LOC = "F15"  ;
-NET "debug<14>"  LOC = "H13"  ;
-NET "debug<15>"  LOC = "G14"  ;
-NET "debug<16>"  LOC = "G16"  ;
-NET "debug<17>"  LOC = "F16"  ;
-NET "debug<18>"  LOC = "J12"  ;
-NET "debug<19>"  LOC = "J13"  ;
-NET "debug<20>"  LOC = "L14"  ;
-NET "debug<21>"  LOC = "L16"  ;
-NET "debug<22>"  LOC = "M15"  ;
-NET "debug<23>"  LOC = "M16"  ;
-NET "debug<24>"  LOC = "L13"  ;
-NET "debug<25>"  LOC = "K13"  ;
-NET "debug<26>"  LOC = "P16"  ;
-NET "debug<27>"  LOC = "N16"  ;
-NET "debug<28>"  LOC = "R15"  ;
-NET "debug<29>"  LOC = "P15"  ;
-NET "debug<30>"  LOC = "N13"  ;
-NET "debug<31>"  LOC = "N14"  ;
-
-## ADC
-NET "adc<11>"  LOC = "B15"  ;
-NET "adc<10>"  LOC = "A8"  ;
-NET "adc<9>"  LOC = "B8"  ;
-NET "adc<8>"  LOC = "C8"  ;
-NET "adc<7>"  LOC = "D8"  ;
-NET "adc<6>"  LOC = "C9"  ;
-NET "adc<5>"  LOC = "A9"  ;
-NET "adc<4>"  LOC = "C10"  ;
-NET "adc<3>"  LOC = "D9"  ;
-NET "adc<2>"  LOC = "A3"  ;
-NET "adc<1>"  LOC = "B3"  ;
-NET "adc<0>"  LOC = "A4"  ;
-NET "RXSYNC"  LOC = "D10"  ;
-
-## DAC
-NET "TXBLANK"  LOC = "K1"  ;
-NET "TXSYNC"  LOC = "J2"  ;
-NET "dac<0>"  LOC = "J1"  ;
-NET "dac<1>"  LOC = "H3"  ;
-NET "dac<2>"  LOC = "J3"  ;
-NET "dac<3>"  LOC = "G2"  ;
-NET "dac<4>"  LOC = "H1"  ;
-NET "dac<5>"  LOC = "N3"  ;
-NET "dac<6>"  LOC = "M4"  ;
-NET "dac<7>"  LOC = "R1"  ;
-NET "dac<8>"  LOC = "P2"  ;
-NET "dac<9>"  LOC = "P1"  ;
-NET "dac<10>"  LOC = "M1"  ;
-NET "dac<11>"  LOC = "N1"  ;
-NET "dac<12>"  LOC = "M3"  ;
-NET "dac<13>"  LOC = "L4"  ;
-
-## TX DB
-NET "io_tx<0>"  LOC = "K4"  ;
-NET "io_tx<1>"  LOC = "L3"  ;
-NET "io_tx<2>"  LOC = "L2"  ;
-NET "io_tx<3>"  LOC = "F1"  ;
-NET "io_tx<4>"  LOC = "F3"  ;
-NET "io_tx<5>"  LOC = "G3"  ;
-NET "io_tx<6>"  LOC = "E3"  ;
-NET "io_tx<7>"  LOC = "E2"  ;
-NET "io_tx<8>"  LOC = "E4"  ;
-NET "io_tx<9>"  LOC = "F4"  ;
-NET "io_tx<10>"  LOC = "D1"  ;
-NET "io_tx<11>"  LOC = "E1"  ;
-NET "io_tx<12>"  LOC = "D4"  ;
-NET "io_tx<13>"  LOC = "D3"  ;
-NET "io_tx<14>"  LOC = "C2"  ;
-NET "io_tx<15>"  LOC = "C1"  ;
-
-## RX DB
-NET "io_rx<0>"  LOC = "D7"  ;
-NET "io_rx<1>"  LOC = "C6"  ;
-NET "io_rx<2>"  LOC = "A6"  ;
-NET "io_rx<3>"  LOC = "B6"  ;
-NET "io_rx<4>"  LOC = "E9"  ;
-NET "io_rx<5>"  LOC = "A7"  ;
-NET "io_rx<6>"  LOC = "C7"  ;
-NET "io_rx<7>"  LOC = "B10"  ;
-NET "io_rx<8>"  LOC = "A10"  ;
-NET "io_rx<9>"  LOC = "C11"  ;
-NET "io_rx<10>"  LOC = "A11"  ;
-NET "io_rx<11>"  LOC = "D11"  ;
-NET "io_rx<12>"  LOC = "B12"  ;
-NET "io_rx<13>"  LOC = "A12"  ;
-NET "io_rx<14>"  LOC = "A14"  ;
-NET "io_rx<15>"  LOC = "A13"  ;
-
-## SPI
-#NET "SEN_AUX"  LOC = "C12"  ;
-#NET "SCLK_AUX"  LOC = "D12"  ;
-#NET "MISO_AUX"  LOC = "J5"  ;
-NET "SCLK_CODEC"  LOC = "K3"  ;
-NET "SEN_CODEC"  LOC = "D13"  ;
-NET "MOSI_CODEC"  LOC = "C13"  ;
-NET "MISO_CODEC"  LOC = "G4"  ;
-
-NET "MISO_RX_DB"  LOC = "E6"  ;
-NET "SEN_RX_DB"  LOC = "B4"  ;
-NET "MOSI_RX_DB"  LOC = "A5"  ;
-NET "SCLK_RX_DB"  LOC = "C5"  ;
-
-NET "MISO_TX_DB"  LOC = "J4"  ;
-NET "SEN_TX_DB"  LOC = "N2"  ;
-NET "MOSI_TX_DB"  LOC = "L1"  ;
-NET "SCLK_TX_DB"  LOC = "G1"  ;
-
-## Dedicated pins
-#NET "TMS"  LOC = "B2"  ;
-#NET "TDO"  LOC = "B16"  ;
-#NET "TDI"  LOC = "B1"  ;
-#NET "TCK"  LOC = "A15"  ;
-
-#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
-#NET "fpga_cfg_done"  LOC = "T15"  ;
diff --git a/fpga/usrp2/top/B100/u1plus.v b/fpga/usrp2/top/B100/u1plus.v
deleted file mode 100644
index 5e3200580..000000000
--- a/fpga/usrp2/top/B100/u1plus.v
+++ /dev/null
@@ -1,173 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module u1plus
-  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
-   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-   output FPGA_TXD, input FPGA_RXD,
-
-   // GPIF
-   inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY,
-   output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE,
-   input IFCLK,
-   
-   inout SDA_FPGA, inout SCL_FPGA, // I2C
-
-   output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,   // DB TX SPI
-   output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,   // DB TX SPI
-   output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC,   // AD9862 main SPI
-
-   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
-   
-   inout [15:0] io_tx, inout [15:0] io_rx,
-
-   output [13:0] dac, output TXSYNC, output TXBLANK,
-   input [11:0] adc, input RXSYNC,
-  
-   input PPS_IN,
-   input reset_n, output reset_codec
-   );
-
-   assign reset_codec = 1;  // Believed to be active low
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Clocking
-   wire  clk_fpga, clk_fpga_in, reset;
-   
-   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
-   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
-
-   BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
-   
-   reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset));
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // SPI
-   wire  mosi, sclk, miso;
-   assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
-   assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
-   assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
-   assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) |
-		 (~SEN_CODEC & MISO_CODEC);
-
-   // /////////////////////////////////////////////////////////////////////////
-   // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
-
-   assign TXBLANK = 0;
-   wire [13:0] tx_i, tx_q;
-
-   genvar i;
-   generate
-      for(i=0;i<14;i=i+1)
-	begin : gen_dacout
-	   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
-		   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
-		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-	   ODDR2_inst (.Q(dac[i]),      // 1-bit DDR output data
-		       .C0(clk_fpga),  // 1-bit clock input
-		       .C1(~clk_fpga), // 1-bit clock input
-		       .CE(1'b1),      // 1-bit clock enable input
-		       .D0(tx_i[i]),   // 1-bit data input (associated with C0)
-		       .D1(tx_q[i]),   // 1-bit data input (associated with C1)
-		       .R(1'b0),       // 1-bit reset input
-		       .S(1'b0));      // 1-bit set input
-	end // block: gen_dacout
-      endgenerate
-   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
-	   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
-	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-   ODDR2_txsnc (.Q(TXSYNC),      // 1-bit DDR output data
-		.C0(clk_fpga),  // 1-bit clock input
-		.C1(~clk_fpga), // 1-bit clock input
-		.CE(1'b1),      // 1-bit clock enable input
-		.D0(1'b0),   // 1-bit data input (associated with C0)
-		.D1(1'b1),   // 1-bit data input (associated with C1)
-		.R(1'b0),       // 1-bit reset input
-		.S(1'b0));      // 1-bit set input
-
-   // /////////////////////////////////////////////////////////////////////////
-   // RX ADC -- handles deinterleaving
-
-   reg [11:0] rx_i, rx_q;
-   wire [11:0] rx_a, rx_b;
-   
-   genvar      j;
-   generate
-      for(j=0;j<12;j=j+1)
-	begin : gen_adcin
-	   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
-		   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
-		   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
-		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-	   IDDR2_inst (.Q0(rx_a[j]),      // 1-bit output captured with C0 clock
-		       .Q1(rx_b[j]),      // 1-bit output captured with C1 clock
-		       .C0(clk_fpga),     // 1-bit clock input
-		       .C1(~clk_fpga),    // 1-bit clock input
-		       .CE(1'b1),         // 1-bit clock enable input
-		       .D(adc[j]),        // 1-bit DDR data input
-		       .R(1'b0),          // 1-bit reset input
-		       .S(1'b0));         // 1-bit set input
-	end // block: gen_adcin
-   endgenerate
-   
-   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
-	   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
-	   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
-	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-   IDDR2_sync (.Q0(rxsync_0),      // 1-bit output captured with C0 clock
-	       .Q1(rxsync_1),      // 1-bit output captured with C1 clock
-	       .C0(clk_fpga),     // 1-bit clock input
-	       .C1(~clk_fpga),    // 1-bit clock input
-	       .CE(1'b1),         // 1-bit clock enable input
-	       .D(RXSYNC),        // 1-bit DDR data input
-	       .R(1'b0),          // 1-bit reset input
-	       .S(1'b0));         // 1-bit set input
-
-   always @(posedge clk_fpga)
-     if(rxsync_0)
-       begin
-	  rx_i <= rx_b;
-	  rx_q <= rx_a;
-       end
-     else
-       begin
-	  rx_i <= rx_a;
-	  rx_q <= rx_b;
-       end
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Main U1E Core
-   u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
-		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
-		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
-		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
-		     .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}),
-		     .gpif_clk(IFCLK),
-
-		     .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
-		     .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
-		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
-		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
-		     .io_tx(io_tx), .io_rx(io_rx),
-		     .tx_i(tx_i), .tx_q(tx_q), 
-		     .rx_i(rx_i), .rx_q(rx_q),
-		     .pps_in(PPS_IN) );
-
-endmodule // u1plus