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authorNicholas Corgan <nick.corgan@ettus.com>2013-05-10 08:30:50 -0700
committerNicholas Corgan <nick.corgan@ettus.com>2013-05-10 08:30:50 -0700
commit1bec070a06c4c4accbcae8c23f2cca13680d300b (patch)
tree9be3449bca58eb6da26f9875c56ae9c244f16c10 /fpga/usrp2/top
parent265daa586730b95d803a694548479cb790ea80fd (diff)
parent845dd30d8ba2113f86ff762e0c848fac9b171655 (diff)
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Merge branch 'maint'
Diffstat (limited to 'fpga/usrp2/top')
-rw-r--r--fpga/usrp2/top/B100/u1plus_core.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index 302565101..9fe09c60e 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -71,7 +71,7 @@ module u1plus_core
localparam SR_GPIO = 224; // 5
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd11, 16'd2}; //major, minor
+ localparam compat_num = {16'd11, 16'd3}; //major, minor
//assign run signals used for ATR logic
wire [NUM_RX_DSPS-1:0] run_rx_n;