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| author | Philip Balister <philip@opensdr.com> | 2010-11-04 08:02:10 -0400 |
|---|---|---|
| committer | Philip Balister <philip@opensdr.com> | 2010-11-04 08:02:10 -0400 |
| commit | 40080e474268291c915f8d68e99506e8ae2a3f75 (patch) | |
| tree | 99581ec02c77b08a11f38af901dc9db35adcbe3a /fpga/usrp2/top/u1e/timing.ucf | |
| parent | 7f8d7b0e2fef1b2d5bb9c8047380dcf958c0c49c (diff) | |
| parent | 16351339eb6962288844cefefbdb3f6eece8aca1 (diff) | |
| download | uhd-40080e474268291c915f8d68e99506e8ae2a3f75.tar.gz uhd-40080e474268291c915f8d68e99506e8ae2a3f75.tar.bz2 uhd-40080e474268291c915f8d68e99506e8ae2a3f75.zip | |
Merge remote branch 'origin/usrp_e_next' into usrp_e_next
Diffstat (limited to 'fpga/usrp2/top/u1e/timing.ucf')
| -rw-r--r-- | fpga/usrp2/top/u1e/timing.ucf | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/timing.ucf b/fpga/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/fpga/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; |