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| author | Josh Blum <josh@joshknows.com> | 2010-10-27 11:36:57 -0700 |
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| committer | Josh Blum <josh@joshknows.com> | 2010-10-27 11:36:57 -0700 |
| commit | cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7 (patch) | |
| tree | 92e2c73cd37f4bde6dd6b4a0765e44c9586e7dcd /fpga/usrp2/top/u1e/cmdfile | |
| parent | 1289d051a1934e48d77be695059b1d23f8668d8a (diff) | |
| parent | 1f77494788fa4fa8450aaf170055553bd0e5fe8e (diff) | |
| download | uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.tar.gz uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.tar.bz2 uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.zip | |
Merge branch 'ue1_rev2' into usrp_e_next
Diffstat (limited to 'fpga/usrp2/top/u1e/cmdfile')
| -rw-r--r-- | fpga/usrp2/top/u1e/cmdfile | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/cmdfile b/fpga/usrp2/top/u1e/cmdfile new file mode 100644 index 000000000..291c723b8 --- /dev/null +++ b/fpga/usrp2/top/u1e/cmdfile @@ -0,0 +1,20 @@ + +# My stuff +-y . +-y ../../control_lib +-y ../../control_lib/newfifo +-y ../../sdr_lib +-y ../../timing +-y ../../coregen +-y ../../gpmc + +# Models +-y ../../models +-y /opt/Xilinx/10.1/ISE/verilog/src/unisims + +# Open Cores +-y ../../opencores/spi/rtl/verilog ++incdir+../../opencores/spi/rtl/verilog +-y ../../opencores/i2c/rtl/verilog ++incdir+../../opencores/i2c/rtl/verilog + |