diff options
| author | Josh Blum <josh@joshknows.com> | 2010-10-27 11:36:57 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-10-27 11:36:57 -0700 |
| commit | cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7 (patch) | |
| tree | 92e2c73cd37f4bde6dd6b4a0765e44c9586e7dcd /fpga/usrp2/top/u1e/Makefile | |
| parent | 1289d051a1934e48d77be695059b1d23f8668d8a (diff) | |
| parent | 1f77494788fa4fa8450aaf170055553bd0e5fe8e (diff) | |
| download | uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.tar.gz uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.tar.bz2 uhd-cfde84d8a1f2e9fc76e9d5c80f8f4aa571fa04a7.zip | |
Merge branch 'ue1_rev2' into usrp_e_next
Diffstat (limited to 'fpga/usrp2/top/u1e/Makefile')
| -rw-r--r-- | fpga/usrp2/top/u1e/Makefile | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/fpga/usrp2/top/u1e/Makefile b/fpga/usrp2/top/u1e/Makefile new file mode 100644 index 000000000..3cb9fd8f3 --- /dev/null +++ b/fpga/usrp2/top/u1e/Makefile @@ -0,0 +1,101 @@ +# +# Copyright 2008 Ettus Research LLC +# + +################################################## +# Project Setup +################################################## +TOP_MODULE = u1e +BUILD_DIR = $(abspath build$(ISE)) + +################################################## +# Include other makefiles +################################################## + +include ../Makefile.common +include ../../fifo/Makefile.srcs +include ../../control_lib/Makefile.srcs +include ../../sdr_lib/Makefile.srcs +include ../../serdes/Makefile.srcs +include ../../simple_gemac/Makefile.srcs +include ../../timing/Makefile.srcs +include ../../opencores/Makefile.srcs +include ../../vrt/Makefile.srcs +include ../../udp/Makefile.srcs +include ../../coregen/Makefile.srcs +include ../../extram/Makefile.srcs +include ../../gpmc/Makefile.srcs + +################################################## +# Project Properties +################################################## +export PROJECT_PROPERTIES := \ +family "Spartan-3A DSP" \ +device xc3sd1800a \ +package cs484 \ +speed -4 \ +top_level_module_type "HDL" \ +synthesis_tool "XST (VHDL/Verilog)" \ +simulator "ISE Simulator (VHDL/Verilog)" \ +"Preferred Language" "Verilog" \ +"Enable Message Filtering" FALSE \ +"Display Incremental Messages" FALSE + +################################################## +# Sources +################################################## +TOP_SRCS = \ +u1e_core.v \ +u1e.v \ +u1e.ucf \ +timing.ucf + +SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ +$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ +$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(GPMC_SRCS) + +################################################## +# Process Properties +################################################## +SYNTHESIZE_PROPERTIES = \ +"Number of Clock Buffers" 8 \ +"Pack I/O Registers into IOBs" Yes \ +"Optimization Effort" High \ +"Optimize Instantiated Primitives" TRUE \ +"Register Balancing" Yes \ +"Use Clock Enable" Auto \ +"Use Synchronous Reset" Auto \ +"Use Synchronous Set" Auto + +TRANSLATE_PROPERTIES = \ +"Macro Search Path" "$(shell pwd)/../../coregen/" + +MAP_PROPERTIES = \ +"Allow Logic Optimization Across Hierarchy" TRUE \ +"Map to Input Functions" 4 \ +"Optimization Strategy (Cover Mode)" Speed \ +"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \ +"Perform Timing-Driven Packing and Placement" TRUE \ +"Map Effort Level" High \ +"Extra Effort" Normal \ +"Combinatorial Logic Optimization" TRUE \ +"Register Duplication" TRUE + +PLACE_ROUTE_PROPERTIES = \ +"Place & Route Effort Level (Overall)" High + +STATIC_TIMING_PROPERTIES = \ +"Number of Paths in Error/Verbose Report" 10 \ +"Report Type" "Error Report" + +GEN_PROG_FILE_PROPERTIES = \ +"Configuration Rate" 6 \ +"Create Binary Configuration File" TRUE \ +"Done (Output Events)" 5 \ +"Enable Bitstream Compression" TRUE \ +"Enable Outputs (Output Events)" 6 \ +"Unused IOB Pins" "Pull Up" + +SIM_MODEL_PROPERTIES = "" |