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authorJosh Blum <josh@joshknows.com>2011-08-31 18:29:34 -0700
committerJosh Blum <josh@joshknows.com>2011-08-31 18:29:34 -0700
commitd6d017aa58fd858a752ac43a6a6c24704758e444 (patch)
tree6f4b3388754d00d149a14c97f4ce6764e5d9a60c /fpga/usrp2/top/python
parent208885b6dc8a01a1d7095cff5b36c8451601259c (diff)
parent4f04b93d23015a56b2a2d4e87541b24de36c9018 (diff)
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Merge branch 'fpga_master' into next
Diffstat (limited to 'fpga/usrp2/top/python')
-rwxr-xr-xfpga/usrp2/top/python/check_timing.py5
1 files changed, 4 insertions, 1 deletions
diff --git a/fpga/usrp2/top/python/check_timing.py b/fpga/usrp2/top/python/check_timing.py
index c57e889d0..0c5918096 100755
--- a/fpga/usrp2/top/python/check_timing.py
+++ b/fpga/usrp2/top/python/check_timing.py
@@ -21,10 +21,13 @@ import re
def print_timing_constraint_summary(twr_file):
output = ""
keep = False
+ done = False
for line in open(twr_file).readlines():
if 'Derived Constraint Report' in line: keep = True
+ if 'constraint' in line and 'met' in line: done = True
+ if not keep and done: keep = True
if keep: output += line
- if 'constraint' in line and 'met' in line: break
+ if done: break
print("\n\n"+output)
if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])