Merge branch 'fpga_next' into uhd_next

5 files changed, 1804 insertions, 0 deletions

diff --git a/fpga/usrp2/top/USRP2/.gitignore b/fpga/usrp2/top/USRP2/.gitignore
new file mode 100644
index 000000000..f50a2b7e5
--- /dev/null
+++ b/fpga/usrp2/top/USRP2/.gitignore
@@ -0,0 +1,57 @@
+/*.ptwx
+/*.xrpt
+/*.zip
+/*_xdb
+/templates
+/netgen
+/_ngo
+/_xmsgs
+/_pace.ucf
+/*.cmd
+/*.ibs
+/*.lfp
+/*.mfp
+/*.bit
+/*.bin
+/*.stx
+/*.par
+/*.unroutes
+/*.ntrc_log
+/*.ngr
+/*.mrp
+/*.html
+/*.lso
+/*.twr
+/*.bld
+/*.ncd
+/*.txt
+/*.cmd_log
+/*.drc
+/*.map
+/*.twr
+/*.xml
+/*.syr
+/*.ngm
+/*.xst
+/*.csv
+/*.html
+/*.lock
+/*.ncd
+/*.twx
+/*.ise_ISE_Backup
+/*.xml
+/*.ut
+/*.xpi
+/*.ngd
+/*.ncd
+/*.pad
+/*.bgn
+/*.ngc
+/*.pcf
+/*.ngd
+/xst
+/*.log
+/*.rpt
+/*.cel
+/*.restore
+/build*
diff --git a/fpga/usrp2/top/USRP2/Makefile b/fpga/usrp2/top/USRP2/Makefile
new file mode 100644
index 000000000..e9b43491a
--- /dev/null
+++ b/fpga/usrp2/top/USRP2/Makefile
@@ -0,0 +1,98 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build)
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
+
+##################################################
+# Project Properties
+##################################################
+PROJECT_PROPERTIES = \
+family Spartan3 \
+device xc3s2000 \
+package fg456 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u2_core.v \
+u2_rev3.v \
+u2_rev3.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp2/top/USRP2/u2_core.v b/fpga/usrp2/top/USRP2/u2_core.v
new file mode 100644
index 000000000..ca9762ac5
--- /dev/null
+++ b/fpga/usrp2/top/USRP2/u2_core.v
@@ -0,0 +1,724 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// ////////////////////////////////////////////////////////////////////////////////
+// Module Name:    u2_core
+// ////////////////////////////////////////////////////////////////////////////////
+
+module u2_core
+  (// Clocks
+   input dsp_clk,
+   input wb_clk,
+   output clock_ready,
+   input clk_to_mac,
+   input pps_in,
+   
+   // Misc, debug
+   output [7:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_time_in,
+   output exp_time_out,
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output [15:0] ser_t,
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,
+   output cpld_mode,
+   output cpld_done,
+   input cpld_din,
+   input cpld_clk,
+   input cpld_detached,
+   output cpld_misc,
+   input cpld_init_b,
+   input por,
+   output config_success,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_on_a,
+   output adc_oe_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_on_b,
+   output adc_oe_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   // I2C
+   input scl_pad_i,
+   output scl_pad_o,
+   output scl_pad_oen_o,
+   input sda_pad_i,
+   output sda_pad_o,
+   output sda_pad_oen_o,
+   
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Generic SPI
+   output sclk,
+   output mosi,
+   input miso,
+   output sen_clk,
+   output sen_dac,
+   output sen_tx_db,
+   output sen_tx_adc,
+   output sen_tx_dac,
+   output sen_rx_db,
+   output sen_rx_adc,
+   output sen_rx_dac,
+   
+   // GPIO to DBoards
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
+   // External RAM
+   input [17:0] RAM_D_pi,
+   output [17:0] RAM_D_po,   
+   output RAM_D_poe,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // Debug stuff
+   output uart_tx_o, 
+   input uart_rx_i,
+   output uart_baud_o,
+   input sim_mode,
+   input [3:0] clock_divider
+   );
+
+   localparam SR_MISC     =   0;   // 7 regs
+   localparam SR_SIMTIMER =   8;   // 2
+   localparam SR_TIME64   =  10;   // 6
+   localparam SR_BUF_POOL =  16;   // 4
+
+   localparam SR_RX_FRONT =  24;   // 5
+   localparam SR_RX_CTRL0 =  32;   // 9
+   localparam SR_RX_DSP0  =  48;   // 7
+   localparam SR_RX_CTRL1 =  80;   // 9
+   localparam SR_RX_DSP1  =  96;   // 7
+
+   localparam SR_TX_FRONT = 128;   // ?
+   localparam SR_TX_CTRL  = 144;   // 6
+   localparam SR_TX_DSP   = 160;   // 5
+
+   localparam SR_UDP_SM   = 192;   // 64
+   
+   // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048
+   // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs
+   // localparam DSP_TX_FIFOSIZE = 9;  unused -- DSPTX uses extram fifo
+   localparam DSP_RX_FIFOSIZE = 10;
+   localparam ETH_TX_FIFOSIZE = 9;
+   localparam ETH_RX_FIFOSIZE = 11;
+   localparam SERDES_TX_FIFOSIZE = 9;
+   localparam SERDES_RX_FIFOSIZE = 9;  // RX currently doesn't use a fifo?
+   
+   wire [7:0] 	set_addr, set_addr_dsp;
+   wire [31:0] 	set_data, set_data_dsp;
+   wire 	set_stb, set_stb_dsp;
+   
+   wire 	ram_loader_done, ram_loader_rst;
+   wire 	wb_rst;
+   wire 	dsp_rst = wb_rst;
+   
+   wire [31:0] 	status;
+   wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
+   wire 	proc_int, overrun0, overrun1, underrun;
+   wire 	uart_tx_int, uart_rx_int;
+
+   wire [31:0] 	debug_gpio_0, debug_gpio_1;
+   wire [31:0] 	atr_lines;
+
+   wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2;
+
+   wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
+   wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
+   wire 	ser_rx_empty, ser_tx_empty, dsp_rx_empty, dsp_tx_empty, eth_rx_empty, eth_tx_empty, eth_rx_empty2;
+	
+   wire 	serdes_link_up;
+   wire 	epoch;
+   wire [31:0] 	irq;
+   wire [63:0] 	vita_time, vita_time_pps;
+   
+   wire 	 run_rx0, run_rx1, run_tx;
+   reg 		 run_rx0_d1, run_rx1_d1;
+   
+   // ///////////////////////////////////////////////////////////////////////////////////////////////
+   // Wishbone Single Master INTERCON
+   localparam 	dw = 32;  // Data bus width
+   localparam 	aw = 16;  // Address bus width, for byte addressibility, 16 = 64K byte memory space
+   localparam	sw = 4;   // Select width -- 32-bit data bus with 8-bit granularity.  
+   
+   wire [dw-1:0] m0_dat_o, m0_dat_i;
+   wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, s2_dat_i, s3_dat_i,
+		 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, s6_dat_i, s7_dat_i,
+		 s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, sa_dat_o, sa_dat_i, sb_dat_i, sb_dat_o,
+		 sc_dat_i, sc_dat_o, sd_dat_i, sd_dat_o, se_dat_i, se_dat_o, sf_dat_i, sf_dat_o;
+   wire [aw-1:0] m0_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
+   wire [sw-1:0] m0_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
+   wire 	 m0_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
+   wire 	 m0_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
+   wire 	 m0_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
+   wire 	 m0_err, m0_rty;
+   wire 	 m0_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,sa_we,sb_we,sc_we,sd_we,se_we,sf_we;
+   
+   wb_1master #(.decode_w(8),
+		.s0_addr(8'b0000_0000),.s0_mask(8'b1100_0000),  // Main RAM (0-16K)
+		.s1_addr(8'b0100_0000),.s1_mask(8'b1111_0000),  // Packet Router (16-20K)
+ 		.s2_addr(8'b0101_0000),.s2_mask(8'b1111_1100),  // SPI
+		.s3_addr(8'b0101_0100),.s3_mask(8'b1111_1100),  // I2C
+		.s4_addr(8'b0101_1000),.s4_mask(8'b1111_1100),  // GPIO
+		.s5_addr(8'b0101_1100),.s5_mask(8'b1111_1100),  // Readback
+		.s6_addr(8'b0110_0000),.s6_mask(8'b1111_0000),  // Ethernet MAC
+		.s7_addr(8'b0111_0000),.s7_mask(8'b1111_0000),  // 20K-24K, Settings Bus (only uses 1K)
+		.s8_addr(8'b1000_0000),.s8_mask(8'b1111_1100),  // PIC
+		.s9_addr(8'b1000_0100),.s9_mask(8'b1111_1100),  // Unused
+		.sa_addr(8'b1000_1000),.sa_mask(8'b1111_1100),  // UART
+		.sb_addr(8'b1000_1100),.sb_mask(8'b1111_1100),  // ATR
+		.sc_addr(8'b1001_0000),.sc_mask(8'b1111_0000),  // Unused
+		.sd_addr(8'b1010_0000),.sd_mask(8'b1111_0000),  // SD Card access
+		.se_addr(8'b1011_0000),.se_mask(8'b1111_0000),  // Unused
+		.sf_addr(8'b1100_0000),.sf_mask(8'b1100_0000),  // Unused
+		.dw(dw),.aw(aw),.sw(sw)) wb_1master
+     (.clk_i(wb_clk),.rst_i(wb_rst),       
+      .m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
+      .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o	(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+      .s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
+      .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o	(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+      .s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
+      .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o	(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+      .s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
+      .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o	(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+      .s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
+      .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o	(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+      .s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
+      .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o	(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+      .s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
+      .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o	(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+      .s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
+      .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o	(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+      .s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
+      .s8_dat_o(s8_dat_o),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o	(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
+      .s8_dat_i(s8_dat_i),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
+      .s9_dat_o(s9_dat_o),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o	(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
+      .s9_dat_i(s9_dat_i),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
+      .sa_dat_o(sa_dat_o),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
+      .sa_dat_i(sa_dat_i),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
+      .sb_dat_o(sb_dat_o),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
+      .sb_dat_i(sb_dat_i),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
+      .sc_dat_o(sc_dat_o),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
+      .sc_dat_i(sc_dat_i),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
+      .sd_dat_o(sd_dat_o),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
+      .sd_dat_i(sd_dat_i),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
+      .se_dat_o(se_dat_o),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
+      .se_dat_i(se_dat_i),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
+      .sf_dat_o(sf_dat_o),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
+      .sf_dat_i(sf_dat_i),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0));
+      
+   //////////////////////////////////////////////////////////////////////////////////////////
+   // Reset Controller
+   system_control sysctrl (.wb_clk_i(wb_clk), // .por_i(por),
+			   .ram_loader_rst_o(ram_loader_rst),
+			   .wb_rst_o(wb_rst),
+			   .ram_loader_done_i(ram_loader_done));
+
+   assign 	 config_success = ram_loader_done;
+   reg 		 takeover = 0;
+
+   wire 	 cpld_start_int, cpld_mode_int, cpld_done_int;
+   
+   always @(posedge wb_clk)
+     if(ram_loader_done)
+       takeover = 1;
+   assign 	 cpld_misc = ~takeover;
+
+   wire 	 sd_clk, sd_csn, sd_mosi, sd_miso;
+   
+   assign 	 sd_miso = cpld_din;
+   assign 	 cpld_start = takeover ? sd_clk	: cpld_start_int;
+   assign 	 cpld_mode = takeover ? sd_csn : cpld_mode_int;
+   assign 	 cpld_done = takeover ? sd_mosi : cpld_done_int;
+   
+   // ///////////////////////////////////////////////////////////////////
+   // RAM Loader
+
+   wire [31:0] 	 ram_loader_dat;
+   wire [15:0] 	 ram_loader_adr;
+   wire [3:0] 	 ram_loader_sel;
+   wire 	 ram_loader_stb, ram_loader_we;
+   ram_loader #(.AWIDTH(aw),.RAM_SIZE(16384))
+     ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
+		 .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
+		 .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
+		 .wb_we(ram_loader_we),
+		 .ram_loader_done(ram_loader_done),
+		 // CPLD Interface
+		 .cpld_clk(cpld_clk),
+		 .cpld_din(cpld_din),
+		 .cpld_start(cpld_start_int),
+		 .cpld_mode(cpld_mode_int),
+		 .cpld_done(cpld_done_int),
+		 .cpld_detached(cpld_detached));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Processor
+
+   assign 	 bus_error = m0_err | m0_rty;
+
+   wire [63:0] zpu_status;
+   zpu_wb_top #(.dat_w(dw), .adr_w(aw), .sel_w(sw))
+     zpu_top0 (.clk(wb_clk), .rst(wb_rst), .enb(ram_loader_done),
+	   // Data Wishbone bus to system bus fabric
+	   .we_o(m0_we),.stb_o(m0_stb),.dat_o(m0_dat_i),.adr_o(m0_adr),
+	   .dat_i(m0_dat_o),.ack_i(m0_ack),.sel_o(m0_sel),.cyc_o(m0_cyc),
+	   // Interrupts and exceptions
+	   .zpu_status(zpu_status), .interrupt(proc_int & 1'b0));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Dual Ported RAM -- D-Port is Slave #0 on main Wishbone
+   // I-port connects directly to processor and ram loader
+
+   ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6))
+     sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+	     
+	     .ram_loader_adr_i(ram_loader_adr[13:0]), .ram_loader_dat_i(ram_loader_dat),
+	     .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
+	     .ram_loader_we_i(ram_loader_we),
+	     .ram_loader_done_i(ram_loader_done),
+	     
+	     .if_adr(16'b0), .if_data(),
+	     
+	     .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
+	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool, slave #1
+   wire 	 rd0_ready_i, rd0_ready_o;
+   wire 	 rd1_ready_i, rd1_ready_o;
+   wire 	 rd2_ready_i, rd2_ready_o;
+   wire 	 rd3_ready_i, rd3_ready_o;
+   wire [35:0] 	 rd0_dat, rd1_dat, rd2_dat, rd3_dat;
+
+   wire 	 wr0_ready_i, wr0_ready_o;
+   wire 	 wr1_ready_i, wr1_ready_o;
+   wire 	 wr2_ready_i, wr2_ready_o;
+   wire 	 wr3_ready_i, wr3_ready_o;
+   wire [35:0] 	 wr0_dat, wr1_dat, wr2_dat, wr3_dat;
+
+   wire [35:0] 	 tx_err_data;
+   wire 	 tx_err_src_rdy, tx_err_dst_rdy;
+
+   wire [31:0] router_debug;
+
+   packet_router #(.BUF_SIZE(9), .UDP_BASE(SR_UDP_SM), .CTRL_BASE(SR_BUF_POOL)) packet_router
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
+      .wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),
+      .wb_dat_o(s1_dat_i),.wb_ack_o(s1_ack),.wb_err_o(),.wb_rty_o(),
+
+      .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+
+      .stream_clk(dsp_clk), .stream_rst(dsp_rst), .stream_clr(1'b0),
+
+      .status(status), .sys_int_o(buffer_int), .debug(router_debug),
+
+      .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o),
+      .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o),
+      .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o),
+      .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o),
+      .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy),
+
+      .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i),
+      .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i),
+      .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i)
+      );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // SPI -- Slave #2
+   spi_top shared_spi
+     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_o),
+      .wb_dat_o(s2_dat_i),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
+      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(spi_int),
+      .ss_pad_o({sen_tx_db,sen_tx_adc,sen_tx_dac,sen_rx_db,sen_rx_adc,sen_rx_dac,sen_dac,sen_clk}),
+      .sclk_pad_o(sclk),.mosi_pad_o(mosi),.miso_pad_i(miso) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // I2C -- Slave #3
+   i2c_master_top #(.ARST_LVL(1)) 
+     i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
+	  .wb_adr_i(s3_adr[4:2]),.wb_dat_i(s3_dat_o[7:0]),.wb_dat_o(s3_dat_i[7:0]),
+	  .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
+	  .wb_ack_o(s3_ack),.wb_inta_o(i2c_int),
+	  .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+	  .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+   assign 	 s3_dat_i[31:8] = 24'd0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // GPIOs -- Slave #4
+   nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		 .gpio({io_tx,io_rx}) );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Buffer Pool Status -- Slave #5   
+   
+   //compatibility number -> increment when the fpga has been sufficiently altered
+   localparam compat_num = 32'd6;
+
+   wb_readback_mux buff_pool_status
+     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
+      .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
+
+      .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
+      .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
+      .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
+      .word11(vita_time[31:0]),.word12(compat_num),.word13(irq),
+      .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0])
+      );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC  Slave #6
+
+   simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), 
+			  .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper
+     (.clk125(clk_to_mac),  .reset(wb_rst),
+      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
+      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
+      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
+      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
+      .sys_clk(dsp_clk),
+      .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
+      .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
+      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack),
+      .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i),
+      .mdio(MDIO), .mdc(MDC),
+      .debug(debug_mac));
+
+   // /////////////////////////////////////////////////////////////////////////
+   // Settings Bus -- Slave #7
+   settings_bus settings_bus
+     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s7_adr),.wb_dat_i(s7_dat_o),
+      .wb_stb_i(s7_stb),.wb_we_i(s7_we),.wb_ack_o(s7_ack),
+      .strobe(set_stb),.addr(set_addr),.data(set_data));
+   
+   assign 	 s7_dat_i = 32'd0;
+
+   settings_bus_crossclock settings_bus_crossclock
+     (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
+      .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp), .set_addr_o(set_addr_dsp), .set_data_o(set_data_dsp));
+   
+   // Output control lines
+   wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
+   assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+   assign 	 {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = serdes_outs[3:0];
+   assign 	 {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
+
+   wire 	 phy_reset;
+   assign 	 PHY_RESETn = ~phy_reset;
+   
+   setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr),
+				      .in(set_data),.out(clock_outs),.changed());
+   setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(serdes_outs),.changed());
+   setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(adc_outs),.changed());
+   setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(phy_reset),.changed());
+
+   // /////////////////////////////////////////////////////////////////////////
+   //  LEDS
+   //    register 8 determines whether leds are controlled by SW or not
+   //    1 = controlled by HW, 0 = by SW
+   //    In Rev3 there are only 6 leds, and the highest one is on the ETH connector
+   
+   wire [7:0] 	 led_src, led_sw;
+   wire [7:0] 	 led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0};
+   
+   setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
+				      .in(set_data),.out(led_sw),.changed());
+
+   setting_reg #(.my_addr(SR_MISC+6),.width(8), .at_reset(8'b0001_1110)) 
+   sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed());
+
+   assign 	 leds = (led_src & led_hw) | (~led_src & led_sw);
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // Interrupt Controller, Slave #8
+
+   // Pass interrupts on dsp_clk to wb_clk.  These need edge triggering in the pic
+   wire 	 underrun_wb, overrun_wb, pps_wb;
+
+   oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb));
+   oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb));
+   oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb));
+   
+   assign irq= {{8'b0},
+		{8'b0},
+		{3'b0, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+		{pps_wb,overrun_wb,underrun_wb,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
+   
+   pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
+	   .we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
+	   .irq(irq) );
+ 	 
+   // /////////////////////////////////////////////////////////////////////////
+   // Master Timer, Slave #9
+
+   // No longer used, replaced with simple_timer below
+   assign s9_ack = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   //  Simple Timer interrupts
+   
+   simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
+     (.clk(wb_clk), .reset(wb_rst),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .onetime_int(onetime_int), .periodic_int(periodic_int));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // UART, Slave #10
+
+   simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
+      .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
+      .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
+      .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // ATR Controller, Slave #11
+
+   atr_controller atr_controller
+     (.clk_i(wb_clk),.rst_i(wb_rst),
+      .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
+      .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
+      .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   
+   // //////////////////////////////////////////////////////////////////////////
+   // Time Sync, Slave #12 
+
+   // No longer used, see time_64bit.  Still need to handle mimo time, though
+   assign sc_ack = 0;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // SD Card Reader / Writer, Slave #13
+
+   sd_spi_wb sd_spi_wb
+     (.clk(wb_clk),.rst(wb_rst),
+      .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
+      .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
+      .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]),
+      .wb_ack_o(sd_ack) );
+
+   assign sd_dat_i[31:8] = 0;
+
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX 0
+   wire [31:0] 	 sample_rx0;
+   wire 	 clear_rx0, strobe_rx0;
+
+   always @(posedge dsp_clk)
+     run_rx0_d1 <= run_rx0;
+   
+   dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0),
+      .debug() );
+
+   setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+      .out(),.changed(clear_rx0));
+
+   vita_rx_chain #(.BASE(SR_RX_CTRL0),.UNIT(0),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain0
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .vita_time(vita_time), .overrun(overrun0),
+      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
+      .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
+      .debug() );
+
+   // /////////////////////////////////////////////////////////////////////////
+   // DSP RX 1
+   wire [31:0] 	 sample_rx1;
+   wire 	 clear_rx1, strobe_rx1;
+
+   always @(posedge dsp_clk)
+     run_rx1_d1 <= run_rx1;
+   
+   dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
+      .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1),
+      .debug() );
+
+   setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+      .out(),.changed(clear_rx1));
+
+   vita_rx_chain #(.BASE(SR_RX_CTRL1),.UNIT(2),.FIFOSIZE(DSP_RX_FIFOSIZE)) vita_rx_chain1
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .vita_time(vita_time), .overrun(overrun1),
+      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
+      .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
+      .debug() );
+
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // DSP TX
+
+   wire [35:0] 	 tx_data;
+   wire 	 tx_src_rdy, tx_dst_rdy;
+   wire [31:0] 	 debug_vt;
+   wire 	 clear_tx;
+
+   setting_reg #(.my_addr(SR_TX_CTRL+1)) sr_clear_tx
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(),.changed(clear_tx));
+
+   ext_fifo #(.EXT_WIDTH(18),.INT_WIDTH(36),.RAM_DEPTH(19),.FIFO_DEPTH(19)) 
+     ext_fifo_i1
+       (.int_clk(dsp_clk),
+	.ext_clk(clk_to_mac),
+	.rst(dsp_rst | clear_tx),
+	.RAM_D_pi(RAM_D_pi),
+	.RAM_D_po(RAM_D_po),
+	.RAM_D_poe(RAM_D_poe),
+	.RAM_A(RAM_A),
+	.RAM_WEn(RAM_WEn),
+	.RAM_CENn(RAM_CENn),
+	.RAM_LDn(RAM_LDn),
+	.RAM_OEn(RAM_OEn),
+	.RAM_CE1n(RAM_CE1n),
+	.datain(rd1_dat),
+	.src_rdy_i(rd1_ready_o),
+	.dst_rdy_o(rd1_ready_i),
+	.dataout(tx_data),
+	.src_rdy_o(tx_src_rdy),
+	.dst_rdy_i(tx_dst_rdy),
+	.debug(debug_extfifo),
+	.debug2(debug_extfifo2) );
+
+   vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
+		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(1),
+		   .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1),
+		   .DSP_NUMBER(0))
+   vita_tx_chain
+     (.clk(dsp_clk), .reset(dsp_rst),
+      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+      .vita_time(vita_time),
+      .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
+      .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
+      .dac_a(dac_a),.dac_b(dac_b),
+      .underrun(underrun), .run(run_tx),
+      .debug(debug_vt));
+   
+   // ///////////////////////////////////////////////////////////////////////////////////
+   // SERDES
+
+   serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+      .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o),
+      .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+      .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o),
+      .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty),
+      .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty),
+      .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) );
+
+   assign RAM_CLK = clk_to_mac;
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // VITA Timing
+
+   wire [31:0] 	 debug_sync;
+
+   time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
+     (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
+      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
+      .debug(debug_sync));
+
+   // /////////////////////////////////////////////////////////////////////////////////////////
+   // Debug Pins
+  
+   assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac};
+   assign debug = 32'd0;
+   assign debug_gpio_0 = 32'd0;
+   assign debug_gpio_1 = 32'd0;
+   
+endmodule // u2_core
diff --git a/fpga/usrp2/top/USRP2/u2_rev3.ucf b/fpga/usrp2/top/USRP2/u2_rev3.ucf
new file mode 100644
index 000000000..8017f61ff
--- /dev/null
+++ b/fpga/usrp2/top/USRP2/u2_rev3.ucf
@@ -0,0 +1,336 @@
+NET "leds[0]"  LOC = "E8"  ; 
+NET "leds[1]"  LOC = "F7"  ; 
+NET "leds[2]"  LOC = "E5"  ; 
+NET "leds[3]"  LOC = "B7"  ; 
+NET "leds[4]"  LOC = "C11"  ;
+NET "leds[5]"  LOC = "AB19"  ;
+NET "debug[0]"  LOC = "N5"  ;
+NET "debug[1]"  LOC = "N6"  ;
+NET "debug[2]"  LOC = "P1"  ;
+NET "debug[3]"  LOC = "P2"  ;
+NET "debug[4]"  LOC = "P4"  ;
+NET "debug[5]"  LOC = "P5"  ;
+NET "debug[6]"  LOC = "R1"  ;
+NET "debug[7]"  LOC = "R2"  ;
+NET "debug[8]"  LOC = "P6"  ;
+NET "debug[9]"  LOC = "R5"  ;
+NET "debug[10]"  LOC = "R4"  ;
+NET "debug[11]"  LOC = "T3"  ;
+NET "debug[12]"  LOC = "U3"  ;
+NET "debug[13]"  LOC = "M2"  ;
+NET "debug[14]"  LOC = "M3"  ;
+NET "debug[15]"  LOC = "M4"  ;
+NET "debug[16]"  LOC = "M5"  ;
+NET "debug[17]"  LOC = "M6"  ;
+NET "debug[18]"  LOC = "N1"  ;
+NET "debug[19]"  LOC = "N2"  ;
+NET "debug[20]"  LOC = "N3"  ;
+NET "debug[21]"  LOC = "T1"  ;
+NET "debug[22]"  LOC = "T2"  ;
+NET "debug[23]"  LOC = "U2"  ;
+NET "debug[24]"  LOC = "T4"  ;
+NET "debug[25]"  LOC = "U4"  ;
+NET "debug[26]"  LOC = "T5"  ;
+NET "debug[27]"  LOC = "T6"  ;
+NET "debug[28]"  LOC = "U5"  ;
+NET "debug[29]"  LOC = "V5"  ;
+NET "debug[30]"  LOC = "W2"  ;
+NET "debug[31]"  LOC = "W3"  ;
+NET "debug_clk[0]"  LOC = "N4"  ;
+NET "debug_clk[1]"  LOC = "M1"  ;
+NET "uart_tx_o"  LOC = "C7"  ;
+NET "uart_rx_i"  LOC = "A3"  ;
+NET "exp_time_in_p"  LOC = "V3"  ; 
+NET "exp_time_in_n"  LOC = "V4"  ; 
+NET "exp_time_out_p"  LOC = "V1"  ; 
+NET "exp_time_out_n"  LOC = "V2"  ; 
+NET "GMII_COL"  LOC = "U16"  ; 
+NET "GMII_CRS"  LOC = "U17"  ; 
+NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[1]"  LOC = "AA20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[2]"  LOC = "AB20"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[3]"  LOC = "Y18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[4]"  LOC = "AA18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[5]"  LOC = "AB18"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[6]"  LOC = "V17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TXD[7]"  LOC = "W17"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "GMII_TX_EN"  LOC = "Y17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "GMII_TX_CLK"  LOC = "W13"  ; 
+NET "GMII_RXD[0]"  LOC = "AA15"  ;
+NET "GMII_RXD[1]"  LOC = "AB15"  ;
+NET "GMII_RXD[2]"  LOC = "U14"  ;
+NET "GMII_RXD[3]"  LOC = "V14"  ;
+NET "GMII_RXD[4]"  LOC = "U13"  ;
+NET "GMII_RXD[5]"  LOC = "V13"  ;
+NET "GMII_RXD[6]"  LOC = "Y13"  ;
+NET "GMII_RXD[7]"  LOC = "AA13"  ;
+NET "GMII_RX_CLK"  LOC = "AA12"  ; 
+NET "GMII_RX_DV"  LOC = "AB16"  ; 
+NET "GMII_RX_ER"  LOC = "AA16"  ; 
+NET "MDIO"  LOC = "Y16" |PULLUP ; 
+NET "MDC"  LOC = "V18"  ; 
+NET "PHY_INTn"  LOC = "AB13"  ; 
+NET "PHY_RESETn"  LOC = "AA19"  ; 
+NET "PHY_CLK"  LOC = "V15"  ; 
+NET "RAM_D[0]"  LOC = "N20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[1]"  LOC = "N21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[2]"  LOC = "N22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[3]"  LOC = "M17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[4]"  LOC = "M18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[5]"  LOC = "M19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[6]"  LOC = "M20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[7]"  LOC = "M21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[8]"  LOC = "M22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[9]"  LOC = "Y22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[10]"  LOC = "Y21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_D[11]"  LOC = "Y20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[12]"  LOC = "Y19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[13]"  LOC = "W22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[14]"  LOC = "W21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[15]"  LOC = "W20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[16]"  LOC = "W19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_D[17]"  LOC = "V22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[0]"  LOC = "U21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[1]"  LOC = "T19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[2]"  LOC = "V21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[3]"  LOC = "V20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[4]"  LOC = "T20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[5]"  LOC = "T21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[6]"  LOC = "T22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[7]"  LOC = "T18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[8]"  LOC = "R18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[9]"  LOC = "P19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[10]"  LOC = "P21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[11]"  LOC = "P22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[12]"  LOC = "N19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[13]"  LOC = "N17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[14]"  LOC = "N18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[15]"  LOC = "T17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[16]"  LOC = "U19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[17]"  LOC = "U18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "RAM_A[18]"  LOC = "V19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST  ;
+NET "RAM_CE1n"  LOC = "U20" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_CENn"  LOC = "P18" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_CLK"  LOC = "P17" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_WEn"  LOC = "R22" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_OEn"  LOC = "R21" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "RAM_LDn"  LOC = "R19" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_enable"  LOC = "W11"  ; 
+NET "ser_prbsen"  LOC = "AA3"  ; 
+NET "ser_loopen"  LOC = "Y4"  ; 
+NET "ser_rx_en"  LOC = "AB9"  ; 
+NET "ser_tx_clk"  LOC = "U7" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_t[0]"  LOC = "V7"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[1]"  LOC = "V10"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[2]"  LOC = "AB4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[3]"  LOC = "AA4"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[4]"  LOC = "Y5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[5]"  LOC = "W5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[6]"  LOC = "AB5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[7]"  LOC = "AA5"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[8]"  LOC = "W6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[9]"  LOC = "V6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[10]"  LOC = "AA6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[11]"  LOC = "Y6"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[12]"  LOC = "W8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[13]"  LOC = "V8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[14]"  LOC = "AB8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_t[15]"  LOC = "AA8"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
+NET "ser_tklsb"  LOC = "U10" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_tkmsb"  LOC = "U11" |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ; 
+NET "ser_rx_clk"  LOC = "AA11"  ; 
+NET "ser_r[0]"  LOC = "AB10"  ;
+NET "ser_r[1]"  LOC = "AA10"  ;
+NET "ser_r[2]"  LOC = "U9"  ;
+NET "ser_r[3]"  LOC = "U6"  ;
+NET "ser_r[4]"  LOC = "AB11"  ;
+NET "ser_r[5]"  LOC = "Y7"  ;
+NET "ser_r[6]"  LOC = "W7"  ;
+NET "ser_r[7]"  LOC = "AB7"  ;
+NET "ser_r[8]"  LOC = "AA7"  ;
+NET "ser_r[9]"  LOC = "W9"  ;
+NET "ser_r[10]"  LOC = "W10"  ;
+NET "ser_r[11]"  LOC = "Y1"  ;
+NET "ser_r[12]"  LOC = "Y3"  ;
+NET "ser_r[13]"  LOC = "Y2"  ;
+NET "ser_r[14]"  LOC = "W4"  ;
+NET "ser_r[15]"  LOC = "W1"  ;
+NET "ser_rklsb"  LOC = "V9"  ;
+NET "ser_rkmsb"  LOC = "Y10"  ; 
+NET "cpld_start"  LOC = "AA9"  ; 
+NET "cpld_mode"  LOC = "U12"  ; 
+NET "cpld_done"  LOC = "V12"  ; 
+NET "cpld_din"  LOC = "AA14"  ; 
+NET "cpld_clk"  LOC = "AB14"  ; 
+NET "cpld_detached"  LOC = "V11"  ;
+NET "cpld_init_b"  LOC = "W12"  ;
+NET "cpld_misc"  LOC = "Y12"  ;
+NET "POR"  LOC = "W18"  ;
+NET "WDI"  LOC = "W15"  ;
+NET "adc_a[0]"  LOC = "A14" | IOBDELAY= "NONE" ;
+NET "adc_a[1]"  LOC = "B14" | IOBDELAY= "NONE" ;
+NET "adc_a[2]"  LOC = "C13" | IOBDELAY= "NONE" ;
+NET "adc_a[3]"  LOC = "D13" | IOBDELAY= "NONE" ;
+NET "adc_a[4]"  LOC = "A13" | IOBDELAY= "NONE" ;
+NET "adc_a[5]"  LOC = "B13" | IOBDELAY= "NONE" ;
+NET "adc_a[6]"  LOC = "E12" | IOBDELAY= "NONE" ;
+NET "adc_a[7]"  LOC = "C22" | IOBDELAY= "NONE" ;
+NET "adc_a[8]"  LOC = "C20" | IOBDELAY= "NONE" ;
+NET "adc_a[9]"  LOC = "C21" | IOBDELAY= "NONE" ;
+NET "adc_a[10]"  LOC = "D20" | IOBDELAY= "NONE" ;
+NET "adc_a[11]"  LOC = "D19" | IOBDELAY= "NONE" ;
+NET "adc_a[12]"  LOC = "D21" | IOBDELAY= "NONE" ;
+NET "adc_a[13]"  LOC = "E18" | IOBDELAY= "NONE" ;
+NET "adc_ovf_a"  LOC = "F18"  ; 
+NET "adc_oen_a"  LOC = "E19"  ; 
+NET "adc_pdn_a"  LOC = "E20"  ; 
+NET "adc_b[0]"  LOC = "A12" | IOBDELAY= "NONE";
+NET "adc_b[1]"  LOC = "E16" | IOBDELAY= "NONE" ;
+NET "adc_b[2]"  LOC = "F12" | IOBDELAY= "NONE" ;
+NET "adc_b[3]"  LOC = "F13" | IOBDELAY= "NONE" ;
+NET "adc_b[4]"  LOC = "F16" | IOBDELAY= "NONE" ;
+NET "adc_b[5]"  LOC = "F17" | IOBDELAY= "NONE" ;
+NET "adc_b[6]"  LOC = "C19" | IOBDELAY= "NONE" ;
+NET "adc_b[7]"  LOC = "B20" | IOBDELAY= "NONE" ;
+NET "adc_b[8]"  LOC = "B19" | IOBDELAY= "NONE" ;
+NET "adc_b[9]"  LOC = "C18" | IOBDELAY= "NONE" ;
+NET "adc_b[10]"  LOC = "D18" | IOBDELAY= "NONE" ;
+NET "adc_b[11]"  LOC = "B18" | IOBDELAY= "NONE" ;
+NET "adc_b[12]"  LOC = "D17" | IOBDELAY= "NONE" ;
+NET "adc_b[13]"  LOC = "E17" | IOBDELAY= "NONE" ;
+NET "adc_ovf_b"  LOC = "B17"  ; 
+NET "adc_oen_b"  LOC = "C17"  ; 
+NET "adc_pdn_b"  LOC = "D15"  ; 
+NET "dac_a[0]"  LOC = "A5"  ;
+NET "dac_a[1]"  LOC = "B5"  ;
+NET "dac_a[2]"  LOC = "C5"  ;
+NET "dac_a[3]"  LOC = "D5"  ;
+NET "dac_a[4]"  LOC = "A4"  ;
+NET "dac_a[5]"  LOC = "B4"  ;
+NET "dac_a[6]"  LOC = "F6"  ;
+NET "dac_a[7]"  LOC = "D10"  ;
+NET "dac_a[8]"  LOC = "D9"  ;
+NET "dac_a[9]"  LOC = "A10"  ;
+NET "dac_a[10]"  LOC = "L2"  ;
+NET "dac_a[11]"  LOC = "L4"  ;
+NET "dac_a[12]"  LOC = "L3"  ;
+NET "dac_a[13]"  LOC = "L6"  ;
+NET "dac_a[14]"  LOC = "L5"  ;
+NET "dac_a[15]"  LOC = "K2"  ;
+NET "dac_b[0]"  LOC = "D11"  ;
+NET "dac_b[1]"  LOC = "E11"  ;
+NET "dac_b[2]"  LOC = "F11"  ;
+NET "dac_b[3]"  LOC = "B10"  ;
+NET "dac_b[4]"  LOC = "C10"  ;
+NET "dac_b[5]"  LOC = "E10"  ;
+NET "dac_b[6]"  LOC = "F10"  ;
+NET "dac_b[7]"  LOC = "A9"  ;
+NET "dac_b[8]"  LOC = "B9"  ;
+NET "dac_b[9]"  LOC = "E9"  ;
+NET "dac_b[10]"  LOC = "F9"  ;
+NET "dac_b[11]"  LOC = "A8"  ;
+NET "dac_b[12]"  LOC = "B8"  ;
+NET "dac_b[13]"  LOC = "D7"  ;
+NET "dac_b[14]"  LOC = "E7"  ;
+NET "dac_b[15]"  LOC = "B6"  ;
+NET "dac_lock"  LOC = "D6"  ;
+NET "SCL"  LOC = "A7"  ; 
+NET "SDA"  LOC = "D8"  ; 
+NET "clk_en[0]"  LOC = "C4"  ;
+NET "clk_en[1]"  LOC = "D1"  ;
+NET "clk_sel[0]"  LOC = "C3"  ;
+NET "clk_sel[1]"  LOC = "C2"  ;
+NET "clk_func"  LOC = "C12"  ; 
+NET "clk_status"  LOC = "B12"  ; 
+NET "clk_fpga_p"  LOC = "A11"  ; 
+NET "clk_fpga_n"  LOC = "B11"  ; 
+NET "clk_to_mac"  LOC = "AB12"  ; 
+NET "pps_in"  LOC = "K1"  ; 
+NET "sclk"  LOC = "K5"  ; 
+NET "sen_clk"  LOC = "K6"  ; 
+NET "sen_dac"  LOC = "L1"  ; 
+NET "sdi"  LOC = "J1"  ; 
+NET "sdo"  LOC = "J2"  ; 
+NET "sen_tx_db"  LOC = "C1"  ; 
+NET "sclk_tx_db"  LOC = "D3"  ; 
+NET "sdo_tx_db"  LOC = "G3"  ; 
+NET "sdi_tx_db"  LOC = "G4"  ; 
+NET "sen_tx_adc"  LOC = "G2"  ; 
+NET "sclk_tx_adc"  LOC = "H1"  ; 
+NET "sdo_tx_adc"  LOC = "H2"  ; 
+NET "sdi_tx_adc"  LOC = "J4"  ; 
+NET "sen_tx_dac"  LOC = "H4"  ; 
+NET "sclk_tx_dac"  LOC = "J5"  ; 
+NET "sdi_tx_dac"  LOC = "J6"  ; 
+NET "io_tx[0]"  LOC = "K4"   ;
+NET "io_tx[1]"  LOC = "K3"   ;
+NET "io_tx[2]"  LOC = "G1"   ;
+NET "io_tx[3]"  LOC = "G5"   ;
+NET "io_tx[4]"  LOC = "H5"   ;
+NET "io_tx[5]"  LOC = "F3"   ;
+NET "io_tx[6]"  LOC = "F2"   ;
+NET "io_tx[7]"  LOC = "F5"   ;
+NET "io_tx[8]"  LOC = "G6"   ;
+NET "io_tx[9]"  LOC = "E2"   ;
+NET "io_tx[10]"  LOC = "E1"   ;
+NET "io_tx[11]"  LOC = "E3"   ;
+NET "io_tx[12]"  LOC = "F4"   ;
+NET "io_tx[13]"  LOC = "D2"   ;
+NET "io_tx[14]"  LOC = "D4"   ;
+NET "io_tx[15]"  LOC = "E4"   ;
+NET "sen_rx_db"  LOC = "D22"  ; 
+NET "sclk_rx_db"  LOC = "F19"  ; 
+NET "sdo_rx_db"  LOC = "G20"  ; 
+NET "sdi_rx_db"  LOC = "H19"  ; 
+NET "sen_rx_adc"  LOC = "H18"  ; 
+NET "sclk_rx_adc"  LOC = "J17"  ; 
+NET "sdo_rx_adc"  LOC = "H21"  ; 
+NET "sdi_rx_adc"  LOC = "H22"  ; 
+NET "sen_rx_dac"  LOC = "J18"  ; 
+NET "sclk_rx_dac"  LOC = "J19"  ; 
+NET "sdi_rx_dac"  LOC = "J21"  ; 
+NET "io_rx[0]"  LOC = "L21"   ;
+NET "io_rx[1]"  LOC = "L20"   ;
+NET "io_rx[2]"  LOC = "L19"   ;
+NET "io_rx[3]"  LOC = "L18"   ;
+NET "io_rx[4]"  LOC = "L17"   ;
+NET "io_rx[5]"  LOC = "K22"   ;
+NET "io_rx[6]"  LOC = "K21"   ;
+NET "io_rx[7]"  LOC = "K20"   ;
+NET "io_rx[8]"  LOC = "G22"   ;
+NET "io_rx[9]"  LOC = "G21"   ;
+NET "io_rx[10]"  LOC = "F21"   ;
+NET "io_rx[11]"  LOC = "F20"   ;
+NET "io_rx[12]"  LOC = "G19"   ;
+NET "io_rx[13]"  LOC = "G18"   ;
+NET "io_rx[14]"  LOC = "G17"   ;
+NET "io_rx[15]"  LOC = "E22"   ;
+
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
+
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
+
+#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
+#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
+#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
+
+TIMESPEC "TS_clk_div_to_dsp_clk" = FROM "clk_div" TO "dcm_out" 10 ns;
diff --git a/fpga/usrp2/top/USRP2/u2_rev3.v b/fpga/usrp2/top/USRP2/u2_rev3.v
new file mode 100644
index 000000000..4b0bb5541
--- /dev/null
+++ b/fpga/usrp2/top/USRP2/u2_rev3.v
@@ -0,0 +1,589 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module u2_rev3
+  (
+   // Misc, debug
+   output [5:0] leds,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+   output uart_tx_o,
+   input uart_rx_i,
+   
+   // Expansion
+   input exp_time_in_p, // Diff
+   input exp_time_in_n, // Diff
+   output exp_time_out_p, // Diff 
+   output exp_time_out_n, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
+   output GMII_GTX_CLK,
+   input GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   input PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout [17:0] RAM_D,
+   output [18:0] RAM_A,
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   output ser_rx_en,
+   
+   output ser_tx_clk,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
+
+   input ser_rx_clk,
+   input [15:0] ser_r,
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output cpld_start,  // AA9
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
+   input cpld_din,     // AA14 Now shared with CFG_Din
+   input cpld_clk,     // AB14 serial clock
+   input cpld_detached,// V11 unused
+   output cpld_init_b,  // W12 unused dual purpose
+   output cpld_misc,  // Y12 
+
+   // Watchdog interface
+   input POR,
+   output WDI,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output reg [15:0] dac_a,
+   output reg [15:0] dac_b,
+   input dac_lock,     // unused for now
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input clk_func,        // FIXME is an input to control the 9510
+   input clk_status,
+
+   // Clocks
+   input clk_fpga_p,  // Diff
+   input clk_fpga_n,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   input sdo_tx_db,
+   output sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   input sdo_tx_adc,
+   output sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout [15:0] io_tx,
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   input sdo_rx_db,
+   output sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   input sdo_rx_adc,
+   output sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+   
+   inout [15:0] io_rx   
+   );
+
+   assign 	cpld_init_b = 0;
+   // FPGA-specific pins connections
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+   wire 	clk90, clk180, clk270;
+
+   // reset the watchdog continuously
+   reg [15:0] 	wd;
+   wire 	config_success;
+   
+   always @(posedge wb_clk)
+     if(~config_success)
+       wd <= 0;
+     else
+       wd <= wd + 1;
+   assign 	WDI = wd[15];
+   
+   wire 	clk_fpga_unbuf;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga_unbuf),.I(clk_fpga_p),.IB(clk_fpga_n));
+   BUFG clk_fpga_BUF (.O(clk_fpga),.I(clk_fpga_unbuf));
+
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+   wire 	cpld_clock_buf;
+   BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock));
+   
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD = "LVDS_25";
+
+   reg [5:0] 	clock_ready_d;
+   always @(posedge clk_fpga)
+     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
+   
+   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
+   assign 	adc_oen_a = ~adc_oe_a;
+   assign 	adc_oen_b = ~adc_oe_b;
+   assign 	adc_pdn_a = ~adc_on_a; 	
+   assign 	adc_pdn_b = ~adc_on_b; 	
+
+   reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
+   reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2;
+
+    // ADC A and B are swapped in schematic to facilitate clean layout
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg1 <= adc_b;
+	adc_b_reg1 <= adc_a;
+	adc_ovf_a_reg1 <= adc_ovf_b;
+	adc_ovf_b_reg1 <= adc_ovf_a;
+     end
+   
+   always @(posedge dsp_clk)
+     begin
+	adc_a_reg2 <= adc_a_reg1;
+	adc_b_reg2 <= adc_b_reg1;
+	adc_ovf_a_reg2 <= adc_ovf_a_reg1;
+	adc_ovf_b_reg2 <= adc_ovf_b_reg1;
+     end // always @ (posedge dsp_clk)
+
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_fpga), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(clk90), 
+                 .CLK180(clk180), 
+                 .CLK270(clk270), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [5:0] leds_int;
+   assign     leds = 6'b011111 ^ leds_int;  // all except eth are active-low
+   
+   // SPI
+   wire 	miso, mosi, sclk_int;
+   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
+   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
+   
+   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
+		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
+		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   wire       ser_rx_clk_buf;
+   BUFG ser_rx_clk_BUF (.O(ser_rx_clk_buf),.I(ser_rx_clk));
+   always @(posedge ser_rx_clk_buf)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+
+   wire [15:0] dac_a_int, dac_b_int;
+   // DAC A and B are swapped in schematic to facilitate clean layout
+   // DAC A is also inverted in schematic to facilitate clean layout
+   always @(posedge dsp_clk) dac_a <= ~dac_b_int;
+   always @(posedge dsp_clk) dac_b <= dac_a_int;
+
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
+
+   wire [17:0] RAM_D_pi;
+   wire [17:0] RAM_D_po;
+   wire        RAM_D_poe;
+   
+   genvar      i;
+
+   //
+   // Instantiate IO for Bidirectional bus to SRAM
+   //
+   
+   generate  
+      for (i=0;i<18;i=i+1)
+        begin : gen_RAM_D_IO
+
+	   IOBUF #(
+		   .DRIVE(12),
+		   .IOSTANDARD("LVCMOS25"),
+		   .SLEW("FAST")
+		   )
+	     RAM_D_i (
+		      .O(RAM_D_pi[i]),
+		      .I(RAM_D_po[i]),
+		      .IO(RAM_D[i]),
+		      .T(RAM_D_poe)
+		      );
+	end // block: gen_RAM_D_IO
+   endgenerate
+
+   //
+   // DCM edits start here
+   //
+
+ 
+   wire RAM_CLK_buf;
+   wire clk_to_mac_buf;
+   wire clk125_ext_clk0;
+   wire clk125_ext_clk180;
+   wire clk125_ext_clk0_buf;
+   wire clk125_ext_clk180_buf;
+   wire clk125_int_buf;
+   wire clk125_int;
+   
+   IBUFG clk_to_mac_buf_i1 (.I(clk_to_mac), 
+			    .O(clk_to_mac_buf));
+   
+   DCM DCM_INST1 (.CLKFB(RAM_CLK_buf), 
+                  .CLKIN(clk_to_mac_buf), 
+                  .DSSEN(1'b0), 
+                  .PSCLK(1'b0), 
+                  .PSEN(1'b0), 
+                  .PSINCDEC(1'b0), 
+                  .RST(1'b0), 
+                  .CLK0(clk125_ext_clk0), 
+                  .CLK180(clk125_ext_clk180) );
+   defparam DCM_INST1.CLK_FEEDBACK = "1X";
+   defparam DCM_INST1.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST1.CLKFX_DIVIDE = 1;
+   defparam DCM_INST1.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST1.CLKIN_PERIOD = 8.000;
+   defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED";
+   defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST1.FACTORY_JF = 16'h8080;
+   defparam DCM_INST1.PHASE_SHIFT = -64;
+   defparam DCM_INST1.STARTUP_WAIT = "FALSE";
+   
+   IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), 
+			 .O(RAM_CLK_buf));
+   BUFG  clk125_ext_clk0_buf_i1 (.I(clk125_ext_clk0), 
+				   .O(clk125_ext_clk0_buf));
+   BUFG  clk125_ext_clk180_buf_i1 (.I(clk125_ext_clk180), 
+				   .O(clk125_ext_clk180_buf));
+
+   OFDDRRSE RAM_CLK_i1 (.Q(RAM_CLK),
+			.C0(clk125_ext_clk0_buf),
+			.C1(clk125_ext_clk180_buf),
+			.CE(1'b1),
+			.D0(1'b1),
+			.D1(1'b0),
+			.R(1'b0),
+			.S(1'b0));
+
+//   SRL16 dcm2_rst_i1 (.D(1'b0),
+//		      .CLK(clk_to_mac_buf),
+//		      .Q(dcm2_rst),
+//		      .A0(1'b1),
+//		      .A1(1'b1),
+//		      .A2(1'b1),
+//		      .A3(1'b1));
+   // synthesis attribute init of dcm2_rst_i1 is "000F";
+      
+   DCM DCM_INST2 (.CLKFB(clk125_int_buf), 
+                  .CLKIN(clk_to_mac_buf), 
+                  .DSSEN(1'b0), 
+                  .PSCLK(1'b0), 
+                  .PSEN(1'b0), 
+                  .PSINCDEC(1'b0), 
+                  .RST(1'b0),
+                  .CLK0(clk125_int));
+   defparam DCM_INST2.CLK_FEEDBACK = "1X";
+   defparam DCM_INST2.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST2.CLKFX_DIVIDE = 1;
+   defparam DCM_INST2.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST2.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST2.CLKIN_PERIOD = 8.000;
+   defparam DCM_INST2.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST2.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST2.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST2.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST2.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST2.FACTORY_JF = 16'h8080;
+   defparam DCM_INST2.PHASE_SHIFT = 0;
+   defparam DCM_INST2.STARTUP_WAIT = "FALSE";
+  
+   BUFG clk125_int_buf_i1 (.I(clk125_int), 
+                           .O(clk125_int_buf));
+   
+   //
+   // DCM edits end here
+   //
+   
+   
+   u2_core
+     u2_core(.dsp_clk           (dsp_clk),
+	     .wb_clk            (wb_clk),
+	     .clock_ready       (clock_ready),
+	     .clk_to_mac	(clk125_int_buf),
+	     .pps_in		(pps_in),
+	     .leds		(leds_int),
+	     .debug		(debug[31:0]),
+	     .debug_clk		(debug_clk[1:0]),
+	     .exp_time_in	(exp_time_in),
+	     .exp_time_out	(exp_time_out),
+	     .GMII_COL		(GMII_COL),
+	     .GMII_CRS		(GMII_CRS),
+	     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+	     .GMII_TX_EN	(GMII_TX_EN_unreg),
+	     .GMII_TX_ER	(GMII_TX_ER_unreg),
+	     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+	     .GMII_TX_CLK	(GMII_TX_CLK),
+	     .GMII_RXD		(GMII_RXD[7:0]),
+	     .GMII_RX_CLK	(GMII_RX_CLK),
+	     .GMII_RX_DV	(GMII_RX_DV),
+	     .GMII_RX_ER	(GMII_RX_ER),
+	     .MDIO		(MDIO),
+	     .MDC		(MDC),
+	     .PHY_INTn		(PHY_INTn),
+	     .PHY_RESETn	(PHY_RESETn),
+	     .ser_enable	(ser_enable),
+	     .ser_prbsen	(ser_prbsen),
+	     .ser_loopen	(ser_loopen),
+	     .ser_rx_en		(ser_rx_en),
+	     .ser_tx_clk	(ser_tx_clk_int),
+	     .ser_t		(ser_t_unreg[15:0]),
+	     .ser_tklsb		(ser_tklsb_unreg),
+	     .ser_tkmsb		(ser_tkmsb_unreg),
+	     .ser_rx_clk	(ser_rx_clk_buf),
+	     .ser_r		(ser_r_int[15:0]),
+	     .ser_rklsb		(ser_rklsb_int),
+	     .ser_rkmsb		(ser_rkmsb_int),
+	     .cpld_start        (cpld_start),
+	     .cpld_mode         (cpld_mode),
+	     .cpld_done         (cpld_done),
+	     .cpld_din          (cpld_din),
+	     .cpld_clk          (cpld_clk),
+	     .cpld_detached     (cpld_detached),
+	     .cpld_misc         (cpld_misc),
+	     .cpld_init_b       (cpld_init_b),
+	     .por               (~POR),
+	     .config_success    (config_success),
+	     .adc_a		(adc_a_reg2),
+	     .adc_ovf_a		(adc_ovf_a_reg2),
+	     .adc_on_a		(adc_on_a),
+	     .adc_oe_a		(adc_oe_a),
+	     .adc_b		(adc_b_reg2),
+	     .adc_ovf_b		(adc_ovf_b_reg2),
+	     .adc_on_b		(adc_on_b),
+	     .adc_oe_b		(adc_oe_b),
+	     .dac_a		(dac_a_int),
+	     .dac_b		(dac_b_int),
+	     .scl_pad_i		(scl_pad_i),
+	     .scl_pad_o		(scl_pad_o),
+	     .scl_pad_oen_o	(scl_pad_oen_o),
+	     .sda_pad_i		(sda_pad_i),
+	     .sda_pad_o		(sda_pad_o),
+	     .sda_pad_oen_o	(sda_pad_oen_o),
+	     .clk_en		(clk_en[1:0]),
+	     .clk_sel		(clk_sel[1:0]),
+	     .clk_func		(clk_func),
+	     .clk_status	(clk_status),
+	     .sclk		(sclk_int),
+	     .mosi		(mosi),
+	     .miso		(miso),
+	     .sen_clk		(sen_clk),
+	     .sen_dac		(sen_dac),
+	     .sen_tx_db		(sen_tx_db),
+	     .sen_tx_adc	(sen_tx_adc),
+	     .sen_tx_dac	(sen_tx_dac),
+	     .sen_rx_db		(sen_rx_db),
+	     .sen_rx_adc	(sen_rx_adc),
+	     .sen_rx_dac	(sen_rx_dac),
+	     .io_tx		(io_tx[15:0]),
+	     .io_rx		(io_rx[15:0]),
+	     .RAM_D_pi             (RAM_D_pi),
+	     .RAM_D_po             (RAM_D_po),
+	     .RAM_D_poe             (RAM_D_poe),
+	     .RAM_A             (RAM_A),
+	     .RAM_CE1n          (RAM_CE1n),
+	     .RAM_CENn          (RAM_CENn),
+	//     .RAM_CLK           (RAM_CLK),
+	     .RAM_WEn           (RAM_WEn),
+	     .RAM_OEn           (RAM_OEn),
+	     .RAM_LDn           (RAM_LDn), 
+	     .uart_tx_o         (uart_tx_o),
+	     .uart_rx_i         (uart_rx_i),
+	     .uart_baud_o       (),
+	     .sim_mode          (1'b0),
+	     .clock_divider     (2)
+	     );
+   
+endmodule // u2_rev2