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| author | Josh Blum <josh@joshknows.com> | 2012-03-23 14:41:08 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-03-23 14:41:08 -0700 |
| commit | 672da0df2d03a50f5bb824aa8d5d9512d040382f (patch) | |
| tree | 94391fb427c864a27a3c046cdc364bf57a0b0f12 /fpga/usrp2/top/USRP2/Makefile | |
| parent | 6acafe3a1762e434529569ad4164a03678996a9e (diff) | |
| parent | 6d70e5b3ad4c973a798dd00335fb8785b8c84ff3 (diff) | |
| download | uhd-672da0df2d03a50f5bb824aa8d5d9512d040382f.tar.gz uhd-672da0df2d03a50f5bb824aa8d5d9512d040382f.tar.bz2 uhd-672da0df2d03a50f5bb824aa8d5d9512d040382f.zip | |
Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/USRP2/Makefile')
| -rw-r--r-- | fpga/usrp2/top/USRP2/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/USRP2/Makefile b/fpga/usrp2/top/USRP2/Makefile index 10610c7dc..94480a811 100644 --- a/fpga/usrp2/top/USRP2/Makefile +++ b/fpga/usrp2/top/USRP2/Makefile @@ -70,7 +70,7 @@ SYNTHESIZE_PROPERTIES = \ "Use Clock Enable" Auto \ "Use Synchronous Reset" Auto \ "Use Synchronous Set" Auto \ -"Verilog Macros" "$(CUSTOM_DEFS)" +"Verilog Macros" "FIFO_CTRL_NO_TIME=1 $(CUSTOM_DEFS)" TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" |