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authorJosh Blum <josh@joshknows.com>2012-02-17 16:55:59 -0800
committerJosh Blum <josh@joshknows.com>2012-02-17 16:55:59 -0800
commitace4489066d1621a09e70650a00d736f0b03ed8c (patch)
treef02b34b70da9e9beb0f34dc5e64d48daa5aa4bf6 /fpga/usrp2/top/N2x0/Makefile.N200R3
parent8f8ac3397aaa85b64aaa8722efdc1c0c40e93052 (diff)
parent2e37dd87234e5beddd6f76fcda714916f761f812 (diff)
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Merge branch 'fpga_next' into next
Diffstat (limited to 'fpga/usrp2/top/N2x0/Makefile.N200R3')
-rw-r--r--fpga/usrp2/top/N2x0/Makefile.N200R312
1 files changed, 9 insertions, 3 deletions
diff --git a/fpga/usrp2/top/N2x0/Makefile.N200R3 b/fpga/usrp2/top/N2x0/Makefile.N200R3
index 9ed5ece00..680cadf44 100644
--- a/fpga/usrp2/top/N2x0/Makefile.N200R3
+++ b/fpga/usrp2/top/N2x0/Makefile.N200R3
@@ -1,5 +1,5 @@
#
-# Copyright 2008 Ettus Research LLC
+# Copyright 2008-2012 Ettus Research LLC
#
##################################################
@@ -8,6 +8,10 @@
TOP_MODULE = u2plus
BUILD_DIR = $(abspath build$(ISE)-N200R3)
+# set me in a custom makefile
+CUSTOM_SRCS =
+CUSTOM_DEFS =
+
##################################################
# Include other makefiles
##################################################
@@ -52,7 +56,8 @@ u2plus.ucf
SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(CUSTOM_SRCS)
##################################################
# Process Properties
@@ -65,7 +70,8 @@ SYNTHESIZE_PROPERTIES = \
"Register Balancing" Yes \
"Use Clock Enable" Auto \
"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
+"Use Synchronous Set" Auto \
+"Verilog Macros" "$(CUSTOM_DEFS)"
TRANSLATE_PROPERTIES = \
"Macro Search Path" "$(shell pwd)/../../coregen/"