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| author | Josh Blum <josh@joshknows.com> | 2011-07-19 14:18:58 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-19 14:18:58 -0700 |
| commit | 07c2e795b2d3fbf77d548e902c558d810c76156d (patch) | |
| tree | a5a5f8536025d2ec97d697c9f528f07902aedefe /fpga/usrp2/top/Makefile.common | |
| parent | 64382c4c8626e429f91865ab27c9e0a69da5edf3 (diff) | |
| download | uhd-07c2e795b2d3fbf77d548e902c558d810c76156d.tar.gz uhd-07c2e795b2d3fbf77d548e902c558d810c76156d.tar.bz2 uhd-07c2e795b2d3fbf77d548e902c558d810c76156d.zip | |
fpga: squashed new_work fpga changes onto uhd next
Diffstat (limited to 'fpga/usrp2/top/Makefile.common')
| -rw-r--r-- | fpga/usrp2/top/Makefile.common | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/fpga/usrp2/top/Makefile.common b/fpga/usrp2/top/Makefile.common index 6f855a070..3a35e71e7 100644 --- a/fpga/usrp2/top/Makefile.common +++ b/fpga/usrp2/top/Makefile.common @@ -1,5 +1,5 @@ # -# Copyright 2008, 2009, 2010 Ettus Research LLC +# Copyright 2008-2011 Ettus Research LLC # ################################################## @@ -14,10 +14,12 @@ endif BASE_DIR = $(abspath ..) ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py +TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT) BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs +TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr ################################################## # Global Targets @@ -35,6 +37,7 @@ synth: $(ISE_FILE) bin: check $(BIN_FILE) $(ISE_HELPER) "Generate Programming File" + $(TIMING_CHECKER) $(TWR_FILE) mcs: $(MCS_FILE) |