Merge branch 'fpga_master' into next

3 files changed, 24 insertions, 42 deletions

diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
index 8df28c9d3..f94685438 100644
--- a/fpga/usrp2/top/E1x0/timing.ucf
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -2,8 +2,22 @@
 NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
 TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
 
+NET "EM_CLK" TNM_NET = "EM_CLK";
+TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 12048 ps HIGH 50 %;
 
+#constrain GPMC IO
+NET "EM_D<*>" MAXDELAY = 5 ns;
+NET "EM_A<*>" MAXDELAY = 5 ns;
+NET "EM_NBE<*>" MAXDELAY = 5 ns;
+NET "EM_NCS4" MAXDELAY = 5 ns;
+NET "EM_NCS6" MAXDELAY = 5 ns;
+NET "EM_NWE" MAXDELAY = 5 ns;
+NET "EM_NOE" MAXDELAY = 5 ns;
 
+#constrain interrupt lines
+NET "overo_gpio144" MAXDELAY = 5 ns; #have space
+NET "overo_gpio146" MAXDELAY = 5 ns; #have data
+NET "overo_gpio147" MAXDELAY = 5 ns; #have msg/aux spi miso
 
 #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
 #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v
index dbd6173f3..ff2e08394 100644
--- a/fpga/usrp2/top/E1x0/u1e.v
+++ b/fpga/usrp2/top/E1x0/u1e.v
@@ -53,32 +53,10 @@ module u1e
 
    // /////////////////////////////////////////////////////////////////////////
    // Clocking
-   wire  clk_fpga, clk_fpga_in;
-   
+   wire  clk_fpga;
+
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
-   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
-
-   wire  clk_2x, dcm_rst, dcm_locked, clk_fb;
-   DCM #(.CLK_FEEDBACK ( "1X" ),
-	 .CLKDV_DIVIDE ( 2 ),
-	 .CLKFX_DIVIDE ( 2 ),
-	 .CLKFX_MULTIPLY ( 2 ),
-	 .CLKIN_DIVIDE_BY_2 ( "FALSE" ),
-	 .CLKIN_PERIOD ( 15.625 ),
-	 .CLKOUT_PHASE_SHIFT ( "NONE" ),
-	 .DESKEW_ADJUST ( "SYSTEM_SYNCHRONOUS" ),
-	 .DFS_FREQUENCY_MODE ( "LOW" ),
-	 .DLL_FREQUENCY_MODE ( "LOW" ),
-	 .DUTY_CYCLE_CORRECTION ( "TRUE" ),
-	 .FACTORY_JF ( 16'h8080 ),
-	 .PHASE_SHIFT ( 0 ),
-	 .STARTUP_WAIT ( "FALSE" ))
-   clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), 
-                .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), 
-		.CLKDV(), .CLKFX(), .CLKFX180(), 
-                .CLK2X(), .CLK2X180(), 
-                .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), 
-                .LOCKED(dcm_locked), .STATUS());
+   clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
 
    // /////////////////////////////////////////////////////////////////////////
    // SPI
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index 8cd51fc10..20dd98a36 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -36,7 +36,7 @@ module u1e_core
    output [13:0] tx_i, output [13:0] tx_q, 
    input [11:0] rx_i, input [11:0] rx_q, 
    
-   input pps_in, output proc_int
+   input pps_in, output reg proc_int
    );
 
    localparam TXFIFOSIZE = 13;
@@ -60,7 +60,7 @@ module u1e_core
    localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
    localparam SR_GLOBAL_RESET = 63;  // 1 reg
 
-   wire [7:0]	COMPAT_NUM = 8'd5;
+   wire [7:0]	COMPAT_NUM = 8'd6;
    
    wire 	wb_clk = clk_fpga;
    wire 	wb_rst, global_reset;
@@ -102,10 +102,7 @@ module u1e_core
    wire [35:0] 	 tx_data, rx_data, tx_err_data;
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
 		 tx_err_src_rdy, tx_err_dst_rdy;
-   reg [15:0] 	 tx_frame_len;
-   wire [15:0] 	 rx_frame_len;
 
-   wire 	 bus_error;
    wire 	 clear_tx, clear_rx;
    
    setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx
@@ -116,14 +113,13 @@ module u1e_core
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(clear_tx));
 
-   gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
+   gpmc #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
    gpmc (.arst(wb_rst),
 	 .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 	 .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 
 	 .EM_NOE(EM_NOE),
 	 
 	 .rx_have_data(rx_have_data), .tx_have_space(tx_have_space),
-	 .bus_error(bus_error), .bus_reset(0),
 	 
 	 .wb_clk(wb_clk), .wb_rst(wb_rst),
 	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
@@ -133,8 +129,7 @@ module u1e_core
 	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
 	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
-	 
-	 .tx_frame_len(tx_frame_len), .rx_frame_len(rx_frame_len),
+
 	 .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
 
 	 .test_rate(test_rate), .test_ctrl(test_ctrl),
@@ -313,8 +308,6 @@ module u1e_core
    localparam REG_CGEN_CTRL = 7'd4;    // out
    localparam REG_CGEN_ST = 7'd6;      // in
    localparam REG_TEST = 7'd8;         // out
-   localparam REG_RX_FRAMELEN = 7'd10; // in
-   localparam REG_TX_FRAMELEN = 7'd12; // out
    localparam REG_XFER_RATE = 7'd14;   // out
    localparam REG_COMPAT = 7'd16;      // in
    
@@ -324,7 +317,6 @@ module u1e_core
 	  reg_leds <= 0;
 	  reg_cgen_ctrl <= 2'b11;
 	  reg_test <= 0;
-	  tx_frame_len <= 0;
 	  xfer_rate <= 0;
        end
      else
@@ -336,8 +328,6 @@ module u1e_core
 	     reg_cgen_ctrl <= s0_dat_mosi;
 	   REG_TEST :
 	     reg_test <= s0_dat_mosi;
-	   REG_TX_FRAMELEN :
-	     tx_frame_len <= s0_dat_mosi;
 	   REG_XFER_RATE :
 	     xfer_rate <= s0_dat_mosi;
 	 endcase // case (s0_adr[6:0])
@@ -352,7 +342,6 @@ module u1e_core
 			(s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
 			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
 			(s0_adr[6:0] == REG_TEST) ? reg_test :
-			(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
 			(s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } :
 			16'hBEEF;
    
@@ -433,7 +422,7 @@ module u1e_core
         // Wishbone interface to RAM
         .wb_clk_i(wb_clk), .wb_rst_i(wb_rst),
         .wb_we_i(s5_we),   .wb_stb_i(s5_stb),
-        .wb_adr_i(s5_adr), .wb_dat_i({16'b0, s5_dat_mosi}),
+        .wb_adr_i({5'b0,s5_adr}), .wb_dat_i({16'b0, s5_dat_mosi}),
         .wb_dat_o(err_data32), .wb_ack_o(s5_ack),
         // Write FIFO Interface
         .wr_data_i(_tx_err_data), .wr_ready_i(_tx_err_src_rdy), .wr_ready_o(_tx_err_dst_rdy),
@@ -444,7 +433,8 @@ module u1e_core
    ////////////////////////////////////////////////////////////////////////////
    // Interrupts
 
-   assign proc_int = (|err_status[1:0]);
+   always @(posedge wb_clk)
+     proc_int <= (|err_status[1:0]);
 
    // /////////////////////////////////////////////////////////////////////////
    // Settings Bus -- Slave #8 + 9