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authorJosh Blum <josh@joshknows.com>2011-10-12 10:14:42 -0700
committerJosh Blum <josh@joshknows.com>2011-10-12 10:14:42 -0700
commit5f2ed309ab506adb61472b7c15fe2fe4b90cfcbb (patch)
tree73b54bf456e449028b68b86c233fbbd7dcdb3323 /fpga/usrp2/top/E1x0
parent5fcad09af2048d8babdcbddc310b069684160697 (diff)
parent2849b0912bf251cfd1c0d9e89d39870ca54bef00 (diff)
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Merge branch 'fpga_master' into uhd_master
Diffstat (limited to 'fpga/usrp2/top/E1x0')
-rw-r--r--fpga/usrp2/top/E1x0/u1e_core.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v
index e1bb50890..adc3c5aab 100644
--- a/fpga/usrp2/top/E1x0/u1e_core.v
+++ b/fpga/usrp2/top/E1x0/u1e_core.v
@@ -335,7 +335,7 @@ module u1e_core
assign test_ctrl = xfer_rate[11:8];
assign test_rate = xfer_rate[7:0];
- assign { debug_led[3:0] } = ~{run_rx0 | run_rx1,run_tx,reg_leds[1:0]};
+ assign { debug_led[3:0] } = ~{1'b1, run_tx, run_rx0 | run_rx1, cgen_st_ld};
assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds :