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| author | Josh Blum <josh@joshknows.com> | 2011-07-19 14:18:58 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-19 14:18:58 -0700 |
| commit | 07c2e795b2d3fbf77d548e902c558d810c76156d (patch) | |
| tree | a5a5f8536025d2ec97d697c9f528f07902aedefe /fpga/usrp2/top/E1x0 | |
| parent | 64382c4c8626e429f91865ab27c9e0a69da5edf3 (diff) | |
| download | uhd-07c2e795b2d3fbf77d548e902c558d810c76156d.tar.gz uhd-07c2e795b2d3fbf77d548e902c558d810c76156d.tar.bz2 uhd-07c2e795b2d3fbf77d548e902c558d810c76156d.zip | |
fpga: squashed new_work fpga changes onto uhd next
Diffstat (limited to 'fpga/usrp2/top/E1x0')
| -rw-r--r-- | fpga/usrp2/top/E1x0/Makefile | 1 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/u1e.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/top/E1x0/u1e_core.v | 4 |
3 files changed, 5 insertions, 4 deletions
diff --git a/fpga/usrp2/top/E1x0/Makefile b/fpga/usrp2/top/E1x0/Makefile index 5d721979b..19fb93ebf 100644 --- a/fpga/usrp2/top/E1x0/Makefile +++ b/fpga/usrp2/top/E1x0/Makefile @@ -72,6 +72,7 @@ TRANSLATE_PROPERTIES = \ "Macro Search Path" "$(shell pwd)/../../coregen/" MAP_PROPERTIES = \ +"Generate Detailed MAP Report" TRUE \ "Allow Logic Optimization Across Hierarchy" TRUE \ "Map to Input Functions" 4 \ "Optimization Strategy (Cover Mode)" Speed \ diff --git a/fpga/usrp2/top/E1x0/u1e.v b/fpga/usrp2/top/E1x0/u1e.v index 4f85b7d6e..dbd6173f3 100644 --- a/fpga/usrp2/top/E1x0/u1e.v +++ b/fpga/usrp2/top/E1x0/u1e.v @@ -76,7 +76,7 @@ module u1e clk_doubler (.CLKFB(clk_fb), .CLKIN(clk_fpga_in), .RST(dcm_rst), .DSSEN(0), .PSCLK(0), .PSEN(0), .PSINCDEC(0), .PSDONE(), .CLKDV(), .CLKFX(), .CLKFX180(), - .CLK2X(clk_2x), .CLK2X180(), + .CLK2X(), .CLK2X180(), .CLK0(clk_fb), .CLK90(clk_fpga), .CLK180(), .CLK270(), .LOCKED(dcm_locked), .STATUS()); @@ -141,7 +141,7 @@ module u1e // ///////////////////////////////////////////////////////////////////////// // Main U1E Core - u1e_core u1e_core(.clk_fpga(clk_fpga), .bus_clk(clk_2x), .rst_fpga(~debug_pb), + u1e_core u1e_core(.clk_fpga(clk_fpga), .rst_fpga(~debug_pb), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), diff --git a/fpga/usrp2/top/E1x0/u1e_core.v b/fpga/usrp2/top/E1x0/u1e_core.v index d481867e3..c4fc16444 100644 --- a/fpga/usrp2/top/E1x0/u1e_core.v +++ b/fpga/usrp2/top/E1x0/u1e_core.v @@ -18,7 +18,7 @@ module u1e_core - (input clk_fpga, input bus_clk, input rst_fpga, + (input clk_fpga, input rst_fpga, output [3:0] debug_led, output [31:0] debug, output [1:0] debug_clk, output debug_txd, input debug_rxd, @@ -117,7 +117,7 @@ module u1e_core .in(set_data),.out(),.changed(clear_tx)); gpmc_async #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE)) - gpmc (.arst(wb_rst), .bus_clk(bus_clk), + gpmc (.arst(wb_rst), .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE), .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), .EM_NOE(EM_NOE), |