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| author | Josh Blum <josh@joshknows.com> | 2011-08-31 18:29:34 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-31 18:29:34 -0700 |
| commit | d6d017aa58fd858a752ac43a6a6c24704758e444 (patch) | |
| tree | 6f4b3388754d00d149a14c97f4ce6764e5d9a60c /fpga/usrp2/top/E1x0/timing.ucf | |
| parent | 208885b6dc8a01a1d7095cff5b36c8451601259c (diff) | |
| parent | 4f04b93d23015a56b2a2d4e87541b24de36c9018 (diff) | |
| download | uhd-d6d017aa58fd858a752ac43a6a6c24704758e444.tar.gz uhd-d6d017aa58fd858a752ac43a6a6c24704758e444.tar.bz2 uhd-d6d017aa58fd858a752ac43a6a6c24704758e444.zip | |
Merge branch 'fpga_master' into next
Diffstat (limited to 'fpga/usrp2/top/E1x0/timing.ucf')
| -rw-r--r-- | fpga/usrp2/top/E1x0/timing.ucf | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf index 8df28c9d3..f94685438 100644 --- a/fpga/usrp2/top/E1x0/timing.ucf +++ b/fpga/usrp2/top/E1x0/timing.ucf @@ -2,8 +2,22 @@ NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; +NET "EM_CLK" TNM_NET = "EM_CLK"; +TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 12048 ps HIGH 50 %; +#constrain GPMC IO +NET "EM_D<*>" MAXDELAY = 5 ns; +NET "EM_A<*>" MAXDELAY = 5 ns; +NET "EM_NBE<*>" MAXDELAY = 5 ns; +NET "EM_NCS4" MAXDELAY = 5 ns; +NET "EM_NCS6" MAXDELAY = 5 ns; +NET "EM_NWE" MAXDELAY = 5 ns; +NET "EM_NOE" MAXDELAY = 5 ns; +#constrain interrupt lines +NET "overo_gpio144" MAXDELAY = 5 ns; #have space +NET "overo_gpio146" MAXDELAY = 5 ns; #have data +NET "overo_gpio147" MAXDELAY = 5 ns; #have msg/aux spi miso #NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; #NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; |