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authorJosh Blum <josh@joshknows.com>2012-08-31 11:20:17 -0700
committerJosh Blum <josh@joshknows.com>2012-08-31 11:20:17 -0700
commit667dcf0b98bb5a99654cf883fb97d2a549582cff (patch)
tree7c845d7ac3f506c000ab495b1d62d976b816b5cd /fpga/usrp2/top/E1x0/timing.ucf
parent05a06254a7f0149425bdda0e5544507bd35a671b (diff)
parent36a7def9aa6cecaa6f3cbf9979544d6fd5848a08 (diff)
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Merge branch 'next'
Diffstat (limited to 'fpga/usrp2/top/E1x0/timing.ucf')
-rw-r--r--fpga/usrp2/top/E1x0/timing.ucf26
1 files changed, 11 insertions, 15 deletions
diff --git a/fpga/usrp2/top/E1x0/timing.ucf b/fpga/usrp2/top/E1x0/timing.ucf
index 47c250c2f..7d3d9e090 100644
--- a/fpga/usrp2/top/E1x0/timing.ucf
+++ b/fpga/usrp2/top/E1x0/timing.ucf
@@ -3,25 +3,21 @@ NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P";
TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %;
NET "EM_CLK" TNM_NET = "EM_CLK";
-TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 12048 ps HIGH 50 %;
+TIMESPEC "TS_em_clk" = PERIOD "EM_CLK" 18867 ps HIGH 50 %;
#constrain GPMC IO
-NET "EM_D<*>" MAXDELAY = 5.5 ns;
-NET "EM_A<*>" MAXDELAY = 5.5 ns;
-NET "EM_NBE<*>" MAXDELAY = 5.5 ns;
-NET "EM_NCS4" MAXDELAY = 5.5 ns;
-NET "EM_NCS6" MAXDELAY = 5.5 ns;
-NET "EM_NWE" MAXDELAY = 5.5 ns;
-NET "EM_NOE" MAXDELAY = 5.5 ns;
+INST "EM_D<*>" TNM = gpmc_net_out;
+INST "EM_D<*>" TNM = gpmc_net;
+INST "EM_A<*>" TNM = gpmc_net;
+INST "EM_NCS4" TNM = gpmc_net;
+INST "EM_NCS6" TNM = gpmc_net;
+INST "EM_NWE" TNM = gpmc_net;
+INST "EM_NOE" TNM = gpmc_net;
+
+TIMEGRP "gpmc_net" OFFSET = IN 6 ns VALID 12 ns BEFORE "EM_CLK" FALLING;
+TIMEGRP "gpmc_net_out" OFFSET = OUT 14 ns AFTER "EM_CLK" RISING; //2 clock cyc per read
#constrain interrupt lines
NET "overo_gpio144" MAXDELAY = 5.5 ns; #have space
NET "overo_gpio146" MAXDELAY = 5.5 ns; #have data
NET "overo_gpio147" MAXDELAY = 5.5 ns; #have msg/aux spi miso
-
-#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP;
-#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP;
-#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-
-#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;
-#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING;